Prakash Dhavali | d5c9f1c | 2015-11-08 19:04:44 -0800 | [diff] [blame] | 1 | /* |
Komal Seelam | 644263d | 2016-02-22 20:45:49 +0530 | [diff] [blame] | 2 | * Copyright (c) 2013-2016 The Linux Foundation. All rights reserved. |
Prakash Dhavali | d5c9f1c | 2015-11-08 19:04:44 -0800 | [diff] [blame] | 3 | * |
| 4 | * Previously licensed under the ISC license by Qualcomm Atheros, Inc. |
| 5 | * |
| 6 | * |
| 7 | * Permission to use, copy, modify, and/or distribute this software for |
| 8 | * any purpose with or without fee is hereby granted, provided that the |
| 9 | * above copyright notice and this permission notice appear in all |
| 10 | * copies. |
| 11 | * |
| 12 | * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL |
| 13 | * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED |
| 14 | * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE |
| 15 | * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL |
| 16 | * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR |
| 17 | * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER |
| 18 | * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR |
| 19 | * PERFORMANCE OF THIS SOFTWARE. |
| 20 | */ |
| 21 | |
| 22 | /* |
| 23 | * This file was originally distributed by Qualcomm Atheros, Inc. |
| 24 | * under proprietary terms before Copyright ownership was assigned |
| 25 | * to the Linux Foundation. |
| 26 | */ |
| 27 | |
Prakash Dhavali | d5c9f1c | 2015-11-08 19:04:44 -0800 | [diff] [blame] | 28 | #include "hif.h" |
| 29 | #include "hif_io32.h" |
| 30 | #include "ce_api.h" |
| 31 | #include "ce_main.h" |
| 32 | #include "ce_internal.h" |
| 33 | #include "ce_reg.h" |
Chouhan, Anurag | fc06aa9 | 2016-03-03 19:05:05 +0530 | [diff] [blame] | 34 | #include "qdf_lock.h" |
Prakash Dhavali | d5c9f1c | 2015-11-08 19:04:44 -0800 | [diff] [blame] | 35 | #include "regtable.h" |
Prakash Dhavali | d5c9f1c | 2015-11-08 19:04:44 -0800 | [diff] [blame] | 36 | #include "epping_main.h" |
| 37 | #include "hif_main.h" |
| 38 | #include "hif_debug.h" |
Prakash Dhavali | d5c9f1c | 2015-11-08 19:04:44 -0800 | [diff] [blame] | 39 | |
| 40 | #ifdef IPA_OFFLOAD |
| 41 | #ifdef QCA_WIFI_3_0 |
| 42 | #define CE_IPA_RING_INIT(ce_desc) \ |
| 43 | do { \ |
| 44 | ce_desc->gather = 0; \ |
| 45 | ce_desc->enable_11h = 0; \ |
| 46 | ce_desc->meta_data_low = 0; \ |
| 47 | ce_desc->packet_result_offset = 64; \ |
| 48 | ce_desc->toeplitz_hash_enable = 0; \ |
| 49 | ce_desc->addr_y_search_disable = 0; \ |
| 50 | ce_desc->addr_x_search_disable = 0; \ |
| 51 | ce_desc->misc_int_disable = 0; \ |
| 52 | ce_desc->target_int_disable = 0; \ |
| 53 | ce_desc->host_int_disable = 0; \ |
| 54 | ce_desc->dest_byte_swap = 0; \ |
| 55 | ce_desc->byte_swap = 0; \ |
| 56 | ce_desc->type = 2; \ |
| 57 | ce_desc->tx_classify = 1; \ |
| 58 | ce_desc->buffer_addr_hi = 0; \ |
| 59 | ce_desc->meta_data = 0; \ |
| 60 | ce_desc->nbytes = 128; \ |
| 61 | } while (0) |
| 62 | #else |
| 63 | #define CE_IPA_RING_INIT(ce_desc) \ |
| 64 | do { \ |
| 65 | ce_desc->byte_swap = 0; \ |
| 66 | ce_desc->nbytes = 60; \ |
| 67 | ce_desc->gather = 0; \ |
| 68 | } while (0) |
| 69 | #endif /* QCA_WIFI_3_0 */ |
| 70 | #endif /* IPA_OFFLOAD */ |
| 71 | |
| 72 | static int war1_allow_sleep; |
| 73 | /* io32 write workaround */ |
| 74 | static int hif_ce_war1; |
| 75 | |
Houston Hoffman | 68e837e | 2015-12-04 12:57:24 -0800 | [diff] [blame] | 76 | #ifdef CONFIG_SLUB_DEBUG_ON |
| 77 | |
| 78 | /** |
| 79 | * struct hif_ce_event - structure for detailing a ce event |
| 80 | * @type: what the event was |
| 81 | * @time: when it happened |
| 82 | * @descriptor: descriptor enqueued or dequeued |
| 83 | * @memory: virtual address that was used |
| 84 | * @index: location of the descriptor in the ce ring; |
| 85 | */ |
| 86 | struct hif_ce_desc_event { |
| 87 | uint16_t index; |
| 88 | enum hif_ce_event_type type; |
| 89 | uint64_t time; |
| 90 | union ce_desc descriptor; |
| 91 | void *memory; |
| 92 | }; |
| 93 | |
| 94 | /* max history to record per copy engine */ |
| 95 | #define HIF_CE_HISTORY_MAX 512 |
Chouhan, Anurag | fc06aa9 | 2016-03-03 19:05:05 +0530 | [diff] [blame] | 96 | qdf_atomic_t hif_ce_desc_history_index[CE_COUNT_MAX]; |
Houston Hoffman | 68e837e | 2015-12-04 12:57:24 -0800 | [diff] [blame] | 97 | struct hif_ce_desc_event hif_ce_desc_history[CE_COUNT_MAX][HIF_CE_HISTORY_MAX]; |
| 98 | |
Houston Hoffman | 4275ba2 | 2015-12-06 21:02:11 -0800 | [diff] [blame] | 99 | |
Houston Hoffman | 68e837e | 2015-12-04 12:57:24 -0800 | [diff] [blame] | 100 | /** |
| 101 | * get_next_record_index() - get the next record index |
| 102 | * @table_index: atomic index variable to increment |
| 103 | * @array_size: array size of the circular buffer |
| 104 | * |
| 105 | * Increment the atomic index and reserve the value. |
| 106 | * Takes care of buffer wrap. |
| 107 | * Guaranteed to be thread safe as long as fewer than array_size contexts |
| 108 | * try to access the array. If there are more than array_size contexts |
| 109 | * trying to access the array, full locking of the recording process would |
| 110 | * be needed to have sane logging. |
| 111 | */ |
Chouhan, Anurag | fc06aa9 | 2016-03-03 19:05:05 +0530 | [diff] [blame] | 112 | static int get_next_record_index(qdf_atomic_t *table_index, int array_size) |
Houston Hoffman | 68e837e | 2015-12-04 12:57:24 -0800 | [diff] [blame] | 113 | { |
Chouhan, Anurag | fc06aa9 | 2016-03-03 19:05:05 +0530 | [diff] [blame] | 114 | int record_index = qdf_atomic_inc_return(table_index); |
Houston Hoffman | 68e837e | 2015-12-04 12:57:24 -0800 | [diff] [blame] | 115 | if (record_index == array_size) |
Chouhan, Anurag | fc06aa9 | 2016-03-03 19:05:05 +0530 | [diff] [blame] | 116 | qdf_atomic_sub(array_size, table_index); |
Houston Hoffman | 68e837e | 2015-12-04 12:57:24 -0800 | [diff] [blame] | 117 | |
| 118 | while (record_index >= array_size) |
| 119 | record_index -= array_size; |
| 120 | return record_index; |
| 121 | } |
| 122 | |
| 123 | /** |
| 124 | * hif_record_ce_desc_event() - record ce descriptor events |
Komal Seelam | bd7c51d | 2016-02-24 10:27:30 +0530 | [diff] [blame] | 125 | * @scn: hif_softc |
Houston Hoffman | 68e837e | 2015-12-04 12:57:24 -0800 | [diff] [blame] | 126 | * @ce_id: which ce is the event occuring on |
| 127 | * @type: what happened |
| 128 | * @descriptor: pointer to the descriptor posted/completed |
| 129 | * @memory: virtual address of buffer related to the descriptor |
| 130 | * @index: index that the descriptor was/will be at. |
| 131 | */ |
Komal Seelam | bd7c51d | 2016-02-24 10:27:30 +0530 | [diff] [blame] | 132 | void hif_record_ce_desc_event(struct hif_softc *scn, int ce_id, |
| 133 | enum hif_ce_event_type type, |
| 134 | union ce_desc *descriptor, |
| 135 | void *memory, int index) |
Houston Hoffman | 68e837e | 2015-12-04 12:57:24 -0800 | [diff] [blame] | 136 | { |
| 137 | int record_index = get_next_record_index( |
| 138 | &hif_ce_desc_history_index[ce_id], HIF_CE_HISTORY_MAX); |
| 139 | |
| 140 | struct hif_ce_desc_event *event = |
| 141 | &hif_ce_desc_history[ce_id][record_index]; |
| 142 | event->type = type; |
Komal Seelam | 7508012 | 2016-03-02 15:18:25 +0530 | [diff] [blame^] | 143 | event->time = qdf_get_monotonic_boottime(); |
Komal Seelam | bd7c51d | 2016-02-24 10:27:30 +0530 | [diff] [blame] | 144 | |
Houston Hoffman | 4275ba2 | 2015-12-06 21:02:11 -0800 | [diff] [blame] | 145 | if (descriptor != NULL) |
| 146 | event->descriptor = *descriptor; |
| 147 | else |
| 148 | memset(&event->descriptor, 0, sizeof(union ce_desc)); |
Houston Hoffman | 68e837e | 2015-12-04 12:57:24 -0800 | [diff] [blame] | 149 | event->memory = memory; |
| 150 | event->index = index; |
| 151 | } |
| 152 | |
| 153 | /** |
| 154 | * ce_init_ce_desc_event_log() - initialize the ce event log |
| 155 | * @ce_id: copy engine id for which we are initializing the log |
| 156 | * @size: size of array to dedicate |
| 157 | * |
| 158 | * Currently the passed size is ignored in favor of a precompiled value. |
| 159 | */ |
| 160 | void ce_init_ce_desc_event_log(int ce_id, int size) |
| 161 | { |
Chouhan, Anurag | fc06aa9 | 2016-03-03 19:05:05 +0530 | [diff] [blame] | 162 | qdf_atomic_init(&hif_ce_desc_history_index[ce_id]); |
Houston Hoffman | 68e837e | 2015-12-04 12:57:24 -0800 | [diff] [blame] | 163 | } |
| 164 | #else |
Komal Seelam | bd7c51d | 2016-02-24 10:27:30 +0530 | [diff] [blame] | 165 | void hif_record_ce_desc_event(struct hif_softc *scn, |
Houston Hoffman | 68e837e | 2015-12-04 12:57:24 -0800 | [diff] [blame] | 166 | int ce_id, enum hif_ce_event_type type, |
| 167 | union ce_desc *descriptor, void *memory, |
| 168 | int index) |
| 169 | { |
| 170 | } |
| 171 | |
Houston Hoffman | 5cc292b | 2015-12-22 11:33:14 -0800 | [diff] [blame] | 172 | inline void ce_init_ce_desc_event_log(int ce_id, int size) |
Houston Hoffman | 68e837e | 2015-12-04 12:57:24 -0800 | [diff] [blame] | 173 | { |
| 174 | } |
| 175 | #endif |
| 176 | |
Prakash Dhavali | d5c9f1c | 2015-11-08 19:04:44 -0800 | [diff] [blame] | 177 | /* |
| 178 | * Support for Copy Engine hardware, which is mainly used for |
| 179 | * communication between Host and Target over a PCIe interconnect. |
| 180 | */ |
| 181 | |
| 182 | /* |
| 183 | * A single CopyEngine (CE) comprises two "rings": |
| 184 | * a source ring |
| 185 | * a destination ring |
| 186 | * |
| 187 | * Each ring consists of a number of descriptors which specify |
| 188 | * an address, length, and meta-data. |
| 189 | * |
| 190 | * Typically, one side of the PCIe interconnect (Host or Target) |
| 191 | * controls one ring and the other side controls the other ring. |
| 192 | * The source side chooses when to initiate a transfer and it |
| 193 | * chooses what to send (buffer address, length). The destination |
| 194 | * side keeps a supply of "anonymous receive buffers" available and |
| 195 | * it handles incoming data as it arrives (when the destination |
| 196 | * recieves an interrupt). |
| 197 | * |
| 198 | * The sender may send a simple buffer (address/length) or it may |
| 199 | * send a small list of buffers. When a small list is sent, hardware |
| 200 | * "gathers" these and they end up in a single destination buffer |
| 201 | * with a single interrupt. |
| 202 | * |
| 203 | * There are several "contexts" managed by this layer -- more, it |
| 204 | * may seem -- than should be needed. These are provided mainly for |
| 205 | * maximum flexibility and especially to facilitate a simpler HIF |
| 206 | * implementation. There are per-CopyEngine recv, send, and watermark |
| 207 | * contexts. These are supplied by the caller when a recv, send, |
| 208 | * or watermark handler is established and they are echoed back to |
| 209 | * the caller when the respective callbacks are invoked. There is |
| 210 | * also a per-transfer context supplied by the caller when a buffer |
| 211 | * (or sendlist) is sent and when a buffer is enqueued for recv. |
| 212 | * These per-transfer contexts are echoed back to the caller when |
| 213 | * the buffer is sent/received. |
| 214 | * Target TX harsh result toeplitz_hash_result |
| 215 | */ |
| 216 | |
| 217 | /* |
| 218 | * Guts of ce_send, used by both ce_send and ce_sendlist_send. |
| 219 | * The caller takes responsibility for any needed locking. |
| 220 | */ |
| 221 | int |
| 222 | ce_completed_send_next_nolock(struct CE_state *CE_state, |
| 223 | void **per_CE_contextp, |
| 224 | void **per_transfer_contextp, |
Chouhan, Anurag | fc06aa9 | 2016-03-03 19:05:05 +0530 | [diff] [blame] | 225 | qdf_dma_addr_t *bufferp, |
Prakash Dhavali | d5c9f1c | 2015-11-08 19:04:44 -0800 | [diff] [blame] | 226 | unsigned int *nbytesp, |
| 227 | unsigned int *transfer_idp, |
| 228 | unsigned int *sw_idx, unsigned int *hw_idx, |
| 229 | uint32_t *toeplitz_hash_result); |
| 230 | |
Komal Seelam | 644263d | 2016-02-22 20:45:49 +0530 | [diff] [blame] | 231 | void war_ce_src_ring_write_idx_set(struct hif_softc *scn, |
Prakash Dhavali | d5c9f1c | 2015-11-08 19:04:44 -0800 | [diff] [blame] | 232 | u32 ctrl_addr, unsigned int write_index) |
| 233 | { |
| 234 | if (hif_ce_war1) { |
| 235 | void __iomem *indicator_addr; |
| 236 | |
| 237 | indicator_addr = scn->mem + ctrl_addr + DST_WATERMARK_ADDRESS; |
| 238 | |
| 239 | if (!war1_allow_sleep |
| 240 | && ctrl_addr == CE_BASE_ADDRESS(CDC_WAR_DATA_CE)) { |
| 241 | hif_write32_mb(indicator_addr, |
| 242 | (CDC_WAR_MAGIC_STR | write_index)); |
| 243 | } else { |
| 244 | unsigned long irq_flags; |
| 245 | local_irq_save(irq_flags); |
| 246 | hif_write32_mb(indicator_addr, 1); |
| 247 | |
| 248 | /* |
| 249 | * PCIE write waits for ACK in IPQ8K, there is no |
| 250 | * need to read back value. |
| 251 | */ |
| 252 | (void)hif_read32_mb(indicator_addr); |
| 253 | (void)hif_read32_mb(indicator_addr); /* conservative */ |
| 254 | |
| 255 | CE_SRC_RING_WRITE_IDX_SET(scn, |
| 256 | ctrl_addr, write_index); |
| 257 | |
| 258 | hif_write32_mb(indicator_addr, 0); |
| 259 | local_irq_restore(irq_flags); |
| 260 | } |
| 261 | } else |
| 262 | CE_SRC_RING_WRITE_IDX_SET(scn, ctrl_addr, write_index); |
| 263 | } |
| 264 | |
| 265 | int |
| 266 | ce_send_nolock(struct CE_handle *copyeng, |
| 267 | void *per_transfer_context, |
Chouhan, Anurag | fc06aa9 | 2016-03-03 19:05:05 +0530 | [diff] [blame] | 268 | qdf_dma_addr_t buffer, |
Prakash Dhavali | d5c9f1c | 2015-11-08 19:04:44 -0800 | [diff] [blame] | 269 | uint32_t nbytes, |
| 270 | uint32_t transfer_id, |
| 271 | uint32_t flags, |
| 272 | uint32_t user_flags) |
| 273 | { |
| 274 | int status; |
| 275 | struct CE_state *CE_state = (struct CE_state *)copyeng; |
| 276 | struct CE_ring_state *src_ring = CE_state->src_ring; |
| 277 | uint32_t ctrl_addr = CE_state->ctrl_addr; |
| 278 | unsigned int nentries_mask = src_ring->nentries_mask; |
| 279 | unsigned int sw_index = src_ring->sw_index; |
| 280 | unsigned int write_index = src_ring->write_index; |
| 281 | uint64_t dma_addr = buffer; |
Komal Seelam | 644263d | 2016-02-22 20:45:49 +0530 | [diff] [blame] | 282 | struct hif_softc *scn = CE_state->scn; |
Prakash Dhavali | d5c9f1c | 2015-11-08 19:04:44 -0800 | [diff] [blame] | 283 | |
Houston Hoffman | 2c32cf6 | 2016-03-14 21:12:00 -0700 | [diff] [blame] | 284 | if (Q_TARGET_ACCESS_BEGIN(scn) < 0) |
Houston Hoffman | 987ab44 | 2016-03-14 21:12:02 -0700 | [diff] [blame] | 285 | return QDF_STATUS_E_FAILURE; |
Prakash Dhavali | d5c9f1c | 2015-11-08 19:04:44 -0800 | [diff] [blame] | 286 | if (unlikely(CE_RING_DELTA(nentries_mask, |
| 287 | write_index, sw_index - 1) <= 0)) { |
| 288 | OL_ATH_CE_PKT_ERROR_COUNT_INCR(scn, CE_RING_DELTA_FAIL); |
Houston Hoffman | 987ab44 | 2016-03-14 21:12:02 -0700 | [diff] [blame] | 289 | Q_TARGET_ACCESS_END(scn); |
| 290 | return QDF_STATUS_E_FAILURE; |
Prakash Dhavali | d5c9f1c | 2015-11-08 19:04:44 -0800 | [diff] [blame] | 291 | } |
| 292 | { |
Houston Hoffman | 68e837e | 2015-12-04 12:57:24 -0800 | [diff] [blame] | 293 | enum hif_ce_event_type event_type = HIF_TX_GATHER_DESC_POST; |
Prakash Dhavali | d5c9f1c | 2015-11-08 19:04:44 -0800 | [diff] [blame] | 294 | struct CE_src_desc *src_ring_base = |
| 295 | (struct CE_src_desc *)src_ring->base_addr_owner_space; |
| 296 | struct CE_src_desc *shadow_base = |
| 297 | (struct CE_src_desc *)src_ring->shadow_base; |
| 298 | struct CE_src_desc *src_desc = |
| 299 | CE_SRC_RING_TO_DESC(src_ring_base, write_index); |
| 300 | struct CE_src_desc *shadow_src_desc = |
| 301 | CE_SRC_RING_TO_DESC(shadow_base, write_index); |
| 302 | |
| 303 | /* Update low 32 bits source descriptor address */ |
| 304 | shadow_src_desc->buffer_addr = |
| 305 | (uint32_t)(dma_addr & 0xFFFFFFFF); |
| 306 | #ifdef QCA_WIFI_3_0 |
| 307 | shadow_src_desc->buffer_addr_hi = |
| 308 | (uint32_t)((dma_addr >> 32) & 0x1F); |
| 309 | user_flags |= shadow_src_desc->buffer_addr_hi; |
| 310 | memcpy(&(((uint32_t *)shadow_src_desc)[1]), &user_flags, |
| 311 | sizeof(uint32_t)); |
| 312 | #endif |
| 313 | shadow_src_desc->meta_data = transfer_id; |
| 314 | |
| 315 | /* |
| 316 | * Set the swap bit if: |
| 317 | * typical sends on this CE are swapped (host is big-endian) |
| 318 | * and this send doesn't disable the swapping |
| 319 | * (data is not bytestream) |
| 320 | */ |
| 321 | shadow_src_desc->byte_swap = |
| 322 | (((CE_state->attr_flags & CE_ATTR_BYTE_SWAP_DATA) |
| 323 | != 0) & ((flags & CE_SEND_FLAG_SWAP_DISABLE) == 0)); |
| 324 | shadow_src_desc->gather = ((flags & CE_SEND_FLAG_GATHER) != 0); |
| 325 | shadow_src_desc->nbytes = nbytes; |
| 326 | |
| 327 | *src_desc = *shadow_src_desc; |
| 328 | |
| 329 | src_ring->per_transfer_context[write_index] = |
| 330 | per_transfer_context; |
| 331 | |
| 332 | /* Update Source Ring Write Index */ |
| 333 | write_index = CE_RING_IDX_INCR(nentries_mask, write_index); |
| 334 | |
| 335 | /* WORKAROUND */ |
| 336 | if (!shadow_src_desc->gather) { |
Houston Hoffman | 68e837e | 2015-12-04 12:57:24 -0800 | [diff] [blame] | 337 | event_type = HIF_TX_DESC_POST; |
Prakash Dhavali | d5c9f1c | 2015-11-08 19:04:44 -0800 | [diff] [blame] | 338 | war_ce_src_ring_write_idx_set(scn, ctrl_addr, |
| 339 | write_index); |
| 340 | } |
| 341 | |
Houston Hoffman | 68e837e | 2015-12-04 12:57:24 -0800 | [diff] [blame] | 342 | /* src_ring->write index hasn't been updated event though |
| 343 | * the register has allready been written to. |
| 344 | */ |
Komal Seelam | bd7c51d | 2016-02-24 10:27:30 +0530 | [diff] [blame] | 345 | hif_record_ce_desc_event(scn, CE_state->id, event_type, |
Houston Hoffman | 68e837e | 2015-12-04 12:57:24 -0800 | [diff] [blame] | 346 | (union ce_desc *) shadow_src_desc, per_transfer_context, |
| 347 | src_ring->write_index); |
| 348 | |
Prakash Dhavali | d5c9f1c | 2015-11-08 19:04:44 -0800 | [diff] [blame] | 349 | src_ring->write_index = write_index; |
Chouhan, Anurag | fc06aa9 | 2016-03-03 19:05:05 +0530 | [diff] [blame] | 350 | status = QDF_STATUS_SUCCESS; |
Prakash Dhavali | d5c9f1c | 2015-11-08 19:04:44 -0800 | [diff] [blame] | 351 | } |
Houston Hoffman | 987ab44 | 2016-03-14 21:12:02 -0700 | [diff] [blame] | 352 | Q_TARGET_ACCESS_END(scn); |
Prakash Dhavali | d5c9f1c | 2015-11-08 19:04:44 -0800 | [diff] [blame] | 353 | return status; |
| 354 | } |
| 355 | |
| 356 | int |
| 357 | ce_send(struct CE_handle *copyeng, |
| 358 | void *per_transfer_context, |
Chouhan, Anurag | fc06aa9 | 2016-03-03 19:05:05 +0530 | [diff] [blame] | 359 | qdf_dma_addr_t buffer, |
Prakash Dhavali | d5c9f1c | 2015-11-08 19:04:44 -0800 | [diff] [blame] | 360 | uint32_t nbytes, |
| 361 | uint32_t transfer_id, |
| 362 | uint32_t flags, |
| 363 | uint32_t user_flag) |
| 364 | { |
| 365 | struct CE_state *CE_state = (struct CE_state *)copyeng; |
| 366 | int status; |
| 367 | |
Chouhan, Anurag | fc06aa9 | 2016-03-03 19:05:05 +0530 | [diff] [blame] | 368 | qdf_spin_lock_bh(&CE_state->ce_index_lock); |
Prakash Dhavali | d5c9f1c | 2015-11-08 19:04:44 -0800 | [diff] [blame] | 369 | status = ce_send_nolock(copyeng, per_transfer_context, buffer, nbytes, |
| 370 | transfer_id, flags, user_flag); |
Chouhan, Anurag | fc06aa9 | 2016-03-03 19:05:05 +0530 | [diff] [blame] | 371 | qdf_spin_unlock_bh(&CE_state->ce_index_lock); |
Prakash Dhavali | d5c9f1c | 2015-11-08 19:04:44 -0800 | [diff] [blame] | 372 | |
| 373 | return status; |
| 374 | } |
| 375 | |
| 376 | unsigned int ce_sendlist_sizeof(void) |
| 377 | { |
| 378 | return sizeof(struct ce_sendlist); |
| 379 | } |
| 380 | |
| 381 | void ce_sendlist_init(struct ce_sendlist *sendlist) |
| 382 | { |
| 383 | struct ce_sendlist_s *sl = (struct ce_sendlist_s *)sendlist; |
| 384 | sl->num_items = 0; |
| 385 | } |
| 386 | |
| 387 | int |
| 388 | ce_sendlist_buf_add(struct ce_sendlist *sendlist, |
Chouhan, Anurag | fc06aa9 | 2016-03-03 19:05:05 +0530 | [diff] [blame] | 389 | qdf_dma_addr_t buffer, |
Prakash Dhavali | d5c9f1c | 2015-11-08 19:04:44 -0800 | [diff] [blame] | 390 | uint32_t nbytes, |
| 391 | uint32_t flags, |
| 392 | uint32_t user_flags) |
| 393 | { |
| 394 | struct ce_sendlist_s *sl = (struct ce_sendlist_s *)sendlist; |
| 395 | unsigned int num_items = sl->num_items; |
| 396 | struct ce_sendlist_item *item; |
| 397 | |
| 398 | if (num_items >= CE_SENDLIST_ITEMS_MAX) { |
Chouhan, Anurag | fc06aa9 | 2016-03-03 19:05:05 +0530 | [diff] [blame] | 399 | QDF_ASSERT(num_items < CE_SENDLIST_ITEMS_MAX); |
| 400 | return QDF_STATUS_E_RESOURCES; |
Prakash Dhavali | d5c9f1c | 2015-11-08 19:04:44 -0800 | [diff] [blame] | 401 | } |
| 402 | |
| 403 | item = &sl->item[num_items]; |
| 404 | item->send_type = CE_SIMPLE_BUFFER_TYPE; |
| 405 | item->data = buffer; |
| 406 | item->u.nbytes = nbytes; |
| 407 | item->flags = flags; |
| 408 | item->user_flags = user_flags; |
| 409 | sl->num_items = num_items + 1; |
Chouhan, Anurag | fc06aa9 | 2016-03-03 19:05:05 +0530 | [diff] [blame] | 410 | return QDF_STATUS_SUCCESS; |
Prakash Dhavali | d5c9f1c | 2015-11-08 19:04:44 -0800 | [diff] [blame] | 411 | } |
| 412 | |
| 413 | int |
| 414 | ce_sendlist_send(struct CE_handle *copyeng, |
| 415 | void *per_transfer_context, |
| 416 | struct ce_sendlist *sendlist, unsigned int transfer_id) |
| 417 | { |
| 418 | int status = -ENOMEM; |
| 419 | struct ce_sendlist_s *sl = (struct ce_sendlist_s *)sendlist; |
| 420 | struct CE_state *CE_state = (struct CE_state *)copyeng; |
| 421 | struct CE_ring_state *src_ring = CE_state->src_ring; |
| 422 | unsigned int nentries_mask = src_ring->nentries_mask; |
| 423 | unsigned int num_items = sl->num_items; |
| 424 | unsigned int sw_index; |
| 425 | unsigned int write_index; |
| 426 | |
Chouhan, Anurag | fc06aa9 | 2016-03-03 19:05:05 +0530 | [diff] [blame] | 427 | QDF_ASSERT((num_items > 0) && (num_items < src_ring->nentries)); |
Prakash Dhavali | d5c9f1c | 2015-11-08 19:04:44 -0800 | [diff] [blame] | 428 | |
Chouhan, Anurag | fc06aa9 | 2016-03-03 19:05:05 +0530 | [diff] [blame] | 429 | qdf_spin_lock_bh(&CE_state->ce_index_lock); |
Prakash Dhavali | d5c9f1c | 2015-11-08 19:04:44 -0800 | [diff] [blame] | 430 | sw_index = src_ring->sw_index; |
| 431 | write_index = src_ring->write_index; |
| 432 | |
| 433 | if (CE_RING_DELTA(nentries_mask, write_index, sw_index - 1) >= |
| 434 | num_items) { |
| 435 | struct ce_sendlist_item *item; |
| 436 | int i; |
| 437 | |
| 438 | /* handle all but the last item uniformly */ |
| 439 | for (i = 0; i < num_items - 1; i++) { |
| 440 | item = &sl->item[i]; |
| 441 | /* TBDXXX: Support extensible sendlist_types? */ |
Chouhan, Anurag | fc06aa9 | 2016-03-03 19:05:05 +0530 | [diff] [blame] | 442 | QDF_ASSERT(item->send_type == CE_SIMPLE_BUFFER_TYPE); |
Prakash Dhavali | d5c9f1c | 2015-11-08 19:04:44 -0800 | [diff] [blame] | 443 | status = ce_send_nolock(copyeng, CE_SENDLIST_ITEM_CTXT, |
Chouhan, Anurag | fc06aa9 | 2016-03-03 19:05:05 +0530 | [diff] [blame] | 444 | (qdf_dma_addr_t) item->data, |
Prakash Dhavali | d5c9f1c | 2015-11-08 19:04:44 -0800 | [diff] [blame] | 445 | item->u.nbytes, transfer_id, |
| 446 | item->flags | CE_SEND_FLAG_GATHER, |
| 447 | item->user_flags); |
Chouhan, Anurag | fc06aa9 | 2016-03-03 19:05:05 +0530 | [diff] [blame] | 448 | QDF_ASSERT(status == QDF_STATUS_SUCCESS); |
Prakash Dhavali | d5c9f1c | 2015-11-08 19:04:44 -0800 | [diff] [blame] | 449 | } |
| 450 | /* provide valid context pointer for final item */ |
| 451 | item = &sl->item[i]; |
| 452 | /* TBDXXX: Support extensible sendlist_types? */ |
Chouhan, Anurag | fc06aa9 | 2016-03-03 19:05:05 +0530 | [diff] [blame] | 453 | QDF_ASSERT(item->send_type == CE_SIMPLE_BUFFER_TYPE); |
Prakash Dhavali | d5c9f1c | 2015-11-08 19:04:44 -0800 | [diff] [blame] | 454 | status = ce_send_nolock(copyeng, per_transfer_context, |
Chouhan, Anurag | fc06aa9 | 2016-03-03 19:05:05 +0530 | [diff] [blame] | 455 | (qdf_dma_addr_t) item->data, |
Prakash Dhavali | d5c9f1c | 2015-11-08 19:04:44 -0800 | [diff] [blame] | 456 | item->u.nbytes, |
| 457 | transfer_id, item->flags, |
| 458 | item->user_flags); |
Chouhan, Anurag | fc06aa9 | 2016-03-03 19:05:05 +0530 | [diff] [blame] | 459 | QDF_ASSERT(status == QDF_STATUS_SUCCESS); |
Vishwajith Upendra | 70f8b6e | 2016-03-01 16:28:23 +0530 | [diff] [blame] | 460 | QDF_NBUF_UPDATE_TX_PKT_COUNT((qdf_nbuf_t)per_transfer_context, |
| 461 | QDF_NBUF_TX_PKT_CE); |
| 462 | DPTRACE(qdf_dp_trace((qdf_nbuf_t)per_transfer_context, |
Chouhan, Anurag | fc06aa9 | 2016-03-03 19:05:05 +0530 | [diff] [blame] | 463 | QDF_DP_TRACE_CE_PACKET_PTR_RECORD, |
Vishwajith Upendra | 70f8b6e | 2016-03-01 16:28:23 +0530 | [diff] [blame] | 464 | (uint8_t *)(((qdf_nbuf_t)per_transfer_context)->data), |
| 465 | sizeof(((qdf_nbuf_t)per_transfer_context)->data))); |
Prakash Dhavali | d5c9f1c | 2015-11-08 19:04:44 -0800 | [diff] [blame] | 466 | } else { |
| 467 | /* |
| 468 | * Probably not worth the additional complexity to support |
| 469 | * partial sends with continuation or notification. We expect |
| 470 | * to use large rings and small sendlists. If we can't handle |
| 471 | * the entire request at once, punt it back to the caller. |
| 472 | */ |
| 473 | } |
Chouhan, Anurag | fc06aa9 | 2016-03-03 19:05:05 +0530 | [diff] [blame] | 474 | qdf_spin_unlock_bh(&CE_state->ce_index_lock); |
Prakash Dhavali | d5c9f1c | 2015-11-08 19:04:44 -0800 | [diff] [blame] | 475 | |
| 476 | return status; |
| 477 | } |
| 478 | |
| 479 | #ifdef WLAN_FEATURE_FASTPATH |
| 480 | #ifdef QCA_WIFI_3_0 |
| 481 | static inline void |
| 482 | ce_buffer_addr_hi_set(struct CE_src_desc *shadow_src_desc, |
| 483 | uint64_t dma_addr, |
| 484 | uint32_t user_flags) |
| 485 | { |
| 486 | shadow_src_desc->buffer_addr_hi = |
| 487 | (uint32_t)((dma_addr >> 32) & 0x1F); |
| 488 | user_flags |= shadow_src_desc->buffer_addr_hi; |
| 489 | memcpy(&(((uint32_t *)shadow_src_desc)[1]), &user_flags, |
| 490 | sizeof(uint32_t)); |
| 491 | } |
| 492 | #else |
| 493 | static inline void |
| 494 | ce_buffer_addr_hi_set(struct CE_src_desc *shadow_src_desc, |
| 495 | uint64_t dma_addr, |
| 496 | uint32_t user_flags) |
| 497 | { |
| 498 | } |
| 499 | #endif |
| 500 | |
| 501 | /** |
| 502 | * ce_send_fast() CE layer Tx buffer posting function |
| 503 | * @copyeng: copy engine handle |
| 504 | * @msdus: iarray of msdu to be sent |
| 505 | * @num_msdus: number of msdus in an array |
| 506 | * @transfer_id: transfer_id |
| 507 | * |
| 508 | * Assumption : Called with an array of MSDU's |
| 509 | * Function: |
| 510 | * For each msdu in the array |
| 511 | * 1. Check no. of available entries |
| 512 | * 2. Create src ring entries (allocated in consistent memory |
| 513 | * 3. Write index to h/w |
| 514 | * |
| 515 | * Return: No. of packets that could be sent |
| 516 | */ |
| 517 | |
Vishwajith Upendra | 70f8b6e | 2016-03-01 16:28:23 +0530 | [diff] [blame] | 518 | int ce_send_fast(struct CE_handle *copyeng, qdf_nbuf_t *msdus, |
Prakash Dhavali | d5c9f1c | 2015-11-08 19:04:44 -0800 | [diff] [blame] | 519 | unsigned int num_msdus, unsigned int transfer_id) |
| 520 | { |
| 521 | struct CE_state *ce_state = (struct CE_state *)copyeng; |
Komal Seelam | 644263d | 2016-02-22 20:45:49 +0530 | [diff] [blame] | 522 | struct hif_softc *scn = ce_state->scn; |
Komal Seelam | 5584a7c | 2016-02-24 19:22:48 +0530 | [diff] [blame] | 523 | struct hif_opaque_softc *hif_hdl = GET_HIF_OPAQUE_HDL(scn); |
Prakash Dhavali | d5c9f1c | 2015-11-08 19:04:44 -0800 | [diff] [blame] | 524 | struct CE_ring_state *src_ring = ce_state->src_ring; |
| 525 | u_int32_t ctrl_addr = ce_state->ctrl_addr; |
| 526 | unsigned int nentries_mask = src_ring->nentries_mask; |
| 527 | unsigned int write_index; |
| 528 | unsigned int sw_index; |
| 529 | unsigned int frag_len; |
Vishwajith Upendra | 70f8b6e | 2016-03-01 16:28:23 +0530 | [diff] [blame] | 530 | qdf_nbuf_t msdu; |
Prakash Dhavali | d5c9f1c | 2015-11-08 19:04:44 -0800 | [diff] [blame] | 531 | int i; |
| 532 | uint64_t dma_addr; |
| 533 | uint32_t user_flags = 0; |
| 534 | |
Chouhan, Anurag | fc06aa9 | 2016-03-03 19:05:05 +0530 | [diff] [blame] | 535 | qdf_spin_lock_bh(&ce_state->ce_index_lock); |
Prakash Dhavali | d5c9f1c | 2015-11-08 19:04:44 -0800 | [diff] [blame] | 536 | sw_index = src_ring->sw_index; |
| 537 | write_index = src_ring->write_index; |
| 538 | |
| 539 | /* 2 msdus per packet */ |
| 540 | for (i = 0; i < num_msdus; i++) { |
| 541 | struct CE_src_desc *src_ring_base = |
| 542 | (struct CE_src_desc *)src_ring->base_addr_owner_space; |
| 543 | struct CE_src_desc *shadow_base = |
| 544 | (struct CE_src_desc *)src_ring->shadow_base; |
| 545 | struct CE_src_desc *src_desc = |
| 546 | CE_SRC_RING_TO_DESC(src_ring_base, write_index); |
| 547 | struct CE_src_desc *shadow_src_desc = |
| 548 | CE_SRC_RING_TO_DESC(shadow_base, write_index); |
| 549 | |
Komal Seelam | 644263d | 2016-02-22 20:45:49 +0530 | [diff] [blame] | 550 | hif_pm_runtime_get_noresume(hif_hdl); |
Prakash Dhavali | d5c9f1c | 2015-11-08 19:04:44 -0800 | [diff] [blame] | 551 | msdu = msdus[i]; |
| 552 | |
| 553 | /* |
| 554 | * First fill out the ring descriptor for the HTC HTT frame |
| 555 | * header. These are uncached writes. Should we use a local |
| 556 | * structure instead? |
| 557 | */ |
| 558 | /* HTT/HTC header can be passed as a argument */ |
Vishwajith Upendra | 70f8b6e | 2016-03-01 16:28:23 +0530 | [diff] [blame] | 559 | dma_addr = qdf_nbuf_get_frag_paddr(msdu, 0); |
Prakash Dhavali | d5c9f1c | 2015-11-08 19:04:44 -0800 | [diff] [blame] | 560 | shadow_src_desc->buffer_addr = (uint32_t)(dma_addr & |
| 561 | 0xFFFFFFFF); |
Vishwajith Upendra | 70f8b6e | 2016-03-01 16:28:23 +0530 | [diff] [blame] | 562 | user_flags = qdf_nbuf_data_attr_get(msdu) & DESC_DATA_FLAG_MASK; |
Prakash Dhavali | d5c9f1c | 2015-11-08 19:04:44 -0800 | [diff] [blame] | 563 | ce_buffer_addr_hi_set(shadow_src_desc, dma_addr, user_flags); |
| 564 | |
| 565 | shadow_src_desc->meta_data = transfer_id; |
Vishwajith Upendra | 70f8b6e | 2016-03-01 16:28:23 +0530 | [diff] [blame] | 566 | shadow_src_desc->nbytes = qdf_nbuf_get_frag_len(msdu, 0); |
Prakash Dhavali | d5c9f1c | 2015-11-08 19:04:44 -0800 | [diff] [blame] | 567 | |
| 568 | /* |
| 569 | * HTC HTT header is a word stream, so byte swap if CE byte |
| 570 | * swap enabled |
| 571 | */ |
| 572 | shadow_src_desc->byte_swap = ((ce_state->attr_flags & |
| 573 | CE_ATTR_BYTE_SWAP_DATA) != 0); |
| 574 | /* For the first one, it still does not need to write */ |
| 575 | shadow_src_desc->gather = 1; |
| 576 | *src_desc = *shadow_src_desc; |
| 577 | |
| 578 | /* By default we could initialize the transfer context to this |
| 579 | * value |
| 580 | */ |
| 581 | src_ring->per_transfer_context[write_index] = |
| 582 | CE_SENDLIST_ITEM_CTXT; |
| 583 | |
| 584 | write_index = CE_RING_IDX_INCR(nentries_mask, write_index); |
| 585 | |
| 586 | src_desc = CE_SRC_RING_TO_DESC(src_ring_base, write_index); |
| 587 | shadow_src_desc = CE_SRC_RING_TO_DESC(shadow_base, write_index); |
| 588 | /* |
| 589 | * Now fill out the ring descriptor for the actual data |
| 590 | * packet |
| 591 | */ |
Vishwajith Upendra | 70f8b6e | 2016-03-01 16:28:23 +0530 | [diff] [blame] | 592 | dma_addr = qdf_nbuf_get_frag_paddr(msdu, 1); |
Prakash Dhavali | d5c9f1c | 2015-11-08 19:04:44 -0800 | [diff] [blame] | 593 | shadow_src_desc->buffer_addr = (uint32_t)(dma_addr & |
| 594 | 0xFFFFFFFF); |
| 595 | /* |
| 596 | * Clear packet offset for all but the first CE desc. |
| 597 | */ |
Chouhan, Anurag | fc06aa9 | 2016-03-03 19:05:05 +0530 | [diff] [blame] | 598 | user_flags &= ~QDF_CE_TX_PKT_OFFSET_BIT_M; |
Prakash Dhavali | d5c9f1c | 2015-11-08 19:04:44 -0800 | [diff] [blame] | 599 | ce_buffer_addr_hi_set(shadow_src_desc, dma_addr, user_flags); |
| 600 | shadow_src_desc->meta_data = transfer_id; |
| 601 | |
| 602 | /* get actual packet length */ |
Vishwajith Upendra | 70f8b6e | 2016-03-01 16:28:23 +0530 | [diff] [blame] | 603 | frag_len = qdf_nbuf_get_frag_len(msdu, 1); |
Houston Hoffman | a5e74c1 | 2015-09-02 18:06:28 -0700 | [diff] [blame] | 604 | |
| 605 | /* only read download_len once */ |
| 606 | shadow_src_desc->nbytes = ce_state->download_len; |
| 607 | if (shadow_src_desc->nbytes > frag_len) |
| 608 | shadow_src_desc->nbytes = frag_len; |
Prakash Dhavali | d5c9f1c | 2015-11-08 19:04:44 -0800 | [diff] [blame] | 609 | |
| 610 | /* Data packet is a byte stream, so disable byte swap */ |
| 611 | shadow_src_desc->byte_swap = 0; |
| 612 | /* For the last one, gather is not set */ |
| 613 | shadow_src_desc->gather = 0; |
| 614 | *src_desc = *shadow_src_desc; |
| 615 | src_ring->per_transfer_context[write_index] = msdu; |
| 616 | write_index = CE_RING_IDX_INCR(nentries_mask, write_index); |
| 617 | } |
| 618 | |
| 619 | /* Write the final index to h/w one-shot */ |
| 620 | if (i) { |
| 621 | src_ring->write_index = write_index; |
Houston Hoffman | f460785 | 2015-12-17 17:14:40 -0800 | [diff] [blame] | 622 | |
Komal Seelam | 644263d | 2016-02-22 20:45:49 +0530 | [diff] [blame] | 623 | if (hif_pm_runtime_get(hif_hdl) == 0) { |
Houston Hoffman | f460785 | 2015-12-17 17:14:40 -0800 | [diff] [blame] | 624 | /* Don't call WAR_XXX from here |
| 625 | * Just call XXX instead, that has the reqd. intel |
| 626 | */ |
| 627 | war_ce_src_ring_write_idx_set(scn, ctrl_addr, |
| 628 | write_index); |
Komal Seelam | 644263d | 2016-02-22 20:45:49 +0530 | [diff] [blame] | 629 | hif_pm_runtime_put(hif_hdl); |
Houston Hoffman | f460785 | 2015-12-17 17:14:40 -0800 | [diff] [blame] | 630 | } |
Prakash Dhavali | d5c9f1c | 2015-11-08 19:04:44 -0800 | [diff] [blame] | 631 | } |
| 632 | |
Chouhan, Anurag | fc06aa9 | 2016-03-03 19:05:05 +0530 | [diff] [blame] | 633 | qdf_spin_unlock_bh(&ce_state->ce_index_lock); |
Prakash Dhavali | d5c9f1c | 2015-11-08 19:04:44 -0800 | [diff] [blame] | 634 | |
| 635 | /* |
| 636 | * If all packets in the array are transmitted, |
| 637 | * i = num_msdus |
| 638 | * Temporarily add an ASSERT |
| 639 | */ |
| 640 | ASSERT(i == num_msdus); |
| 641 | return i; |
| 642 | } |
| 643 | #endif /* WLAN_FEATURE_FASTPATH */ |
| 644 | |
Houston Hoffman | 4411ad4 | 2016-03-14 21:12:04 -0700 | [diff] [blame] | 645 | /** |
| 646 | * ce_recv_buf_enqueue() - enqueue a recv buffer into a copy engine |
| 647 | * @coyeng: copy engine handle |
| 648 | * @per_recv_context: virtual address of the nbuf |
| 649 | * @buffer: physical address of the nbuf |
| 650 | * |
| 651 | * Return: 0 if the buffer is enqueued |
| 652 | */ |
Prakash Dhavali | d5c9f1c | 2015-11-08 19:04:44 -0800 | [diff] [blame] | 653 | int |
| 654 | ce_recv_buf_enqueue(struct CE_handle *copyeng, |
Chouhan, Anurag | fc06aa9 | 2016-03-03 19:05:05 +0530 | [diff] [blame] | 655 | void *per_recv_context, qdf_dma_addr_t buffer) |
Prakash Dhavali | d5c9f1c | 2015-11-08 19:04:44 -0800 | [diff] [blame] | 656 | { |
| 657 | int status; |
| 658 | struct CE_state *CE_state = (struct CE_state *)copyeng; |
| 659 | struct CE_ring_state *dest_ring = CE_state->dest_ring; |
| 660 | uint32_t ctrl_addr = CE_state->ctrl_addr; |
| 661 | unsigned int nentries_mask = dest_ring->nentries_mask; |
| 662 | unsigned int write_index; |
| 663 | unsigned int sw_index; |
Prakash Dhavali | d5c9f1c | 2015-11-08 19:04:44 -0800 | [diff] [blame] | 664 | uint64_t dma_addr = buffer; |
Komal Seelam | 644263d | 2016-02-22 20:45:49 +0530 | [diff] [blame] | 665 | struct hif_softc *scn = CE_state->scn; |
Prakash Dhavali | d5c9f1c | 2015-11-08 19:04:44 -0800 | [diff] [blame] | 666 | |
Chouhan, Anurag | fc06aa9 | 2016-03-03 19:05:05 +0530 | [diff] [blame] | 667 | qdf_spin_lock_bh(&CE_state->ce_index_lock); |
Prakash Dhavali | d5c9f1c | 2015-11-08 19:04:44 -0800 | [diff] [blame] | 668 | write_index = dest_ring->write_index; |
| 669 | sw_index = dest_ring->sw_index; |
| 670 | |
Houston Hoffman | 4411ad4 | 2016-03-14 21:12:04 -0700 | [diff] [blame] | 671 | if (Q_TARGET_ACCESS_BEGIN(scn) < 0) { |
Chouhan, Anurag | fc06aa9 | 2016-03-03 19:05:05 +0530 | [diff] [blame] | 672 | qdf_spin_unlock_bh(&CE_state->ce_index_lock); |
Houston Hoffman | 4411ad4 | 2016-03-14 21:12:04 -0700 | [diff] [blame] | 673 | return -EIO; |
Prakash Dhavali | d5c9f1c | 2015-11-08 19:04:44 -0800 | [diff] [blame] | 674 | } |
| 675 | |
| 676 | if (CE_RING_DELTA(nentries_mask, write_index, sw_index - 1) > 0) { |
| 677 | struct CE_dest_desc *dest_ring_base = |
| 678 | (struct CE_dest_desc *)dest_ring-> |
| 679 | base_addr_owner_space; |
| 680 | struct CE_dest_desc *dest_desc = |
| 681 | CE_DEST_RING_TO_DESC(dest_ring_base, write_index); |
| 682 | |
| 683 | /* Update low 32 bit destination descriptor */ |
| 684 | dest_desc->buffer_addr = (uint32_t)(dma_addr & 0xFFFFFFFF); |
| 685 | #ifdef QCA_WIFI_3_0 |
| 686 | dest_desc->buffer_addr_hi = |
| 687 | (uint32_t)((dma_addr >> 32) & 0x1F); |
| 688 | #endif |
| 689 | dest_desc->nbytes = 0; |
| 690 | |
| 691 | dest_ring->per_transfer_context[write_index] = |
| 692 | per_recv_context; |
| 693 | |
Komal Seelam | bd7c51d | 2016-02-24 10:27:30 +0530 | [diff] [blame] | 694 | hif_record_ce_desc_event(scn, CE_state->id, HIF_RX_DESC_POST, |
Houston Hoffman | 68e837e | 2015-12-04 12:57:24 -0800 | [diff] [blame] | 695 | (union ce_desc *) dest_desc, per_recv_context, |
| 696 | write_index); |
| 697 | |
Prakash Dhavali | d5c9f1c | 2015-11-08 19:04:44 -0800 | [diff] [blame] | 698 | /* Update Destination Ring Write Index */ |
| 699 | write_index = CE_RING_IDX_INCR(nentries_mask, write_index); |
| 700 | CE_DEST_RING_WRITE_IDX_SET(scn, ctrl_addr, write_index); |
| 701 | dest_ring->write_index = write_index; |
Chouhan, Anurag | fc06aa9 | 2016-03-03 19:05:05 +0530 | [diff] [blame] | 702 | status = QDF_STATUS_SUCCESS; |
Prakash Dhavali | d5c9f1c | 2015-11-08 19:04:44 -0800 | [diff] [blame] | 703 | } else { |
Chouhan, Anurag | fc06aa9 | 2016-03-03 19:05:05 +0530 | [diff] [blame] | 704 | status = QDF_STATUS_E_FAILURE; |
Prakash Dhavali | d5c9f1c | 2015-11-08 19:04:44 -0800 | [diff] [blame] | 705 | } |
Houston Hoffman | 4411ad4 | 2016-03-14 21:12:04 -0700 | [diff] [blame] | 706 | Q_TARGET_ACCESS_END(scn); |
Chouhan, Anurag | fc06aa9 | 2016-03-03 19:05:05 +0530 | [diff] [blame] | 707 | qdf_spin_unlock_bh(&CE_state->ce_index_lock); |
Prakash Dhavali | d5c9f1c | 2015-11-08 19:04:44 -0800 | [diff] [blame] | 708 | return status; |
| 709 | } |
| 710 | |
| 711 | void |
| 712 | ce_send_watermarks_set(struct CE_handle *copyeng, |
| 713 | unsigned int low_alert_nentries, |
| 714 | unsigned int high_alert_nentries) |
| 715 | { |
| 716 | struct CE_state *CE_state = (struct CE_state *)copyeng; |
| 717 | uint32_t ctrl_addr = CE_state->ctrl_addr; |
Komal Seelam | 644263d | 2016-02-22 20:45:49 +0530 | [diff] [blame] | 718 | struct hif_softc *scn = CE_state->scn; |
Prakash Dhavali | d5c9f1c | 2015-11-08 19:04:44 -0800 | [diff] [blame] | 719 | |
Prakash Dhavali | d5c9f1c | 2015-11-08 19:04:44 -0800 | [diff] [blame] | 720 | CE_SRC_RING_LOWMARK_SET(scn, ctrl_addr, low_alert_nentries); |
| 721 | CE_SRC_RING_HIGHMARK_SET(scn, ctrl_addr, high_alert_nentries); |
Prakash Dhavali | d5c9f1c | 2015-11-08 19:04:44 -0800 | [diff] [blame] | 722 | } |
| 723 | |
| 724 | void |
| 725 | ce_recv_watermarks_set(struct CE_handle *copyeng, |
| 726 | unsigned int low_alert_nentries, |
| 727 | unsigned int high_alert_nentries) |
| 728 | { |
| 729 | struct CE_state *CE_state = (struct CE_state *)copyeng; |
| 730 | uint32_t ctrl_addr = CE_state->ctrl_addr; |
Komal Seelam | 644263d | 2016-02-22 20:45:49 +0530 | [diff] [blame] | 731 | struct hif_softc *scn = CE_state->scn; |
Prakash Dhavali | d5c9f1c | 2015-11-08 19:04:44 -0800 | [diff] [blame] | 732 | |
Prakash Dhavali | d5c9f1c | 2015-11-08 19:04:44 -0800 | [diff] [blame] | 733 | CE_DEST_RING_LOWMARK_SET(scn, ctrl_addr, |
| 734 | low_alert_nentries); |
| 735 | CE_DEST_RING_HIGHMARK_SET(scn, ctrl_addr, |
| 736 | high_alert_nentries); |
Prakash Dhavali | d5c9f1c | 2015-11-08 19:04:44 -0800 | [diff] [blame] | 737 | } |
| 738 | |
| 739 | unsigned int ce_send_entries_avail(struct CE_handle *copyeng) |
| 740 | { |
| 741 | struct CE_state *CE_state = (struct CE_state *)copyeng; |
| 742 | struct CE_ring_state *src_ring = CE_state->src_ring; |
| 743 | unsigned int nentries_mask = src_ring->nentries_mask; |
| 744 | unsigned int sw_index; |
| 745 | unsigned int write_index; |
| 746 | |
Chouhan, Anurag | fc06aa9 | 2016-03-03 19:05:05 +0530 | [diff] [blame] | 747 | qdf_spin_lock(&CE_state->ce_index_lock); |
Prakash Dhavali | d5c9f1c | 2015-11-08 19:04:44 -0800 | [diff] [blame] | 748 | sw_index = src_ring->sw_index; |
| 749 | write_index = src_ring->write_index; |
Chouhan, Anurag | fc06aa9 | 2016-03-03 19:05:05 +0530 | [diff] [blame] | 750 | qdf_spin_unlock(&CE_state->ce_index_lock); |
Prakash Dhavali | d5c9f1c | 2015-11-08 19:04:44 -0800 | [diff] [blame] | 751 | |
| 752 | return CE_RING_DELTA(nentries_mask, write_index, sw_index - 1); |
| 753 | } |
| 754 | |
| 755 | unsigned int ce_recv_entries_avail(struct CE_handle *copyeng) |
| 756 | { |
| 757 | struct CE_state *CE_state = (struct CE_state *)copyeng; |
| 758 | struct CE_ring_state *dest_ring = CE_state->dest_ring; |
| 759 | unsigned int nentries_mask = dest_ring->nentries_mask; |
| 760 | unsigned int sw_index; |
| 761 | unsigned int write_index; |
| 762 | |
Chouhan, Anurag | fc06aa9 | 2016-03-03 19:05:05 +0530 | [diff] [blame] | 763 | qdf_spin_lock(&CE_state->ce_index_lock); |
Prakash Dhavali | d5c9f1c | 2015-11-08 19:04:44 -0800 | [diff] [blame] | 764 | sw_index = dest_ring->sw_index; |
| 765 | write_index = dest_ring->write_index; |
Chouhan, Anurag | fc06aa9 | 2016-03-03 19:05:05 +0530 | [diff] [blame] | 766 | qdf_spin_unlock(&CE_state->ce_index_lock); |
Prakash Dhavali | d5c9f1c | 2015-11-08 19:04:44 -0800 | [diff] [blame] | 767 | |
| 768 | return CE_RING_DELTA(nentries_mask, write_index, sw_index - 1); |
| 769 | } |
| 770 | |
| 771 | /* |
| 772 | * Guts of ce_send_entries_done. |
| 773 | * The caller takes responsibility for any necessary locking. |
| 774 | */ |
| 775 | unsigned int |
Komal Seelam | 644263d | 2016-02-22 20:45:49 +0530 | [diff] [blame] | 776 | ce_send_entries_done_nolock(struct hif_softc *scn, |
Prakash Dhavali | d5c9f1c | 2015-11-08 19:04:44 -0800 | [diff] [blame] | 777 | struct CE_state *CE_state) |
| 778 | { |
| 779 | struct CE_ring_state *src_ring = CE_state->src_ring; |
| 780 | uint32_t ctrl_addr = CE_state->ctrl_addr; |
| 781 | unsigned int nentries_mask = src_ring->nentries_mask; |
| 782 | unsigned int sw_index; |
| 783 | unsigned int read_index; |
| 784 | |
| 785 | sw_index = src_ring->sw_index; |
| 786 | read_index = CE_SRC_RING_READ_IDX_GET(scn, ctrl_addr); |
| 787 | |
| 788 | return CE_RING_DELTA(nentries_mask, sw_index, read_index); |
| 789 | } |
| 790 | |
| 791 | unsigned int ce_send_entries_done(struct CE_handle *copyeng) |
| 792 | { |
| 793 | struct CE_state *CE_state = (struct CE_state *)copyeng; |
| 794 | unsigned int nentries; |
| 795 | |
Chouhan, Anurag | fc06aa9 | 2016-03-03 19:05:05 +0530 | [diff] [blame] | 796 | qdf_spin_lock(&CE_state->ce_index_lock); |
Prakash Dhavali | d5c9f1c | 2015-11-08 19:04:44 -0800 | [diff] [blame] | 797 | nentries = ce_send_entries_done_nolock(CE_state->scn, CE_state); |
Chouhan, Anurag | fc06aa9 | 2016-03-03 19:05:05 +0530 | [diff] [blame] | 798 | qdf_spin_unlock(&CE_state->ce_index_lock); |
Prakash Dhavali | d5c9f1c | 2015-11-08 19:04:44 -0800 | [diff] [blame] | 799 | |
| 800 | return nentries; |
| 801 | } |
| 802 | |
| 803 | /* |
| 804 | * Guts of ce_recv_entries_done. |
| 805 | * The caller takes responsibility for any necessary locking. |
| 806 | */ |
| 807 | unsigned int |
Komal Seelam | 644263d | 2016-02-22 20:45:49 +0530 | [diff] [blame] | 808 | ce_recv_entries_done_nolock(struct hif_softc *scn, |
Prakash Dhavali | d5c9f1c | 2015-11-08 19:04:44 -0800 | [diff] [blame] | 809 | struct CE_state *CE_state) |
| 810 | { |
| 811 | struct CE_ring_state *dest_ring = CE_state->dest_ring; |
| 812 | uint32_t ctrl_addr = CE_state->ctrl_addr; |
| 813 | unsigned int nentries_mask = dest_ring->nentries_mask; |
| 814 | unsigned int sw_index; |
| 815 | unsigned int read_index; |
| 816 | |
| 817 | sw_index = dest_ring->sw_index; |
| 818 | read_index = CE_DEST_RING_READ_IDX_GET(scn, ctrl_addr); |
| 819 | |
| 820 | return CE_RING_DELTA(nentries_mask, sw_index, read_index); |
| 821 | } |
| 822 | |
| 823 | unsigned int ce_recv_entries_done(struct CE_handle *copyeng) |
| 824 | { |
| 825 | struct CE_state *CE_state = (struct CE_state *)copyeng; |
| 826 | unsigned int nentries; |
| 827 | |
Chouhan, Anurag | fc06aa9 | 2016-03-03 19:05:05 +0530 | [diff] [blame] | 828 | qdf_spin_lock(&CE_state->ce_index_lock); |
Prakash Dhavali | d5c9f1c | 2015-11-08 19:04:44 -0800 | [diff] [blame] | 829 | nentries = ce_recv_entries_done_nolock(CE_state->scn, CE_state); |
Chouhan, Anurag | fc06aa9 | 2016-03-03 19:05:05 +0530 | [diff] [blame] | 830 | qdf_spin_unlock(&CE_state->ce_index_lock); |
Prakash Dhavali | d5c9f1c | 2015-11-08 19:04:44 -0800 | [diff] [blame] | 831 | |
| 832 | return nentries; |
| 833 | } |
| 834 | |
| 835 | /* Debug support */ |
| 836 | void *ce_debug_cmplrn_context; /* completed recv next context */ |
| 837 | void *ce_debug_cnclsn_context; /* cancel send next context */ |
| 838 | void *ce_debug_rvkrn_context; /* revoke receive next context */ |
| 839 | void *ce_debug_cmplsn_context; /* completed send next context */ |
| 840 | |
| 841 | /* |
| 842 | * Guts of ce_completed_recv_next. |
| 843 | * The caller takes responsibility for any necessary locking. |
| 844 | */ |
| 845 | int |
| 846 | ce_completed_recv_next_nolock(struct CE_state *CE_state, |
| 847 | void **per_CE_contextp, |
| 848 | void **per_transfer_contextp, |
Chouhan, Anurag | fc06aa9 | 2016-03-03 19:05:05 +0530 | [diff] [blame] | 849 | qdf_dma_addr_t *bufferp, |
Prakash Dhavali | d5c9f1c | 2015-11-08 19:04:44 -0800 | [diff] [blame] | 850 | unsigned int *nbytesp, |
| 851 | unsigned int *transfer_idp, |
| 852 | unsigned int *flagsp) |
| 853 | { |
| 854 | int status; |
| 855 | struct CE_ring_state *dest_ring = CE_state->dest_ring; |
| 856 | unsigned int nentries_mask = dest_ring->nentries_mask; |
| 857 | unsigned int sw_index = dest_ring->sw_index; |
Komal Seelam | bd7c51d | 2016-02-24 10:27:30 +0530 | [diff] [blame] | 858 | struct hif_softc *scn = CE_state->scn; |
Prakash Dhavali | d5c9f1c | 2015-11-08 19:04:44 -0800 | [diff] [blame] | 859 | struct CE_dest_desc *dest_ring_base = |
| 860 | (struct CE_dest_desc *)dest_ring->base_addr_owner_space; |
| 861 | struct CE_dest_desc *dest_desc = |
| 862 | CE_DEST_RING_TO_DESC(dest_ring_base, sw_index); |
| 863 | int nbytes; |
| 864 | struct CE_dest_desc dest_desc_info; |
| 865 | /* |
| 866 | * By copying the dest_desc_info element to local memory, we could |
| 867 | * avoid extra memory read from non-cachable memory. |
| 868 | */ |
| 869 | dest_desc_info = *dest_desc; |
| 870 | nbytes = dest_desc_info.nbytes; |
| 871 | if (nbytes == 0) { |
| 872 | /* |
| 873 | * This closes a relatively unusual race where the Host |
| 874 | * sees the updated DRRI before the update to the |
| 875 | * corresponding descriptor has completed. We treat this |
| 876 | * as a descriptor that is not yet done. |
| 877 | */ |
Chouhan, Anurag | fc06aa9 | 2016-03-03 19:05:05 +0530 | [diff] [blame] | 878 | status = QDF_STATUS_E_FAILURE; |
Prakash Dhavali | d5c9f1c | 2015-11-08 19:04:44 -0800 | [diff] [blame] | 879 | goto done; |
| 880 | } |
| 881 | |
Komal Seelam | bd7c51d | 2016-02-24 10:27:30 +0530 | [diff] [blame] | 882 | hif_record_ce_desc_event(scn, CE_state->id, HIF_RX_DESC_COMPLETION, |
Houston Hoffman | 68e837e | 2015-12-04 12:57:24 -0800 | [diff] [blame] | 883 | (union ce_desc *) dest_desc, |
| 884 | dest_ring->per_transfer_context[sw_index], |
| 885 | sw_index); |
| 886 | |
Prakash Dhavali | d5c9f1c | 2015-11-08 19:04:44 -0800 | [diff] [blame] | 887 | dest_desc->nbytes = 0; |
| 888 | |
| 889 | /* Return data from completed destination descriptor */ |
| 890 | *bufferp = HIF_CE_DESC_ADDR_TO_DMA(&dest_desc_info); |
| 891 | *nbytesp = nbytes; |
| 892 | *transfer_idp = dest_desc_info.meta_data; |
| 893 | *flagsp = (dest_desc_info.byte_swap) ? CE_RECV_FLAG_SWAPPED : 0; |
| 894 | |
| 895 | if (per_CE_contextp) { |
| 896 | *per_CE_contextp = CE_state->recv_context; |
| 897 | } |
| 898 | |
| 899 | ce_debug_cmplrn_context = dest_ring->per_transfer_context[sw_index]; |
| 900 | if (per_transfer_contextp) { |
| 901 | *per_transfer_contextp = ce_debug_cmplrn_context; |
| 902 | } |
| 903 | dest_ring->per_transfer_context[sw_index] = 0; /* sanity */ |
| 904 | |
| 905 | /* Update sw_index */ |
| 906 | sw_index = CE_RING_IDX_INCR(nentries_mask, sw_index); |
| 907 | dest_ring->sw_index = sw_index; |
Chouhan, Anurag | fc06aa9 | 2016-03-03 19:05:05 +0530 | [diff] [blame] | 908 | status = QDF_STATUS_SUCCESS; |
Prakash Dhavali | d5c9f1c | 2015-11-08 19:04:44 -0800 | [diff] [blame] | 909 | |
| 910 | done: |
| 911 | return status; |
| 912 | } |
| 913 | |
| 914 | int |
| 915 | ce_completed_recv_next(struct CE_handle *copyeng, |
| 916 | void **per_CE_contextp, |
| 917 | void **per_transfer_contextp, |
Chouhan, Anurag | fc06aa9 | 2016-03-03 19:05:05 +0530 | [diff] [blame] | 918 | qdf_dma_addr_t *bufferp, |
Prakash Dhavali | d5c9f1c | 2015-11-08 19:04:44 -0800 | [diff] [blame] | 919 | unsigned int *nbytesp, |
| 920 | unsigned int *transfer_idp, unsigned int *flagsp) |
| 921 | { |
| 922 | struct CE_state *CE_state = (struct CE_state *)copyeng; |
| 923 | int status; |
| 924 | |
Chouhan, Anurag | fc06aa9 | 2016-03-03 19:05:05 +0530 | [diff] [blame] | 925 | qdf_spin_lock_bh(&CE_state->ce_index_lock); |
Prakash Dhavali | d5c9f1c | 2015-11-08 19:04:44 -0800 | [diff] [blame] | 926 | status = |
| 927 | ce_completed_recv_next_nolock(CE_state, per_CE_contextp, |
| 928 | per_transfer_contextp, bufferp, |
| 929 | nbytesp, transfer_idp, flagsp); |
Chouhan, Anurag | fc06aa9 | 2016-03-03 19:05:05 +0530 | [diff] [blame] | 930 | qdf_spin_unlock_bh(&CE_state->ce_index_lock); |
Prakash Dhavali | d5c9f1c | 2015-11-08 19:04:44 -0800 | [diff] [blame] | 931 | |
| 932 | return status; |
| 933 | } |
| 934 | |
| 935 | /* NB: Modeled after ce_completed_recv_next_nolock */ |
Chouhan, Anurag | fc06aa9 | 2016-03-03 19:05:05 +0530 | [diff] [blame] | 936 | QDF_STATUS |
Prakash Dhavali | d5c9f1c | 2015-11-08 19:04:44 -0800 | [diff] [blame] | 937 | ce_revoke_recv_next(struct CE_handle *copyeng, |
| 938 | void **per_CE_contextp, |
Chouhan, Anurag | fc06aa9 | 2016-03-03 19:05:05 +0530 | [diff] [blame] | 939 | void **per_transfer_contextp, qdf_dma_addr_t *bufferp) |
Prakash Dhavali | d5c9f1c | 2015-11-08 19:04:44 -0800 | [diff] [blame] | 940 | { |
| 941 | struct CE_state *CE_state; |
| 942 | struct CE_ring_state *dest_ring; |
| 943 | unsigned int nentries_mask; |
| 944 | unsigned int sw_index; |
| 945 | unsigned int write_index; |
Chouhan, Anurag | fc06aa9 | 2016-03-03 19:05:05 +0530 | [diff] [blame] | 946 | QDF_STATUS status; |
Komal Seelam | 644263d | 2016-02-22 20:45:49 +0530 | [diff] [blame] | 947 | struct hif_softc *scn; |
Prakash Dhavali | d5c9f1c | 2015-11-08 19:04:44 -0800 | [diff] [blame] | 948 | |
| 949 | CE_state = (struct CE_state *)copyeng; |
| 950 | dest_ring = CE_state->dest_ring; |
| 951 | if (!dest_ring) { |
Chouhan, Anurag | fc06aa9 | 2016-03-03 19:05:05 +0530 | [diff] [blame] | 952 | return QDF_STATUS_E_FAILURE; |
Prakash Dhavali | d5c9f1c | 2015-11-08 19:04:44 -0800 | [diff] [blame] | 953 | } |
| 954 | |
| 955 | scn = CE_state->scn; |
Chouhan, Anurag | fc06aa9 | 2016-03-03 19:05:05 +0530 | [diff] [blame] | 956 | qdf_spin_lock(&CE_state->ce_index_lock); |
Prakash Dhavali | d5c9f1c | 2015-11-08 19:04:44 -0800 | [diff] [blame] | 957 | nentries_mask = dest_ring->nentries_mask; |
| 958 | sw_index = dest_ring->sw_index; |
| 959 | write_index = dest_ring->write_index; |
| 960 | if (write_index != sw_index) { |
| 961 | struct CE_dest_desc *dest_ring_base = |
| 962 | (struct CE_dest_desc *)dest_ring-> |
| 963 | base_addr_owner_space; |
| 964 | struct CE_dest_desc *dest_desc = |
| 965 | CE_DEST_RING_TO_DESC(dest_ring_base, sw_index); |
| 966 | |
| 967 | /* Return data from completed destination descriptor */ |
| 968 | *bufferp = HIF_CE_DESC_ADDR_TO_DMA(dest_desc); |
| 969 | |
| 970 | if (per_CE_contextp) { |
| 971 | *per_CE_contextp = CE_state->recv_context; |
| 972 | } |
| 973 | |
| 974 | ce_debug_rvkrn_context = |
| 975 | dest_ring->per_transfer_context[sw_index]; |
| 976 | if (per_transfer_contextp) { |
| 977 | *per_transfer_contextp = ce_debug_rvkrn_context; |
| 978 | } |
| 979 | dest_ring->per_transfer_context[sw_index] = 0; /* sanity */ |
| 980 | |
| 981 | /* Update sw_index */ |
| 982 | sw_index = CE_RING_IDX_INCR(nentries_mask, sw_index); |
| 983 | dest_ring->sw_index = sw_index; |
Chouhan, Anurag | fc06aa9 | 2016-03-03 19:05:05 +0530 | [diff] [blame] | 984 | status = QDF_STATUS_SUCCESS; |
Prakash Dhavali | d5c9f1c | 2015-11-08 19:04:44 -0800 | [diff] [blame] | 985 | } else { |
Chouhan, Anurag | fc06aa9 | 2016-03-03 19:05:05 +0530 | [diff] [blame] | 986 | status = QDF_STATUS_E_FAILURE; |
Prakash Dhavali | d5c9f1c | 2015-11-08 19:04:44 -0800 | [diff] [blame] | 987 | } |
Chouhan, Anurag | fc06aa9 | 2016-03-03 19:05:05 +0530 | [diff] [blame] | 988 | qdf_spin_unlock(&CE_state->ce_index_lock); |
Prakash Dhavali | d5c9f1c | 2015-11-08 19:04:44 -0800 | [diff] [blame] | 989 | |
| 990 | return status; |
| 991 | } |
| 992 | |
| 993 | /* |
| 994 | * Guts of ce_completed_send_next. |
| 995 | * The caller takes responsibility for any necessary locking. |
| 996 | */ |
| 997 | int |
| 998 | ce_completed_send_next_nolock(struct CE_state *CE_state, |
| 999 | void **per_CE_contextp, |
| 1000 | void **per_transfer_contextp, |
Chouhan, Anurag | fc06aa9 | 2016-03-03 19:05:05 +0530 | [diff] [blame] | 1001 | qdf_dma_addr_t *bufferp, |
Prakash Dhavali | d5c9f1c | 2015-11-08 19:04:44 -0800 | [diff] [blame] | 1002 | unsigned int *nbytesp, |
| 1003 | unsigned int *transfer_idp, |
| 1004 | unsigned int *sw_idx, |
| 1005 | unsigned int *hw_idx, |
| 1006 | uint32_t *toeplitz_hash_result) |
| 1007 | { |
Chouhan, Anurag | fc06aa9 | 2016-03-03 19:05:05 +0530 | [diff] [blame] | 1008 | int status = QDF_STATUS_E_FAILURE; |
Prakash Dhavali | d5c9f1c | 2015-11-08 19:04:44 -0800 | [diff] [blame] | 1009 | struct CE_ring_state *src_ring = CE_state->src_ring; |
| 1010 | uint32_t ctrl_addr = CE_state->ctrl_addr; |
| 1011 | unsigned int nentries_mask = src_ring->nentries_mask; |
| 1012 | unsigned int sw_index = src_ring->sw_index; |
| 1013 | unsigned int read_index; |
Komal Seelam | 644263d | 2016-02-22 20:45:49 +0530 | [diff] [blame] | 1014 | struct hif_softc *scn = CE_state->scn; |
Prakash Dhavali | d5c9f1c | 2015-11-08 19:04:44 -0800 | [diff] [blame] | 1015 | |
| 1016 | if (src_ring->hw_index == sw_index) { |
| 1017 | /* |
| 1018 | * The SW completion index has caught up with the cached |
| 1019 | * version of the HW completion index. |
| 1020 | * Update the cached HW completion index to see whether |
| 1021 | * the SW has really caught up to the HW, or if the cached |
| 1022 | * value of the HW index has become stale. |
| 1023 | */ |
Houston Hoffman | 2c32cf6 | 2016-03-14 21:12:00 -0700 | [diff] [blame] | 1024 | if (Q_TARGET_ACCESS_BEGIN(scn) < 0) |
Houston Hoffman | 987ab44 | 2016-03-14 21:12:02 -0700 | [diff] [blame] | 1025 | return QDF_STATUS_E_FAILURE; |
Prakash Dhavali | d5c9f1c | 2015-11-08 19:04:44 -0800 | [diff] [blame] | 1026 | src_ring->hw_index = |
Houston Hoffman | 3d0cda8 | 2015-12-03 13:25:05 -0800 | [diff] [blame] | 1027 | CE_SRC_RING_READ_IDX_GET_FROM_DDR(scn, ctrl_addr); |
Houston Hoffman | 2c32cf6 | 2016-03-14 21:12:00 -0700 | [diff] [blame] | 1028 | if (Q_TARGET_ACCESS_END(scn) < 0) |
Houston Hoffman | 987ab44 | 2016-03-14 21:12:02 -0700 | [diff] [blame] | 1029 | return QDF_STATUS_E_FAILURE; |
Prakash Dhavali | d5c9f1c | 2015-11-08 19:04:44 -0800 | [diff] [blame] | 1030 | } |
| 1031 | read_index = src_ring->hw_index; |
| 1032 | |
| 1033 | if (sw_idx) |
| 1034 | *sw_idx = sw_index; |
| 1035 | |
| 1036 | if (hw_idx) |
| 1037 | *hw_idx = read_index; |
| 1038 | |
| 1039 | if ((read_index != sw_index) && (read_index != 0xffffffff)) { |
| 1040 | struct CE_src_desc *shadow_base = |
| 1041 | (struct CE_src_desc *)src_ring->shadow_base; |
| 1042 | struct CE_src_desc *shadow_src_desc = |
| 1043 | CE_SRC_RING_TO_DESC(shadow_base, sw_index); |
| 1044 | #ifdef QCA_WIFI_3_0 |
| 1045 | struct CE_src_desc *src_ring_base = |
| 1046 | (struct CE_src_desc *)src_ring->base_addr_owner_space; |
| 1047 | struct CE_src_desc *src_desc = |
| 1048 | CE_SRC_RING_TO_DESC(src_ring_base, sw_index); |
| 1049 | #endif |
Komal Seelam | bd7c51d | 2016-02-24 10:27:30 +0530 | [diff] [blame] | 1050 | hif_record_ce_desc_event(scn, CE_state->id, |
| 1051 | HIF_TX_DESC_COMPLETION, |
Houston Hoffman | 68e837e | 2015-12-04 12:57:24 -0800 | [diff] [blame] | 1052 | (union ce_desc *) shadow_src_desc, |
| 1053 | src_ring->per_transfer_context[sw_index], |
| 1054 | sw_index); |
| 1055 | |
Prakash Dhavali | d5c9f1c | 2015-11-08 19:04:44 -0800 | [diff] [blame] | 1056 | /* Return data from completed source descriptor */ |
| 1057 | *bufferp = HIF_CE_DESC_ADDR_TO_DMA(shadow_src_desc); |
| 1058 | *nbytesp = shadow_src_desc->nbytes; |
| 1059 | *transfer_idp = shadow_src_desc->meta_data; |
| 1060 | #ifdef QCA_WIFI_3_0 |
| 1061 | *toeplitz_hash_result = src_desc->toeplitz_hash_result; |
| 1062 | #else |
| 1063 | *toeplitz_hash_result = 0; |
| 1064 | #endif |
| 1065 | if (per_CE_contextp) { |
| 1066 | *per_CE_contextp = CE_state->send_context; |
| 1067 | } |
| 1068 | |
| 1069 | ce_debug_cmplsn_context = |
| 1070 | src_ring->per_transfer_context[sw_index]; |
| 1071 | if (per_transfer_contextp) { |
| 1072 | *per_transfer_contextp = ce_debug_cmplsn_context; |
| 1073 | } |
| 1074 | src_ring->per_transfer_context[sw_index] = 0; /* sanity */ |
| 1075 | |
| 1076 | /* Update sw_index */ |
| 1077 | sw_index = CE_RING_IDX_INCR(nentries_mask, sw_index); |
| 1078 | src_ring->sw_index = sw_index; |
Chouhan, Anurag | fc06aa9 | 2016-03-03 19:05:05 +0530 | [diff] [blame] | 1079 | status = QDF_STATUS_SUCCESS; |
Prakash Dhavali | d5c9f1c | 2015-11-08 19:04:44 -0800 | [diff] [blame] | 1080 | } |
| 1081 | |
| 1082 | return status; |
| 1083 | } |
| 1084 | |
| 1085 | /* NB: Modeled after ce_completed_send_next */ |
Chouhan, Anurag | fc06aa9 | 2016-03-03 19:05:05 +0530 | [diff] [blame] | 1086 | QDF_STATUS |
Prakash Dhavali | d5c9f1c | 2015-11-08 19:04:44 -0800 | [diff] [blame] | 1087 | ce_cancel_send_next(struct CE_handle *copyeng, |
| 1088 | void **per_CE_contextp, |
| 1089 | void **per_transfer_contextp, |
Chouhan, Anurag | fc06aa9 | 2016-03-03 19:05:05 +0530 | [diff] [blame] | 1090 | qdf_dma_addr_t *bufferp, |
Prakash Dhavali | d5c9f1c | 2015-11-08 19:04:44 -0800 | [diff] [blame] | 1091 | unsigned int *nbytesp, |
| 1092 | unsigned int *transfer_idp, |
| 1093 | uint32_t *toeplitz_hash_result) |
| 1094 | { |
| 1095 | struct CE_state *CE_state; |
| 1096 | struct CE_ring_state *src_ring; |
| 1097 | unsigned int nentries_mask; |
| 1098 | unsigned int sw_index; |
| 1099 | unsigned int write_index; |
Chouhan, Anurag | fc06aa9 | 2016-03-03 19:05:05 +0530 | [diff] [blame] | 1100 | QDF_STATUS status; |
Komal Seelam | 644263d | 2016-02-22 20:45:49 +0530 | [diff] [blame] | 1101 | struct hif_softc *scn; |
Prakash Dhavali | d5c9f1c | 2015-11-08 19:04:44 -0800 | [diff] [blame] | 1102 | |
| 1103 | CE_state = (struct CE_state *)copyeng; |
| 1104 | src_ring = CE_state->src_ring; |
| 1105 | if (!src_ring) { |
Chouhan, Anurag | fc06aa9 | 2016-03-03 19:05:05 +0530 | [diff] [blame] | 1106 | return QDF_STATUS_E_FAILURE; |
Prakash Dhavali | d5c9f1c | 2015-11-08 19:04:44 -0800 | [diff] [blame] | 1107 | } |
| 1108 | |
| 1109 | scn = CE_state->scn; |
Chouhan, Anurag | fc06aa9 | 2016-03-03 19:05:05 +0530 | [diff] [blame] | 1110 | qdf_spin_lock(&CE_state->ce_index_lock); |
Prakash Dhavali | d5c9f1c | 2015-11-08 19:04:44 -0800 | [diff] [blame] | 1111 | nentries_mask = src_ring->nentries_mask; |
| 1112 | sw_index = src_ring->sw_index; |
| 1113 | write_index = src_ring->write_index; |
| 1114 | |
| 1115 | if (write_index != sw_index) { |
| 1116 | struct CE_src_desc *src_ring_base = |
| 1117 | (struct CE_src_desc *)src_ring->base_addr_owner_space; |
| 1118 | struct CE_src_desc *src_desc = |
| 1119 | CE_SRC_RING_TO_DESC(src_ring_base, sw_index); |
| 1120 | |
| 1121 | /* Return data from completed source descriptor */ |
| 1122 | *bufferp = HIF_CE_DESC_ADDR_TO_DMA(src_desc); |
| 1123 | *nbytesp = src_desc->nbytes; |
| 1124 | *transfer_idp = src_desc->meta_data; |
| 1125 | #ifdef QCA_WIFI_3_0 |
| 1126 | *toeplitz_hash_result = src_desc->toeplitz_hash_result; |
| 1127 | #else |
| 1128 | *toeplitz_hash_result = 0; |
| 1129 | #endif |
| 1130 | |
| 1131 | if (per_CE_contextp) { |
| 1132 | *per_CE_contextp = CE_state->send_context; |
| 1133 | } |
| 1134 | |
| 1135 | ce_debug_cnclsn_context = |
| 1136 | src_ring->per_transfer_context[sw_index]; |
| 1137 | if (per_transfer_contextp) { |
| 1138 | *per_transfer_contextp = ce_debug_cnclsn_context; |
| 1139 | } |
| 1140 | src_ring->per_transfer_context[sw_index] = 0; /* sanity */ |
| 1141 | |
| 1142 | /* Update sw_index */ |
| 1143 | sw_index = CE_RING_IDX_INCR(nentries_mask, sw_index); |
| 1144 | src_ring->sw_index = sw_index; |
Chouhan, Anurag | fc06aa9 | 2016-03-03 19:05:05 +0530 | [diff] [blame] | 1145 | status = QDF_STATUS_SUCCESS; |
Prakash Dhavali | d5c9f1c | 2015-11-08 19:04:44 -0800 | [diff] [blame] | 1146 | } else { |
Chouhan, Anurag | fc06aa9 | 2016-03-03 19:05:05 +0530 | [diff] [blame] | 1147 | status = QDF_STATUS_E_FAILURE; |
Prakash Dhavali | d5c9f1c | 2015-11-08 19:04:44 -0800 | [diff] [blame] | 1148 | } |
Chouhan, Anurag | fc06aa9 | 2016-03-03 19:05:05 +0530 | [diff] [blame] | 1149 | qdf_spin_unlock(&CE_state->ce_index_lock); |
Prakash Dhavali | d5c9f1c | 2015-11-08 19:04:44 -0800 | [diff] [blame] | 1150 | |
| 1151 | return status; |
| 1152 | } |
| 1153 | |
| 1154 | /* Shift bits to convert IS_*_RING_*_WATERMARK_MASK to CE_WM_FLAG_*_* */ |
| 1155 | #define CE_WM_SHFT 1 |
| 1156 | |
| 1157 | int |
| 1158 | ce_completed_send_next(struct CE_handle *copyeng, |
| 1159 | void **per_CE_contextp, |
| 1160 | void **per_transfer_contextp, |
Chouhan, Anurag | fc06aa9 | 2016-03-03 19:05:05 +0530 | [diff] [blame] | 1161 | qdf_dma_addr_t *bufferp, |
Prakash Dhavali | d5c9f1c | 2015-11-08 19:04:44 -0800 | [diff] [blame] | 1162 | unsigned int *nbytesp, |
| 1163 | unsigned int *transfer_idp, |
| 1164 | unsigned int *sw_idx, |
| 1165 | unsigned int *hw_idx, |
| 1166 | unsigned int *toeplitz_hash_result) |
| 1167 | { |
| 1168 | struct CE_state *CE_state = (struct CE_state *)copyeng; |
| 1169 | int status; |
| 1170 | |
Chouhan, Anurag | fc06aa9 | 2016-03-03 19:05:05 +0530 | [diff] [blame] | 1171 | qdf_spin_lock_bh(&CE_state->ce_index_lock); |
Prakash Dhavali | d5c9f1c | 2015-11-08 19:04:44 -0800 | [diff] [blame] | 1172 | status = |
| 1173 | ce_completed_send_next_nolock(CE_state, per_CE_contextp, |
| 1174 | per_transfer_contextp, bufferp, |
| 1175 | nbytesp, transfer_idp, sw_idx, |
| 1176 | hw_idx, toeplitz_hash_result); |
Chouhan, Anurag | fc06aa9 | 2016-03-03 19:05:05 +0530 | [diff] [blame] | 1177 | qdf_spin_unlock_bh(&CE_state->ce_index_lock); |
Prakash Dhavali | d5c9f1c | 2015-11-08 19:04:44 -0800 | [diff] [blame] | 1178 | |
| 1179 | return status; |
| 1180 | } |
| 1181 | |
| 1182 | #ifdef ATH_11AC_TXCOMPACT |
| 1183 | /* CE engine descriptor reap |
| 1184 | * Similar to ce_per_engine_service , Only difference is ce_per_engine_service |
| 1185 | * does recieve and reaping of completed descriptor , |
| 1186 | * This function only handles reaping of Tx complete descriptor. |
| 1187 | * The Function is called from threshold reap poll routine |
| 1188 | * hif_send_complete_check so should not countain recieve functionality |
| 1189 | * within it . |
| 1190 | */ |
| 1191 | |
Komal Seelam | 644263d | 2016-02-22 20:45:49 +0530 | [diff] [blame] | 1192 | void ce_per_engine_servicereap(struct hif_softc *scn, unsigned int ce_id) |
Prakash Dhavali | d5c9f1c | 2015-11-08 19:04:44 -0800 | [diff] [blame] | 1193 | { |
| 1194 | void *CE_context; |
| 1195 | void *transfer_context; |
Chouhan, Anurag | fc06aa9 | 2016-03-03 19:05:05 +0530 | [diff] [blame] | 1196 | qdf_dma_addr_t buf; |
Prakash Dhavali | d5c9f1c | 2015-11-08 19:04:44 -0800 | [diff] [blame] | 1197 | unsigned int nbytes; |
| 1198 | unsigned int id; |
| 1199 | unsigned int sw_idx, hw_idx; |
| 1200 | uint32_t toeplitz_hash_result; |
Houston Hoffman | a575ec2 | 2015-12-14 16:35:15 -0800 | [diff] [blame] | 1201 | struct CE_state *CE_state = scn->ce_id_to_state[ce_id]; |
Prakash Dhavali | d5c9f1c | 2015-11-08 19:04:44 -0800 | [diff] [blame] | 1202 | |
Houston Hoffman | bac9454 | 2016-03-14 21:11:59 -0700 | [diff] [blame] | 1203 | if (Q_TARGET_ACCESS_BEGIN(scn) < 0) |
| 1204 | return; |
| 1205 | |
Komal Seelam | bd7c51d | 2016-02-24 10:27:30 +0530 | [diff] [blame] | 1206 | hif_record_ce_desc_event(scn, ce_id, HIF_CE_REAP_ENTRY, |
Houston Hoffman | a575ec2 | 2015-12-14 16:35:15 -0800 | [diff] [blame] | 1207 | NULL, NULL, 0); |
Prakash Dhavali | d5c9f1c | 2015-11-08 19:04:44 -0800 | [diff] [blame] | 1208 | |
| 1209 | /* Since this function is called from both user context and |
| 1210 | * tasklet context the spinlock has to lock the bottom halves. |
| 1211 | * This fix assumes that ATH_11AC_TXCOMPACT flag is always |
| 1212 | * enabled in TX polling mode. If this is not the case, more |
| 1213 | * bottom halve spin lock changes are needed. Due to data path |
| 1214 | * performance concern, after internal discussion we've decided |
| 1215 | * to make minimum change, i.e., only address the issue occured |
| 1216 | * in this function. The possible negative effect of this minimum |
| 1217 | * change is that, in the future, if some other function will also |
| 1218 | * be opened to let the user context to use, those cases need to be |
| 1219 | * addressed by change spin_lock to spin_lock_bh also. |
| 1220 | */ |
| 1221 | |
Chouhan, Anurag | fc06aa9 | 2016-03-03 19:05:05 +0530 | [diff] [blame] | 1222 | qdf_spin_lock_bh(&CE_state->ce_index_lock); |
Prakash Dhavali | d5c9f1c | 2015-11-08 19:04:44 -0800 | [diff] [blame] | 1223 | |
| 1224 | if (CE_state->send_cb) { |
| 1225 | { |
| 1226 | /* Pop completed send buffers and call the |
| 1227 | * registered send callback for each |
| 1228 | */ |
| 1229 | while (ce_completed_send_next_nolock |
| 1230 | (CE_state, &CE_context, |
| 1231 | &transfer_context, &buf, |
| 1232 | &nbytes, &id, &sw_idx, &hw_idx, |
| 1233 | &toeplitz_hash_result) == |
Chouhan, Anurag | fc06aa9 | 2016-03-03 19:05:05 +0530 | [diff] [blame] | 1234 | QDF_STATUS_SUCCESS) { |
Houston Hoffman | a575ec2 | 2015-12-14 16:35:15 -0800 | [diff] [blame] | 1235 | if (ce_id != CE_HTT_H2T_MSG) { |
Chouhan, Anurag | fc06aa9 | 2016-03-03 19:05:05 +0530 | [diff] [blame] | 1236 | qdf_spin_unlock_bh( |
Houston Hoffman | 44b7e4a | 2015-09-03 17:01:22 -0700 | [diff] [blame] | 1237 | &CE_state->ce_index_lock); |
| 1238 | CE_state->send_cb( |
| 1239 | (struct CE_handle *) |
Prakash Dhavali | d5c9f1c | 2015-11-08 19:04:44 -0800 | [diff] [blame] | 1240 | CE_state, CE_context, |
| 1241 | transfer_context, buf, |
| 1242 | nbytes, id, sw_idx, hw_idx, |
| 1243 | toeplitz_hash_result); |
Chouhan, Anurag | fc06aa9 | 2016-03-03 19:05:05 +0530 | [diff] [blame] | 1244 | qdf_spin_lock_bh( |
Houston Hoffman | 44b7e4a | 2015-09-03 17:01:22 -0700 | [diff] [blame] | 1245 | &CE_state->ce_index_lock); |
Prakash Dhavali | d5c9f1c | 2015-11-08 19:04:44 -0800 | [diff] [blame] | 1246 | } else { |
| 1247 | struct HIF_CE_pipe_info *pipe_info = |
| 1248 | (struct HIF_CE_pipe_info *) |
| 1249 | CE_context; |
| 1250 | |
Chouhan, Anurag | fc06aa9 | 2016-03-03 19:05:05 +0530 | [diff] [blame] | 1251 | qdf_spin_lock_bh(&pipe_info-> |
Prakash Dhavali | d5c9f1c | 2015-11-08 19:04:44 -0800 | [diff] [blame] | 1252 | completion_freeq_lock); |
| 1253 | pipe_info->num_sends_allowed++; |
Chouhan, Anurag | fc06aa9 | 2016-03-03 19:05:05 +0530 | [diff] [blame] | 1254 | qdf_spin_unlock_bh(&pipe_info-> |
Prakash Dhavali | d5c9f1c | 2015-11-08 19:04:44 -0800 | [diff] [blame] | 1255 | completion_freeq_lock); |
| 1256 | } |
| 1257 | } |
| 1258 | } |
| 1259 | } |
| 1260 | |
Chouhan, Anurag | fc06aa9 | 2016-03-03 19:05:05 +0530 | [diff] [blame] | 1261 | qdf_spin_unlock_bh(&CE_state->ce_index_lock); |
Houston Hoffman | a575ec2 | 2015-12-14 16:35:15 -0800 | [diff] [blame] | 1262 | |
Komal Seelam | bd7c51d | 2016-02-24 10:27:30 +0530 | [diff] [blame] | 1263 | hif_record_ce_desc_event(scn, ce_id, HIF_CE_REAP_EXIT, |
Houston Hoffman | a575ec2 | 2015-12-14 16:35:15 -0800 | [diff] [blame] | 1264 | NULL, NULL, 0); |
Houston Hoffman | bac9454 | 2016-03-14 21:11:59 -0700 | [diff] [blame] | 1265 | Q_TARGET_ACCESS_END(scn); |
Prakash Dhavali | d5c9f1c | 2015-11-08 19:04:44 -0800 | [diff] [blame] | 1266 | } |
| 1267 | |
| 1268 | #endif /*ATH_11AC_TXCOMPACT */ |
| 1269 | |
| 1270 | /* |
| 1271 | * Number of times to check for any pending tx/rx completion on |
| 1272 | * a copy engine, this count should be big enough. Once we hit |
| 1273 | * this threashold we'll not check for any Tx/Rx comlpetion in same |
| 1274 | * interrupt handling. Note that this threashold is only used for |
| 1275 | * Rx interrupt processing, this can be used tor Tx as well if we |
| 1276 | * suspect any infinite loop in checking for pending Tx completion. |
| 1277 | */ |
| 1278 | #define CE_TXRX_COMP_CHECK_THRESHOLD 20 |
| 1279 | |
| 1280 | /* |
| 1281 | * Guts of interrupt handler for per-engine interrupts on a particular CE. |
| 1282 | * |
| 1283 | * Invokes registered callbacks for recv_complete, |
| 1284 | * send_complete, and watermarks. |
| 1285 | * |
| 1286 | * Returns: number of messages processed |
| 1287 | */ |
| 1288 | |
Komal Seelam | 644263d | 2016-02-22 20:45:49 +0530 | [diff] [blame] | 1289 | int ce_per_engine_service(struct hif_softc *scn, unsigned int CE_id) |
Prakash Dhavali | d5c9f1c | 2015-11-08 19:04:44 -0800 | [diff] [blame] | 1290 | { |
| 1291 | struct CE_state *CE_state = scn->ce_id_to_state[CE_id]; |
| 1292 | uint32_t ctrl_addr = CE_state->ctrl_addr; |
| 1293 | void *CE_context; |
| 1294 | void *transfer_context; |
Chouhan, Anurag | fc06aa9 | 2016-03-03 19:05:05 +0530 | [diff] [blame] | 1295 | qdf_dma_addr_t buf; |
Prakash Dhavali | d5c9f1c | 2015-11-08 19:04:44 -0800 | [diff] [blame] | 1296 | unsigned int nbytes; |
| 1297 | unsigned int id; |
| 1298 | unsigned int flags; |
| 1299 | uint32_t CE_int_status; |
| 1300 | unsigned int more_comp_cnt = 0; |
| 1301 | unsigned int more_snd_comp_cnt = 0; |
| 1302 | unsigned int sw_idx, hw_idx; |
| 1303 | uint32_t toeplitz_hash_result; |
Komal Seelam | bd7c51d | 2016-02-24 10:27:30 +0530 | [diff] [blame] | 1304 | uint32_t mode = hif_get_conparam(scn); |
Prakash Dhavali | d5c9f1c | 2015-11-08 19:04:44 -0800 | [diff] [blame] | 1305 | |
| 1306 | if (Q_TARGET_ACCESS_BEGIN(scn) < 0) { |
| 1307 | HIF_ERROR("[premature rc=0]\n"); |
| 1308 | return 0; /* no work done */ |
| 1309 | } |
| 1310 | |
Chouhan, Anurag | fc06aa9 | 2016-03-03 19:05:05 +0530 | [diff] [blame] | 1311 | qdf_spin_lock(&CE_state->ce_index_lock); |
Prakash Dhavali | d5c9f1c | 2015-11-08 19:04:44 -0800 | [diff] [blame] | 1312 | |
| 1313 | /* Clear force_break flag and re-initialize receive_count to 0 */ |
| 1314 | |
| 1315 | /* NAPI: scn variables- thread/multi-processing safety? */ |
Houston Hoffman | 5bf441a | 2015-09-02 11:52:10 -0700 | [diff] [blame] | 1316 | CE_state->receive_count = 0; |
Houston Hoffman | 18c7fc5 | 2015-09-02 11:44:42 -0700 | [diff] [blame] | 1317 | CE_state->force_break = 0; |
Prakash Dhavali | d5c9f1c | 2015-11-08 19:04:44 -0800 | [diff] [blame] | 1318 | more_completions: |
| 1319 | if (CE_state->recv_cb) { |
| 1320 | |
| 1321 | /* Pop completed recv buffers and call |
| 1322 | * the registered recv callback for each |
| 1323 | */ |
| 1324 | while (ce_completed_recv_next_nolock |
| 1325 | (CE_state, &CE_context, &transfer_context, |
| 1326 | &buf, &nbytes, &id, &flags) == |
Chouhan, Anurag | fc06aa9 | 2016-03-03 19:05:05 +0530 | [diff] [blame] | 1327 | QDF_STATUS_SUCCESS) { |
| 1328 | qdf_spin_unlock(&CE_state->ce_index_lock); |
Prakash Dhavali | d5c9f1c | 2015-11-08 19:04:44 -0800 | [diff] [blame] | 1329 | CE_state->recv_cb((struct CE_handle *)CE_state, |
| 1330 | CE_context, transfer_context, buf, |
| 1331 | nbytes, id, flags); |
| 1332 | |
| 1333 | /* |
| 1334 | * EV #112693 - |
| 1335 | * [Peregrine][ES1][WB342][Win8x86][Performance] |
| 1336 | * BSoD_0x133 occurred in VHT80 UDP_DL |
| 1337 | * Break out DPC by force if number of loops in |
| 1338 | * hif_pci_ce_recv_data reaches MAX_NUM_OF_RECEIVES |
| 1339 | * to avoid spending too long time in |
| 1340 | * DPC for each interrupt handling. Schedule another |
| 1341 | * DPC to avoid data loss if we had taken |
| 1342 | * force-break action before apply to Windows OS |
| 1343 | * only currently, Linux/MAC os can expand to their |
| 1344 | * platform if necessary |
| 1345 | */ |
| 1346 | |
| 1347 | /* Break the receive processes by |
| 1348 | * force if force_break set up |
| 1349 | */ |
Chouhan, Anurag | fc06aa9 | 2016-03-03 19:05:05 +0530 | [diff] [blame] | 1350 | if (qdf_unlikely(CE_state->force_break)) { |
| 1351 | qdf_atomic_set(&CE_state->rx_pending, 1); |
Prakash Dhavali | d5c9f1c | 2015-11-08 19:04:44 -0800 | [diff] [blame] | 1352 | CE_ENGINE_INT_STATUS_CLEAR(scn, ctrl_addr, |
| 1353 | HOST_IS_COPY_COMPLETE_MASK); |
| 1354 | if (Q_TARGET_ACCESS_END(scn) < 0) |
| 1355 | HIF_ERROR("<--[premature rc=%d]\n", |
Houston Hoffman | 5bf441a | 2015-09-02 11:52:10 -0700 | [diff] [blame] | 1356 | CE_state->receive_count); |
| 1357 | return CE_state->receive_count; |
Prakash Dhavali | d5c9f1c | 2015-11-08 19:04:44 -0800 | [diff] [blame] | 1358 | } |
Chouhan, Anurag | fc06aa9 | 2016-03-03 19:05:05 +0530 | [diff] [blame] | 1359 | qdf_spin_lock(&CE_state->ce_index_lock); |
Prakash Dhavali | d5c9f1c | 2015-11-08 19:04:44 -0800 | [diff] [blame] | 1360 | } |
| 1361 | } |
| 1362 | |
| 1363 | /* |
| 1364 | * Attention: We may experience potential infinite loop for below |
| 1365 | * While Loop during Sending Stress test. |
| 1366 | * Resolve the same way as Receive Case (Refer to EV #112693) |
| 1367 | */ |
| 1368 | |
| 1369 | if (CE_state->send_cb) { |
| 1370 | /* Pop completed send buffers and call |
| 1371 | * the registered send callback for each |
| 1372 | */ |
| 1373 | |
| 1374 | #ifdef ATH_11AC_TXCOMPACT |
| 1375 | while (ce_completed_send_next_nolock |
| 1376 | (CE_state, &CE_context, |
| 1377 | &transfer_context, &buf, &nbytes, |
| 1378 | &id, &sw_idx, &hw_idx, |
Chouhan, Anurag | fc06aa9 | 2016-03-03 19:05:05 +0530 | [diff] [blame] | 1379 | &toeplitz_hash_result) == QDF_STATUS_SUCCESS) { |
Prakash Dhavali | d5c9f1c | 2015-11-08 19:04:44 -0800 | [diff] [blame] | 1380 | |
| 1381 | if (CE_id != CE_HTT_H2T_MSG || |
Komal Seelam | bd7c51d | 2016-02-24 10:27:30 +0530 | [diff] [blame] | 1382 | WLAN_IS_EPPING_ENABLED(mode)) { |
Chouhan, Anurag | fc06aa9 | 2016-03-03 19:05:05 +0530 | [diff] [blame] | 1383 | qdf_spin_unlock(&CE_state->ce_index_lock); |
Prakash Dhavali | d5c9f1c | 2015-11-08 19:04:44 -0800 | [diff] [blame] | 1384 | CE_state->send_cb((struct CE_handle *)CE_state, |
| 1385 | CE_context, transfer_context, |
| 1386 | buf, nbytes, id, sw_idx, |
| 1387 | hw_idx, toeplitz_hash_result); |
Chouhan, Anurag | fc06aa9 | 2016-03-03 19:05:05 +0530 | [diff] [blame] | 1388 | qdf_spin_lock(&CE_state->ce_index_lock); |
Prakash Dhavali | d5c9f1c | 2015-11-08 19:04:44 -0800 | [diff] [blame] | 1389 | } else { |
| 1390 | struct HIF_CE_pipe_info *pipe_info = |
| 1391 | (struct HIF_CE_pipe_info *)CE_context; |
| 1392 | |
Chouhan, Anurag | fc06aa9 | 2016-03-03 19:05:05 +0530 | [diff] [blame] | 1393 | qdf_spin_lock(&pipe_info-> |
Prakash Dhavali | d5c9f1c | 2015-11-08 19:04:44 -0800 | [diff] [blame] | 1394 | completion_freeq_lock); |
| 1395 | pipe_info->num_sends_allowed++; |
Chouhan, Anurag | fc06aa9 | 2016-03-03 19:05:05 +0530 | [diff] [blame] | 1396 | qdf_spin_unlock(&pipe_info-> |
Prakash Dhavali | d5c9f1c | 2015-11-08 19:04:44 -0800 | [diff] [blame] | 1397 | completion_freeq_lock); |
| 1398 | } |
| 1399 | } |
| 1400 | #else /*ATH_11AC_TXCOMPACT */ |
| 1401 | while (ce_completed_send_next_nolock |
| 1402 | (CE_state, &CE_context, |
| 1403 | &transfer_context, &buf, &nbytes, |
| 1404 | &id, &sw_idx, &hw_idx, |
Chouhan, Anurag | fc06aa9 | 2016-03-03 19:05:05 +0530 | [diff] [blame] | 1405 | &toeplitz_hash_result) == QDF_STATUS_SUCCESS) { |
| 1406 | qdf_spin_unlock(&CE_state->ce_index_lock); |
Prakash Dhavali | d5c9f1c | 2015-11-08 19:04:44 -0800 | [diff] [blame] | 1407 | CE_state->send_cb((struct CE_handle *)CE_state, |
| 1408 | CE_context, transfer_context, buf, |
| 1409 | nbytes, id, sw_idx, hw_idx, |
| 1410 | toeplitz_hash_result); |
Chouhan, Anurag | fc06aa9 | 2016-03-03 19:05:05 +0530 | [diff] [blame] | 1411 | qdf_spin_lock(&CE_state->ce_index_lock); |
Prakash Dhavali | d5c9f1c | 2015-11-08 19:04:44 -0800 | [diff] [blame] | 1412 | } |
| 1413 | #endif /*ATH_11AC_TXCOMPACT */ |
| 1414 | } |
| 1415 | |
| 1416 | more_watermarks: |
| 1417 | if (CE_state->misc_cbs) { |
| 1418 | CE_int_status = CE_ENGINE_INT_STATUS_GET(scn, ctrl_addr); |
| 1419 | if (CE_int_status & CE_WATERMARK_MASK) { |
| 1420 | if (CE_state->watermark_cb) { |
Chouhan, Anurag | fc06aa9 | 2016-03-03 19:05:05 +0530 | [diff] [blame] | 1421 | qdf_spin_unlock(&CE_state->ce_index_lock); |
Prakash Dhavali | d5c9f1c | 2015-11-08 19:04:44 -0800 | [diff] [blame] | 1422 | /* Convert HW IS bits to software flags */ |
| 1423 | flags = |
| 1424 | (CE_int_status & CE_WATERMARK_MASK) >> |
| 1425 | CE_WM_SHFT; |
| 1426 | |
| 1427 | CE_state-> |
| 1428 | watermark_cb((struct CE_handle *)CE_state, |
| 1429 | CE_state->wm_context, flags); |
Chouhan, Anurag | fc06aa9 | 2016-03-03 19:05:05 +0530 | [diff] [blame] | 1430 | qdf_spin_lock(&CE_state->ce_index_lock); |
Prakash Dhavali | d5c9f1c | 2015-11-08 19:04:44 -0800 | [diff] [blame] | 1431 | } |
| 1432 | } |
| 1433 | } |
| 1434 | |
| 1435 | /* |
| 1436 | * Clear the misc interrupts (watermark) that were handled above, |
| 1437 | * and that will be checked again below. |
| 1438 | * Clear and check for copy-complete interrupts again, just in case |
| 1439 | * more copy completions happened while the misc interrupts were being |
| 1440 | * handled. |
| 1441 | */ |
| 1442 | CE_ENGINE_INT_STATUS_CLEAR(scn, ctrl_addr, |
| 1443 | CE_WATERMARK_MASK | |
| 1444 | HOST_IS_COPY_COMPLETE_MASK); |
| 1445 | |
| 1446 | /* |
| 1447 | * Now that per-engine interrupts are cleared, verify that |
| 1448 | * no recv interrupts arrive while processing send interrupts, |
| 1449 | * and no recv or send interrupts happened while processing |
| 1450 | * misc interrupts.Go back and check again.Keep checking until |
| 1451 | * we find no more events to process. |
| 1452 | */ |
| 1453 | if (CE_state->recv_cb && ce_recv_entries_done_nolock(scn, CE_state)) { |
Komal Seelam | bd7c51d | 2016-02-24 10:27:30 +0530 | [diff] [blame] | 1454 | if (WLAN_IS_EPPING_ENABLED(mode) || |
Prakash Dhavali | d5c9f1c | 2015-11-08 19:04:44 -0800 | [diff] [blame] | 1455 | more_comp_cnt++ < CE_TXRX_COMP_CHECK_THRESHOLD) { |
| 1456 | goto more_completions; |
| 1457 | } else { |
| 1458 | HIF_ERROR( |
| 1459 | "%s:Potential infinite loop detected during Rx processing nentries_mask:0x%x sw read_idx:0x%x hw read_idx:0x%x", |
| 1460 | __func__, CE_state->dest_ring->nentries_mask, |
| 1461 | CE_state->dest_ring->sw_index, |
| 1462 | CE_DEST_RING_READ_IDX_GET(scn, |
| 1463 | CE_state->ctrl_addr)); |
| 1464 | } |
| 1465 | } |
| 1466 | |
| 1467 | if (CE_state->send_cb && ce_send_entries_done_nolock(scn, CE_state)) { |
Komal Seelam | bd7c51d | 2016-02-24 10:27:30 +0530 | [diff] [blame] | 1468 | if (WLAN_IS_EPPING_ENABLED(mode) || |
Prakash Dhavali | d5c9f1c | 2015-11-08 19:04:44 -0800 | [diff] [blame] | 1469 | more_snd_comp_cnt++ < CE_TXRX_COMP_CHECK_THRESHOLD) { |
| 1470 | goto more_completions; |
| 1471 | } else { |
| 1472 | HIF_ERROR( |
| 1473 | "%s:Potential infinite loop detected during send completion nentries_mask:0x%x sw read_idx:0x%x hw read_idx:0x%x", |
| 1474 | __func__, CE_state->src_ring->nentries_mask, |
| 1475 | CE_state->src_ring->sw_index, |
| 1476 | CE_SRC_RING_READ_IDX_GET(scn, |
| 1477 | CE_state->ctrl_addr)); |
| 1478 | } |
| 1479 | } |
| 1480 | |
| 1481 | if (CE_state->misc_cbs) { |
| 1482 | CE_int_status = CE_ENGINE_INT_STATUS_GET(scn, ctrl_addr); |
| 1483 | if (CE_int_status & CE_WATERMARK_MASK) { |
| 1484 | if (CE_state->watermark_cb) { |
| 1485 | goto more_watermarks; |
| 1486 | } |
| 1487 | } |
| 1488 | } |
| 1489 | |
Chouhan, Anurag | fc06aa9 | 2016-03-03 19:05:05 +0530 | [diff] [blame] | 1490 | qdf_spin_unlock(&CE_state->ce_index_lock); |
| 1491 | qdf_atomic_set(&CE_state->rx_pending, 0); |
Prakash Dhavali | d5c9f1c | 2015-11-08 19:04:44 -0800 | [diff] [blame] | 1492 | |
| 1493 | if (Q_TARGET_ACCESS_END(scn) < 0) |
Houston Hoffman | 5bf441a | 2015-09-02 11:52:10 -0700 | [diff] [blame] | 1494 | HIF_ERROR("<--[premature rc=%d]\n", CE_state->receive_count); |
| 1495 | return CE_state->receive_count; |
Prakash Dhavali | d5c9f1c | 2015-11-08 19:04:44 -0800 | [diff] [blame] | 1496 | } |
| 1497 | |
| 1498 | /* |
| 1499 | * Handler for per-engine interrupts on ALL active CEs. |
| 1500 | * This is used in cases where the system is sharing a |
| 1501 | * single interrput for all CEs |
| 1502 | */ |
| 1503 | |
Komal Seelam | 644263d | 2016-02-22 20:45:49 +0530 | [diff] [blame] | 1504 | void ce_per_engine_service_any(int irq, struct hif_softc *scn) |
Prakash Dhavali | d5c9f1c | 2015-11-08 19:04:44 -0800 | [diff] [blame] | 1505 | { |
| 1506 | int CE_id; |
| 1507 | uint32_t intr_summary; |
| 1508 | |
Houston Hoffman | bac9454 | 2016-03-14 21:11:59 -0700 | [diff] [blame] | 1509 | if (Q_TARGET_ACCESS_BEGIN(scn) < 0) |
| 1510 | return; |
| 1511 | |
Chouhan, Anurag | fc06aa9 | 2016-03-03 19:05:05 +0530 | [diff] [blame] | 1512 | if (!qdf_atomic_read(&scn->tasklet_from_intr)) { |
Prakash Dhavali | d5c9f1c | 2015-11-08 19:04:44 -0800 | [diff] [blame] | 1513 | for (CE_id = 0; CE_id < scn->ce_count; CE_id++) { |
| 1514 | struct CE_state *CE_state = scn->ce_id_to_state[CE_id]; |
Chouhan, Anurag | fc06aa9 | 2016-03-03 19:05:05 +0530 | [diff] [blame] | 1515 | if (qdf_atomic_read(&CE_state->rx_pending)) { |
| 1516 | qdf_atomic_set(&CE_state->rx_pending, 0); |
Prakash Dhavali | d5c9f1c | 2015-11-08 19:04:44 -0800 | [diff] [blame] | 1517 | ce_per_engine_service(scn, CE_id); |
| 1518 | } |
| 1519 | } |
| 1520 | |
Houston Hoffman | bac9454 | 2016-03-14 21:11:59 -0700 | [diff] [blame] | 1521 | Q_TARGET_ACCESS_END(scn); |
Prakash Dhavali | d5c9f1c | 2015-11-08 19:04:44 -0800 | [diff] [blame] | 1522 | return; |
| 1523 | } |
| 1524 | |
| 1525 | intr_summary = CE_INTERRUPT_SUMMARY(scn); |
| 1526 | |
| 1527 | for (CE_id = 0; intr_summary && (CE_id < scn->ce_count); CE_id++) { |
| 1528 | if (intr_summary & (1 << CE_id)) { |
| 1529 | intr_summary &= ~(1 << CE_id); |
| 1530 | } else { |
| 1531 | continue; /* no intr pending on this CE */ |
| 1532 | } |
| 1533 | |
| 1534 | ce_per_engine_service(scn, CE_id); |
| 1535 | } |
| 1536 | |
Houston Hoffman | bac9454 | 2016-03-14 21:11:59 -0700 | [diff] [blame] | 1537 | Q_TARGET_ACCESS_END(scn); |
Prakash Dhavali | d5c9f1c | 2015-11-08 19:04:44 -0800 | [diff] [blame] | 1538 | } |
| 1539 | |
| 1540 | /* |
| 1541 | * Adjust interrupts for the copy complete handler. |
| 1542 | * If it's needed for either send or recv, then unmask |
| 1543 | * this interrupt; otherwise, mask it. |
| 1544 | * |
| 1545 | * Called with target_lock held. |
| 1546 | */ |
| 1547 | static void |
| 1548 | ce_per_engine_handler_adjust(struct CE_state *CE_state, |
| 1549 | int disable_copy_compl_intr) |
| 1550 | { |
| 1551 | uint32_t ctrl_addr = CE_state->ctrl_addr; |
Komal Seelam | 644263d | 2016-02-22 20:45:49 +0530 | [diff] [blame] | 1552 | struct hif_softc *scn = CE_state->scn; |
Prakash Dhavali | d5c9f1c | 2015-11-08 19:04:44 -0800 | [diff] [blame] | 1553 | |
| 1554 | CE_state->disable_copy_compl_intr = disable_copy_compl_intr; |
Houston Hoffman | bac9454 | 2016-03-14 21:11:59 -0700 | [diff] [blame] | 1555 | |
| 1556 | if (Q_TARGET_ACCESS_BEGIN(scn) < 0) |
| 1557 | return; |
| 1558 | |
Prakash Dhavali | d5c9f1c | 2015-11-08 19:04:44 -0800 | [diff] [blame] | 1559 | if ((!disable_copy_compl_intr) && |
| 1560 | (CE_state->send_cb || CE_state->recv_cb)) { |
| 1561 | CE_COPY_COMPLETE_INTR_ENABLE(scn, ctrl_addr); |
| 1562 | } else { |
| 1563 | CE_COPY_COMPLETE_INTR_DISABLE(scn, ctrl_addr); |
| 1564 | } |
| 1565 | |
| 1566 | if (CE_state->watermark_cb) { |
| 1567 | CE_WATERMARK_INTR_ENABLE(scn, ctrl_addr); |
| 1568 | } else { |
| 1569 | CE_WATERMARK_INTR_DISABLE(scn, ctrl_addr); |
| 1570 | } |
Houston Hoffman | bac9454 | 2016-03-14 21:11:59 -0700 | [diff] [blame] | 1571 | Q_TARGET_ACCESS_END(scn); |
Prakash Dhavali | d5c9f1c | 2015-11-08 19:04:44 -0800 | [diff] [blame] | 1572 | } |
| 1573 | |
| 1574 | /*Iterate the CE_state list and disable the compl interrupt |
| 1575 | * if it has been registered already. |
| 1576 | */ |
Komal Seelam | 644263d | 2016-02-22 20:45:49 +0530 | [diff] [blame] | 1577 | void ce_disable_any_copy_compl_intr_nolock(struct hif_softc *scn) |
Prakash Dhavali | d5c9f1c | 2015-11-08 19:04:44 -0800 | [diff] [blame] | 1578 | { |
| 1579 | int CE_id; |
| 1580 | |
Houston Hoffman | bac9454 | 2016-03-14 21:11:59 -0700 | [diff] [blame] | 1581 | if (Q_TARGET_ACCESS_BEGIN(scn) < 0) |
| 1582 | return; |
| 1583 | |
Prakash Dhavali | d5c9f1c | 2015-11-08 19:04:44 -0800 | [diff] [blame] | 1584 | for (CE_id = 0; CE_id < scn->ce_count; CE_id++) { |
| 1585 | struct CE_state *CE_state = scn->ce_id_to_state[CE_id]; |
| 1586 | uint32_t ctrl_addr = CE_state->ctrl_addr; |
| 1587 | |
| 1588 | /* if the interrupt is currently enabled, disable it */ |
| 1589 | if (!CE_state->disable_copy_compl_intr |
| 1590 | && (CE_state->send_cb || CE_state->recv_cb)) { |
| 1591 | CE_COPY_COMPLETE_INTR_DISABLE(scn, ctrl_addr); |
| 1592 | } |
| 1593 | |
| 1594 | if (CE_state->watermark_cb) { |
| 1595 | CE_WATERMARK_INTR_DISABLE(scn, ctrl_addr); |
| 1596 | } |
| 1597 | } |
Houston Hoffman | bac9454 | 2016-03-14 21:11:59 -0700 | [diff] [blame] | 1598 | Q_TARGET_ACCESS_END(scn); |
Prakash Dhavali | d5c9f1c | 2015-11-08 19:04:44 -0800 | [diff] [blame] | 1599 | } |
| 1600 | |
Komal Seelam | 644263d | 2016-02-22 20:45:49 +0530 | [diff] [blame] | 1601 | void ce_enable_any_copy_compl_intr_nolock(struct hif_softc *scn) |
Prakash Dhavali | d5c9f1c | 2015-11-08 19:04:44 -0800 | [diff] [blame] | 1602 | { |
| 1603 | int CE_id; |
| 1604 | |
Houston Hoffman | bac9454 | 2016-03-14 21:11:59 -0700 | [diff] [blame] | 1605 | if (Q_TARGET_ACCESS_BEGIN(scn) < 0) |
| 1606 | return; |
| 1607 | |
Prakash Dhavali | d5c9f1c | 2015-11-08 19:04:44 -0800 | [diff] [blame] | 1608 | for (CE_id = 0; CE_id < scn->ce_count; CE_id++) { |
| 1609 | struct CE_state *CE_state = scn->ce_id_to_state[CE_id]; |
| 1610 | uint32_t ctrl_addr = CE_state->ctrl_addr; |
| 1611 | |
| 1612 | /* |
| 1613 | * If the CE is supposed to have copy complete interrupts |
| 1614 | * enabled (i.e. there a callback registered, and the |
| 1615 | * "disable" flag is not set), then re-enable the interrupt. |
| 1616 | */ |
| 1617 | if (!CE_state->disable_copy_compl_intr |
| 1618 | && (CE_state->send_cb || CE_state->recv_cb)) { |
| 1619 | CE_COPY_COMPLETE_INTR_ENABLE(scn, ctrl_addr); |
| 1620 | } |
| 1621 | |
| 1622 | if (CE_state->watermark_cb) { |
| 1623 | CE_WATERMARK_INTR_ENABLE(scn, ctrl_addr); |
| 1624 | } |
| 1625 | } |
Houston Hoffman | bac9454 | 2016-03-14 21:11:59 -0700 | [diff] [blame] | 1626 | Q_TARGET_ACCESS_END(scn); |
Prakash Dhavali | d5c9f1c | 2015-11-08 19:04:44 -0800 | [diff] [blame] | 1627 | } |
| 1628 | |
Houston Hoffman | a837c9a | 2015-09-03 12:47:01 -0700 | [diff] [blame] | 1629 | /** |
| 1630 | * ce_send_cb_register(): register completion handler |
| 1631 | * @copyeng: CE_state representing the ce we are adding the behavior to |
| 1632 | * @fn_ptr: callback that the ce should use when processing tx completions |
| 1633 | * @disable_interrupts: if the interupts should be enabled or not. |
| 1634 | * |
| 1635 | * Caller should guarantee that no transactions are in progress before |
| 1636 | * switching the callback function. |
| 1637 | * |
| 1638 | * Registers the send context before the fn pointer so that if the cb is valid |
| 1639 | * the context should be valid. |
| 1640 | * |
| 1641 | * Beware that currently this function will enable completion interrupts. |
| 1642 | */ |
Prakash Dhavali | d5c9f1c | 2015-11-08 19:04:44 -0800 | [diff] [blame] | 1643 | void |
| 1644 | ce_send_cb_register(struct CE_handle *copyeng, |
| 1645 | ce_send_cb fn_ptr, |
| 1646 | void *ce_send_context, int disable_interrupts) |
| 1647 | { |
| 1648 | struct CE_state *CE_state = (struct CE_state *)copyeng; |
| 1649 | |
Sanjay Devnani | 9ce1577 | 2015-11-12 14:08:57 -0800 | [diff] [blame] | 1650 | if (CE_state == NULL) { |
| 1651 | pr_err("%s: Error CE state = NULL\n", __func__); |
| 1652 | return; |
| 1653 | } |
Prakash Dhavali | d5c9f1c | 2015-11-08 19:04:44 -0800 | [diff] [blame] | 1654 | CE_state->send_context = ce_send_context; |
Houston Hoffman | a837c9a | 2015-09-03 12:47:01 -0700 | [diff] [blame] | 1655 | CE_state->send_cb = fn_ptr; |
Prakash Dhavali | d5c9f1c | 2015-11-08 19:04:44 -0800 | [diff] [blame] | 1656 | ce_per_engine_handler_adjust(CE_state, disable_interrupts); |
Prakash Dhavali | d5c9f1c | 2015-11-08 19:04:44 -0800 | [diff] [blame] | 1657 | } |
| 1658 | |
Houston Hoffman | a837c9a | 2015-09-03 12:47:01 -0700 | [diff] [blame] | 1659 | /** |
| 1660 | * ce_recv_cb_register(): register completion handler |
| 1661 | * @copyeng: CE_state representing the ce we are adding the behavior to |
| 1662 | * @fn_ptr: callback that the ce should use when processing rx completions |
| 1663 | * @disable_interrupts: if the interupts should be enabled or not. |
| 1664 | * |
| 1665 | * Registers the send context before the fn pointer so that if the cb is valid |
| 1666 | * the context should be valid. |
| 1667 | * |
| 1668 | * Caller should guarantee that no transactions are in progress before |
| 1669 | * switching the callback function. |
| 1670 | */ |
Prakash Dhavali | d5c9f1c | 2015-11-08 19:04:44 -0800 | [diff] [blame] | 1671 | void |
| 1672 | ce_recv_cb_register(struct CE_handle *copyeng, |
| 1673 | CE_recv_cb fn_ptr, |
| 1674 | void *CE_recv_context, int disable_interrupts) |
| 1675 | { |
| 1676 | struct CE_state *CE_state = (struct CE_state *)copyeng; |
| 1677 | |
Sanjay Devnani | 9ce1577 | 2015-11-12 14:08:57 -0800 | [diff] [blame] | 1678 | if (CE_state == NULL) { |
| 1679 | pr_err("%s: ERROR CE state = NULL\n", __func__); |
| 1680 | return; |
| 1681 | } |
Prakash Dhavali | d5c9f1c | 2015-11-08 19:04:44 -0800 | [diff] [blame] | 1682 | CE_state->recv_context = CE_recv_context; |
Houston Hoffman | a837c9a | 2015-09-03 12:47:01 -0700 | [diff] [blame] | 1683 | CE_state->recv_cb = fn_ptr; |
Prakash Dhavali | d5c9f1c | 2015-11-08 19:04:44 -0800 | [diff] [blame] | 1684 | ce_per_engine_handler_adjust(CE_state, disable_interrupts); |
Prakash Dhavali | d5c9f1c | 2015-11-08 19:04:44 -0800 | [diff] [blame] | 1685 | } |
| 1686 | |
Houston Hoffman | a837c9a | 2015-09-03 12:47:01 -0700 | [diff] [blame] | 1687 | /** |
| 1688 | * ce_watermark_cb_register(): register completion handler |
| 1689 | * @copyeng: CE_state representing the ce we are adding the behavior to |
| 1690 | * @fn_ptr: callback that the ce should use when processing watermark events |
| 1691 | * |
| 1692 | * Caller should guarantee that no watermark events are being processed before |
| 1693 | * switching the callback function. |
| 1694 | */ |
Prakash Dhavali | d5c9f1c | 2015-11-08 19:04:44 -0800 | [diff] [blame] | 1695 | void |
| 1696 | ce_watermark_cb_register(struct CE_handle *copyeng, |
| 1697 | CE_watermark_cb fn_ptr, void *CE_wm_context) |
| 1698 | { |
| 1699 | struct CE_state *CE_state = (struct CE_state *)copyeng; |
| 1700 | |
Prakash Dhavali | d5c9f1c | 2015-11-08 19:04:44 -0800 | [diff] [blame] | 1701 | CE_state->watermark_cb = fn_ptr; |
| 1702 | CE_state->wm_context = CE_wm_context; |
| 1703 | ce_per_engine_handler_adjust(CE_state, 0); |
| 1704 | if (fn_ptr) { |
| 1705 | CE_state->misc_cbs = 1; |
| 1706 | } |
Prakash Dhavali | d5c9f1c | 2015-11-08 19:04:44 -0800 | [diff] [blame] | 1707 | } |
| 1708 | |
| 1709 | #ifdef WLAN_FEATURE_FASTPATH |
| 1710 | /** |
| 1711 | * ce_pkt_dl_len_set() set the HTT packet download length |
| 1712 | * @hif_sc: HIF context |
| 1713 | * @pkt_download_len: download length |
| 1714 | * |
| 1715 | * Return: None |
| 1716 | */ |
| 1717 | void ce_pkt_dl_len_set(void *hif_sc, u_int32_t pkt_download_len) |
| 1718 | { |
Komal Seelam | 644263d | 2016-02-22 20:45:49 +0530 | [diff] [blame] | 1719 | struct hif_softc *sc = (struct hif_softc *)(hif_sc); |
Prakash Dhavali | d5c9f1c | 2015-11-08 19:04:44 -0800 | [diff] [blame] | 1720 | struct CE_state *ce_state = sc->ce_id_to_state[CE_HTT_H2T_MSG]; |
| 1721 | |
Chouhan, Anurag | fc06aa9 | 2016-03-03 19:05:05 +0530 | [diff] [blame] | 1722 | qdf_assert_always(ce_state); |
Prakash Dhavali | d5c9f1c | 2015-11-08 19:04:44 -0800 | [diff] [blame] | 1723 | |
Prakash Dhavali | d5c9f1c | 2015-11-08 19:04:44 -0800 | [diff] [blame] | 1724 | ce_state->download_len = pkt_download_len; |
Prakash Dhavali | d5c9f1c | 2015-11-08 19:04:44 -0800 | [diff] [blame] | 1725 | |
Chouhan, Anurag | fc06aa9 | 2016-03-03 19:05:05 +0530 | [diff] [blame] | 1726 | qdf_print("%s CE %d Pkt download length %d", __func__, |
Prakash Dhavali | d5c9f1c | 2015-11-08 19:04:44 -0800 | [diff] [blame] | 1727 | ce_state->id, ce_state->download_len); |
| 1728 | } |
| 1729 | #else |
| 1730 | void ce_pkt_dl_len_set(void *hif_sc, u_int32_t pkt_download_len) |
| 1731 | { |
| 1732 | } |
| 1733 | #endif /* WLAN_FEATURE_FASTPATH */ |
| 1734 | |
Komal Seelam | 644263d | 2016-02-22 20:45:49 +0530 | [diff] [blame] | 1735 | bool ce_get_rx_pending(struct hif_softc *scn) |
Prakash Dhavali | d5c9f1c | 2015-11-08 19:04:44 -0800 | [diff] [blame] | 1736 | { |
| 1737 | int CE_id; |
| 1738 | |
| 1739 | for (CE_id = 0; CE_id < scn->ce_count; CE_id++) { |
| 1740 | struct CE_state *CE_state = scn->ce_id_to_state[CE_id]; |
Chouhan, Anurag | fc06aa9 | 2016-03-03 19:05:05 +0530 | [diff] [blame] | 1741 | if (qdf_atomic_read(&CE_state->rx_pending)) |
Prakash Dhavali | d5c9f1c | 2015-11-08 19:04:44 -0800 | [diff] [blame] | 1742 | return true; |
| 1743 | } |
| 1744 | |
| 1745 | return false; |
| 1746 | } |
| 1747 | |
| 1748 | /** |
| 1749 | * ce_check_rx_pending() - ce_check_rx_pending |
Komal Seelam | 644263d | 2016-02-22 20:45:49 +0530 | [diff] [blame] | 1750 | * @scn: hif_softc |
Prakash Dhavali | d5c9f1c | 2015-11-08 19:04:44 -0800 | [diff] [blame] | 1751 | * @ce_id: ce_id |
| 1752 | * |
| 1753 | * Return: bool |
| 1754 | */ |
Komal Seelam | 644263d | 2016-02-22 20:45:49 +0530 | [diff] [blame] | 1755 | bool ce_check_rx_pending(struct hif_softc *scn, int ce_id) |
Prakash Dhavali | d5c9f1c | 2015-11-08 19:04:44 -0800 | [diff] [blame] | 1756 | { |
| 1757 | struct CE_state *CE_state = scn->ce_id_to_state[ce_id]; |
Chouhan, Anurag | fc06aa9 | 2016-03-03 19:05:05 +0530 | [diff] [blame] | 1758 | if (qdf_atomic_read(&CE_state->rx_pending)) |
Prakash Dhavali | d5c9f1c | 2015-11-08 19:04:44 -0800 | [diff] [blame] | 1759 | return true; |
| 1760 | else |
| 1761 | return false; |
| 1762 | } |
Houston Hoffman | 8ed92e5 | 2015-09-02 14:49:48 -0700 | [diff] [blame] | 1763 | |
| 1764 | /** |
| 1765 | * ce_enable_msi(): write the msi configuration to the target |
| 1766 | * @scn: hif context |
| 1767 | * @CE_id: which copy engine will be configured for msi interupts |
| 1768 | * @msi_addr_lo: Hardware will write to this address to generate an interrupt |
| 1769 | * @msi_addr_hi: Hardware will write to this address to generate an interrupt |
| 1770 | * @msi_data: Hardware will write this data to generate an interrupt |
| 1771 | * |
| 1772 | * should be done in the initialization sequence so no locking would be needed |
| 1773 | */ |
Komal Seelam | 644263d | 2016-02-22 20:45:49 +0530 | [diff] [blame] | 1774 | void ce_enable_msi(struct hif_softc *scn, unsigned int CE_id, |
Prakash Dhavali | d5c9f1c | 2015-11-08 19:04:44 -0800 | [diff] [blame] | 1775 | uint32_t msi_addr_lo, uint32_t msi_addr_hi, |
| 1776 | uint32_t msi_data) |
| 1777 | { |
| 1778 | #ifdef WLAN_ENABLE_QCA6180 |
| 1779 | struct CE_state *CE_state; |
| 1780 | A_target_id_t targid; |
| 1781 | u_int32_t ctrl_addr; |
| 1782 | uint32_t tmp; |
| 1783 | |
Prakash Dhavali | d5c9f1c | 2015-11-08 19:04:44 -0800 | [diff] [blame] | 1784 | CE_state = scn->ce_id_to_state[CE_id]; |
| 1785 | if (!CE_state) { |
| 1786 | HIF_ERROR("%s: error - CE_state = NULL", __func__); |
Prakash Dhavali | d5c9f1c | 2015-11-08 19:04:44 -0800 | [diff] [blame] | 1787 | return; |
| 1788 | } |
| 1789 | targid = TARGID(sc); |
| 1790 | ctrl_addr = CE_state->ctrl_addr; |
| 1791 | CE_MSI_ADDR_LOW_SET(scn, ctrl_addr, msi_addr_lo); |
| 1792 | CE_MSI_ADDR_HIGH_SET(scn, ctrl_addr, msi_addr_hi); |
| 1793 | CE_MSI_DATA_SET(scn, ctrl_addr, msi_data); |
| 1794 | tmp = CE_CTRL_REGISTER1_GET(scn, ctrl_addr); |
| 1795 | tmp |= (1 << CE_MSI_ENABLE_BIT); |
| 1796 | CE_CTRL_REGISTER1_SET(scn, ctrl_addr, tmp); |
Prakash Dhavali | d5c9f1c | 2015-11-08 19:04:44 -0800 | [diff] [blame] | 1797 | #endif |
| 1798 | } |
| 1799 | |
| 1800 | #ifdef IPA_OFFLOAD |
Leo Chang | d85f78d | 2015-11-13 10:55:34 -0800 | [diff] [blame] | 1801 | /** |
| 1802 | * ce_ipa_get_resource() - get uc resource on copyengine |
| 1803 | * @ce: copyengine context |
| 1804 | * @ce_sr_base_paddr: copyengine source ring base physical address |
| 1805 | * @ce_sr_ring_size: copyengine source ring size |
| 1806 | * @ce_reg_paddr: copyengine register physical address |
| 1807 | * |
Prakash Dhavali | d5c9f1c | 2015-11-08 19:04:44 -0800 | [diff] [blame] | 1808 | * Copy engine should release resource to micro controller |
| 1809 | * Micro controller needs |
Leo Chang | d85f78d | 2015-11-13 10:55:34 -0800 | [diff] [blame] | 1810 | * - Copy engine source descriptor base address |
| 1811 | * - Copy engine source descriptor size |
| 1812 | * - PCI BAR address to access copy engine regiser |
| 1813 | * |
| 1814 | * Return: None |
Prakash Dhavali | d5c9f1c | 2015-11-08 19:04:44 -0800 | [diff] [blame] | 1815 | */ |
| 1816 | void ce_ipa_get_resource(struct CE_handle *ce, |
Chouhan, Anurag | fc06aa9 | 2016-03-03 19:05:05 +0530 | [diff] [blame] | 1817 | qdf_dma_addr_t *ce_sr_base_paddr, |
Prakash Dhavali | d5c9f1c | 2015-11-08 19:04:44 -0800 | [diff] [blame] | 1818 | uint32_t *ce_sr_ring_size, |
Chouhan, Anurag | fc06aa9 | 2016-03-03 19:05:05 +0530 | [diff] [blame] | 1819 | qdf_dma_addr_t *ce_reg_paddr) |
Prakash Dhavali | d5c9f1c | 2015-11-08 19:04:44 -0800 | [diff] [blame] | 1820 | { |
| 1821 | struct CE_state *CE_state = (struct CE_state *)ce; |
| 1822 | uint32_t ring_loop; |
| 1823 | struct CE_src_desc *ce_desc; |
Chouhan, Anurag | fc06aa9 | 2016-03-03 19:05:05 +0530 | [diff] [blame] | 1824 | qdf_dma_addr_t phy_mem_base; |
Komal Seelam | 644263d | 2016-02-22 20:45:49 +0530 | [diff] [blame] | 1825 | struct hif_softc *scn = CE_state->scn; |
Prakash Dhavali | d5c9f1c | 2015-11-08 19:04:44 -0800 | [diff] [blame] | 1826 | |
| 1827 | if (CE_RUNNING != CE_state->state) { |
| 1828 | *ce_sr_base_paddr = 0; |
| 1829 | *ce_sr_ring_size = 0; |
| 1830 | return; |
| 1831 | } |
| 1832 | |
| 1833 | /* Update default value for descriptor */ |
| 1834 | for (ring_loop = 0; ring_loop < CE_state->src_ring->nentries; |
| 1835 | ring_loop++) { |
| 1836 | ce_desc = (struct CE_src_desc *) |
| 1837 | ((char *)CE_state->src_ring->base_addr_owner_space + |
| 1838 | ring_loop * (sizeof(struct CE_src_desc))); |
| 1839 | CE_IPA_RING_INIT(ce_desc); |
| 1840 | } |
| 1841 | |
| 1842 | /* Get BAR address */ |
| 1843 | hif_read_phy_mem_base(CE_state->scn, &phy_mem_base); |
| 1844 | |
Leo Chang | d85f78d | 2015-11-13 10:55:34 -0800 | [diff] [blame] | 1845 | *ce_sr_base_paddr = CE_state->src_ring->base_addr_CE_space; |
| 1846 | *ce_sr_ring_size = (uint32_t) (CE_state->src_ring->nentries * |
| 1847 | sizeof(struct CE_src_desc)); |
Prakash Dhavali | d5c9f1c | 2015-11-08 19:04:44 -0800 | [diff] [blame] | 1848 | *ce_reg_paddr = phy_mem_base + CE_BASE_ADDRESS(CE_state->id) + |
| 1849 | SR_WR_INDEX_ADDRESS; |
| 1850 | return; |
| 1851 | } |
| 1852 | #endif /* IPA_OFFLOAD */ |
| 1853 | |