Prakash Dhavali | d5c9f1c | 2015-11-08 19:04:44 -0800 | [diff] [blame] | 1 | /* |
Houston Hoffman | ebc6814 | 2016-01-18 15:38:27 -0800 | [diff] [blame] | 2 | * Copyright (c) 2013-2016 The Linux Foundation. All rights reserved. |
Prakash Dhavali | d5c9f1c | 2015-11-08 19:04:44 -0800 | [diff] [blame] | 3 | * |
| 4 | * Previously licensed under the ISC license by Qualcomm Atheros, Inc. |
| 5 | * |
| 6 | * |
| 7 | * Permission to use, copy, modify, and/or distribute this software for |
| 8 | * any purpose with or without fee is hereby granted, provided that the |
| 9 | * above copyright notice and this permission notice appear in all |
| 10 | * copies. |
| 11 | * |
| 12 | * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL |
| 13 | * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED |
| 14 | * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE |
| 15 | * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL |
| 16 | * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR |
| 17 | * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER |
| 18 | * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR |
| 19 | * PERFORMANCE OF THIS SOFTWARE. |
| 20 | */ |
| 21 | |
| 22 | /* |
| 23 | * This file was originally distributed by Qualcomm Atheros, Inc. |
| 24 | * under proprietary terms before Copyright ownership was assigned |
| 25 | * to the Linux Foundation. |
| 26 | */ |
| 27 | |
| 28 | #ifndef _HIF_H_ |
| 29 | #define _HIF_H_ |
| 30 | |
| 31 | #ifdef __cplusplus |
| 32 | extern "C" { |
| 33 | #endif /* __cplusplus */ |
| 34 | |
| 35 | /* Header files */ |
| 36 | #include "athdefs.h" |
| 37 | #include "a_types.h" |
| 38 | #include "osapi_linux.h" |
| 39 | #include "cdf_status.h" |
| 40 | #include "cdf_nbuf.h" |
| 41 | #include "ol_if_athvar.h" |
| 42 | #include <linux/platform_device.h> |
| 43 | #ifdef HIF_PCI |
| 44 | #include <linux/pci.h> |
| 45 | #endif /* HIF_PCI */ |
| 46 | |
| 47 | #define ENABLE_MBOX_DUMMY_SPACE_FEATURE 1 |
| 48 | |
| 49 | typedef struct htc_callbacks HTC_CALLBACKS; |
| 50 | typedef void __iomem *A_target_id_t; |
| 51 | |
| 52 | #define HIF_TYPE_AR6002 2 |
| 53 | #define HIF_TYPE_AR6003 3 |
| 54 | #define HIF_TYPE_AR6004 5 |
| 55 | #define HIF_TYPE_AR9888 6 |
| 56 | #define HIF_TYPE_AR6320 7 |
| 57 | #define HIF_TYPE_AR6320V2 8 |
| 58 | /* For attaching Peregrine 2.0 board host_reg_tbl only */ |
| 59 | #define HIF_TYPE_AR9888V2 8 |
| 60 | #define HIF_TYPE_QCA6180 9 |
| 61 | #define HIF_TYPE_ADRASTEA 10 |
| 62 | |
| 63 | #define TARGET_TYPE_UNKNOWN 0 |
| 64 | #define TARGET_TYPE_AR6001 1 |
| 65 | #define TARGET_TYPE_AR6002 2 |
| 66 | #define TARGET_TYPE_AR6003 3 |
| 67 | #define TARGET_TYPE_AR6004 5 |
| 68 | #define TARGET_TYPE_AR6006 6 |
| 69 | #define TARGET_TYPE_AR9888 7 |
| 70 | #define TARGET_TYPE_AR6320 8 |
| 71 | #define TARGET_TYPE_AR900B 9 |
| 72 | /* For attach Peregrine 2.0 board target_reg_tbl only */ |
| 73 | #define TARGET_TYPE_AR9888V2 10 |
| 74 | /* For attach Rome1.0 target_reg_tbl only*/ |
| 75 | #define TARGET_TYPE_AR6320V1 11 |
| 76 | /* For Rome2.0/2.1 target_reg_tbl ID*/ |
| 77 | #define TARGET_TYPE_AR6320V2 12 |
| 78 | /* For Rome3.0 target_reg_tbl ID*/ |
| 79 | #define TARGET_TYPE_AR6320V3 13 |
| 80 | /* For Tufello1.0 target_reg_tbl ID*/ |
| 81 | #define TARGET_TYPE_QCA9377V1 14 |
| 82 | /* For QCA6180 target */ |
| 83 | #define TARGET_TYPE_QCA6180 15 |
| 84 | /* For Adrastea target */ |
| 85 | #define TARGET_TYPE_ADRASTEA 16 |
| 86 | |
| 87 | struct CE_state; |
Sanjay Devnani | 9ce1577 | 2015-11-12 14:08:57 -0800 | [diff] [blame] | 88 | #ifdef QCA_WIFI_3_0_ADRASTEA |
| 89 | #define CE_COUNT_MAX 12 |
| 90 | #else |
Prakash Dhavali | d5c9f1c | 2015-11-08 19:04:44 -0800 | [diff] [blame] | 91 | #define CE_COUNT_MAX 8 |
Sanjay Devnani | 9ce1577 | 2015-11-12 14:08:57 -0800 | [diff] [blame] | 92 | #endif |
Prakash Dhavali | d5c9f1c | 2015-11-08 19:04:44 -0800 | [diff] [blame] | 93 | |
| 94 | /* These numbers are selected so that the product is close to current |
| 95 | higher limit of packets HIF services at one shot (1000) */ |
| 96 | #define QCA_NAPI_BUDGET 64 |
| 97 | #define QCA_NAPI_DEF_SCALE 16 |
| 98 | /* NOTE: This is to adapt non-NAPI solution to use |
| 99 | the same "budget" as NAPI. Will be removed |
| 100 | `once decision about NAPI is made */ |
| 101 | #define HIF_NAPI_MAX_RECEIVES (QCA_NAPI_BUDGET * QCA_NAPI_DEF_SCALE) |
| 102 | |
| 103 | /* NOTE: "napi->scale" can be changed, |
| 104 | but this does not change the number of buckets */ |
| 105 | #define QCA_NAPI_NUM_BUCKETS (QCA_NAPI_BUDGET / QCA_NAPI_DEF_SCALE) |
| 106 | struct qca_napi_stat { |
| 107 | uint32_t napi_schedules; |
| 108 | uint32_t napi_polls; |
| 109 | uint32_t napi_completes; |
| 110 | uint32_t napi_workdone; |
| 111 | uint32_t napi_budget_uses[QCA_NAPI_NUM_BUCKETS]; |
| 112 | }; |
| 113 | |
| 114 | /** |
| 115 | * per NAPI instance data structure |
| 116 | * This data structure holds stuff per NAPI instance. |
| 117 | * Note that, in the current implementation, though scale is |
| 118 | * an instance variable, it is set to the same value for all |
| 119 | * instances. |
| 120 | */ |
| 121 | struct qca_napi_info { |
| 122 | struct napi_struct napi; /* one NAPI Instance per CE in phase I */ |
| 123 | uint8_t scale; /* currently same on all instances */ |
| 124 | uint8_t id; |
| 125 | struct qca_napi_stat stats[NR_CPUS]; |
| 126 | }; |
| 127 | |
| 128 | /** |
| 129 | * NAPI data-sructure common to all NAPI instances. |
| 130 | * |
| 131 | * A variable of this type will be stored in hif module context. |
| 132 | */ |
| 133 | |
| 134 | struct qca_napi_data { |
| 135 | /* NOTE: make sure the mutex is inited only at the very beginning |
| 136 | once for the lifetime of the driver. For now, granularity of one |
| 137 | is OK, but we might want to have a better granularity later */ |
| 138 | struct mutex mutex; |
| 139 | uint32_t state; |
| 140 | uint32_t ce_map; /* bitmap of created/registered NAPI |
| 141 | instances, indexed by pipe_id, |
| 142 | not used by clients (clients use an |
| 143 | id returned by create) */ |
| 144 | struct net_device netdev; /* dummy net_dev */ |
| 145 | struct qca_napi_info napis[CE_COUNT_MAX]; |
| 146 | }; |
| 147 | |
Komal Seelam | 91553ce | 2016-01-27 18:57:10 +0530 | [diff] [blame^] | 148 | /** |
| 149 | * struct hif_config_info - Place Holder for hif configuration |
| 150 | * @enable_uart_print: UART Print |
| 151 | * @enable_self_recovery: Self Recovery |
| 152 | * @enable_fw_log: To Enable FW LOG |
| 153 | * @enable_lpass_support: LPASS support |
| 154 | * @enable_ramdump_collection: Ramdump Collection |
| 155 | * @max_no_of_peers: Max Number of Peers |
| 156 | * |
| 157 | * Structure for holding ini parameters. |
| 158 | */ |
| 159 | struct hif_config_info { |
| 160 | bool enable_uart_print; |
| 161 | bool enable_self_recovery; |
| 162 | bool enable_fw_log; |
| 163 | bool enable_lpass_support; |
| 164 | bool enable_ramdump_collection; |
| 165 | uint8_t max_no_of_peers; |
| 166 | }; |
| 167 | |
| 168 | /** |
| 169 | * struct hif_target_info - Target Information |
| 170 | * @target_version: Target Version |
| 171 | * @target_type: Target Type |
| 172 | * @target_revision: Target Revision |
| 173 | * @soc_version: SOC Version |
| 174 | * |
| 175 | * Structure to hold target information. |
| 176 | */ |
| 177 | struct hif_target_info { |
| 178 | uint32_t target_version; |
| 179 | uint32_t target_type; |
| 180 | uint32_t target_revision; |
| 181 | uint32_t soc_version; |
| 182 | }; |
| 183 | |
Prakash Dhavali | d5c9f1c | 2015-11-08 19:04:44 -0800 | [diff] [blame] | 184 | struct ol_softc { |
| 185 | void __iomem *mem; /* IO mapped memory base address */ |
| 186 | cdf_dma_addr_t mem_pa; |
Komal Seelam | 91553ce | 2016-01-27 18:57:10 +0530 | [diff] [blame^] | 187 | struct hif_config_info hif_config; |
| 188 | struct hif_target_info target_info; |
Prakash Dhavali | d5c9f1c | 2015-11-08 19:04:44 -0800 | [diff] [blame] | 189 | /* |
| 190 | * handle for code that uses the osdep.h version of OS |
| 191 | * abstraction primitives |
| 192 | */ |
| 193 | struct _NIC_DEV aps_osdev; |
| 194 | enum ath_hal_bus_type bus_type; |
| 195 | uint32_t lcr_val; |
| 196 | bool pkt_log_init; |
| 197 | bool request_irq_done; |
| 198 | /* |
| 199 | * handle for code that uses cdf version of OS |
| 200 | * abstraction primitives |
| 201 | */ |
| 202 | cdf_device_t cdf_dev; |
| 203 | |
Prakash Dhavali | d5c9f1c | 2015-11-08 19:04:44 -0800 | [diff] [blame] | 204 | /* Packet statistics */ |
| 205 | struct ol_ath_stats pkt_stats; |
| 206 | |
Prakash Dhavali | d5c9f1c | 2015-11-08 19:04:44 -0800 | [diff] [blame] | 207 | ol_target_status target_status; |
Prakash Dhavali | d5c9f1c | 2015-11-08 19:04:44 -0800 | [diff] [blame] | 208 | /* calibration data is stored in flash */ |
| 209 | uint8_t *cal_in_flash; |
| 210 | /* virtual address for the calibration data on the flash */ |
| 211 | void *cal_mem; |
| 212 | /* status of target init */ |
| 213 | WLAN_INIT_STATUS wlan_init_status; |
| 214 | |
| 215 | /* BMI info */ |
| 216 | /* OS-dependent private info for BMI */ |
Prakash Dhavali | d5c9f1c | 2015-11-08 19:04:44 -0800 | [diff] [blame] | 217 | bool bmi_done; |
Prakash Dhavali | d5c9f1c | 2015-11-08 19:04:44 -0800 | [diff] [blame] | 218 | uint8_t *bmi_cmd_buff; |
| 219 | dma_addr_t bmi_cmd_da; |
| 220 | OS_DMA_MEM_CONTEXT(bmicmd_dmacontext) |
| 221 | |
| 222 | uint8_t *bmi_rsp_buff; |
| 223 | dma_addr_t bmi_rsp_da; |
| 224 | /* length of last response */ |
Prakash Dhavali | d5c9f1c | 2015-11-08 19:04:44 -0800 | [diff] [blame] | 225 | OS_DMA_MEM_CONTEXT(bmirsp_dmacontext) |
| 226 | |
| 227 | void *msi_magic; |
| 228 | dma_addr_t msi_magic_da; |
| 229 | OS_DMA_MEM_CONTEXT(msi_dmacontext) |
| 230 | |
| 231 | /* Handles for Lower Layers : filled in at init time */ |
| 232 | hif_handle_t hif_hdl; |
| 233 | #ifdef HIF_PCI |
| 234 | struct hif_pci_softc *hif_sc; |
| 235 | #endif |
| 236 | |
| 237 | #ifdef WLAN_FEATURE_FASTPATH |
| 238 | int fastpath_mode_on; /* Duplicating this for data path efficiency */ |
| 239 | #endif /* WLAN_FEATURE_FASTPATH */ |
| 240 | |
| 241 | /* HTC handles */ |
| 242 | void *htc_handle; |
| 243 | |
Prakash Dhavali | d5c9f1c | 2015-11-08 19:04:44 -0800 | [diff] [blame] | 244 | uint8_t vow_extstats; |
Prakash Dhavali | d5c9f1c | 2015-11-08 19:04:44 -0800 | [diff] [blame] | 245 | #ifdef CONFIG_CNSS |
| 246 | struct cnss_fw_files fw_files; |
| 247 | #endif |
| 248 | #if defined(CONFIG_CNSS) |
| 249 | void *ramdump_base; |
| 250 | unsigned long ramdump_address; |
| 251 | unsigned long ramdump_size; |
| 252 | #endif |
Prakash Dhavali | d5c9f1c | 2015-11-08 19:04:44 -0800 | [diff] [blame] | 253 | struct targetdef_s *targetdef; |
| 254 | struct ce_reg_def *target_ce_def; |
| 255 | struct hostdef_s *hostdef; |
| 256 | struct host_shadow_regs_s *host_shadow_regs; |
| 257 | bool athdiag_procfs_inited; |
| 258 | /* |
| 259 | * Guard changes to Target HW state and to software |
| 260 | * structures that track hardware state. |
| 261 | */ |
Prakash Dhavali | d5c9f1c | 2015-11-08 19:04:44 -0800 | [diff] [blame] | 262 | unsigned int ce_count; /* Number of Copy Engines supported */ |
Prakash Dhavali | d5c9f1c | 2015-11-08 19:04:44 -0800 | [diff] [blame] | 263 | struct CE_state *ce_id_to_state[CE_COUNT_MAX]; /* CE id to CE_state */ |
| 264 | #ifdef FEATURE_NAPI |
| 265 | struct qca_napi_data napi_data; |
| 266 | #endif /* FEATURE_NAPI */ |
| 267 | int htc_endpoint; |
| 268 | bool recovery; |
| 269 | bool hif_init_done; |
| 270 | int linkstate_vote; |
| 271 | atomic_t link_suspended; |
| 272 | atomic_t wow_done; |
| 273 | atomic_t tasklet_from_intr; |
| 274 | atomic_t active_tasklet_cnt; |
| 275 | bool notice_send; |
| 276 | #ifdef HIF_PCI |
| 277 | cdf_spinlock_t irq_lock; |
| 278 | uint32_t ce_irq_summary; |
| 279 | #endif |
Sanjay Devnani | b925d7e | 2015-11-12 14:43:58 -0800 | [diff] [blame] | 280 | uint32_t *vaddr_rri_on_ddr; |
Prakash Dhavali | d5c9f1c | 2015-11-08 19:04:44 -0800 | [diff] [blame] | 281 | }; |
| 282 | |
| 283 | typedef enum { |
| 284 | HIF_DEVICE_POWER_UP, /* HIF layer should power up interface |
| 285 | * and/or module */ |
| 286 | HIF_DEVICE_POWER_DOWN, /* HIF layer should initiate bus-specific |
| 287 | * measures to minimize power */ |
| 288 | HIF_DEVICE_POWER_CUT /* HIF layer should initiate bus-specific |
| 289 | * AND/OR platform-specific measures |
| 290 | * to completely power-off the module and |
| 291 | * associated hardware (i.e. cut power |
| 292 | * supplies) */ |
| 293 | } HIF_DEVICE_POWER_CHANGE_TYPE; |
| 294 | |
| 295 | /** |
| 296 | * enum hif_enable_type: what triggered the enabling of hif |
| 297 | * |
| 298 | * @HIF_ENABLE_TYPE_PROBE: probe triggered enable |
| 299 | * @HIF_ENABLE_TYPE_REINIT: reinit triggered enable |
| 300 | */ |
| 301 | enum hif_enable_type { |
| 302 | HIF_ENABLE_TYPE_PROBE, |
| 303 | HIF_ENABLE_TYPE_REINIT, |
| 304 | HIF_ENABLE_TYPE_MAX |
| 305 | }; |
| 306 | |
| 307 | /** |
| 308 | * enum hif_disable_type: what triggered the disabling of hif |
| 309 | * |
| 310 | * @HIF_DISABLE_TYPE_PROBE_ERROR: probe error triggered disable |
| 311 | * @HIF_DISABLE_TYPE_REINIT_ERROR: reinit error triggered |
| 312 | * disable |
| 313 | * @HIF_DISABLE_TYPE_REMOVE: remove triggered disable |
| 314 | * @HIF_DISABLE_TYPE_SHUTDOWN: shutdown triggered disable |
| 315 | */ |
| 316 | enum hif_disable_type { |
| 317 | HIF_DISABLE_TYPE_PROBE_ERROR, |
| 318 | HIF_DISABLE_TYPE_REINIT_ERROR, |
| 319 | HIF_DISABLE_TYPE_REMOVE, |
| 320 | HIF_DISABLE_TYPE_SHUTDOWN, |
| 321 | HIF_DISABLE_TYPE_MAX |
| 322 | }; |
| 323 | |
| 324 | #ifdef CONFIG_ATH_PCIE_ACCESS_DEBUG |
| 325 | typedef struct _HID_ACCESS_LOG { |
| 326 | uint32_t seqnum; |
| 327 | bool is_write; |
| 328 | void *addr; |
| 329 | uint32_t value; |
| 330 | } HIF_ACCESS_LOG; |
| 331 | #endif |
| 332 | |
| 333 | #define HIF_MAX_DEVICES 1 |
| 334 | |
| 335 | struct htc_callbacks { |
| 336 | void *context; /* context to pass to the dsrhandler |
| 337 | * note : rwCompletionHandler is provided |
| 338 | * the context passed to hif_read_write */ |
| 339 | int (*rwCompletionHandler)(void *rwContext, int status); |
| 340 | int (*dsrHandler)(void *context); |
| 341 | }; |
| 342 | |
| 343 | typedef struct osdrv_callbacks { |
| 344 | void *context; /* context to pass for all callbacks |
| 345 | * except deviceRemovedHandler |
| 346 | * the deviceRemovedHandler is only |
| 347 | * called if the device is claimed */ |
| 348 | int (*deviceInsertedHandler)(void *context, void *hif_handle); |
| 349 | int (*deviceRemovedHandler)(void *claimedContext, |
| 350 | void *hif_handle); |
| 351 | int (*deviceSuspendHandler)(void *context); |
| 352 | int (*deviceResumeHandler)(void *context); |
| 353 | int (*deviceWakeupHandler)(void *context); |
| 354 | int (*devicePowerChangeHandler)(void *context, |
| 355 | HIF_DEVICE_POWER_CHANGE_TYPE |
| 356 | config); |
| 357 | } OSDRV_CALLBACKS; |
| 358 | |
| 359 | /* |
| 360 | * This API is used to perform any global initialization of the HIF layer |
| 361 | * and to set OS driver callbacks (i.e. insertion/removal) to the HIF layer |
| 362 | * |
| 363 | */ |
| 364 | int hif_init(OSDRV_CALLBACKS *callbacks); |
| 365 | |
Prakash Dhavali | d5c9f1c | 2015-11-08 19:04:44 -0800 | [diff] [blame] | 366 | /* This API detaches the HTC layer from the HIF device */ |
| 367 | void hif_detach_htc(struct ol_softc *scn); |
| 368 | |
| 369 | /****************************************************************/ |
| 370 | /* BMI and Diag window abstraction */ |
| 371 | /****************************************************************/ |
| 372 | |
| 373 | #define HIF_BMI_EXCHANGE_NO_TIMEOUT ((uint32_t)(0)) |
| 374 | |
| 375 | #define DIAG_TRANSFER_LIMIT 2048U /* maximum number of bytes that can be |
| 376 | * handled atomically by |
| 377 | * DiagRead/DiagWrite */ |
| 378 | |
| 379 | /* |
| 380 | * API to handle HIF-specific BMI message exchanges, this API is synchronous |
| 381 | * and only allowed to be called from a context that can block (sleep) */ |
| 382 | CDF_STATUS hif_exchange_bmi_msg(struct ol_softc *scn, |
| 383 | uint8_t *pSendMessage, |
| 384 | uint32_t Length, |
| 385 | uint8_t *pResponseMessage, |
| 386 | uint32_t *pResponseLength, uint32_t TimeoutMS); |
| 387 | |
| 388 | /* |
| 389 | * APIs to handle HIF specific diagnostic read accesses. These APIs are |
| 390 | * synchronous and only allowed to be called from a context that |
| 391 | * can block (sleep). They are not high performance APIs. |
| 392 | * |
| 393 | * hif_diag_read_access reads a 4 Byte aligned/length value from a |
| 394 | * Target register or memory word. |
| 395 | * |
| 396 | * hif_diag_read_mem reads an arbitrary length of arbitrarily aligned memory. |
| 397 | */ |
| 398 | CDF_STATUS hif_diag_read_access(struct ol_softc *scn, uint32_t address, |
| 399 | uint32_t *data); |
| 400 | CDF_STATUS hif_diag_read_mem(struct ol_softc *scn, uint32_t address, |
| 401 | uint8_t *data, int nbytes); |
| 402 | void hif_dump_target_memory(struct ol_softc *scn, void *ramdump_base, |
| 403 | uint32_t address, uint32_t size); |
| 404 | /* |
| 405 | * APIs to handle HIF specific diagnostic write accesses. These APIs are |
| 406 | * synchronous and only allowed to be called from a context that |
| 407 | * can block (sleep). |
| 408 | * They are not high performance APIs. |
| 409 | * |
| 410 | * hif_diag_write_access writes a 4 Byte aligned/length value to a |
| 411 | * Target register or memory word. |
| 412 | * |
| 413 | * hif_diag_write_mem writes an arbitrary length of arbitrarily aligned memory. |
| 414 | */ |
| 415 | CDF_STATUS hif_diag_write_access(struct ol_softc *scn, uint32_t address, |
| 416 | uint32_t data); |
| 417 | CDF_STATUS hif_diag_write_mem(struct ol_softc *scn, uint32_t address, |
| 418 | uint8_t *data, int nbytes); |
| 419 | |
| 420 | /* |
| 421 | * Set the FASTPATH_mode_on flag in sc, for use by data path |
| 422 | */ |
| 423 | #ifdef WLAN_FEATURE_FASTPATH |
| 424 | void hif_enable_fastpath(struct ol_softc *hif_dev); |
| 425 | #endif |
| 426 | |
| 427 | #if defined(HIF_PCI) && !defined(A_SIMOS_DEVHOST) |
| 428 | /* |
| 429 | * This API allows the Host to access Target registers of a given |
| 430 | * A_target_id_t directly and relatively efficiently over PCIe. |
| 431 | * This allows the Host to avoid extra overhead associated with |
| 432 | * sending a message to firmware and waiting for a response message |
| 433 | * from firmware, as is done on other interconnects. |
| 434 | * |
| 435 | * Yet there is some complexity with direct accesses because the |
| 436 | * Target's power state is not known a priori. The Host must issue |
| 437 | * special PCIe reads/writes in order to explicitly wake the Target |
| 438 | * and to verify that it is awake and will remain awake. |
| 439 | * |
| 440 | * NB: Host endianness conversion is left for the caller to handle. |
| 441 | * These interfaces handle access; not interpretation. |
| 442 | * |
| 443 | * Usage: |
| 444 | * During initialization, use A_TARGET_ID to obtain an 'target ID' |
| 445 | * for use with these interfaces. |
| 446 | * |
| 447 | * Use A_TARGET_READ and A_TARGET_WRITE to access Target space. |
| 448 | * These calls must be bracketed by A_TARGET_ACCESS_BEGIN and |
| 449 | * A_TARGET_ACCESS_END. A single BEGIN/END pair is adequate for |
| 450 | * multiple READ/WRITE operations. |
| 451 | * |
| 452 | * Use A_TARGET_ACCESS_BEGIN to put the Target in a state in |
| 453 | * which it is legal for the Host to directly access it. This |
| 454 | * may involve waking the Target from a low power state, which |
| 455 | * may take up to 2Ms! |
| 456 | * |
| 457 | * Use A_TARGET_ACCESS_END to tell the Target that as far as |
| 458 | * this code path is concerned, it no longer needs to remain |
| 459 | * directly accessible. BEGIN/END is under a reference counter; |
| 460 | * multiple code paths may issue BEGIN/END on a single targid. |
| 461 | * |
| 462 | * For added efficiency, the Host may use A_TARGET_ACCESS_LIKELY. |
| 463 | * The LIKELY interface works just like A_TARGET_ACCESS_BEGIN, |
| 464 | * except that it may return before the Target is actually |
| 465 | * available. It's a vague indication that some Target accesses |
| 466 | * are expected "soon". When the LIKELY API is used, |
| 467 | * A_TARGET_ACCESS_BEGIN must be used before any access. |
| 468 | * |
| 469 | * There are several uses for the LIKELY/UNLIKELY API: |
| 470 | * -If there is some potential time before Target accesses |
| 471 | * and we want to get a head start on waking the Target |
| 472 | * (e.g. to overlap Target wake with Host-side malloc) |
| 473 | * -High-level code knows that it will call low-level |
| 474 | * functions that will use BEGIN/END, and we don't want |
| 475 | * to allow the Target to sleep until the entire sequence |
| 476 | * has completed. |
| 477 | * |
| 478 | * A_TARGET_ACCESS_OK verifies that the Target can be |
| 479 | * accessed. In general, this should not be needed, but it |
| 480 | * may be useful for debugging or for special uses. |
| 481 | * |
| 482 | * Note that there must be a matching END for each BEGIN |
| 483 | * AND there must be a matching UNLIKELY for each LIKELY! |
| 484 | * |
| 485 | * NB: This API is designed to allow some flexibility in tradeoffs |
| 486 | * between Target power utilization and Host efficiency and |
| 487 | * system performance. |
| 488 | */ |
| 489 | |
| 490 | /* |
| 491 | * Enable/disable CDC max performance workaround |
| 492 | * For max-performace set this to 0 |
| 493 | * To allow SoC to enter sleep set this to 1 |
| 494 | */ |
| 495 | #define CONFIG_DISABLE_CDC_MAX_PERF_WAR 0 |
| 496 | #endif |
| 497 | |
| 498 | #ifdef IPA_OFFLOAD |
Prakash Dhavali | d5c9f1c | 2015-11-08 19:04:44 -0800 | [diff] [blame] | 499 | void hif_ipa_get_ce_resource(struct ol_softc *scn, |
Leo Chang | d85f78d | 2015-11-13 10:55:34 -0800 | [diff] [blame] | 500 | cdf_dma_addr_t *ce_sr_base_paddr, |
Prakash Dhavali | d5c9f1c | 2015-11-08 19:04:44 -0800 | [diff] [blame] | 501 | uint32_t *ce_sr_ring_size, |
| 502 | cdf_dma_addr_t *ce_reg_paddr); |
| 503 | #else |
Leo Chang | d85f78d | 2015-11-13 10:55:34 -0800 | [diff] [blame] | 504 | /** |
| 505 | * hif_ipa_get_ce_resource() - get uc resource on hif |
| 506 | * @scn: bus context |
| 507 | * @ce_sr_base_paddr: copyengine source ring base physical address |
| 508 | * @ce_sr_ring_size: copyengine source ring size |
| 509 | * @ce_reg_paddr: copyengine register physical address |
| 510 | * |
| 511 | * IPA micro controller data path offload feature enabled, |
| 512 | * HIF should release copy engine related resource information to IPA UC |
| 513 | * IPA UC will access hardware resource with released information |
| 514 | * |
| 515 | * Return: None |
| 516 | */ |
Prakash Dhavali | d5c9f1c | 2015-11-08 19:04:44 -0800 | [diff] [blame] | 517 | static inline void hif_ipa_get_ce_resource(struct ol_softc *scn, |
Leo Chang | d85f78d | 2015-11-13 10:55:34 -0800 | [diff] [blame] | 518 | cdf_dma_addr_t *ce_sr_base_paddr, |
Prakash Dhavali | d5c9f1c | 2015-11-08 19:04:44 -0800 | [diff] [blame] | 519 | uint32_t *ce_sr_ring_size, |
| 520 | cdf_dma_addr_t *ce_reg_paddr) |
| 521 | { |
| 522 | return; |
| 523 | } |
| 524 | #endif /* IPA_OFFLOAD */ |
| 525 | |
| 526 | |
| 527 | void hif_read_phy_mem_base(struct ol_softc *scn, |
| 528 | cdf_dma_addr_t *bar_value); |
| 529 | |
| 530 | /** |
| 531 | * @brief List of callbacks - filled in by HTC. |
| 532 | */ |
| 533 | struct hif_msg_callbacks { |
| 534 | void *Context; |
| 535 | /**< context meaningful to HTC */ |
| 536 | CDF_STATUS (*txCompletionHandler)(void *Context, cdf_nbuf_t wbuf, |
| 537 | uint32_t transferID, |
| 538 | uint32_t toeplitz_hash_result); |
| 539 | CDF_STATUS (*rxCompletionHandler)(void *Context, cdf_nbuf_t wbuf, |
| 540 | uint8_t pipeID); |
| 541 | void (*txResourceAvailHandler)(void *context, uint8_t pipe); |
| 542 | void (*fwEventHandler)(void *context, CDF_STATUS status); |
| 543 | }; |
| 544 | |
| 545 | #define HIF_DATA_ATTR_SET_TX_CLASSIFY(attr, v) \ |
| 546 | (attr |= (v & 0x01) << 5) |
| 547 | #define HIF_DATA_ATTR_SET_ENCAPSULATION_TYPE(attr, v) \ |
| 548 | (attr |= (v & 0x03) << 6) |
| 549 | #define HIF_DATA_ATTR_SET_ADDR_X_SEARCH_DISABLE(attr, v) \ |
| 550 | (attr |= (v & 0x01) << 13) |
| 551 | #define HIF_DATA_ATTR_SET_ADDR_Y_SEARCH_DISABLE(attr, v) \ |
| 552 | (attr |= (v & 0x01) << 14) |
| 553 | #define HIF_DATA_ATTR_SET_TOEPLITZ_HASH_ENABLE(attr, v) \ |
| 554 | (attr |= (v & 0x01) << 15) |
| 555 | #define HIF_DATA_ATTR_SET_PACKET_OR_RESULT_OFFSET(attr, v) \ |
| 556 | (attr |= (v & 0x0FFF) << 16) |
| 557 | #define HIF_DATA_ATTR_SET_ENABLE_11H(attr, v) \ |
| 558 | (attr |= (v & 0x01) << 30) |
| 559 | |
| 560 | #ifdef HIF_PCI |
| 561 | typedef struct pci_device_id hif_bus_id; |
| 562 | #else |
| 563 | typedef struct device hif_bus_id; |
| 564 | #endif |
| 565 | |
| 566 | void hif_post_init(struct ol_softc *scn, void *hHTC, |
| 567 | struct hif_msg_callbacks *callbacks); |
| 568 | CDF_STATUS hif_start(struct ol_softc *scn); |
| 569 | void hif_stop(struct ol_softc *scn); |
| 570 | void hif_flush_surprise_remove(struct ol_softc *scn); |
| 571 | void hif_dump(struct ol_softc *scn, uint8_t CmdId, bool start); |
| 572 | CDF_STATUS hif_send_head(struct ol_softc *scn, uint8_t PipeID, |
| 573 | uint32_t transferID, uint32_t nbytes, |
| 574 | cdf_nbuf_t wbuf, uint32_t data_attr); |
| 575 | void hif_send_complete_check(struct ol_softc *scn, uint8_t PipeID, |
| 576 | int force); |
| 577 | void hif_cancel_deferred_target_sleep(struct ol_softc *scn); |
| 578 | void hif_get_default_pipe(struct ol_softc *scn, uint8_t *ULPipe, |
| 579 | uint8_t *DLPipe); |
Sanjay Devnani | c319c82 | 2015-11-06 16:44:28 -0800 | [diff] [blame] | 580 | int hif_map_service_to_pipe(struct ol_softc *scn, uint16_t svc_id, |
| 581 | uint8_t *ul_pipe, uint8_t *dl_pipe, int *ul_is_polled, |
| 582 | int *dl_is_polled); |
Prakash Dhavali | d5c9f1c | 2015-11-08 19:04:44 -0800 | [diff] [blame] | 583 | uint16_t hif_get_free_queue_number(struct ol_softc *scn, uint8_t PipeID); |
| 584 | void *hif_get_targetdef(struct ol_softc *scn); |
| 585 | void hi_fsuspendwow(struct ol_softc *scn); |
| 586 | uint32_t hif_hia_item_address(uint32_t target_type, uint32_t item_offset); |
| 587 | void hif_set_target_sleep(struct ol_softc *scn, bool sleep_ok, |
| 588 | bool wait_for_it); |
| 589 | int hif_check_fw_reg(struct ol_softc *scn); |
| 590 | int hif_check_soc_status(struct ol_softc *scn); |
Prakash Dhavali | d5c9f1c | 2015-11-08 19:04:44 -0800 | [diff] [blame] | 591 | void hif_disable_isr(void *scn); |
| 592 | void hif_reset_soc(void *scn); |
| 593 | void hif_disable_aspm(void); |
| 594 | void hif_save_htc_htt_config_endpoint(int htc_endpoint); |
Houston Hoffman | 3cfe686 | 2016-01-08 10:33:55 -0800 | [diff] [blame] | 595 | CDF_STATUS hif_open(enum ath_hal_bus_type bus_type); |
Prakash Dhavali | d5c9f1c | 2015-11-08 19:04:44 -0800 | [diff] [blame] | 596 | void hif_close(void *hif_ctx); |
| 597 | CDF_STATUS hif_enable(void *hif_ctx, struct device *dev, void *bdev, |
| 598 | const hif_bus_id *bid, enum ath_hal_bus_type bus_type, |
| 599 | enum hif_enable_type type); |
| 600 | void hif_disable(void *hif_ctx, enum hif_disable_type type); |
| 601 | void hif_enable_power_gating(void *hif_ctx); |
Houston Hoffman | 9078a15 | 2015-11-02 16:15:02 -0800 | [diff] [blame] | 602 | |
| 603 | #ifdef FEATURE_RUNTIME_PM |
| 604 | struct hif_pm_runtime_lock; |
| 605 | int hif_pm_runtime_get(void *hif_ctx); |
Houston Hoffman | f460785 | 2015-12-17 17:14:40 -0800 | [diff] [blame] | 606 | void hif_pm_runtime_get_noresume(void *hif_ctx); |
Houston Hoffman | 9078a15 | 2015-11-02 16:15:02 -0800 | [diff] [blame] | 607 | int hif_pm_runtime_put(void *hif_ctx); |
| 608 | struct hif_pm_runtime_lock *hif_runtime_lock_init(const char *name); |
| 609 | void hif_runtime_lock_deinit(struct hif_pm_runtime_lock *lock); |
| 610 | int hif_pm_runtime_prevent_suspend(void *ol_sc, |
| 611 | struct hif_pm_runtime_lock *lock); |
| 612 | int hif_pm_runtime_allow_suspend(void *ol_sc, |
| 613 | struct hif_pm_runtime_lock *lock); |
| 614 | int hif_pm_runtime_prevent_suspend_timeout(void *ol_sc, |
| 615 | struct hif_pm_runtime_lock *lock, unsigned int delay); |
| 616 | #else |
| 617 | struct hif_pm_runtime_lock { |
| 618 | const char *name; |
| 619 | }; |
Houston Hoffman | f460785 | 2015-12-17 17:14:40 -0800 | [diff] [blame] | 620 | |
| 621 | static inline void hif_pm_runtime_get_noresume(void *hif_ctx) |
| 622 | {} |
| 623 | |
Houston Hoffman | 9078a15 | 2015-11-02 16:15:02 -0800 | [diff] [blame] | 624 | static inline int hif_pm_runtime_get(void *hif_ctx) |
| 625 | { return 0; } |
| 626 | static inline int hif_pm_runtime_put(void *hif_ctx) |
| 627 | { return 0; } |
| 628 | static inline struct hif_pm_runtime_lock *hif_runtime_lock_init( |
| 629 | const char *name) |
| 630 | { return NULL; } |
| 631 | static inline void hif_runtime_lock_deinit(struct hif_pm_runtime_lock *lock) |
| 632 | {} |
| 633 | |
| 634 | static inline int hif_pm_runtime_prevent_suspend(void *ol_sc, |
| 635 | struct hif_pm_runtime_lock *lock) |
| 636 | { return 0; } |
| 637 | static inline int hif_pm_runtime_allow_suspend(void *ol_sc, |
| 638 | struct hif_pm_runtime_lock *lock) |
| 639 | { return 0; } |
| 640 | static inline int hif_pm_runtime_prevent_suspend_timeout(void *ol_sc, |
| 641 | struct hif_pm_runtime_lock *lock, unsigned int delay) |
| 642 | { return 0; } |
| 643 | #endif |
| 644 | |
Houston Hoffman | 62aa58d | 2015-11-02 21:14:55 -0800 | [diff] [blame] | 645 | void hif_enable_power_management(void *hif_ctx); |
Houston Hoffman | 53b34c4 | 2015-11-18 15:51:32 -0800 | [diff] [blame] | 646 | void hif_disable_power_management(void *hif_ctx); |
Houston Hoffman | 78467a8 | 2016-01-05 20:08:56 -0800 | [diff] [blame] | 647 | |
Prakash Dhavali | d5c9f1c | 2015-11-08 19:04:44 -0800 | [diff] [blame] | 648 | void hif_vote_link_down(void); |
| 649 | void hif_vote_link_up(void); |
| 650 | bool hif_can_suspend_link(void); |
Houston Hoffman | 78467a8 | 2016-01-05 20:08:56 -0800 | [diff] [blame] | 651 | |
| 652 | int hif_bus_resume(void); |
| 653 | int hif_bus_suspend(void); |
Houston Hoffman | 692cc05 | 2015-11-10 18:42:47 -0800 | [diff] [blame] | 654 | |
| 655 | #ifdef FEATURE_RUNTIME_PM |
Houston Hoffman | 78467a8 | 2016-01-05 20:08:56 -0800 | [diff] [blame] | 656 | int hif_pre_runtime_suspend(void); |
| 657 | void hif_pre_runtime_resume(void); |
| 658 | int hif_runtime_suspend(void); |
| 659 | int hif_runtime_resume(void); |
| 660 | void hif_process_runtime_suspend_success(void); |
| 661 | void hif_process_runtime_suspend_failure(void); |
| 662 | void hif_process_runtime_resume_success(void); |
Houston Hoffman | 692cc05 | 2015-11-10 18:42:47 -0800 | [diff] [blame] | 663 | #endif |
| 664 | |
Govind Singh | 2443fb3 | 2016-01-13 17:44:48 +0530 | [diff] [blame] | 665 | int hif_dump_registers(struct ol_softc *scn); |
Prakash Dhavali | d5c9f1c | 2015-11-08 19:04:44 -0800 | [diff] [blame] | 666 | int ol_copy_ramdump(struct ol_softc *scn); |
| 667 | void hif_pktlogmod_exit(void *hif_ctx); |
| 668 | void hif_crash_shutdown(void *hif_ctx); |
Komal Seelam | 91553ce | 2016-01-27 18:57:10 +0530 | [diff] [blame^] | 669 | void hif_get_hw_info(struct ol_softc *scn, u32 *version, u32 *revision, |
| 670 | const char **target_name); |
| 671 | struct hif_target_info *hif_get_target_info_handle(struct ol_softc *scn); |
| 672 | struct hif_config_info *hif_get_ini_handle(struct ol_softc *scn); |
Prakash Dhavali | d5c9f1c | 2015-11-08 19:04:44 -0800 | [diff] [blame] | 673 | #ifdef __cplusplus |
| 674 | } |
| 675 | #endif |
| 676 | #endif /* _HIF_H_ */ |