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gerrit-public.fairphone.software / platform / vendor / qcom-opensource / wlan / qcacld-3.0 / ed1efd9653a47820382b65cce4a1b4bfec5a8df2 / . / core / mac / src / cfg / cfg_proc_msg.c
blob: 5b74e20b8f271cb95e476f0ff3b890b28265465c [file] [log] [blame]
Prakash Dhavali7090c5f2015-11-02 17:55:19 -0800[diff] [blame]1/*
Rajeev Kumar416b73f2017-01-21 16:45:21 -0800[diff] [blame]2 * Copyright (c) 2011-2017 The Linux Foundation. All rights reserved.
Prakash Dhavali7090c5f2015-11-02 17:55:19 -0800[diff] [blame]3 *
4 * Previously licensed under the ISC license by Qualcomm Atheros, Inc.
5 *
6 *
7 * Permission to use, copy, modify, and/or distribute this software for
8 * any purpose with or without fee is hereby granted, provided that the
9 * above copyright notice and this permission notice appear in all
10 * copies.
11 *
12 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
13 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
14 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
15 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
16 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
17 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
18 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
19 * PERFORMANCE OF THIS SOFTWARE.
20 */
21
22/*
23 * This file was originally distributed by Qualcomm Atheros, Inc.
24 * under proprietary terms before Copyright ownership was assigned
25 * to the Linux Foundation.
26 */
27
28/*
29 * This file contains CFG functions for processing host messages.
30 */
31#include "cds_api.h"
32#include "ani_global.h"
33#include "cfg_priv.h"
34#include "cfg_debug.h"
35#include "wma_types.h"
36
37cgstatic cfg_static[CFG_PARAM_MAX_NUM] = {
38 {WNI_CFG_STA_ID,
39 CFG_CTL_VALID | CFG_CTL_RE | CFG_CTL_WE | CFG_CTL_RELOAD |
40 CFG_CTL_NTF_HAL,
41 0, 255, 1},
Prakash Dhavali7090c5f2015-11-02 17:55:19 -0800[diff] [blame]42 {WNI_CFG_CFP_PERIOD,
43 CFG_CTL_VALID | CFG_CTL_RE | CFG_CTL_INT,
44 WNI_CFG_CFP_PERIOD_STAMIN,
45 WNI_CFG_CFP_PERIOD_STAMAX,
46 WNI_CFG_CFP_PERIOD_STADEF},
47 {WNI_CFG_CFP_MAX_DURATION,
48 CFG_CTL_VALID | CFG_CTL_RE | CFG_CTL_INT,
49 WNI_CFG_CFP_MAX_DURATION_STAMIN,
50 WNI_CFG_CFP_MAX_DURATION_STAMAX,
51 WNI_CFG_CFP_MAX_DURATION_STADEF},
52 {WNI_CFG_SSID,
53 CFG_CTL_VALID | CFG_CTL_RE | CFG_CTL_WE | CFG_CTL_RESTART,
54 0, 255, 6},
55 {WNI_CFG_BEACON_INTERVAL,
56 CFG_CTL_VALID | CFG_CTL_RE | CFG_CTL_WE | CFG_CTL_INT |
57 CFG_CTL_NTF_SCH,
58 WNI_CFG_BEACON_INTERVAL_STAMIN,
59 WNI_CFG_BEACON_INTERVAL_STAMAX,
60 WNI_CFG_BEACON_INTERVAL_STADEF},
61 {WNI_CFG_DTIM_PERIOD,
62 CFG_CTL_VALID | CFG_CTL_RE | CFG_CTL_INT,
63 WNI_CFG_DTIM_PERIOD_STAMIN,
64 WNI_CFG_DTIM_PERIOD_STAMAX,
65 WNI_CFG_DTIM_PERIOD_STADEF},
66 {WNI_CFG_WEP_KEY_LENGTH,
67 CFG_CTL_VALID | CFG_CTL_RE | CFG_CTL_WE | CFG_CTL_INT |
68 CFG_CTL_RESTART,
69 WNI_CFG_WEP_KEY_LENGTH_STAMIN,
70 WNI_CFG_WEP_KEY_LENGTH_STAMAX,
71 WNI_CFG_WEP_KEY_LENGTH_STADEF},
72 {WNI_CFG_WEP_DEFAULT_KEY_1,
73 CFG_CTL_VALID | CFG_CTL_WE | CFG_CTL_RESTART,
74 0, 65535, 0},
75 {WNI_CFG_WEP_DEFAULT_KEY_2,
76 CFG_CTL_VALID | CFG_CTL_WE | CFG_CTL_RESTART,
77 1, 1, 1},
78 {WNI_CFG_WEP_DEFAULT_KEY_3,
79 CFG_CTL_VALID | CFG_CTL_WE | CFG_CTL_RESTART,
80 0, 5, 5},
81 {WNI_CFG_WEP_DEFAULT_KEY_4,
82 CFG_CTL_VALID | CFG_CTL_WE | CFG_CTL_RESTART,
83 0, 1, 0},
84 {WNI_CFG_WEP_DEFAULT_KEYID,
85 CFG_CTL_VALID | CFG_CTL_RE | CFG_CTL_WE | CFG_CTL_INT |
86 CFG_CTL_NTF_LIM,
87 WNI_CFG_WEP_DEFAULT_KEYID_STAMIN,
88 WNI_CFG_WEP_DEFAULT_KEYID_STAMAX,
89 WNI_CFG_WEP_DEFAULT_KEYID_STADEF},
90 {WNI_CFG_EXCLUDE_UNENCRYPTED,
91 CFG_CTL_VALID | CFG_CTL_RE | CFG_CTL_WE | CFG_CTL_INT |
92 CFG_CTL_NTF_LIM,
93 WNI_CFG_EXCLUDE_UNENCRYPTED_STAMIN,
94 WNI_CFG_EXCLUDE_UNENCRYPTED_STAMAX,
95 WNI_CFG_EXCLUDE_UNENCRYPTED_STADEF},
96 {WNI_CFG_RTS_THRESHOLD,
97 CFG_CTL_VALID | CFG_CTL_RE | CFG_CTL_WE | CFG_CTL_INT |
98 CFG_CTL_NTF_HAL,
99 WNI_CFG_RTS_THRESHOLD_STAMIN,
100 WNI_CFG_RTS_THRESHOLD_STAMAX,
101 WNI_CFG_RTS_THRESHOLD_STADEF},
102 {WNI_CFG_SHORT_RETRY_LIMIT,
103 CFG_CTL_VALID | CFG_CTL_RE | CFG_CTL_WE | CFG_CTL_INT |
104 CFG_CTL_NTF_HAL,
105 WNI_CFG_SHORT_RETRY_LIMIT_STAMIN,
106 WNI_CFG_SHORT_RETRY_LIMIT_STAMAX,
107 WNI_CFG_SHORT_RETRY_LIMIT_STADEF},
108 {WNI_CFG_LONG_RETRY_LIMIT,
109 CFG_CTL_VALID | CFG_CTL_RE | CFG_CTL_WE | CFG_CTL_INT |
110 CFG_CTL_NTF_HAL,
111 WNI_CFG_LONG_RETRY_LIMIT_STAMIN,
112 WNI_CFG_LONG_RETRY_LIMIT_STAMAX,
113 WNI_CFG_LONG_RETRY_LIMIT_STADEF},
114 {WNI_CFG_FRAGMENTATION_THRESHOLD,
115 CFG_CTL_VALID | CFG_CTL_RE | CFG_CTL_WE | CFG_CTL_INT |
116 CFG_CTL_NTF_HAL,
117 WNI_CFG_FRAGMENTATION_THRESHOLD_STAMIN,
118 WNI_CFG_FRAGMENTATION_THRESHOLD_STAMAX,
119 WNI_CFG_FRAGMENTATION_THRESHOLD_STADEF},
120 {WNI_CFG_ACTIVE_MINIMUM_CHANNEL_TIME,
121 CFG_CTL_VALID | CFG_CTL_RE | CFG_CTL_WE | CFG_CTL_INT,
122 WNI_CFG_ACTIVE_MINIMUM_CHANNEL_TIME_STAMIN,
123 WNI_CFG_ACTIVE_MINIMUM_CHANNEL_TIME_STAMAX,
124 WNI_CFG_ACTIVE_MINIMUM_CHANNEL_TIME_STADEF},
125 {WNI_CFG_ACTIVE_MAXIMUM_CHANNEL_TIME,
126 CFG_CTL_VALID | CFG_CTL_RE | CFG_CTL_WE | CFG_CTL_INT,
127 WNI_CFG_ACTIVE_MAXIMUM_CHANNEL_TIME_STAMIN,
128 WNI_CFG_ACTIVE_MAXIMUM_CHANNEL_TIME_STAMAX,
129 WNI_CFG_ACTIVE_MAXIMUM_CHANNEL_TIME_STADEF},
130 {WNI_CFG_PASSIVE_MINIMUM_CHANNEL_TIME,
131 CFG_CTL_VALID | CFG_CTL_RE | CFG_CTL_WE | CFG_CTL_INT,
132 WNI_CFG_PASSIVE_MINIMUM_CHANNEL_TIME_STAMIN,
133 WNI_CFG_PASSIVE_MINIMUM_CHANNEL_TIME_STAMAX,
134 WNI_CFG_PASSIVE_MINIMUM_CHANNEL_TIME_STADEF},
135 {WNI_CFG_PASSIVE_MAXIMUM_CHANNEL_TIME,
136 CFG_CTL_VALID | CFG_CTL_RE | CFG_CTL_WE | CFG_CTL_INT,
137 WNI_CFG_PASSIVE_MAXIMUM_CHANNEL_TIME_STAMIN,
138 WNI_CFG_PASSIVE_MAXIMUM_CHANNEL_TIME_STAMAX,
139 WNI_CFG_PASSIVE_MAXIMUM_CHANNEL_TIME_STADEF},
140 {WNI_CFG_JOIN_FAILURE_TIMEOUT,
141 CFG_CTL_VALID | CFG_CTL_RE | CFG_CTL_WE | CFG_CTL_INT,
142 WNI_CFG_JOIN_FAILURE_TIMEOUT_STAMIN,
143 WNI_CFG_JOIN_FAILURE_TIMEOUT_STAMAX,
144 WNI_CFG_JOIN_FAILURE_TIMEOUT_STADEF},
145 {WNI_CFG_AUTHENTICATE_FAILURE_TIMEOUT,
146 CFG_CTL_VALID | CFG_CTL_RE | CFG_CTL_WE | CFG_CTL_INT,
147 WNI_CFG_AUTHENTICATE_FAILURE_TIMEOUT_STAMIN,
148 WNI_CFG_AUTHENTICATE_FAILURE_TIMEOUT_STAMAX,
149 WNI_CFG_AUTHENTICATE_FAILURE_TIMEOUT_STADEF},
150 {WNI_CFG_AUTHENTICATE_RSP_TIMEOUT,
151 CFG_CTL_VALID | CFG_CTL_RE | CFG_CTL_WE | CFG_CTL_INT,
152 WNI_CFG_AUTHENTICATE_RSP_TIMEOUT_STAMIN,
153 WNI_CFG_AUTHENTICATE_RSP_TIMEOUT_STAMAX,
154 WNI_CFG_AUTHENTICATE_RSP_TIMEOUT_STADEF},
155 {WNI_CFG_ASSOCIATION_FAILURE_TIMEOUT,
156 CFG_CTL_VALID | CFG_CTL_RE | CFG_CTL_WE | CFG_CTL_INT |
157 CFG_CTL_NTF_LIM,
158 WNI_CFG_ASSOCIATION_FAILURE_TIMEOUT_STAMIN,
159 WNI_CFG_ASSOCIATION_FAILURE_TIMEOUT_STAMAX,
160 WNI_CFG_ASSOCIATION_FAILURE_TIMEOUT_STADEF},
161 {WNI_CFG_REASSOCIATION_FAILURE_TIMEOUT,
162 CFG_CTL_VALID | CFG_CTL_RE | CFG_CTL_WE | CFG_CTL_INT,
163 WNI_CFG_REASSOCIATION_FAILURE_TIMEOUT_STAMIN,
164 WNI_CFG_REASSOCIATION_FAILURE_TIMEOUT_STAMAX,
165 WNI_CFG_REASSOCIATION_FAILURE_TIMEOUT_STADEF},
Prakash Dhavali7090c5f2015-11-02 17:55:19 -0800[diff] [blame]166 {WNI_CFG_PS_ENABLE_BCN_FILTER,
167 CFG_CTL_VALID | CFG_CTL_RE | CFG_CTL_WE | CFG_CTL_INT |
168 CFG_CTL_NTF_HAL,
169 WNI_CFG_PS_ENABLE_BCN_FILTER_STAMIN,
170 WNI_CFG_PS_ENABLE_BCN_FILTER_STAMAX,
171 WNI_CFG_PS_ENABLE_BCN_FILTER_STADEF},
172 {WNI_CFG_PS_ENABLE_HEART_BEAT,
173 CFG_CTL_VALID | CFG_CTL_RE | CFG_CTL_WE | CFG_CTL_INT |
174 CFG_CTL_NTF_HAL,
175 WNI_CFG_PS_ENABLE_HEART_BEAT_STAMIN,
176 WNI_CFG_PS_ENABLE_HEART_BEAT_STAMAX,
177 WNI_CFG_PS_ENABLE_HEART_BEAT_STADEF},
178 {WNI_CFG_PS_ENABLE_RSSI_MONITOR,
179 CFG_CTL_VALID | CFG_CTL_RE | CFG_CTL_WE | CFG_CTL_INT |
180 CFG_CTL_NTF_HAL,
181 WNI_CFG_PS_ENABLE_RSSI_MONITOR_STAMIN,
182 WNI_CFG_PS_ENABLE_RSSI_MONITOR_STAMAX,
183 WNI_CFG_PS_ENABLE_RSSI_MONITOR_STADEF},
184 {WNI_CFG_PS_DATA_INACTIVITY_TIMEOUT,
185 CFG_CTL_VALID | CFG_CTL_RE | CFG_CTL_WE | CFG_CTL_INT |
186 CFG_CTL_NTF_HAL,
187 WNI_CFG_PS_DATA_INACTIVITY_TIMEOUT_STAMIN,
188 WNI_CFG_PS_DATA_INACTIVITY_TIMEOUT_STAMAX,
189 WNI_CFG_PS_DATA_INACTIVITY_TIMEOUT_STADEF},
190 {WNI_CFG_RF_SETTLING_TIME_CLK,
191 CFG_CTL_VALID | CFG_CTL_RE | CFG_CTL_WE | CFG_CTL_INT |
192 CFG_CTL_NTF_HAL,
193 WNI_CFG_RF_SETTLING_TIME_CLK_STAMIN,
194 WNI_CFG_RF_SETTLING_TIME_CLK_STAMAX,
195 WNI_CFG_RF_SETTLING_TIME_CLK_STADEF},
196 {WNI_CFG_SUPPORTED_RATES_11B,
197 CFG_CTL_VALID | CFG_CTL_RE,
198 0, 3, 1},
199 {WNI_CFG_SUPPORTED_RATES_11A, CFG_CTL_VALID | CFG_CTL_RE,
200 0, 255, 15},
201 {WNI_CFG_PHY_MODE,
202 CFG_CTL_VALID | CFG_CTL_RE | CFG_CTL_WE | CFG_CTL_INT |
203 CFG_CTL_RESTART,
204 WNI_CFG_PHY_MODE_STAMIN,
205 WNI_CFG_PHY_MODE_STAMAX,
206 WNI_CFG_PHY_MODE_STADEF},
207 {WNI_CFG_DOT11_MODE,
208 CFG_CTL_VALID | CFG_CTL_RE | CFG_CTL_WE | CFG_CTL_INT | CFG_CTL_RESTART |
209 CFG_CTL_NTF_LIM,
210 WNI_CFG_DOT11_MODE_STAMIN,
211 WNI_CFG_DOT11_MODE_STAMAX,
212 WNI_CFG_DOT11_MODE_STADEF},
213 {WNI_CFG_OPERATIONAL_RATE_SET,
214 CFG_CTL_VALID | CFG_CTL_RE | CFG_CTL_WE | CFG_CTL_RESTART,
215 0, 1, 1},
216 {WNI_CFG_EXTENDED_OPERATIONAL_RATE_SET,
217 CFG_CTL_VALID | CFG_CTL_RE | CFG_CTL_WE | CFG_CTL_RESTART,
218 0, 65535, 65534},
219 {WNI_CFG_PROPRIETARY_OPERATIONAL_RATE_SET,
220 CFG_CTL_VALID | CFG_CTL_RE | CFG_CTL_WE | CFG_CTL_RESTART,
221 0, 0, 0},
222 {WNI_CFG_LISTEN_INTERVAL,
223 CFG_CTL_VALID | CFG_CTL_RE | CFG_CTL_WE | CFG_CTL_INT |
224 CFG_CTL_RESTART,
225 WNI_CFG_LISTEN_INTERVAL_STAMIN,
226 WNI_CFG_LISTEN_INTERVAL_STAMAX,
227 WNI_CFG_LISTEN_INTERVAL_STADEF},
228 {WNI_CFG_VALID_CHANNEL_LIST,
229 CFG_CTL_VALID | CFG_CTL_RE | CFG_CTL_WE | CFG_CTL_RESTART |
230 CFG_CTL_NTF_LIM,
231 0, 1, 1},
232 {WNI_CFG_CURRENT_CHANNEL,
233 CFG_CTL_VALID | CFG_CTL_RE | CFG_CTL_INT,
234 WNI_CFG_CURRENT_CHANNEL_STAMIN,
235 WNI_CFG_CURRENT_CHANNEL_STAMAX,
236 WNI_CFG_CURRENT_CHANNEL_STADEF},
Prakash Dhavali7090c5f2015-11-02 17:55:19 -0800[diff] [blame]237 {WNI_CFG_DEFAULT_RATE_INDEX_24GHZ,
238 CFG_CTL_VALID | CFG_CTL_RE | CFG_CTL_WE | CFG_CTL_INT,
239 WNI_CFG_DEFAULT_RATE_INDEX_24GHZ_STAMIN,
240 WNI_CFG_DEFAULT_RATE_INDEX_24GHZ_STAMAX,
241 WNI_CFG_DEFAULT_RATE_INDEX_24GHZ_STADEF},
Prakash Dhavali7090c5f2015-11-02 17:55:19 -0800[diff] [blame]242 {WNI_CFG_FIXED_RATE,
243 CFG_CTL_VALID | CFG_CTL_RE | CFG_CTL_WE | CFG_CTL_INT |
244 CFG_CTL_NTF_HAL,
245 WNI_CFG_FIXED_RATE_STAMIN,
246 WNI_CFG_FIXED_RATE_STAMAX,
247 WNI_CFG_FIXED_RATE_STADEF},
Prakash Dhavali7090c5f2015-11-02 17:55:19 -0800[diff] [blame]248 {WNI_CFG_APSD_ENABLED,
249 CFG_CTL_VALID | CFG_CTL_RE | CFG_CTL_WE | CFG_CTL_INT,
250 WNI_CFG_APSD_ENABLED_STAMIN,
251 WNI_CFG_APSD_ENABLED_STAMAX,
252 WNI_CFG_APSD_ENABLED_STADEF},
253 {WNI_CFG_SHARED_KEY_AUTH_ENABLE,
254 CFG_CTL_VALID | CFG_CTL_RE | CFG_CTL_WE | CFG_CTL_INT,
255 WNI_CFG_SHARED_KEY_AUTH_ENABLE_STAMIN,
256 WNI_CFG_SHARED_KEY_AUTH_ENABLE_STAMAX,
257 WNI_CFG_SHARED_KEY_AUTH_ENABLE_STADEF},
258 {WNI_CFG_OPEN_SYSTEM_AUTH_ENABLE,
259 CFG_CTL_VALID | CFG_CTL_RE | CFG_CTL_WE | CFG_CTL_INT,
260 WNI_CFG_OPEN_SYSTEM_AUTH_ENABLE_STAMIN,
261 WNI_CFG_OPEN_SYSTEM_AUTH_ENABLE_STAMAX,
262 WNI_CFG_OPEN_SYSTEM_AUTH_ENABLE_STADEF},
263 {WNI_CFG_AUTHENTICATION_TYPE,
264 CFG_CTL_VALID | CFG_CTL_RE | CFG_CTL_WE | CFG_CTL_INT |
265 CFG_CTL_RESTART,
266 WNI_CFG_AUTHENTICATION_TYPE_STAMIN,
267 WNI_CFG_AUTHENTICATION_TYPE_STAMAX,
268 WNI_CFG_AUTHENTICATION_TYPE_STADEF},
Prakash Dhavali7090c5f2015-11-02 17:55:19 -0800[diff] [blame]269 {WNI_CFG_PRIVACY_ENABLED,
270 CFG_CTL_VALID | CFG_CTL_RE | CFG_CTL_WE | CFG_CTL_INT |
271 CFG_CTL_RESTART,
272 WNI_CFG_PRIVACY_ENABLED_STAMIN,
273 WNI_CFG_PRIVACY_ENABLED_STAMAX,
274 WNI_CFG_PRIVACY_ENABLED_STADEF},
275 {WNI_CFG_SHORT_PREAMBLE,
276 CFG_CTL_VALID | CFG_CTL_RE | CFG_CTL_WE | CFG_CTL_INT |
277 CFG_CTL_RESTART,
278 WNI_CFG_SHORT_PREAMBLE_STAMIN,
279 WNI_CFG_SHORT_PREAMBLE_STAMAX,
280 WNI_CFG_SHORT_PREAMBLE_STADEF},
Prakash Dhavali7090c5f2015-11-02 17:55:19 -0800[diff] [blame]281 {WNI_CFG_ACCEPT_SHORT_SLOT_ASSOC_ONLY,
282 CFG_CTL_VALID | CFG_CTL_RE | CFG_CTL_WE | CFG_CTL_INT |
283 CFG_CTL_RESTART,
284 WNI_CFG_ACCEPT_SHORT_SLOT_ASSOC_ONLY_STAMIN,
285 WNI_CFG_ACCEPT_SHORT_SLOT_ASSOC_ONLY_STAMAX,
286 WNI_CFG_ACCEPT_SHORT_SLOT_ASSOC_ONLY_STADEF},
287 {WNI_CFG_QOS_ENABLED,
288 CFG_CTL_VALID | CFG_CTL_RE | CFG_CTL_WE | CFG_CTL_INT |
289 CFG_CTL_RESTART,
290 WNI_CFG_QOS_ENABLED_STAMIN,
291 WNI_CFG_QOS_ENABLED_STAMAX,
292 WNI_CFG_QOS_ENABLED_STADEF},
293 {WNI_CFG_HCF_ENABLED,
294 CFG_CTL_VALID | CFG_CTL_RE | CFG_CTL_WE | CFG_CTL_INT |
295 CFG_CTL_RESTART,
296 WNI_CFG_HCF_ENABLED_STAMIN,
297 WNI_CFG_HCF_ENABLED_STAMAX,
298 WNI_CFG_HCF_ENABLED_STADEF},
299 {WNI_CFG_RSN_ENABLED,
300 CFG_CTL_VALID | CFG_CTL_RE | CFG_CTL_WE | CFG_CTL_INT |
301 CFG_CTL_RESTART,
302 WNI_CFG_RSN_ENABLED_STAMIN,
303 WNI_CFG_RSN_ENABLED_STAMAX,
304 WNI_CFG_RSN_ENABLED_STADEF},
305 {WNI_CFG_MAX_NUM_PRE_AUTH,
306 CFG_CTL_VALID | CFG_CTL_RE | CFG_CTL_WE | CFG_CTL_INT |
307 CFG_CTL_RESTART,
308 WNI_CFG_MAX_NUM_PRE_AUTH_STAMIN,
309 WNI_CFG_MAX_NUM_PRE_AUTH_STAMAX,
310 WNI_CFG_MAX_NUM_PRE_AUTH_STADEF},
Prakash Dhavali7090c5f2015-11-02 17:55:19 -0800[diff] [blame]311 {WNI_CFG_HEART_BEAT_THRESHOLD,
312 CFG_CTL_VALID | CFG_CTL_RE | CFG_CTL_WE | CFG_CTL_INT |
313 CFG_CTL_NTF_LIM,
314 WNI_CFG_HEART_BEAT_THRESHOLD_STAMIN,
315 WNI_CFG_HEART_BEAT_THRESHOLD_STAMAX,
316 WNI_CFG_HEART_BEAT_THRESHOLD_STADEF},
317 {WNI_CFG_PROBE_AFTER_HB_FAIL_TIMEOUT,
318 CFG_CTL_VALID | CFG_CTL_RE | CFG_CTL_WE |
319 CFG_CTL_INT,
320 WNI_CFG_PROBE_AFTER_HB_FAIL_TIMEOUT_STAMIN,
321 WNI_CFG_PROBE_AFTER_HB_FAIL_TIMEOUT_STAMAX,
322 WNI_CFG_PROBE_AFTER_HB_FAIL_TIMEOUT_STADEF},
Prakash Dhavali7090c5f2015-11-02 17:55:19 -0800[diff] [blame]323 {WNI_CFG_MANUFACTURER_NAME,
324 CFG_CTL_VALID | CFG_CTL_RE,
325 0, 0, 0},
326 {WNI_CFG_MODEL_NUMBER,
327 CFG_CTL_VALID | CFG_CTL_RE,
328 0, 0, 0},
329 {WNI_CFG_MODEL_NAME,
330 CFG_CTL_VALID | CFG_CTL_RE,
331 0, 0, 0},
332 {WNI_CFG_MANUFACTURER_PRODUCT_NAME,
333 CFG_CTL_VALID | CFG_CTL_RE,
334 0, 0, 0},
335 {WNI_CFG_MANUFACTURER_PRODUCT_VERSION,
336 CFG_CTL_VALID | CFG_CTL_RE,
337 0, 0, 0},
338 {WNI_CFG_11D_ENABLED,
339 CFG_CTL_VALID | CFG_CTL_RE | CFG_CTL_WE | CFG_CTL_INT |
340 CFG_CTL_RESTART,
341 WNI_CFG_11D_ENABLED_STAMIN,
342 WNI_CFG_11D_ENABLED_STAMAX,
343 WNI_CFG_11D_ENABLED_STADEF},
344 {WNI_CFG_MAX_TX_POWER_2_4,
345 CFG_CTL_VALID | CFG_CTL_RE | CFG_CTL_WE,
346 0, 0, 0},
347 {WNI_CFG_MAX_TX_POWER_5,
348 CFG_CTL_VALID | CFG_CTL_RE | CFG_CTL_WE,
349 0, 0, 0},
Prakash Dhavali7090c5f2015-11-02 17:55:19 -0800[diff] [blame]350 {WNI_CFG_CURRENT_TX_POWER_LEVEL,
351 CFG_CTL_VALID | CFG_CTL_RE | CFG_CTL_WE | CFG_CTL_INT,
352 WNI_CFG_CURRENT_TX_POWER_LEVEL_STAMIN,
353 WNI_CFG_CURRENT_TX_POWER_LEVEL_STAMAX,
354 WNI_CFG_CURRENT_TX_POWER_LEVEL_STADEF},
355 {WNI_CFG_NEW_BSS_FOUND_IND,
356 CFG_CTL_VALID | CFG_CTL_RE | CFG_CTL_WE | CFG_CTL_INT,
357 WNI_CFG_NEW_BSS_FOUND_IND_STAMIN,
358 WNI_CFG_NEW_BSS_FOUND_IND_STAMAX,
359 WNI_CFG_NEW_BSS_FOUND_IND_STADEF},
Prakash Dhavali7090c5f2015-11-02 17:55:19 -0800[diff] [blame]360 {WNI_CFG_COUNTRY_CODE,
361 CFG_CTL_VALID | CFG_CTL_RE | CFG_CTL_WE,
362 0, 0, 0},
363 {WNI_CFG_11H_ENABLED,
364 CFG_CTL_VALID | CFG_CTL_RE | CFG_CTL_WE | CFG_CTL_INT |
365 CFG_CTL_RESTART,
366 WNI_CFG_11H_ENABLED_STAMIN,
367 WNI_CFG_11H_ENABLED_STAMAX,
368 WNI_CFG_11H_ENABLED_STADEF},
369 {WNI_CFG_WT_CNF_TIMEOUT,
370 CFG_CTL_VALID | CFG_CTL_RE | CFG_CTL_WE | CFG_CTL_INT,
371 WNI_CFG_WT_CNF_TIMEOUT_STAMIN,
372 WNI_CFG_WT_CNF_TIMEOUT_STAMAX,
373 WNI_CFG_WT_CNF_TIMEOUT_STADEF},
Prakash Dhavali7090c5f2015-11-02 17:55:19 -0800[diff] [blame]374 {WNI_CFG_LOG_LEVEL,
375 CFG_CTL_VALID | CFG_CTL_RE | CFG_CTL_WE | CFG_CTL_INT,
376 WNI_CFG_LOG_LEVEL_STAMIN,
377 WNI_CFG_LOG_LEVEL_STAMAX,
378 WNI_CFG_LOG_LEVEL_STADEF},
379 {WNI_CFG_OLBC_DETECT_TIMEOUT,
380 CFG_CTL_VALID | CFG_CTL_RE | CFG_CTL_WE | CFG_CTL_INT,
381 WNI_CFG_OLBC_DETECT_TIMEOUT_STAMIN,
382 WNI_CFG_OLBC_DETECT_TIMEOUT_STAMAX,
383 WNI_CFG_OLBC_DETECT_TIMEOUT_STADEF},
384 {WNI_CFG_PROTECTION_ENABLED,
385 CFG_CTL_VALID | CFG_CTL_RE | CFG_CTL_WE | CFG_CTL_INT |
386 CFG_CTL_RESTART | CFG_CTL_NTF_LIM,
387 WNI_CFG_PROTECTION_ENABLED_STAMIN,
388 WNI_CFG_PROTECTION_ENABLED_STAMAX,
389 WNI_CFG_PROTECTION_ENABLED_STADEF},
390 {WNI_CFG_11G_PROTECTION_ALWAYS,
391 CFG_CTL_VALID | CFG_CTL_RE | CFG_CTL_WE | CFG_CTL_INT |
392 CFG_CTL_RESTART,
393 WNI_CFG_11G_PROTECTION_ALWAYS_STAMIN,
394 WNI_CFG_11G_PROTECTION_ALWAYS_STAMAX,
395 WNI_CFG_11G_PROTECTION_ALWAYS_STADEF},
396 {WNI_CFG_FORCE_POLICY_PROTECTION,
397 CFG_CTL_VALID | CFG_CTL_RE | CFG_CTL_WE | CFG_CTL_INT |
398 CFG_CTL_RESTART | CFG_CTL_NTF_HAL,
399 WNI_CFG_FORCE_POLICY_PROTECTION_STAMIN,
400 WNI_CFG_FORCE_POLICY_PROTECTION_STAMAX,
401 WNI_CFG_FORCE_POLICY_PROTECTION_STADEF},
402 {WNI_CFG_11G_SHORT_PREAMBLE_ENABLED,
403 CFG_CTL_VALID | CFG_CTL_RE | CFG_CTL_WE | CFG_CTL_INT |
404 CFG_CTL_RESTART,
405 WNI_CFG_11G_SHORT_PREAMBLE_ENABLED_STAMIN,
406 WNI_CFG_11G_SHORT_PREAMBLE_ENABLED_STAMAX,
407 WNI_CFG_11G_SHORT_PREAMBLE_ENABLED_STADEF},
408 {WNI_CFG_11G_SHORT_SLOT_TIME_ENABLED,
409 CFG_CTL_VALID | CFG_CTL_RE | CFG_CTL_WE | CFG_CTL_INT |
410 CFG_CTL_RESTART,
411 WNI_CFG_11G_SHORT_SLOT_TIME_ENABLED_STAMIN,
412 WNI_CFG_11G_SHORT_SLOT_TIME_ENABLED_STAMAX,
413 WNI_CFG_11G_SHORT_SLOT_TIME_ENABLED_STADEF},
414 {WNI_CFG_11G_ONLY_POLICY,
415 CFG_CTL_VALID | CFG_CTL_RE | CFG_CTL_WE | CFG_CTL_INT,
416 WNI_CFG_11G_ONLY_POLICY_STAMIN,
417 WNI_CFG_11G_ONLY_POLICY_STAMAX,
418 WNI_CFG_11G_ONLY_POLICY_STADEF},
Prakash Dhavali7090c5f2015-11-02 17:55:19 -0800[diff] [blame]419 {WNI_CFG_WME_ENABLED,
420 CFG_CTL_VALID | CFG_CTL_RE | CFG_CTL_WE | CFG_CTL_INT |
421 CFG_CTL_RESTART,
422 WNI_CFG_WME_ENABLED_STAMIN,
423 WNI_CFG_WME_ENABLED_STAMAX,
424 WNI_CFG_WME_ENABLED_STADEF},
425 {WNI_CFG_ADDTS_RSP_TIMEOUT,
426 CFG_CTL_VALID | CFG_CTL_RE | CFG_CTL_WE | CFG_CTL_INT,
427 WNI_CFG_ADDTS_RSP_TIMEOUT_STAMIN,
428 WNI_CFG_ADDTS_RSP_TIMEOUT_STAMAX,
429 WNI_CFG_ADDTS_RSP_TIMEOUT_STADEF},
430 {WNI_CFG_MAX_SP_LENGTH,
431 CFG_CTL_VALID | CFG_CTL_RE | CFG_CTL_WE | CFG_CTL_INT,
432 WNI_CFG_MAX_SP_LENGTH_STAMIN,
433 WNI_CFG_MAX_SP_LENGTH_STAMAX,
434 WNI_CFG_MAX_SP_LENGTH_STADEF},
Prakash Dhavali7090c5f2015-11-02 17:55:19 -0800[diff] [blame]435 {WNI_CFG_WSM_ENABLED,
436 CFG_CTL_VALID | CFG_CTL_RE | CFG_CTL_WE | CFG_CTL_INT,
437 WNI_CFG_WSM_ENABLED_STAMIN,
438 WNI_CFG_WSM_ENABLED_STAMAX,
439 WNI_CFG_WSM_ENABLED_STADEF},
440 {WNI_CFG_EDCA_PROFILE,
441 CFG_CTL_VALID | CFG_CTL_RE | CFG_CTL_WE | CFG_CTL_INT |
442 CFG_CTL_NTF_SCH,
443 WNI_CFG_EDCA_PROFILE_STAMIN,
444 WNI_CFG_EDCA_PROFILE_STAMAX,
445 WNI_CFG_EDCA_PROFILE_STADEF},
446 {WNI_CFG_EDCA_ANI_ACBK_LOCAL,
447 CFG_CTL_VALID | CFG_CTL_RE | CFG_CTL_WE | CFG_CTL_RESTART,
448 0, 0, 0},
449 {WNI_CFG_EDCA_ANI_ACBE_LOCAL,
450 CFG_CTL_VALID | CFG_CTL_RE | CFG_CTL_WE | CFG_CTL_RESTART,
451 0, 0, 0},
452 {WNI_CFG_EDCA_ANI_ACVI_LOCAL,
453 CFG_CTL_VALID | CFG_CTL_RE | CFG_CTL_WE | CFG_CTL_RESTART,
454 0, 0, 0},
455 {WNI_CFG_EDCA_ANI_ACVO_LOCAL,
456 CFG_CTL_VALID | CFG_CTL_RE | CFG_CTL_WE | CFG_CTL_RESTART,
457 0, 0, 0},
458 {WNI_CFG_EDCA_ANI_ACBK,
459 CFG_CTL_VALID | CFG_CTL_RE | CFG_CTL_WE | CFG_CTL_RESTART,
460 0, 0, 0},
461 {WNI_CFG_EDCA_ANI_ACBE,
462 CFG_CTL_VALID | CFG_CTL_RE | CFG_CTL_WE | CFG_CTL_RESTART,
463 0, 0, 0},
464 {WNI_CFG_EDCA_ANI_ACVI,
465 CFG_CTL_VALID | CFG_CTL_RE | CFG_CTL_WE | CFG_CTL_RESTART,
466 0, 0, 0},
467 {WNI_CFG_EDCA_ANI_ACVO,
468 CFG_CTL_VALID | CFG_CTL_RE | CFG_CTL_WE | CFG_CTL_RESTART,
469 0, 0, 0},
470 {WNI_CFG_EDCA_WME_ACBK_LOCAL,
471 CFG_CTL_VALID | CFG_CTL_RE | CFG_CTL_WE | CFG_CTL_RESTART,
472 0, 0, 0},
473 {WNI_CFG_EDCA_WME_ACBE_LOCAL,
474 CFG_CTL_VALID | CFG_CTL_RE | CFG_CTL_WE | CFG_CTL_RESTART,
475 0, 0, 0},
476 {WNI_CFG_EDCA_WME_ACVI_LOCAL,
477 CFG_CTL_VALID | CFG_CTL_RE | CFG_CTL_WE | CFG_CTL_RESTART,
478 0, 0, 0},
479 {WNI_CFG_EDCA_WME_ACVO_LOCAL,
480 CFG_CTL_VALID | CFG_CTL_RE | CFG_CTL_WE | CFG_CTL_RESTART,
481 0, 0, 0},
482 {WNI_CFG_EDCA_WME_ACBK,
483 CFG_CTL_VALID | CFG_CTL_RE | CFG_CTL_WE | CFG_CTL_RESTART,
484 0, 0, 0},
485 {WNI_CFG_EDCA_WME_ACBE,
486 CFG_CTL_VALID | CFG_CTL_RE | CFG_CTL_WE | CFG_CTL_RESTART,
487 0, 0, 0},
488 {WNI_CFG_EDCA_WME_ACVI,
489 CFG_CTL_VALID | CFG_CTL_RE | CFG_CTL_WE | CFG_CTL_RESTART,
490 0, 0, 0},
491 {WNI_CFG_EDCA_WME_ACVO,
492 CFG_CTL_VALID | CFG_CTL_RE | CFG_CTL_WE | CFG_CTL_RESTART,
493 0, 0, 0},
Prakash Dhavali7090c5f2015-11-02 17:55:19 -0800[diff] [blame]494 {WNI_CFG_LOCAL_POWER_CONSTRAINT,
495 CFG_CTL_VALID | CFG_CTL_RE | CFG_CTL_WE | CFG_CTL_INT |
496 CFG_CTL_RESTART,
497 WNI_CFG_LOCAL_POWER_CONSTRAINT_STAMIN,
498 WNI_CFG_LOCAL_POWER_CONSTRAINT_STAMAX,
499 WNI_CFG_LOCAL_POWER_CONSTRAINT_STADEF},
500 {WNI_CFG_ADMIT_POLICY,
501 CFG_CTL_VALID | CFG_CTL_RE | CFG_CTL_WE | CFG_CTL_INT |
502 CFG_CTL_RESTART,
503 WNI_CFG_ADMIT_POLICY_STAMIN,
504 WNI_CFG_ADMIT_POLICY_STAMAX,
505 WNI_CFG_ADMIT_POLICY_STADEF},
506 {WNI_CFG_ADMIT_BWFACTOR,
507 CFG_CTL_VALID | CFG_CTL_RE | CFG_CTL_WE | CFG_CTL_INT |
508 CFG_CTL_RESTART,
509 WNI_CFG_ADMIT_BWFACTOR_STAMIN,
510 WNI_CFG_ADMIT_BWFACTOR_STAMAX,
511 WNI_CFG_ADMIT_BWFACTOR_STADEF},
Prakash Dhavali7090c5f2015-11-02 17:55:19 -0800[diff] [blame]512 {WNI_CFG_CHANNEL_BONDING_MODE,
513 CFG_CTL_VALID | CFG_CTL_RE | CFG_CTL_WE | CFG_CTL_INT |
514 CFG_CTL_RESTART | CFG_CTL_NTF_LIM,
515 WNI_CFG_CHANNEL_BONDING_MODE_STAMIN,
516 WNI_CFG_CHANNEL_BONDING_MODE_STAMAX,
517 WNI_CFG_CHANNEL_BONDING_MODE_STADEF},
Prakash Dhavali7090c5f2015-11-02 17:55:19 -0800[diff] [blame]518 {WNI_CFG_DYNAMIC_THRESHOLD_ZERO,
519 CFG_CTL_VALID | CFG_CTL_RE | CFG_CTL_WE | CFG_CTL_INT |
520 CFG_CTL_NTF_HAL,
521 WNI_CFG_DYNAMIC_THRESHOLD_ZERO_STAMIN,
522 WNI_CFG_DYNAMIC_THRESHOLD_ZERO_STAMAX,
523 WNI_CFG_DYNAMIC_THRESHOLD_ZERO_STADEF},
524 {WNI_CFG_DYNAMIC_THRESHOLD_ONE,
525 CFG_CTL_VALID | CFG_CTL_RE | CFG_CTL_WE | CFG_CTL_INT |
526 CFG_CTL_NTF_HAL,
527 WNI_CFG_DYNAMIC_THRESHOLD_ONE_STAMIN,
528 WNI_CFG_DYNAMIC_THRESHOLD_ONE_STAMAX,
529 WNI_CFG_DYNAMIC_THRESHOLD_ONE_STADEF},
530 {WNI_CFG_DYNAMIC_THRESHOLD_TWO,
531 CFG_CTL_VALID | CFG_CTL_RE | CFG_CTL_WE | CFG_CTL_INT |
532 CFG_CTL_NTF_HAL,
533 WNI_CFG_DYNAMIC_THRESHOLD_TWO_STAMIN,
534 WNI_CFG_DYNAMIC_THRESHOLD_TWO_STAMAX,
535 WNI_CFG_DYNAMIC_THRESHOLD_TWO_STADEF},
Prakash Dhavali7090c5f2015-11-02 17:55:19 -0800[diff] [blame]536 {WNI_CFG_SCAN_CONTROL_LIST,
537 CFG_CTL_VALID | CFG_CTL_RE | CFG_CTL_WE | CFG_CTL_RESTART |
538 CFG_CTL_NTF_LIM,
539 0, 0, 0},
Prakash Dhavali7090c5f2015-11-02 17:55:19 -0800[diff] [blame]540 {WNI_CFG_BLOCK_ACK_ENABLED,
541 CFG_CTL_VALID | CFG_CTL_RE | CFG_CTL_WE | CFG_CTL_INT |
542 CFG_CTL_RESTART | CFG_CTL_NTF_LIM,
543 WNI_CFG_BLOCK_ACK_ENABLED_STAMIN,
544 WNI_CFG_BLOCK_ACK_ENABLED_STAMAX,
545 WNI_CFG_BLOCK_ACK_ENABLED_STADEF},
Prakash Dhavali7090c5f2015-11-02 17:55:19 -0800[diff] [blame]546 {WNI_CFG_HT_CAP_INFO,
547 CFG_CTL_VALID | CFG_CTL_RE | CFG_CTL_WE | CFG_CTL_INT |
548 CFG_CTL_RESTART | CFG_CTL_NTF_LIM,
549 WNI_CFG_HT_CAP_INFO_STAMIN,
550 WNI_CFG_HT_CAP_INFO_STAMAX,
551 WNI_CFG_HT_CAP_INFO_STADEF},
552 {WNI_CFG_HT_AMPDU_PARAMS,
553 CFG_CTL_VALID | CFG_CTL_RE | CFG_CTL_WE | CFG_CTL_INT |
554 CFG_CTL_RESTART | CFG_CTL_NTF_LIM,
555 WNI_CFG_HT_AMPDU_PARAMS_STAMIN,
556 WNI_CFG_HT_AMPDU_PARAMS_STAMAX,
557 WNI_CFG_HT_AMPDU_PARAMS_STADEF},
558 {WNI_CFG_SUPPORTED_MCS_SET,
559 CFG_CTL_VALID | CFG_CTL_RE | CFG_CTL_WE | CFG_CTL_SAVE |
560 CFG_CTL_RESTART | CFG_CTL_NTF_LIM,
561 0, 0, 0},
562 {WNI_CFG_EXT_HT_CAP_INFO,
563 CFG_CTL_VALID | CFG_CTL_RE | CFG_CTL_WE | CFG_CTL_INT | CFG_CTL_SAVE |
564 CFG_CTL_RESTART | CFG_CTL_NTF_LIM,
565 WNI_CFG_EXT_HT_CAP_INFO_STAMIN,
566 WNI_CFG_EXT_HT_CAP_INFO_STAMAX,
567 WNI_CFG_EXT_HT_CAP_INFO_STADEF},
568 {WNI_CFG_TX_BF_CAP,
569 CFG_CTL_VALID | CFG_CTL_RE | CFG_CTL_INT | CFG_CTL_RESTART |
570 CFG_CTL_NTF_LIM,
571 WNI_CFG_TX_BF_CAP_STAMIN,
572 4294967295u,
573 WNI_CFG_TX_BF_CAP_STADEF},
574 {WNI_CFG_AS_CAP,
575 CFG_CTL_VALID | CFG_CTL_RE | CFG_CTL_WE | CFG_CTL_INT | CFG_CTL_SAVE |
576 CFG_CTL_RESTART | CFG_CTL_NTF_LIM,
577 WNI_CFG_AS_CAP_STAMIN,
578 WNI_CFG_AS_CAP_STAMAX,
579 WNI_CFG_AS_CAP_STADEF},
580 {WNI_CFG_HT_INFO_FIELD1,
581 CFG_CTL_VALID | CFG_CTL_RE | CFG_CTL_WE | CFG_CTL_INT |
582 CFG_CTL_RESTART | CFG_CTL_NTF_LIM,
583 WNI_CFG_HT_INFO_FIELD1_STAMIN,
584 WNI_CFG_HT_INFO_FIELD1_STAMAX,
585 WNI_CFG_HT_INFO_FIELD1_STADEF},
586 {WNI_CFG_HT_INFO_FIELD2,
587 CFG_CTL_VALID | CFG_CTL_RE | CFG_CTL_WE | CFG_CTL_INT | CFG_CTL_SAVE |
588 CFG_CTL_NTF_LIM,
589 WNI_CFG_HT_INFO_FIELD2_STAMIN,
590 WNI_CFG_HT_INFO_FIELD2_STAMAX,
591 WNI_CFG_HT_INFO_FIELD2_STADEF},
592 {WNI_CFG_HT_INFO_FIELD3,
593 CFG_CTL_VALID | CFG_CTL_RE | CFG_CTL_WE | CFG_CTL_INT | CFG_CTL_SAVE |
594 CFG_CTL_NTF_LIM,
595 WNI_CFG_HT_INFO_FIELD3_STAMIN,
596 WNI_CFG_HT_INFO_FIELD3_STAMAX,
597 WNI_CFG_HT_INFO_FIELD3_STADEF},
598 {WNI_CFG_BASIC_MCS_SET,
599 CFG_CTL_VALID | CFG_CTL_RE | CFG_CTL_WE | CFG_CTL_SAVE |
600 CFG_CTL_RESTART | CFG_CTL_NTF_LIM,
601 0, 0, 0},
602 {WNI_CFG_CURRENT_MCS_SET,
603 CFG_CTL_VALID | CFG_CTL_RE | CFG_CTL_WE | CFG_CTL_SAVE |
604 CFG_CTL_RESTART | CFG_CTL_NTF_LIM,
605 0, 0, 0},
Prakash Dhavali7090c5f2015-11-02 17:55:19 -0800[diff] [blame]606 {WNI_CFG_VHT_MAX_MPDU_LENGTH,
607 CFG_CTL_VALID | CFG_CTL_RE | CFG_CTL_WE | CFG_CTL_INT |
608 CFG_CTL_NTF_LIM,
609 WNI_CFG_VHT_MAX_MPDU_LENGTH_STAMIN,
610 WNI_CFG_VHT_MAX_MPDU_LENGTH_STAMAX,
611 WNI_CFG_VHT_MAX_MPDU_LENGTH_STADEF},
612 {WNI_CFG_VHT_SUPPORTED_CHAN_WIDTH_SET,
613 CFG_CTL_VALID | CFG_CTL_RE | CFG_CTL_WE | CFG_CTL_INT |
614 CFG_CTL_NTF_LIM,
615 WNI_CFG_VHT_SUPPORTED_CHAN_WIDTH_SET_STAMIN,
616 WNI_CFG_VHT_SUPPORTED_CHAN_WIDTH_SET_STAMAX,
617 WNI_CFG_VHT_SUPPORTED_CHAN_WIDTH_SET_STADEF},
618 {WNI_CFG_VHT_LDPC_CODING_CAP,
619 CFG_CTL_VALID | CFG_CTL_RE | CFG_CTL_WE | CFG_CTL_INT |
620 CFG_CTL_NTF_LIM,
621 WNI_CFG_VHT_LDPC_CODING_CAP_STAMIN,
622 WNI_CFG_VHT_LDPC_CODING_CAP_STAMAX,
623 WNI_CFG_VHT_LDPC_CODING_CAP_STADEF},
624 {WNI_CFG_VHT_SHORT_GI_80MHZ,
625 CFG_CTL_VALID | CFG_CTL_RE | CFG_CTL_WE | CFG_CTL_INT |
626 CFG_CTL_NTF_LIM,
627 WNI_CFG_VHT_SHORT_GI_80MHZ_STAMIN,
628 WNI_CFG_VHT_SHORT_GI_80MHZ_STAMAX,
629 WNI_CFG_VHT_SHORT_GI_80MHZ_STADEF},
630 {WNI_CFG_VHT_SHORT_GI_160_AND_80_PLUS_80MHZ,
631 CFG_CTL_VALID | CFG_CTL_RE | CFG_CTL_WE | CFG_CTL_INT |
632 CFG_CTL_NTF_LIM,
633 WNI_CFG_VHT_SHORT_GI_160_AND_80_PLUS_80MHZ_STAMIN,
634 WNI_CFG_VHT_SHORT_GI_160_AND_80_PLUS_80MHZ_STAMAX,
635 WNI_CFG_VHT_SHORT_GI_160_AND_80_PLUS_80MHZ_STADEF},
636 {WNI_CFG_VHT_TXSTBC,
637 CFG_CTL_VALID | CFG_CTL_RE | CFG_CTL_WE | CFG_CTL_INT |
638 CFG_CTL_NTF_LIM,
639 WNI_CFG_VHT_TXSTBC_STAMIN,
640 WNI_CFG_VHT_TXSTBC_STAMAX,
641 WNI_CFG_VHT_TXSTBC_STADEF},
642 {WNI_CFG_VHT_RXSTBC,
643 CFG_CTL_VALID | CFG_CTL_RE | CFG_CTL_WE | CFG_CTL_INT |
644 CFG_CTL_NTF_LIM,
645 WNI_CFG_VHT_RXSTBC_STAMIN,
646 WNI_CFG_VHT_RXSTBC_STAMAX,
647 WNI_CFG_VHT_RXSTBC_STADEF},
648 {WNI_CFG_VHT_SU_BEAMFORMER_CAP,
649 CFG_CTL_VALID | CFG_CTL_RE | CFG_CTL_WE | CFG_CTL_INT |
650 CFG_CTL_NTF_LIM,
651 WNI_CFG_VHT_SU_BEAMFORMER_CAP_STAMIN,
652 WNI_CFG_VHT_SU_BEAMFORMER_CAP_STAMAX,
653 WNI_CFG_VHT_SU_BEAMFORMER_CAP_STADEF},
654 {WNI_CFG_VHT_SU_BEAMFORMEE_CAP,
655 CFG_CTL_VALID | CFG_CTL_RE | CFG_CTL_WE | CFG_CTL_INT |
656 CFG_CTL_NTF_LIM,
657 WNI_CFG_VHT_SU_BEAMFORMEE_CAP_STAMIN,
658 WNI_CFG_VHT_SU_BEAMFORMEE_CAP_STAMAX,
659 WNI_CFG_VHT_SU_BEAMFORMEE_CAP_STADEF},
660 {WNI_CFG_VHT_CSN_BEAMFORMEE_ANT_SUPPORTED,
661 CFG_CTL_VALID | CFG_CTL_RE | CFG_CTL_WE | CFG_CTL_INT |
662 CFG_CTL_NTF_LIM,
663 WNI_CFG_VHT_CSN_BEAMFORMEE_ANT_SUPPORTED_STAMIN,
664 WNI_CFG_VHT_CSN_BEAMFORMEE_ANT_SUPPORTED_STAMAX,
665 WNI_CFG_VHT_CSN_BEAMFORMEE_ANT_SUPPORTED_STADEF},
666 {WNI_CFG_VHT_NUM_SOUNDING_DIMENSIONS,
667 CFG_CTL_VALID | CFG_CTL_RE | CFG_CTL_WE | CFG_CTL_INT |
668 CFG_CTL_NTF_LIM,
669 WNI_CFG_VHT_NUM_SOUNDING_DIMENSIONS_STAMIN,
670 WNI_CFG_VHT_NUM_SOUNDING_DIMENSIONS_STAMAX,
671 WNI_CFG_VHT_NUM_SOUNDING_DIMENSIONS_STADEF},
672 {WNI_CFG_VHT_MU_BEAMFORMER_CAP,
673 CFG_CTL_VALID | CFG_CTL_RE | CFG_CTL_WE | CFG_CTL_INT |
674 CFG_CTL_NTF_LIM,
675 WNI_CFG_VHT_MU_BEAMFORMER_CAP_STAMIN,
676 WNI_CFG_VHT_MU_BEAMFORMER_CAP_STAMAX,
677 WNI_CFG_VHT_MU_BEAMFORMER_CAP_STADEF},
678 {WNI_CFG_VHT_MU_BEAMFORMEE_CAP,
679 CFG_CTL_VALID | CFG_CTL_RE | CFG_CTL_WE | CFG_CTL_INT |
680 CFG_CTL_NTF_LIM,
681 WNI_CFG_VHT_MU_BEAMFORMEE_CAP_STAMIN,
682 WNI_CFG_VHT_MU_BEAMFORMEE_CAP_STAMAX,
683 WNI_CFG_VHT_MU_BEAMFORMEE_CAP_STADEF},
684 {WNI_CFG_VHT_TXOP_PS,
685 CFG_CTL_VALID | CFG_CTL_RE | CFG_CTL_WE | CFG_CTL_INT |
686 CFG_CTL_NTF_LIM,
687 WNI_CFG_VHT_TXOP_PS_STAMIN,
688 WNI_CFG_VHT_TXOP_PS_STAMAX,
689 WNI_CFG_VHT_TXOP_PS_STADEF},
690 {WNI_CFG_VHT_HTC_VHTC_CAP,
691 CFG_CTL_VALID | CFG_CTL_RE | CFG_CTL_WE | CFG_CTL_INT |
692 CFG_CTL_NTF_LIM,
693 WNI_CFG_VHT_HTC_VHTC_CAP_STAMIN,
694 WNI_CFG_VHT_HTC_VHTC_CAP_STAMAX,
695 WNI_CFG_VHT_HTC_VHTC_CAP_STADEF},
696 {WNI_CFG_VHT_AMPDU_LEN_EXPONENT,
697 CFG_CTL_VALID | CFG_CTL_RE | CFG_CTL_WE | CFG_CTL_INT |
698 CFG_CTL_NTF_LIM,
699 WNI_CFG_VHT_AMPDU_LEN_EXPONENT_STAMIN,
700 WNI_CFG_VHT_AMPDU_LEN_EXPONENT_STAMAX,
701 WNI_CFG_VHT_AMPDU_LEN_EXPONENT_STADEF},
702 {WNI_CFG_VHT_LINK_ADAPTATION_CAP,
703 CFG_CTL_VALID | CFG_CTL_RE | CFG_CTL_WE | CFG_CTL_INT |
704 CFG_CTL_NTF_LIM,
705 WNI_CFG_VHT_LINK_ADAPTATION_CAP_STAMIN,
706 WNI_CFG_VHT_LINK_ADAPTATION_CAP_STAMAX,
707 WNI_CFG_VHT_LINK_ADAPTATION_CAP_STADEF},
708 {WNI_CFG_VHT_RX_ANT_PATTERN,
709 CFG_CTL_VALID | CFG_CTL_RE | CFG_CTL_WE | CFG_CTL_INT |
710 CFG_CTL_NTF_LIM,
711 WNI_CFG_VHT_RX_ANT_PATTERN_STAMIN,
712 WNI_CFG_VHT_RX_ANT_PATTERN_STAMAX,
713 WNI_CFG_VHT_RX_ANT_PATTERN_STADEF},
714 {WNI_CFG_VHT_TX_ANT_PATTERN,
715 CFG_CTL_VALID | CFG_CTL_RE | CFG_CTL_WE | CFG_CTL_INT |
716 CFG_CTL_NTF_LIM,
717 WNI_CFG_VHT_TX_ANT_PATTERN_STAMIN,
718 WNI_CFG_VHT_TX_ANT_PATTERN_STAMAX,
719 WNI_CFG_VHT_TX_ANT_PATTERN_STADEF},
720 {WNI_CFG_VHT_RX_MCS_MAP,
721 CFG_CTL_VALID | CFG_CTL_RE | CFG_CTL_WE | CFG_CTL_INT |
722 CFG_CTL_NTF_LIM,
723 WNI_CFG_VHT_RX_MCS_MAP_STAMIN,
724 WNI_CFG_VHT_RX_MCS_MAP_STAMAX,
725 WNI_CFG_VHT_RX_MCS_MAP_STADEF},
726 {WNI_CFG_VHT_TX_MCS_MAP,
727 CFG_CTL_VALID | CFG_CTL_RE | CFG_CTL_WE | CFG_CTL_INT |
728 CFG_CTL_NTF_LIM,
729 WNI_CFG_VHT_TX_MCS_MAP_STAMIN,
730 WNI_CFG_VHT_TX_MCS_MAP_STAMAX,
731 WNI_CFG_VHT_TX_MCS_MAP_STADEF},
732 {WNI_CFG_VHT_RX_HIGHEST_SUPPORTED_DATA_RATE,
733 CFG_CTL_VALID | CFG_CTL_RE | CFG_CTL_WE | CFG_CTL_INT |
734 CFG_CTL_NTF_LIM,
735 WNI_CFG_VHT_RX_HIGHEST_SUPPORTED_DATA_RATE_STAMIN,
736 WNI_CFG_VHT_RX_HIGHEST_SUPPORTED_DATA_RATE_STAMAX,
737 WNI_CFG_VHT_RX_HIGHEST_SUPPORTED_DATA_RATE_STADEF},
738 {WNI_CFG_VHT_TX_HIGHEST_SUPPORTED_DATA_RATE,
739 CFG_CTL_VALID | CFG_CTL_RE | CFG_CTL_WE | CFG_CTL_INT |
740 CFG_CTL_NTF_LIM,
741 WNI_CFG_VHT_TX_HIGHEST_SUPPORTED_DATA_RATE_STAMIN,
742 WNI_CFG_VHT_TX_HIGHEST_SUPPORTED_DATA_RATE_STAMAX,
743 WNI_CFG_VHT_TX_HIGHEST_SUPPORTED_DATA_RATE_STADEF},
Prakash Dhavali7090c5f2015-11-02 17:55:19 -0800[diff] [blame]744 {WNI_CFG_VHT_BASIC_MCS_SET,
745 CFG_CTL_VALID | CFG_CTL_RE | CFG_CTL_WE | CFG_CTL_INT |
746 CFG_CTL_NTF_LIM,
747 WNI_CFG_VHT_BASIC_MCS_SET_STAMIN,
748 WNI_CFG_VHT_BASIC_MCS_SET_STAMAX,
749 WNI_CFG_VHT_BASIC_MCS_SET_STADEF},
750 {WNI_CFG_VHT_MU_MIMO_CAP_STA_COUNT,
751 CFG_CTL_VALID | CFG_CTL_RE | CFG_CTL_WE | CFG_CTL_INT |
752 CFG_CTL_NTF_LIM,
753 WNI_CFG_VHT_MU_MIMO_CAP_STA_COUNT_STAMIN,
754 WNI_CFG_VHT_MU_MIMO_CAP_STA_COUNT_STAMAX,
755 WNI_CFG_VHT_MU_MIMO_CAP_STA_COUNT_STADEF},
756 {WNI_CFG_VHT_SS_UNDER_UTIL,
757 CFG_CTL_VALID | CFG_CTL_RE | CFG_CTL_WE | CFG_CTL_INT |
758 CFG_CTL_NTF_LIM,
759 WNI_CFG_VHT_SS_UNDER_UTIL_STAMIN,
760 WNI_CFG_VHT_SS_UNDER_UTIL_STAMAX,
761 WNI_CFG_VHT_SS_UNDER_UTIL_STADEF},
762 {WNI_CFG_VHT_40MHZ_UTILIZATION,
763 CFG_CTL_VALID | CFG_CTL_RE | CFG_CTL_WE | CFG_CTL_INT |
764 CFG_CTL_NTF_LIM,
765 WNI_CFG_VHT_40MHZ_UTILIZATION_STAMIN,
766 WNI_CFG_VHT_40MHZ_UTILIZATION_STAMAX,
767 WNI_CFG_VHT_40MHZ_UTILIZATION_STADEF},
768 {WNI_CFG_VHT_80MHZ_UTILIZATION,
769 CFG_CTL_VALID | CFG_CTL_RE | CFG_CTL_WE | CFG_CTL_INT |
770 CFG_CTL_NTF_LIM,
771 WNI_CFG_VHT_80MHZ_UTILIZATION_STAMIN,
772 WNI_CFG_VHT_80MHZ_UTILIZATION_STAMAX,
773 WNI_CFG_VHT_80MHZ_UTILIZATION_STADEF},
774 {WNI_CFG_VHT_160MHZ_UTILIZATION,
775 CFG_CTL_VALID | CFG_CTL_RE | CFG_CTL_WE | CFG_CTL_INT |
776 CFG_CTL_NTF_LIM,
777 WNI_CFG_VHT_80MHZ_UTILIZATION_STADEF,
778 WNI_CFG_VHT_160MHZ_UTILIZATION_STAMAX,
779 WNI_CFG_VHT_160MHZ_UTILIZATION_STADEF},
Prakash Dhavali7090c5f2015-11-02 17:55:19 -0800[diff] [blame]780 {WNI_CFG_MPDU_DENSITY,
781 CFG_CTL_VALID | CFG_CTL_RE | CFG_CTL_WE | CFG_CTL_INT |
782 CFG_CTL_RESTART | CFG_CTL_NTF_LIM,
783 WNI_CFG_MPDU_DENSITY_STAMIN,
784 WNI_CFG_MPDU_DENSITY_STAMAX,
785 WNI_CFG_MPDU_DENSITY_STADEF},
786 {WNI_CFG_MAX_RX_AMPDU_FACTOR,
787 CFG_CTL_VALID | CFG_CTL_RE | CFG_CTL_WE | CFG_CTL_INT |
788 CFG_CTL_RESTART | CFG_CTL_NTF_LIM,
789 WNI_CFG_MAX_RX_AMPDU_FACTOR_STAMIN,
790 WNI_CFG_MAX_RX_AMPDU_FACTOR_STAMAX,
791 WNI_CFG_MAX_RX_AMPDU_FACTOR_STAMAX},
Prakash Dhavali7090c5f2015-11-02 17:55:19 -0800[diff] [blame]792 {WNI_CFG_MAX_PS_POLL,
793 CFG_CTL_VALID | CFG_CTL_RE | CFG_CTL_WE | CFG_CTL_INT |
794 CFG_CTL_NTF_LIM,
795 WNI_CFG_MAX_PS_POLL_STAMIN,
796 WNI_CFG_MAX_PS_POLL_STAMAX,
797 WNI_CFG_MAX_PS_POLL_STADEF},
Prakash Dhavali7090c5f2015-11-02 17:55:19 -0800[diff] [blame]798 {WNI_CFG_RSSI_FILTER_PERIOD,
799 CFG_CTL_VALID | CFG_CTL_RE | CFG_CTL_WE | CFG_CTL_INT |
800 CFG_CTL_NTF_LIM,
801 WNI_CFG_RSSI_FILTER_PERIOD_STAMIN,
802 WNI_CFG_RSSI_FILTER_PERIOD_STAMAX,
803 WNI_CFG_RSSI_FILTER_PERIOD_STADEF},
Prakash Dhavali7090c5f2015-11-02 17:55:19 -0800[diff] [blame]804 {WNI_CFG_SCAN_IN_POWERSAVE,
805 CFG_CTL_VALID | CFG_CTL_RE | CFG_CTL_WE | CFG_CTL_INT |
806 CFG_CTL_NTF_LIM,
807 WNI_CFG_SCAN_IN_POWERSAVE_STAMIN,
808 WNI_CFG_SCAN_IN_POWERSAVE_STAMAX,
809 WNI_CFG_SCAN_IN_POWERSAVE_STADEF},
810 {WNI_CFG_IGNORE_DTIM,
811 CFG_CTL_VALID | CFG_CTL_RE | CFG_CTL_WE | CFG_CTL_INT,
812 WNI_CFG_IGNORE_DTIM_STAMIN,
813 WNI_CFG_IGNORE_DTIM_STAMAX,
814 WNI_CFG_IGNORE_DTIM_STADEF},
815 {WNI_CFG_WOWLAN_UCAST_PATTERN_FILTER_ENABLE,
816 CFG_CTL_VALID | CFG_CTL_RE | CFG_CTL_WE | CFG_CTL_INT,
817 WNI_CFG_WOWLAN_UCAST_PATTERN_FILTER_ENABLE_STAMIN,
818 WNI_CFG_WOWLAN_UCAST_PATTERN_FILTER_ENABLE_STAMAX,
819 WNI_CFG_WOWLAN_UCAST_PATTERN_FILTER_ENABLE_STADEF},
820 {WNI_CFG_WOWLAN_CHANNEL_SWITCH_ENABLE,
821 CFG_CTL_VALID | CFG_CTL_RE | CFG_CTL_WE | CFG_CTL_INT,
822 WNI_CFG_WOWLAN_CHANNEL_SWITCH_ENABLE_STAMIN,
823 WNI_CFG_WOWLAN_CHANNEL_SWITCH_ENABLE_STAMAX,
824 WNI_CFG_WOWLAN_CHANNEL_SWITCH_ENABLE_STADEF},
825 {WNI_CFG_WOWLAN_DEAUTH_ENABLE,
826 CFG_CTL_VALID | CFG_CTL_RE | CFG_CTL_WE | CFG_CTL_INT,
827 WNI_CFG_WOWLAN_DEAUTH_ENABLE_STAMIN,
828 WNI_CFG_WOWLAN_DEAUTH_ENABLE_STAMAX,
829 WNI_CFG_WOWLAN_DEAUTH_ENABLE_STADEF},
830 {WNI_CFG_WOWLAN_DISASSOC_ENABLE,
831 CFG_CTL_VALID | CFG_CTL_RE | CFG_CTL_WE | CFG_CTL_INT,
832 WNI_CFG_WOWLAN_DISASSOC_ENABLE_STAMIN,
833 WNI_CFG_WOWLAN_DISASSOC_ENABLE_STAMAX,
834 WNI_CFG_WOWLAN_DISASSOC_ENABLE_STADEF},
835 {WNI_CFG_WOWLAN_MAX_MISSED_BEACON,
836 CFG_CTL_VALID | CFG_CTL_RE | CFG_CTL_WE | CFG_CTL_INT,
837 WNI_CFG_WOWLAN_MAX_MISSED_BEACON_STAMIN,
838 WNI_CFG_WOWLAN_MAX_MISSED_BEACON_STAMAX,
839 WNI_CFG_WOWLAN_MAX_MISSED_BEACON_STADEF},
840 {WNI_CFG_WOWLAN_MAX_SLEEP_PERIOD,
841 CFG_CTL_VALID | CFG_CTL_RE | CFG_CTL_WE | CFG_CTL_INT,
842 WNI_CFG_WOWLAN_MAX_SLEEP_PERIOD_STAMIN,
843 WNI_CFG_WOWLAN_MAX_SLEEP_PERIOD_STAMAX,
844 WNI_CFG_WOWLAN_MAX_SLEEP_PERIOD_STADEF},
Prakash Dhavali7090c5f2015-11-02 17:55:19 -0800[diff] [blame]845 {WNI_CFG_MAX_MEDIUM_TIME,
846 CFG_CTL_VALID | CFG_CTL_RE | CFG_CTL_WE | CFG_CTL_INT |
847 CFG_CTL_NTF_HAL,
848 WNI_CFG_MAX_MEDIUM_TIME_STAMIN,
849 WNI_CFG_MAX_MEDIUM_TIME_STAMAX,
850 WNI_CFG_MAX_MEDIUM_TIME_STADEF},
Prakash Dhavali7090c5f2015-11-02 17:55:19 -0800[diff] [blame]851 {WNI_CFG_IBSS_AUTO_BSSID,
852 CFG_CTL_VALID | CFG_CTL_RE | CFG_CTL_WE | CFG_CTL_INT,
853 WNI_CFG_IBSS_AUTO_BSSID_STAMIN,
854 WNI_CFG_IBSS_AUTO_BSSID_STAMAX,
855 WNI_CFG_IBSS_AUTO_BSSID_STADEF},
Prakash Dhavali7090c5f2015-11-02 17:55:19 -0800[diff] [blame]856 {WNI_CFG_PROBE_RSP_BCN_ADDNIE_FLAG,
857 CFG_CTL_VALID | CFG_CTL_RE | CFG_CTL_WE | CFG_CTL_INT |
858 CFG_CTL_NTF_LIM,
859 WNI_CFG_PROBE_RSP_BCN_ADDNIE_FLAG_STAMIN,
860 WNI_CFG_PROBE_RSP_BCN_ADDNIE_FLAG_STAMAX,
861 WNI_CFG_PROBE_RSP_BCN_ADDNIE_FLAG_STADEF},
Prakash Dhavali7090c5f2015-11-02 17:55:19 -0800[diff] [blame]862 {WNI_CFG_WPS_ENABLE,
863 CFG_CTL_VALID | CFG_CTL_RE | CFG_CTL_WE | CFG_CTL_INT |
864 CFG_CTL_NTF_LIM,
865 WNI_CFG_WPS_ENABLE_STAMIN,
866 WNI_CFG_WPS_ENABLE_STAMAX,
867 WNI_CFG_WPS_ENABLE_STADEF},
868 {WNI_CFG_WPS_STATE,
869 CFG_CTL_VALID | CFG_CTL_RE | CFG_CTL_WE | CFG_CTL_INT |
870 CFG_CTL_NTF_LIM,
871 WNI_CFG_WPS_STATE_STAMIN,
872 WNI_CFG_WPS_STATE_STAMAX,
873 WNI_CFG_WPS_STATE_STADEF},
Prakash Dhavali7090c5f2015-11-02 17:55:19 -0800[diff] [blame]874 {WNI_CFG_WPS_VERSION,
875 CFG_CTL_VALID | CFG_CTL_RE | CFG_CTL_WE | CFG_CTL_INT |
876 CFG_CTL_NTF_LIM,
877 WNI_CFG_WPS_VERSION_STAMIN,
878 WNI_CFG_WPS_VERSION_STAMAX,
879 WNI_CFG_WPS_VERSION_STADEF},
Prakash Dhavali7090c5f2015-11-02 17:55:19 -0800[diff] [blame]880 {WNI_CFG_WPS_CFG_METHOD,
881 CFG_CTL_VALID | CFG_CTL_RE | CFG_CTL_WE | CFG_CTL_INT |
882 CFG_CTL_NTF_LIM,
883 WNI_CFG_WPS_CFG_METHOD_STAMIN,
884 4294967295u,
885 WNI_CFG_WPS_CFG_METHOD_STADEF},
886 {WNI_CFG_WPS_UUID,
887 CFG_CTL_VALID | CFG_CTL_RE | CFG_CTL_WE | CFG_CTL_NTF_LIM,
888 0, 0, 0},
889 {WNI_CFG_WPS_PRIMARY_DEVICE_CATEGORY,
890 CFG_CTL_VALID | CFG_CTL_RE | CFG_CTL_WE | CFG_CTL_INT |
891 CFG_CTL_NTF_LIM,
892 WNI_CFG_WPS_PRIMARY_DEVICE_CATEGORY_STAMIN,
893 WNI_CFG_WPS_PRIMARY_DEVICE_CATEGORY_STAMAX,
894 WNI_CFG_WPS_PRIMARY_DEVICE_CATEGORY_STADEF},
895 {WNI_CFG_WPS_PIMARY_DEVICE_OUI,
896 CFG_CTL_VALID | CFG_CTL_RE | CFG_CTL_WE | CFG_CTL_INT |
897 CFG_CTL_NTF_LIM,
898 WNI_CFG_WPS_PIMARY_DEVICE_OUI_STAMIN,
899 4294967295u,
900 WNI_CFG_WPS_PIMARY_DEVICE_OUI_STADEF},
901 {WNI_CFG_WPS_DEVICE_SUB_CATEGORY,
902 CFG_CTL_VALID | CFG_CTL_RE | CFG_CTL_WE | CFG_CTL_INT |
903 CFG_CTL_NTF_LIM,
904 WNI_CFG_WPS_DEVICE_SUB_CATEGORY_STAMIN,
905 WNI_CFG_WPS_DEVICE_SUB_CATEGORY_STAMAX,
906 WNI_CFG_WPS_DEVICE_SUB_CATEGORY_STADEF},
Prakash Dhavali7090c5f2015-11-02 17:55:19 -0800[diff] [blame]907 {WNI_CFG_WPS_DEVICE_PASSWORD_ID,
908 CFG_CTL_VALID | CFG_CTL_RE | CFG_CTL_WE | CFG_CTL_INT |
909 CFG_CTL_NTF_LIM,
910 WNI_CFG_WPS_DEVICE_PASSWORD_ID_STAMIN,
911 4294967295u,
912 WNI_CFG_WPS_DEVICE_PASSWORD_ID_STADEF},
Prakash Dhavali7090c5f2015-11-02 17:55:19 -0800[diff] [blame]913 {WNI_CFG_LOW_GAIN_OVERRIDE,
914 CFG_CTL_VALID | CFG_CTL_RE | CFG_CTL_WE | CFG_CTL_INT |
915 CFG_CTL_NTF_HAL,
916 WNI_CFG_LOW_GAIN_OVERRIDE_STAMIN,
917 WNI_CFG_LOW_GAIN_OVERRIDE_STAMAX,
918 WNI_CFG_LOW_GAIN_OVERRIDE_STADEF},
Prakash Dhavali7090c5f2015-11-02 17:55:19 -0800[diff] [blame]919 {WNI_CFG_SINGLE_TID_RC,
920 CFG_CTL_VALID | CFG_CTL_RE | CFG_CTL_WE | CFG_CTL_INT,
921 WNI_CFG_SINGLE_TID_RC_STAMIN,
922 WNI_CFG_SINGLE_TID_RC_STAMAX,
923 WNI_CFG_SINGLE_TID_RC_STADEF},
Prakash Dhavali7090c5f2015-11-02 17:55:19 -0800[diff] [blame]924 {WNI_CFG_MCAST_BCAST_FILTER_SETTING,
925 CFG_CTL_VALID | CFG_CTL_RE | CFG_CTL_WE | CFG_CTL_INT |
926 CFG_CTL_NTF_HAL,
927 WNI_CFG_MCAST_BCAST_FILTER_SETTING_STAMIN,
928 WNI_CFG_MCAST_BCAST_FILTER_SETTING_STAMAX,
929 WNI_CFG_MCAST_BCAST_FILTER_SETTING_STADEF},
Prakash Dhavali7090c5f2015-11-02 17:55:19 -0800[diff] [blame]930 {WNI_CFG_DYNAMIC_PS_POLL_VALUE,
931 CFG_CTL_VALID | CFG_CTL_RE | CFG_CTL_WE | CFG_CTL_INT |
932 CFG_CTL_NTF_HAL,
933 WNI_CFG_DYNAMIC_PS_POLL_VALUE_STAMIN,
934 WNI_CFG_DYNAMIC_PS_POLL_VALUE_STAMAX,
935 WNI_CFG_DYNAMIC_PS_POLL_VALUE_STADEF},
936 {WNI_CFG_PS_NULLDATA_AP_RESP_TIMEOUT,
937 CFG_CTL_VALID | CFG_CTL_RE | CFG_CTL_WE | CFG_CTL_INT |
938 CFG_CTL_NTF_HAL,
939 WNI_CFG_PS_NULLDATA_AP_RESP_TIMEOUT_STAMIN,
940 WNI_CFG_PS_NULLDATA_AP_RESP_TIMEOUT_STAMAX,
941 WNI_CFG_PS_NULLDATA_AP_RESP_TIMEOUT_STADEF},
942 {WNI_CFG_TELE_BCN_WAKEUP_EN,
943 CFG_CTL_VALID | CFG_CTL_RE | CFG_CTL_WE | CFG_CTL_INT |
944 CFG_CTL_NTF_HAL,
945 WNI_CFG_TELE_BCN_WAKEUP_EN_STAMIN,
946 WNI_CFG_TELE_BCN_WAKEUP_EN_STAMAX,
947 WNI_CFG_TELE_BCN_WAKEUP_EN_STADEF},
948 {WNI_CFG_TELE_BCN_TRANS_LI,
949 CFG_CTL_VALID | CFG_CTL_RE | CFG_CTL_WE | CFG_CTL_INT |
950 CFG_CTL_NTF_HAL,
951 WNI_CFG_TELE_BCN_TRANS_LI_STAMIN,
952 WNI_CFG_TELE_BCN_TRANS_LI_STAMAX,
953 WNI_CFG_TELE_BCN_TRANS_LI_STADEF},
954 {WNI_CFG_TELE_BCN_TRANS_LI_IDLE_BCNS,
955 CFG_CTL_VALID | CFG_CTL_RE | CFG_CTL_WE | CFG_CTL_INT |
956 CFG_CTL_NTF_HAL,
957 WNI_CFG_TELE_BCN_TRANS_LI_IDLE_BCNS_STAMIN,
958 WNI_CFG_TELE_BCN_TRANS_LI_IDLE_BCNS_STAMAX,
959 WNI_CFG_TELE_BCN_TRANS_LI_IDLE_BCNS_STADEF},
960 {WNI_CFG_TELE_BCN_MAX_LI,
961 CFG_CTL_VALID | CFG_CTL_RE | CFG_CTL_WE | CFG_CTL_INT |
962 CFG_CTL_NTF_HAL,
963 WNI_CFG_TELE_BCN_MAX_LI_STAMIN,
964 WNI_CFG_TELE_BCN_MAX_LI_STAMAX,
965 WNI_CFG_TELE_BCN_MAX_LI_STADEF},
966 {WNI_CFG_TELE_BCN_MAX_LI_IDLE_BCNS,
967 CFG_CTL_VALID | CFG_CTL_RE | CFG_CTL_WE | CFG_CTL_INT |
968 CFG_CTL_NTF_HAL,
969 WNI_CFG_TELE_BCN_MAX_LI_IDLE_BCNS_STAMIN,
970 WNI_CFG_TELE_BCN_MAX_LI_IDLE_BCNS_STAMAX,
971 WNI_CFG_TELE_BCN_MAX_LI_IDLE_BCNS_STADEF},
Prakash Dhavali7090c5f2015-11-02 17:55:19 -0800[diff] [blame]972 {WNI_CFG_INFRA_STA_KEEP_ALIVE_PERIOD,
973 CFG_CTL_VALID | CFG_CTL_RE | CFG_CTL_WE | CFG_CTL_INT |
974 CFG_CTL_NTF_HAL,
975 WNI_CFG_INFRA_STA_KEEP_ALIVE_PERIOD_STAMIN,
976 WNI_CFG_INFRA_STA_KEEP_ALIVE_PERIOD_STAMAX,
977 WNI_CFG_INFRA_STA_KEEP_ALIVE_PERIOD_STADEF},
978 {WNI_CFG_ASSOC_STA_LIMIT,
979 CFG_CTL_VALID | CFG_CTL_RE | CFG_CTL_WE | CFG_CTL_INT |
980 CFG_CTL_NTF_LIM,
981 WNI_CFG_ASSOC_STA_LIMIT_STAMIN,
982 WNI_CFG_ASSOC_STA_LIMIT_STAMAX,
983 WNI_CFG_ASSOC_STA_LIMIT_STADEF},
Prakash Dhavali7090c5f2015-11-02 17:55:19 -0800[diff] [blame]984 {WNI_CFG_AP_DATA_AVAIL_POLL_PERIOD,
985 CFG_CTL_VALID | CFG_CTL_RE | CFG_CTL_WE | CFG_CTL_INT,
986 WNI_CFG_AP_DATA_AVAIL_POLL_PERIOD_STAMIN,
987 WNI_CFG_AP_DATA_AVAIL_POLL_PERIOD_STAMAX,
988 WNI_CFG_AP_DATA_AVAIL_POLL_PERIOD_STADEF},
Prakash Dhavali7090c5f2015-11-02 17:55:19 -0800[diff] [blame]989 {WNI_CFG_ENABLE_LTE_COEX,
990 CFG_CTL_VALID | CFG_CTL_RE | CFG_CTL_WE | CFG_CTL_INT,
991 WNI_CFG_ENABLE_LTE_COEX_STAMIN,
992 WNI_CFG_ENABLE_LTE_COEX_STAMAX,
993 WNI_CFG_ENABLE_LTE_COEX_STADEF},
994 {WNI_CFG_AP_KEEP_ALIVE_TIMEOUT,
995 CFG_CTL_VALID | CFG_CTL_RE | CFG_CTL_WE | CFG_CTL_INT |
996 CFG_CTL_NTF_HAL,
997 WNI_CFG_AP_KEEP_ALIVE_TIMEOUT_STAMIN,
998 WNI_CFG_AP_KEEP_ALIVE_TIMEOUT_STAMAX,
999 WNI_CFG_AP_KEEP_ALIVE_TIMEOUT_STADEF},
1000 {WNI_CFG_GO_KEEP_ALIVE_TIMEOUT,
1001 CFG_CTL_VALID | CFG_CTL_RE | CFG_CTL_WE | CFG_CTL_INT |
1002 CFG_CTL_NTF_HAL,
1003 WNI_CFG_GO_KEEP_ALIVE_TIMEOUT_STAMIN,
1004 WNI_CFG_GO_KEEP_ALIVE_TIMEOUT_STAMAX,
1005 WNI_CFG_GO_KEEP_ALIVE_TIMEOUT_STADEF},
1006 {WNI_CFG_ENABLE_MC_ADDR_LIST,
1007 CFG_CTL_VALID | CFG_CTL_RE | CFG_CTL_WE | CFG_CTL_INT |
1008 CFG_CTL_NTF_HAL,
1009 WNI_CFG_ENABLE_MC_ADDR_LIST_STAMIN,
1010 WNI_CFG_ENABLE_MC_ADDR_LIST_STAMAX,
1011 WNI_CFG_ENABLE_MC_ADDR_LIST_STADEF},
Prakash Dhavali7090c5f2015-11-02 17:55:19 -0800[diff] [blame]1012 {WNI_CFG_ENABLE_LPWR_IMG_TRANSITION,
1013 CFG_CTL_VALID | CFG_CTL_RE | CFG_CTL_WE | CFG_CTL_INT,
1014 WNI_CFG_ENABLE_LPWR_IMG_TRANSITION_STAMIN,
1015 WNI_CFG_ENABLE_LPWR_IMG_TRANSITION_STAMAX,
1016 WNI_CFG_ENABLE_LPWR_IMG_TRANSITION_STADEF},
1017 {WNI_CFG_ENABLE_MCC_ADAPTIVE_SCHED,
1018 CFG_CTL_VALID | CFG_CTL_RE | CFG_CTL_WE | CFG_CTL_INT,
1019 WNI_CFG_ENABLE_MCC_ADAPTIVE_SCHED_STAMIN,
1020 WNI_CFG_ENABLE_MCC_ADAPTIVE_SCHED_STAMAX,
1021 WNI_CFG_ENABLE_MCC_ADAPTIVE_SCHED_STADEF},
1022 {WNI_CFG_DISABLE_LDPC_WITH_TXBF_AP,
1023 CFG_CTL_VALID | CFG_CTL_RE | CFG_CTL_WE | CFG_CTL_INT,
1024 WNI_CFG_DISABLE_LDPC_WITH_TXBF_AP_STAMIN,
1025 WNI_CFG_DISABLE_LDPC_WITH_TXBF_AP_STAMAX,
1026 WNI_CFG_DISABLE_LDPC_WITH_TXBF_AP_STADEF},
1027 {WNI_CFG_AP_LINK_MONITOR_TIMEOUT,
1028 CFG_CTL_VALID | CFG_CTL_RE | CFG_CTL_WE | CFG_CTL_INT |
1029 CFG_CTL_NTF_HAL,
1030 WNI_CFG_AP_LINK_MONITOR_TIMEOUT_STAMIN,
1031 WNI_CFG_AP_LINK_MONITOR_TIMEOUT_STAMAX,
1032 WNI_CFG_AP_LINK_MONITOR_TIMEOUT_STADEF},
1033 {WNI_CFG_TDLS_QOS_WMM_UAPSD_MASK,
1034 CFG_CTL_VALID | CFG_CTL_RE | CFG_CTL_WE | CFG_CTL_INT |
1035 CFG_CTL_NTF_LIM,
1036 WNI_CFG_TDLS_QOS_WMM_UAPSD_MASK_STAMIN,
1037 WNI_CFG_TDLS_QOS_WMM_UAPSD_MASK_STAMAX,
1038 WNI_CFG_TDLS_QOS_WMM_UAPSD_MASK_STADEF},
1039 {WNI_CFG_TDLS_BUF_STA_ENABLED,
1040 CFG_CTL_VALID | CFG_CTL_RE | CFG_CTL_WE | CFG_CTL_INT |
1041 CFG_CTL_NTF_LIM,
1042 WNI_CFG_TDLS_BUF_STA_ENABLED_STAMIN,
1043 WNI_CFG_TDLS_BUF_STA_ENABLED_STAMAX,
1044 WNI_CFG_TDLS_BUF_STA_ENABLED_STADEF},
1045 {WNI_CFG_TDLS_PUAPSD_INACT_TIME,
1046 CFG_CTL_VALID | CFG_CTL_RE | CFG_CTL_WE | CFG_CTL_INT |
1047 CFG_CTL_NTF_LIM,
1048 WNI_CFG_TDLS_PUAPSD_INACT_TIME_STAMIN,
1049 WNI_CFG_TDLS_PUAPSD_INACT_TIME_STAMAX,
1050 WNI_CFG_TDLS_PUAPSD_INACT_TIME_STADEF},
1051 {WNI_CFG_TDLS_RX_FRAME_THRESHOLD,
1052 CFG_CTL_VALID | CFG_CTL_RE | CFG_CTL_WE | CFG_CTL_INT |
1053 CFG_CTL_NTF_LIM,
1054 WNI_CFG_TDLS_RX_FRAME_THRESHOLD_STAMIN,
1055 WNI_CFG_TDLS_RX_FRAME_THRESHOLD_STAMAX,
1056 WNI_CFG_TDLS_RX_FRAME_THRESHOLD_STADEF},
1057 {WNI_CFG_PMF_SA_QUERY_MAX_RETRIES,
1058 CFG_CTL_VALID | CFG_CTL_RE | CFG_CTL_WE | CFG_CTL_INT |
1059 CFG_CTL_RESTART,
1060 WNI_CFG_PMF_SA_QUERY_MAX_RETRIES_STAMIN,
1061 WNI_CFG_PMF_SA_QUERY_MAX_RETRIES_STAMAX,
1062 WNI_CFG_PMF_SA_QUERY_MAX_RETRIES_STADEF},
1063 {WNI_CFG_PMF_SA_QUERY_RETRY_INTERVAL,
1064 CFG_CTL_VALID | CFG_CTL_RE | CFG_CTL_WE | CFG_CTL_INT |
1065 CFG_CTL_RESTART,
1066 WNI_CFG_PMF_SA_QUERY_RETRY_INTERVAL_STAMIN,
1067 WNI_CFG_PMF_SA_QUERY_RETRY_INTERVAL_STAMAX,
1068 WNI_CFG_PMF_SA_QUERY_RETRY_INTERVAL_STADEF},
1069 {WNI_CFG_ENABLE_ADAPT_RX_DRAIN,
1070 CFG_CTL_VALID | CFG_CTL_RE | CFG_CTL_WE | CFG_CTL_INT |
1071 CFG_CTL_NTF_HAL,
1072 WNI_CFG_ENABLE_ADAPT_RX_DRAIN_STAMIN,
1073 WNI_CFG_ENABLE_ADAPT_RX_DRAIN_STAMAX,
1074 WNI_CFG_ENABLE_ADAPT_RX_DRAIN_STADEF},
Prakash Dhavali7090c5f2015-11-02 17:55:19 -0800[diff] [blame]1075 {WNI_CFG_ANTENNA_DIVESITY,
1076 CFG_CTL_VALID | CFG_CTL_RE | CFG_CTL_WE | CFG_CTL_INT |
1077 CFG_CTL_NTF_HAL,
1078 WNI_CFG_ANTENNA_DIVESITY_STAMIN,
1079 WNI_CFG_ANTENNA_DIVESITY_STAMAX,
1080 WNI_CFG_ANTENNA_DIVESITY_STADEF},
1081 {WNI_CFG_GO_LINK_MONITOR_TIMEOUT,
1082 CFG_CTL_VALID | CFG_CTL_RE | CFG_CTL_WE | CFG_CTL_INT |
1083 CFG_CTL_NTF_HAL,
1084 WNI_CFG_GO_LINK_MONITOR_TIMEOUT_STAMIN,
1085 WNI_CFG_GO_LINK_MONITOR_TIMEOUT_STAMAX,
1086 WNI_CFG_GO_LINK_MONITOR_TIMEOUT_STADEF},
1087 {WNI_CFG_RMC_ACTION_PERIOD_FREQUENCY,
1088 CFG_CTL_VALID | CFG_CTL_RE | CFG_CTL_WE | CFG_CTL_INT |
1089 CFG_CTL_NTF_HAL,
1090 WNI_CFG_RMC_ACTION_PERIOD_FREQUENCY_STAMIN,
1091 WNI_CFG_RMC_ACTION_PERIOD_FREQUENCY_STAMAX,
1092 WNI_CFG_RMC_ACTION_PERIOD_FREQUENCY_STADEF},
1093 {WNI_CFG_CURRENT_RSSI,
1094 CFG_CTL_VALID | CFG_CTL_RE | CFG_CTL_WE | CFG_CTL_INT,
1095 WNI_CFG_CURRENT_RSSI_STAMIN,
1096 WNI_CFG_CURRENT_RSSI_STAMAX,
1097 WNI_CFG_CURRENT_RSSI_STADEF},
1098 {WNI_CFG_RTT3_ENABLE,
1099 CFG_CTL_VALID | CFG_CTL_RE | CFG_CTL_WE | CFG_CTL_INT,
1100 WNI_CFG_RTT3_ENABLE_STAMIN,
1101 WNI_CFG_RTT3_ENABLE_STAMAX,
1102 WNI_CFG_RTT3_ENABLE_STADEF},
1103 {WNI_CFG_DEBUG_P2P_REMAIN_ON_CHANNEL,
1104 CFG_CTL_VALID | CFG_CTL_RE | CFG_CTL_WE | CFG_CTL_INT,
1105 WNI_CFG_DEBUG_P2P_REMAIN_ON_CHANNEL_STAMIN,
1106 WNI_CFG_DEBUG_P2P_REMAIN_ON_CHANNEL_STAMAX,
1107 WNI_CFG_DEBUG_P2P_REMAIN_ON_CHANNEL_STADEF},
1108 {WNI_CFG_TDLS_OFF_CHANNEL_ENABLED,
1109 CFG_CTL_VALID | CFG_CTL_RE | CFG_CTL_WE | CFG_CTL_INT |
1110 CFG_CTL_NTF_LIM,
1111 WNI_CFG_TDLS_OFF_CHANNEL_ENABLED_STAMIN,
1112 WNI_CFG_TDLS_OFF_CHANNEL_ENABLED_STAMAX,
1113 WNI_CFG_TDLS_OFF_CHANNEL_ENABLED_STADEF},
1114 {WNI_CFG_IBSS_ATIM_WIN_SIZE,
1115 CFG_CTL_VALID | CFG_CTL_RE | CFG_CTL_WE | CFG_CTL_INT,
1116 WNI_CFG_IBSS_ATIM_WIN_SIZE_STAMIN,
1117 WNI_CFG_IBSS_ATIM_WIN_SIZE_STAMAX,
1118 WNI_CFG_IBSS_ATIM_WIN_SIZE_STADEF},
1119 {WNI_CFG_DFS_MASTER_ENABLED,
1120 CFG_CTL_VALID | CFG_CTL_RE | CFG_CTL_WE | CFG_CTL_INT,
1121 WNI_CFG_DFS_MASTER_ENABLED_STAMIN,
1122 WNI_CFG_DFS_MASTER_ENABLED_STAMAX,
1123 WNI_CFG_DFS_MASTER_ENABLED_STADEF},
1124 {WNI_CFG_VHT_ENABLE_TXBF_20MHZ,
1125 CFG_CTL_VALID | CFG_CTL_RE | CFG_CTL_WE | CFG_CTL_INT,
1126 WNI_CFG_VHT_ENABLE_TXBF_20MHZ_STAMIN,
1127 WNI_CFG_VHT_ENABLE_TXBF_20MHZ_STAMAX,
1128 WNI_CFG_VHT_ENABLE_TXBF_20MHZ_STADEF},
1129 {WNI_CFG_TDLS_WMM_MODE_ENABLED,
1130 CFG_CTL_VALID | CFG_CTL_RE | CFG_CTL_WE | CFG_CTL_INT |
1131 CFG_CTL_NTF_LIM,
1132 WNI_CFG_TDLS_WMM_MODE_ENABLED_STAMIN,
1133 WNI_CFG_TDLS_WMM_MODE_ENABLED_STAMAX,
Sandeep Puligillae0875662016-02-12 16:09:21 -0800[diff] [blame]1134 WNI_CFG_TDLS_WMM_MODE_ENABLED_STADEF},
1135 {WNI_CFG_OBSS_HT40_SCAN_PASSIVE_DWELL_TIME,
1136 CFG_CTL_VALID | CFG_CTL_RE | CFG_CTL_WE | CFG_CTL_INT |
1137 CFG_CTL_NTF_LIM,
1138 WNI_CFG_OBSS_HT40_SCAN_PASSIVE_DWELL_TIME_STAMIN,
1139 WNI_CFG_OBSS_HT40_SCAN_PASSIVE_DWELL_TIME_STAMAX,
1140 WNI_CFG_OBSS_HT40_SCAN_PASSIVE_DWELL_TIME_STADEF},
1141 {WNI_CFG_OBSS_HT40_SCAN_ACTIVE_DWELL_TIME,
1142 CFG_CTL_VALID | CFG_CTL_RE | CFG_CTL_WE | CFG_CTL_INT |
1143 CFG_CTL_NTF_LIM,
1144 WNI_CFG_OBSS_HT40_SCAN_ACTIVE_DWELL_TIME_STAMIN,
1145 WNI_CFG_OBSS_HT40_SCAN_ACTIVE_DWELL_TIME_STAMAX,
1146 WNI_CFG_OBSS_HT40_SCAN_ACTIVE_DWELL_TIME_STADEF},
1147 {WNI_CFG_OBSS_HT40_SCAN_WIDTH_TRIGGER_INTERVAL,
1148 CFG_CTL_VALID | CFG_CTL_RE | CFG_CTL_WE | CFG_CTL_INT |
1149 CFG_CTL_NTF_LIM,
1150 WNI_CFG_OBSS_HT40_SCAN_WIDTH_TRIGGER_INTERVAL_STAMIN,
1151 WNI_CFG_OBSS_HT40_SCAN_WIDTH_TRIGGER_INTERVAL_STAMAX,
1152 WNI_CFG_OBSS_HT40_SCAN_WIDTH_TRIGGER_INTERVAL_STADEF},
1153 {WNI_CFG_OBSS_HT40_SCAN_PASSIVE_TOTAL_PER_CHANNEL,
1154 CFG_CTL_VALID | CFG_CTL_RE | CFG_CTL_WE | CFG_CTL_INT |
1155 CFG_CTL_NTF_LIM,
1156 WNI_CFG_OBSS_HT40_SCAN_PASSIVE_TOTAL_PER_CHANNEL_STAMIN,
1157 WNI_CFG_OBSS_HT40_SCAN_PASSIVE_TOTAL_PER_CHANNEL_STAMAX,
1158 WNI_CFG_OBSS_HT40_SCAN_PASSIVE_TOTAL_PER_CHANNEL_STADEF},
1159 {WNI_CFG_OBSS_HT40_SCAN_ACTIVE_TOTAL_PER_CHANNEL,
1160 CFG_CTL_VALID | CFG_CTL_RE | CFG_CTL_WE | CFG_CTL_INT |
1161 CFG_CTL_NTF_LIM,
1162 WNI_CFG_OBSS_HT40_SCAN_ACTIVE_TOTAL_PER_CHANNEL_STAMIN,
1163 WNI_CFG_OBSS_HT40_SCAN_ACTIVE_TOTAL_PER_CHANNEL_STAMAX,
1164 WNI_CFG_OBSS_HT40_SCAN_ACTIVE_TOTAL_PER_CHANNEL_STADEF},
1165 {WNI_CFG_OBSS_HT40_WIDTH_CH_TRANSITION_DELAY,
1166 CFG_CTL_VALID | CFG_CTL_RE | CFG_CTL_WE | CFG_CTL_INT |
1167 CFG_CTL_NTF_LIM,
1168 WNI_CFG_OBSS_HT40_WIDTH_CH_TRANSITION_DELAY_STAMIN,
1169 WNI_CFG_OBSS_HT40_WIDTH_CH_TRANSITION_DELAY_STAMAX,
1170 WNI_CFG_OBSS_HT40_WIDTH_CH_TRANSITION_DELAY_STADEF},
1171 {WNI_CFG_OBSS_HT40_SCAN_ACTIVITY_THRESHOLD,
1172 CFG_CTL_VALID | CFG_CTL_RE | CFG_CTL_WE | CFG_CTL_INT |
1173 CFG_CTL_NTF_LIM,
1174 WNI_CFG_OBSS_HT40_SCAN_ACTIVITY_THRESHOLD_STAMIN,
1175 WNI_CFG_OBSS_HT40_SCAN_ACTIVITY_THRESHOLD_STAMAX,
Rajeev Kumar Sirasanagandlaaf474742016-09-06 17:54:50 +0530[diff] [blame]1176 WNI_CFG_OBSS_HT40_SCAN_ACTIVITY_THRESHOLD_STADEF},
1177 {WNI_CFG_TGT_GTX_USR_CFG,
1178 CFG_CTL_VALID | CFG_CTL_RE | CFG_CTL_WE | CFG_CTL_INT,
1179 WNI_CFG_TGT_GTX_USR_CFG_STAMIN,
1180 WNI_CFG_TGT_GTX_USR_CFG_STAMAX,
Hong Shi417824f2017-01-12 02:31:14 +0800[diff] [blame]1181 WNI_CFG_TGT_GTX_USR_CFG_STADEF},
1182 {WNI_CFG_MAX_HT_MCS_TX_DATA,
1183 CFG_CTL_VALID | CFG_CTL_RE | CFG_CTL_WE | CFG_CTL_INT,
1184 WNI_CFG_MAX_HT_MCS_TX_DATA_STAMIN,
1185 WNI_CFG_MAX_HT_MCS_TX_DATA_STAMAX,
Hong Shia9ef8712017-02-19 21:54:02 +0800[diff] [blame]1186 WNI_CFG_MAX_HT_MCS_TX_DATA_STADEF},
1187 {WNI_CFG_DISABLE_ABG_RATE_FOR_TX_DATA,
1188 CFG_CTL_VALID | CFG_CTL_RE | CFG_CTL_WE | CFG_CTL_INT,
1189 WNI_CFG_DISABLE_ABG_RATE_FOR_TX_DATA_STAMIN,
1190 WNI_CFG_DISABLE_ABG_RATE_FOR_TX_DATA_STAMAX,
Hong Shib90718f2017-02-20 00:57:22 +0800[diff] [blame]1191 WNI_CFG_DISABLE_ABG_RATE_FOR_TX_DATA_STADEF},
1192 {WNI_CFG_RATE_FOR_TX_MGMT,
1193 CFG_CTL_VALID | CFG_CTL_RE | CFG_CTL_WE | CFG_CTL_INT,
1194 WNI_CFG_RATE_FOR_TX_MGMT_STAMIN,
1195 WNI_CFG_RATE_FOR_TX_MGMT_STAMAX,
Krishna Kumaar Natarajaned1efd92016-09-24 18:05:47 -0700[diff] [blame^]1196 WNI_CFG_RATE_FOR_TX_MGMT_STADEF},
1197 {WNI_CFG_HE_CONTROL,
1198 CFG_CTL_VALID | CFG_CTL_RE | CFG_CTL_WE | CFG_CTL_INT,
1199 WNI_CFG_HE_CONTROL_STAMIN, WNI_CFG_HE_CONTROL_STAMAX,
1200 WNI_CFG_HE_CONTROL_STADEF},
1201 {WNI_CFG_HE_TWT_REQUESTOR,
1202 CFG_CTL_VALID | CFG_CTL_RE | CFG_CTL_WE | CFG_CTL_INT,
1203 WNI_CFG_HE_TWT_REQUESTOR_STAMIN, WNI_CFG_HE_TWT_REQUESTOR_STAMAX,
1204 WNI_CFG_HE_TWT_REQUESTOR_STADEF},
1205 {WNI_CFG_HE_TWT_RESPONDER,
1206 CFG_CTL_VALID | CFG_CTL_RE | CFG_CTL_WE | CFG_CTL_INT,
1207 WNI_CFG_HE_TWT_RESPONDER_STAMIN, WNI_CFG_HE_TWT_RESPONDER_STAMAX,
1208 WNI_CFG_HE_TWT_RESPONDER_STADEF},
1209 {WNI_CFG_HE_FRAGMENTATION,
1210 CFG_CTL_VALID | CFG_CTL_RE | CFG_CTL_WE | CFG_CTL_INT,
1211 WNI_CFG_HE_FRAGMENTATION_STAMIN, WNI_CFG_HE_FRAGMENTATION_STAMAX,
1212 WNI_CFG_HE_FRAGMENTATION_STADEF},
1213 {WNI_CFG_HE_MAX_FRAG_MSDU,
1214 CFG_CTL_VALID | CFG_CTL_RE | CFG_CTL_WE | CFG_CTL_INT,
1215 WNI_CFG_HE_MAX_FRAG_MSDU_STAMIN, WNI_CFG_HE_MAX_FRAG_MSDU_STAMAX,
1216 WNI_CFG_HE_MAX_FRAG_MSDU_STADEF},
1217 {WNI_CFG_HE_MIN_FRAG_SIZE,
1218 CFG_CTL_VALID | CFG_CTL_RE | CFG_CTL_WE | CFG_CTL_INT,
1219 WNI_CFG_HE_MIN_FRAG_SIZE_STAMIN, WNI_CFG_HE_MIN_FRAG_SIZE_STAMAX,
1220 WNI_CFG_HE_MIN_FRAG_SIZE_STADEF},
1221 {WNI_CFG_HE_TRIG_PAD,
1222 CFG_CTL_VALID | CFG_CTL_RE | CFG_CTL_WE | CFG_CTL_INT,
1223 WNI_CFG_HE_TRIG_PAD_STAMIN, WNI_CFG_HE_TRIG_PAD_STAMAX,
1224 WNI_CFG_HE_TRIG_PAD_STADEF},
1225 {WNI_CFG_HE_MTID_AGGR,
1226 CFG_CTL_VALID | CFG_CTL_RE | CFG_CTL_WE | CFG_CTL_INT,
1227 WNI_CFG_HE_MTID_AGGR_STAMIN, WNI_CFG_HE_MTID_AGGR_STAMAX,
1228 WNI_CFG_HE_MTID_AGGR_STADEF},
1229 {WNI_CFG_HE_LINK_ADAPTATION,
1230 CFG_CTL_VALID | CFG_CTL_RE | CFG_CTL_WE | CFG_CTL_INT,
1231 WNI_CFG_HE_LINK_ADAPTATION_STAMIN, WNI_CFG_HE_LINK_ADAPTATION_STAMAX,
1232 WNI_CFG_HE_LINK_ADAPTATION_STADEF},
1233 {WNI_CFG_HE_ALL_ACK,
1234 CFG_CTL_VALID | CFG_CTL_RE | CFG_CTL_WE | CFG_CTL_INT,
1235 WNI_CFG_HE_ALL_ACK_STAMIN, WNI_CFG_HE_ALL_ACK_STAMAX,
1236 WNI_CFG_HE_ALL_ACK_STADEF},
1237 {WNI_CFG_HE_UL_MU_RSP_SCHEDULING,
1238 CFG_CTL_VALID | CFG_CTL_RE | CFG_CTL_WE | CFG_CTL_INT,
1239 WNI_CFG_HE_UL_MU_RSP_SCHEDULING_STAMIN,
1240 WNI_CFG_HE_UL_MU_RSP_SCHEDULING_STAMAX,
1241 WNI_CFG_HE_UL_MU_RSP_SCHEDULING_STADEF},
1242 {WNI_CFG_HE_BUFFER_STATUS_RPT,
1243 CFG_CTL_VALID | CFG_CTL_RE | CFG_CTL_WE | CFG_CTL_INT,
1244 WNI_CFG_HE_BUFFER_STATUS_RPT_STAMIN,
1245 WNI_CFG_HE_BUFFER_STATUS_RPT_STAMAX,
1246 WNI_CFG_HE_BUFFER_STATUS_RPT_STADEF},
1247 {WNI_CFG_HE_BCAST_TWT,
1248 CFG_CTL_VALID | CFG_CTL_RE | CFG_CTL_WE | CFG_CTL_INT,
1249 WNI_CFG_HE_BCAST_TWT_STAMIN, WNI_CFG_HE_BCAST_TWT_STAMAX,
1250 WNI_CFG_HE_BCAST_TWT_STADEF},
1251 {WNI_CFG_HE_BA_32BIT,
1252 CFG_CTL_VALID | CFG_CTL_RE | CFG_CTL_WE | CFG_CTL_INT,
1253 WNI_CFG_HE_BA_32BIT_STAMIN, WNI_CFG_HE_BA_32BIT_STAMAX,
1254 WNI_CFG_HE_BA_32BIT_STADEF},
1255 {WNI_CFG_HE_MU_CASCADING,
1256 CFG_CTL_VALID | CFG_CTL_RE | CFG_CTL_WE | CFG_CTL_INT,
1257 WNI_CFG_HE_MU_CASCADING_STAMIN, WNI_CFG_HE_MU_CASCADING_STAMAX,
1258 WNI_CFG_HE_MU_CASCADING_STADEF},
1259 {WNI_CFG_HE_MULTI_TID,
1260 CFG_CTL_VALID | CFG_CTL_RE | CFG_CTL_WE | CFG_CTL_INT,
1261 WNI_CFG_HE_MULTI_TID_STAMIN, WNI_CFG_HE_MULTI_TID_STAMAX,
1262 WNI_CFG_HE_MULTI_TID_STADEF},
1263 {WNI_CFG_HE_DL_MU_BA,
1264 CFG_CTL_VALID | CFG_CTL_RE | CFG_CTL_WE | CFG_CTL_INT,
1265 WNI_CFG_HE_DL_MU_BA_STAMIN, WNI_CFG_HE_DL_MU_BA_STAMAX,
1266 WNI_CFG_HE_DL_MU_BA_STADEF},
1267 {WNI_CFG_HE_OMI,
1268 CFG_CTL_VALID | CFG_CTL_RE | CFG_CTL_WE | CFG_CTL_INT,
1269 WNI_CFG_HE_OMI_STAMIN, WNI_CFG_HE_OMI_STAMAX,
1270 WNI_CFG_HE_OMI_STADEF},
1271 {WNI_CFG_HE_OFDMA_RA,
1272 CFG_CTL_VALID | CFG_CTL_RE | CFG_CTL_WE | CFG_CTL_INT,
1273 WNI_CFG_HE_OFDMA_RA_STAMIN, WNI_CFG_HE_OFDMA_RA_STAMAX,
1274 WNI_CFG_HE_OFDMA_RA_STADEF},
1275 {WNI_CFG_HE_MAX_AMPDU_LEN,
1276 CFG_CTL_VALID | CFG_CTL_RE | CFG_CTL_WE | CFG_CTL_INT,
1277 WNI_CFG_HE_MAX_AMPDU_LEN_STAMIN, WNI_CFG_HE_MAX_AMPDU_LEN_STAMAX,
1278 WNI_CFG_HE_MAX_AMPDU_LEN_STADEF},
1279 {WNI_CFG_HE_AMSDU_FRAG,
1280 CFG_CTL_VALID | CFG_CTL_RE | CFG_CTL_WE | CFG_CTL_INT,
1281 WNI_CFG_HE_AMSDU_FRAG_STAMIN, WNI_CFG_HE_AMSDU_FRAG_STAMAX,
1282 WNI_CFG_HE_AMSDU_FRAG_STADEF},
1283 {WNI_CFG_HE_FLEX_TWT_SCHED,
1284 CFG_CTL_VALID | CFG_CTL_RE | CFG_CTL_WE | CFG_CTL_INT,
1285 WNI_CFG_HE_FLEX_TWT_SCHED_STAMIN, WNI_CFG_HE_FLEX_TWT_SCHED_STAMAX,
1286 WNI_CFG_HE_FLEX_TWT_SCHED_STADEF},
1287 {WNI_CFG_HE_RX_CTRL,
1288 CFG_CTL_VALID | CFG_CTL_RE | CFG_CTL_WE | CFG_CTL_INT,
1289 WNI_CFG_HE_RX_CTRL_STAMIN, WNI_CFG_HE_RX_CTRL_STAMAX,
1290 WNI_CFG_HE_RX_CTRL_STADEF},
1291 {WNI_CFG_HE_BSRP_AMPDU_AGGR,
1292 CFG_CTL_VALID | CFG_CTL_RE | CFG_CTL_WE | CFG_CTL_INT,
1293 WNI_CFG_HE_BSRP_AMPDU_AGGR_STAMIN, WNI_CFG_HE_BSRP_AMPDU_AGGR_STAMAX,
1294 WNI_CFG_HE_BSRP_AMPDU_AGGR_STADEF},
1295 {WNI_CFG_HE_QTP,
1296 CFG_CTL_VALID | CFG_CTL_RE | CFG_CTL_WE | CFG_CTL_INT,
1297 WNI_CFG_HE_QTP_STAMIN, WNI_CFG_HE_QTP_STAMAX,
1298 WNI_CFG_HE_QTP_STADEF},
1299 {WNI_CFG_HE_A_BQR,
1300 CFG_CTL_VALID | CFG_CTL_RE | CFG_CTL_WE | CFG_CTL_INT,
1301 WNI_CFG_HE_A_BQR_STAMIN, WNI_CFG_HE_A_BQR_STAMAX,
1302 WNI_CFG_HE_A_BQR_STADEF},
1303 {WNI_CFG_HE_DUAL_BAND,
1304 CFG_CTL_VALID | CFG_CTL_RE | CFG_CTL_WE | CFG_CTL_INT,
1305 WNI_CFG_HE_DUAL_BAND_STAMIN, WNI_CFG_HE_DUAL_BAND_STAMAX,
1306 WNI_CFG_HE_DUAL_BAND_STADEF},
1307 {WNI_CFG_HE_CHAN_WIDTH,
1308 CFG_CTL_VALID | CFG_CTL_RE | CFG_CTL_WE | CFG_CTL_INT,
1309 WNI_CFG_HE_CHAN_WIDTH_STAMIN, WNI_CFG_HE_CHAN_WIDTH_STAMAX,
1310 WNI_CFG_HE_CHAN_WIDTH_STADEF},
1311 {WNI_CFG_HE_RX_PREAM_PUNC,
1312 CFG_CTL_VALID | CFG_CTL_RE | CFG_CTL_WE | CFG_CTL_INT,
1313 WNI_CFG_HE_RX_PREAM_PUNC_STAMIN, WNI_CFG_HE_RX_PREAM_PUNC_STAMAX,
1314 WNI_CFG_HE_RX_PREAM_PUNC_STADEF},
1315 {WNI_CFG_HE_CLASS_OF_DEVICE,
1316 CFG_CTL_VALID | CFG_CTL_RE | CFG_CTL_WE | CFG_CTL_INT,
1317 WNI_CFG_HE_CLASS_OF_DEVICE_STAMIN, WNI_CFG_HE_CLASS_OF_DEVICE_STAMAX,
1318 WNI_CFG_HE_CLASS_OF_DEVICE_STADEF},
1319 {WNI_CFG_HE_LDPC,
1320 CFG_CTL_VALID | CFG_CTL_RE | CFG_CTL_WE | CFG_CTL_INT,
1321 WNI_CFG_HE_LDPC_STAMIN, WNI_CFG_HE_LDPC_STAMAX,
1322 WNI_CFG_HE_LDPC_STADEF},
1323 {WNI_CFG_HE_LTF_PPDU,
1324 CFG_CTL_VALID | CFG_CTL_RE | CFG_CTL_WE | CFG_CTL_INT,
1325 WNI_CFG_HE_LTF_PPDU_STAMIN, WNI_CFG_HE_LTF_PPDU_STAMAX,
1326 WNI_CFG_HE_LTF_PPDU_STADEF},
1327 {WNI_CFG_HE_LTF_NDP,
1328 CFG_CTL_VALID | CFG_CTL_RE | CFG_CTL_WE | CFG_CTL_INT,
1329 WNI_CFG_HE_LTF_NDP_STAMIN, WNI_CFG_HE_LTF_NDP_STAMAX,
1330 WNI_CFG_HE_LTF_NDP_STADEF},
1331 {WNI_CFG_HE_STBC,
1332 CFG_CTL_VALID | CFG_CTL_RE | CFG_CTL_WE | CFG_CTL_INT,
1333 WNI_CFG_HE_STBC_STAMIN, WNI_CFG_HE_STBC_STAMAX,
1334 WNI_CFG_HE_STBC_STADEF},
1335 {WNI_CFG_HE_DOPPLER,
1336 CFG_CTL_VALID | CFG_CTL_RE | CFG_CTL_WE | CFG_CTL_INT,
1337 WNI_CFG_HE_DOPPLER_STAMIN, WNI_CFG_HE_DOPPLER_STAMAX,
1338 WNI_CFG_HE_DOPPLER_STADEF},
1339 {WNI_CFG_HE_UL_MUMIMO,
1340 CFG_CTL_VALID | CFG_CTL_RE | CFG_CTL_WE | CFG_CTL_INT,
1341 WNI_CFG_HE_UL_MUMIMO_STAMIN, WNI_CFG_HE_UL_MUMIMO_STAMAX,
1342 WNI_CFG_HE_UL_MUMIMO_STADEF},
1343 {WNI_CFG_HE_DCM_TX,
1344 CFG_CTL_VALID | CFG_CTL_RE | CFG_CTL_WE | CFG_CTL_INT,
1345 WNI_CFG_HE_DCM_TX_STAMIN, WNI_CFG_HE_DCM_TX_STAMAX,
1346 WNI_CFG_HE_DCM_TX_STADEF},
1347 {WNI_CFG_HE_DCM_RX,
1348 CFG_CTL_VALID | CFG_CTL_RE | CFG_CTL_WE | CFG_CTL_INT,
1349 WNI_CFG_HE_DCM_RX_STAMIN, WNI_CFG_HE_DCM_RX_STAMAX,
1350 WNI_CFG_HE_DCM_RX_STADEF},
1351 {WNI_CFG_HE_MU_PPDU,
1352 CFG_CTL_VALID | CFG_CTL_RE | CFG_CTL_WE | CFG_CTL_INT,
1353 WNI_CFG_HE_MU_PPDU_STAMIN, WNI_CFG_HE_MU_PPDU_STAMAX,
1354 WNI_CFG_HE_MU_PPDU_STADEF},
1355 {WNI_CFG_HE_SU_BEAMFORMER,
1356 CFG_CTL_VALID | CFG_CTL_RE | CFG_CTL_WE | CFG_CTL_INT,
1357 CFG_CTL_VALID | CFG_CTL_RE | CFG_CTL_WE | CFG_CTL_INT,
1358 WNI_CFG_HE_SU_BEAMFORMER_STAMIN, WNI_CFG_HE_SU_BEAMFORMER_STAMAX,
1359 WNI_CFG_HE_SU_BEAMFORMER_STADEF},
1360 {WNI_CFG_HE_SU_BEAMFORMEE,
1361 CFG_CTL_VALID | CFG_CTL_RE | CFG_CTL_WE | CFG_CTL_INT,
1362 WNI_CFG_HE_SU_BEAMFORMEE_STAMIN, WNI_CFG_HE_SU_BEAMFORMEE_STAMAX,
1363 WNI_CFG_HE_SU_BEAMFORMEE_STADEF},
1364 {WNI_CFG_HE_MU_BEAMFORMER,
1365 CFG_CTL_VALID | CFG_CTL_RE | CFG_CTL_WE | CFG_CTL_INT,
1366 WNI_CFG_HE_MU_BEAMFORMER_STAMIN, WNI_CFG_HE_MU_BEAMFORMER_STAMAX,
1367 WNI_CFG_HE_MU_BEAMFORMER_STADEF},
1368 {WNI_CFG_HE_BFEE_STS_LT80,
1369 CFG_CTL_VALID | CFG_CTL_RE | CFG_CTL_WE | CFG_CTL_INT,
1370 WNI_CFG_HE_BFEE_STS_LT80_STAMIN, WNI_CFG_HE_BFEE_STS_LT80_STAMAX,
1371 WNI_CFG_HE_BFEE_STS_LT80_STADEF},
1372 {WNI_CFG_HE_NSTS_TOT_LT80,
1373 CFG_CTL_VALID | CFG_CTL_RE | CFG_CTL_WE | CFG_CTL_INT,
1374 WNI_CFG_HE_NSTS_TOT_LT80_STAMIN, WNI_CFG_HE_NSTS_TOT_LT80_STAMAX,
1375 WNI_CFG_HE_NSTS_TOT_LT80_STADEF},
1376 {WNI_CFG_HE_BFEE_STS_GT80,
1377 CFG_CTL_VALID | CFG_CTL_RE | CFG_CTL_WE | CFG_CTL_INT,
1378 WNI_CFG_HE_BFEE_STS_GT80_STAMIN, WNI_CFG_HE_BFEE_STS_GT80_STAMAX,
1379 WNI_CFG_HE_BFEE_STS_GT80_STADEF},
1380 {WNI_CFG_HE_NSTS_TOT_GT80,
1381 CFG_CTL_VALID | CFG_CTL_RE | CFG_CTL_WE | CFG_CTL_INT,
1382 WNI_CFG_HE_NSTS_TOT_GT80_STAMIN, WNI_CFG_HE_NSTS_TOT_GT80_STAMAX,
1383 WNI_CFG_HE_NSTS_TOT_GT80_STADEF},
1384 {WNI_CFG_HE_NUM_SOUND_LT80,
1385 CFG_CTL_VALID | CFG_CTL_RE | CFG_CTL_WE | CFG_CTL_INT,
1386 WNI_CFG_HE_NUM_SOUND_LT80_STAMIN, WNI_CFG_HE_NUM_SOUND_LT80_STAMAX,
1387 WNI_CFG_HE_NUM_SOUND_LT80_STADEF},
1388 {WNI_CFG_HE_NUM_SOUND_GT80,
1389 CFG_CTL_VALID | CFG_CTL_RE | CFG_CTL_WE | CFG_CTL_INT,
1390 WNI_CFG_HE_NUM_SOUND_GT80_STAMIN, WNI_CFG_HE_NUM_SOUND_GT80_STAMAX,
1391 WNI_CFG_HE_NUM_SOUND_GT80_STADEF},
1392 {WNI_CFG_HE_SU_FEED_TONE16,
1393 CFG_CTL_VALID | CFG_CTL_RE | CFG_CTL_WE | CFG_CTL_INT,
1394 WNI_CFG_HE_SU_FEED_TONE16_STAMIN, WNI_CFG_HE_SU_FEED_TONE16_STAMAX,
1395 WNI_CFG_HE_SU_FEED_TONE16_STADEF},
1396 {WNI_CFG_HE_MU_FEED_TONE16,
1397 CFG_CTL_VALID | CFG_CTL_RE | CFG_CTL_WE | CFG_CTL_INT,
1398 WNI_CFG_HE_MU_FEED_TONE16_STAMIN, WNI_CFG_HE_MU_FEED_TONE16_STAMAX,
1399 WNI_CFG_HE_MU_FEED_TONE16_STADEF},
1400 {WNI_CFG_HE_CODEBOOK_SU,
1401 CFG_CTL_VALID | CFG_CTL_RE | CFG_CTL_WE | CFG_CTL_INT,
1402 WNI_CFG_HE_CODEBOOK_SU_STAMIN, WNI_CFG_HE_CODEBOOK_SU_STAMAX,
1403 WNI_CFG_HE_CODEBOOK_SU_STADEF},
1404 {WNI_CFG_HE_CODEBOOK_MU,
1405 CFG_CTL_VALID | CFG_CTL_RE | CFG_CTL_WE | CFG_CTL_INT,
1406 WNI_CFG_HE_CODEBOOK_MU_STAMIN, WNI_CFG_HE_CODEBOOK_MU_STAMAX,
1407 WNI_CFG_HE_CODEBOOK_MU_STADEF},
1408 {WNI_CFG_HE_BFRM_FEED,
1409 CFG_CTL_VALID | CFG_CTL_RE | CFG_CTL_WE | CFG_CTL_INT,
1410 WNI_CFG_HE_BFRM_FEED_STAMIN, WNI_CFG_HE_BFRM_FEED_STAMAX,
1411 WNI_CFG_HE_BFRM_FEED_STADEF},
1412 {WNI_CFG_HE_ER_SU_PPDU,
1413 CFG_CTL_VALID | CFG_CTL_RE | CFG_CTL_WE | CFG_CTL_INT,
1414 WNI_CFG_HE_ER_SU_PPDU_STAMIN, WNI_CFG_HE_ER_SU_PPDU_STAMAX,
1415 WNI_CFG_HE_ER_SU_PPDU_STADEF},
1416 {WNI_CFG_HE_DL_PART_BW,
1417 CFG_CTL_VALID | CFG_CTL_RE | CFG_CTL_WE | CFG_CTL_INT,
1418 WNI_CFG_HE_DL_PART_BW_STAMIN, WNI_CFG_HE_DL_PART_BW_STAMAX,
1419 WNI_CFG_HE_DL_PART_BW_STADEF},
1420 {WNI_CFG_HE_PPET_PRESENT,
1421 CFG_CTL_VALID | CFG_CTL_RE | CFG_CTL_WE | CFG_CTL_INT,
1422 WNI_CFG_HE_PPET_PRESENT_STAMIN, WNI_CFG_HE_PPET_PRESENT_STAMAX,
1423 WNI_CFG_HE_PPET_PRESENT_STADEF},
1424 {WNI_CFG_HE_SRP,
1425 CFG_CTL_VALID | CFG_CTL_RE | CFG_CTL_WE | CFG_CTL_INT,
1426 WNI_CFG_HE_SRP_STAMIN, WNI_CFG_HE_SRP_STAMAX,
1427 WNI_CFG_HE_SRP_STADEF},
1428 {WNI_CFG_HE_POWER_BOOST,
1429 CFG_CTL_VALID | CFG_CTL_RE | CFG_CTL_WE | CFG_CTL_INT,
1430 WNI_CFG_HE_POWER_BOOST_STAMIN, WNI_CFG_HE_POWER_BOOST_STAMAX,
1431 WNI_CFG_HE_POWER_BOOST_STADEF},
1432 {WNI_CFG_HE_4x_LTF_GI,
1433 CFG_CTL_VALID | CFG_CTL_RE | CFG_CTL_WE | CFG_CTL_INT,
1434 WNI_CFG_HE_4x_LTF_GI_STAMIN, WNI_CFG_HE_4x_LTF_GI_STAMAX,
1435 WNI_CFG_HE_4x_LTF_GI_STADEF},
1436 {WNI_CFG_HE_NSS,
1437 CFG_CTL_VALID | CFG_CTL_RE | CFG_CTL_WE | CFG_CTL_INT,
1438 WNI_CFG_HE_NSS_STAMIN, WNI_CFG_HE_NSS_STAMAX,
1439 WNI_CFG_HE_NSS_STADEF},
1440 {WNI_CFG_HE_MCS,
1441 CFG_CTL_VALID | CFG_CTL_RE | CFG_CTL_WE | CFG_CTL_INT,
1442 WNI_CFG_HE_MCS_STAMIN, WNI_CFG_HE_MCS_STAMAX,
1443 WNI_CFG_HE_MCS_STADEF},
1444 {WNI_CFG_HE_PPET,
1445 CFG_CTL_VALID | CFG_CTL_RE | CFG_CTL_WE,
1446 0, 0, 0}
Prakash Dhavali7090c5f2015-11-02 17:55:19 -0800[diff] [blame]1447};
1448
1449
1450cfgstatic_string cfg_static_string[CFG_MAX_STATIC_STRING] = {
1451
1452 {WNI_CFG_STA_ID,
1453 WNI_CFG_STA_ID_LEN,
1454 6,
1455 {0x22, 0x22, 0x44, 0x44, 0x33, 0x33} },
1456 {WNI_CFG_SSID,
1457 WNI_CFG_SSID_LEN,
1458 10,
1459 {1, 2, 3, 4, 5, 6, 7, 8, 9, 0} },
1460 {WNI_CFG_WEP_DEFAULT_KEY_1,
1461 WNI_CFG_WEP_DEFAULT_KEY_1_LEN,
1462 0,
1463 {0} },
1464 {WNI_CFG_WEP_DEFAULT_KEY_2,
1465 WNI_CFG_WEP_DEFAULT_KEY_2_LEN,
1466 0,
1467 {0} },
1468 {WNI_CFG_WEP_DEFAULT_KEY_3,
1469 WNI_CFG_WEP_DEFAULT_KEY_3_LEN,
1470 0,
1471 {0} },
1472 {WNI_CFG_WEP_DEFAULT_KEY_4,
1473 WNI_CFG_WEP_DEFAULT_KEY_4_LEN,
1474 0,
1475 {0} },
1476 {WNI_CFG_SUPPORTED_RATES_11B,
1477 WNI_CFG_SUPPORTED_RATES_11B_LEN,
1478 4,
1479 {2, 4, 11, 22} },
1480 {WNI_CFG_SUPPORTED_RATES_11A,
1481 WNI_CFG_SUPPORTED_RATES_11A_LEN,
1482 8,
1483 {12, 18, 24, 36, 48, 72, 96, 108} },
1484 {WNI_CFG_OPERATIONAL_RATE_SET,
1485 WNI_CFG_OPERATIONAL_RATE_SET_LEN,
1486 0,
1487 {0} },
1488 {WNI_CFG_EXTENDED_OPERATIONAL_RATE_SET,
1489 WNI_CFG_EXTENDED_OPERATIONAL_RATE_SET_LEN,
1490 0,
1491 {0} },
1492 {WNI_CFG_PROPRIETARY_OPERATIONAL_RATE_SET,
1493 WNI_CFG_PROPRIETARY_OPERATIONAL_RATE_SET_LEN,
1494 4,
1495 {1, 3, 5, 7} },
1496 {WNI_CFG_VALID_CHANNEL_LIST,
1497 WNI_CFG_VALID_CHANNEL_LIST_LEN,
1498 55,
1499 {36, 40, 44, 48, 52, 56, 60, 64, 1, 6, 11, 34, 38, 42, 46, 2, 3, 4,
1500 5, 7, 8, 9, 10, 12, 13, 14, 100, 104, 108, 112, 116, 120, 124, 128,
1501 132, 136, 140, 149, 151, 153, 155, 157, 159, 161, 50, 54, 58, 62, 240,
1502 242, 244, 246, 248, 250, 252} },
1503
Prakash Dhavali7090c5f2015-11-02 17:55:19 -0800[diff] [blame]1504 {WNI_CFG_MANUFACTURER_NAME,
1505 WNI_CFG_MANUFACTURER_NAME_LEN,
1506 8,
1507 {0x51, 0x75, 0x61, 0x6c, 0x63, 0x6f, 0x6d, 0x6d} },
1508 {WNI_CFG_MODEL_NUMBER,
1509 WNI_CFG_MODEL_NUMBER_LEN,
1510 6,
1511 {0x4d, 0x4e, 0x31, 0x32, 0x33, 0x34} },
1512 {WNI_CFG_MODEL_NAME,
1513 WNI_CFG_MODEL_NAME_LEN,
1514 7,
1515 {0x57, 0x46, 0x52, 0x34, 0x30, 0x33, 0x31} },
1516 {WNI_CFG_MANUFACTURER_PRODUCT_NAME,
1517 WNI_CFG_MANUFACTURER_PRODUCT_NAME_LEN,
1518 6,
1519 {0x31, 0x31, 0x6e, 0x2d, 0x41, 0x50} },
1520 {WNI_CFG_MANUFACTURER_PRODUCT_VERSION,
1521 WNI_CFG_MANUFACTURER_PRODUCT_VERSION_LEN,
1522 6,
1523 {0x53, 0x4e, 0x31, 0x32, 0x33, 0x34} },
1524 {WNI_CFG_MAX_TX_POWER_2_4,
1525 WNI_CFG_MAX_TX_POWER_2_4_LEN,
1526 3,
1527 {0x1, 0xe, 0x14} },
1528 {WNI_CFG_MAX_TX_POWER_5,
1529 WNI_CFG_MAX_TX_POWER_5_LEN,
1530 3,
1531 {0x24, 0x7e, 0x14} },
Prakash Dhavali7090c5f2015-11-02 17:55:19 -0800[diff] [blame]1532 {WNI_CFG_COUNTRY_CODE,
1533 WNI_CFG_COUNTRY_CODE_LEN,
1534 0,
1535 {0} },
1536 {WNI_CFG_EDCA_ANI_ACBK_LOCAL,
1537 WNI_CFG_EDCA_ANI_ACBK_LOCAL_LEN,
1538 17,
1539 {0x0, 0x7, 0x0, 0xf, 0x3, 0xff, 0x0, 0x0, 0x1f, 0x3, 0xff, 0x0, 0x0,
1540 0xf, 0x3, 0xff, 0x0} },
1541 {WNI_CFG_EDCA_ANI_ACBE_LOCAL,
1542 WNI_CFG_EDCA_ANI_ACBE_LOCAL_LEN,
1543 17,
1544 {0x0, 0x2, 0x0, 0xf, 0x3, 0xff, 0x64, 0x0, 0x1f, 0x3, 0xff, 0x64, 0x0,
1545 0xf, 0x3, 0xff, 0x64} },
1546 {WNI_CFG_EDCA_ANI_ACVI_LOCAL,
1547 WNI_CFG_EDCA_ANI_ACVI_LOCAL_LEN,
1548 17,
1549 {0x0, 0x2, 0x0, 0x7, 0x0, 0xf, 0xc8, 0x0, 0xf, 0x0, 0x1f, 0xbc, 0x0,
1550 0x7, 0x0, 0xf, 0xc8} },
1551 {WNI_CFG_EDCA_ANI_ACVO_LOCAL,
1552 WNI_CFG_EDCA_ANI_ACVO_LOCAL_LEN,
1553 17,
1554 {0x0, 0x2, 0x0, 0x3, 0x0, 0x7, 0x64, 0x0, 0x7, 0x0, 0xf, 0x66, 0x0,
1555 0x3, 0x0, 0x7, 0x64} },
1556 {WNI_CFG_EDCA_ANI_ACBK,
1557 WNI_CFG_EDCA_ANI_ACBK_LEN,
1558 17,
1559 {0x0, 0x7, 0x0, 0xf, 0x3, 0xff, 0x0, 0x0, 0x1f, 0x3, 0xff, 0x0, 0x0,
1560 0xf, 0x3, 0xff, 0x0} },
1561 {WNI_CFG_EDCA_ANI_ACBE,
1562 WNI_CFG_EDCA_ANI_ACBE_LEN,
1563 17,
1564 {0x0, 0x2, 0x0, 0xf, 0x3, 0xff, 0x64, 0x0, 0x1f, 0x3, 0xff, 0x64, 0x0,
1565 0xf, 0x3, 0xff, 0x64} },
1566 {WNI_CFG_EDCA_ANI_ACVI,
1567 WNI_CFG_EDCA_ANI_ACVI_LEN,
1568 17, {0x0, 0x2, 0x0, 0x7, 0x0, 0xf, 0xc8, 0x0, 0xf, 0x0, 0x1f,
1569 0xbc, 0x0, 0x7, 0x0, 0xf, 0xc8} },
1570 {WNI_CFG_EDCA_ANI_ACVO,
1571 WNI_CFG_EDCA_ANI_ACVO_LEN,
1572 17,
1573 {0x0, 0x2, 0x0, 0x3, 0x0, 0x7, 0x64, 0x0, 0x7, 0x0, 0xf, 0x66, 0x0, 0x3,
1574 0x0, 0x7, 0x64} },
1575 {WNI_CFG_EDCA_WME_ACBK_LOCAL,
1576 WNI_CFG_EDCA_WME_ACBK_LOCAL_LEN,
1577 17, {0x0, 0x7, 0x0, 0xf, 0x3, 0xff, 0x0, 0x0, 0x1f, 0x3, 0xff,
1578 0x0, 0x0, 0xf, 0x3, 0xff, 0x0} },
1579 {WNI_CFG_EDCA_WME_ACBE_LOCAL,
1580 WNI_CFG_EDCA_WME_ACBE_LOCAL_LEN,
1581 17, {0x0, 0x3, 0x0, 0xf, 0x0, 0x3f, 0x0, 0x0, 0x1f, 0x3, 0xff,
1582 0x0, 0x0, 0xf, 0x0, 0x3f, 0x0} },
1583 {WNI_CFG_EDCA_WME_ACVI_LOCAL,
1584 WNI_CFG_EDCA_WME_ACVI_LOCAL_LEN,
1585 17,
1586 {0x0, 0x1, 0x0, 0x7, 0x0, 0xf, 0x5e, 0x0, 0x7, 0x0, 0xf, 0xbc, 0x0, 0x7,
1587 0x0, 0xf, 0x5e} },
1588 {WNI_CFG_EDCA_WME_ACVO_LOCAL,
1589 WNI_CFG_EDCA_WME_ACVO_LOCAL_LEN,
1590 17,
1591 {0x0, 0x1, 0x0, 0x3, 0x0, 0x7, 0x2f, 0x0, 0x3, 0x0, 0x7, 0x66, 0x0, 0x3,
1592 0x0, 0x7, 0x2f} },
1593 {WNI_CFG_EDCA_WME_ACBK,
1594 WNI_CFG_EDCA_WME_ACBK_LEN,
1595 17,
1596 {0x0, 0x7, 0x0, 0xf, 0x3, 0xff, 0x0, 0x0, 0xf, 0x3, 0xff, 0x0, 0x0, 0xf,
1597 0x3, 0xff, 0x0} },
1598 {WNI_CFG_EDCA_WME_ACBE,
1599 WNI_CFG_EDCA_WME_ACBE_LEN,
1600 17,
1601 {0x0, 0x3, 0x0, 0xf, 0x3, 0xff, 0x0, 0x0, 0xf, 0x3, 0xff, 0x0, 0x0, 0xf,
1602 0x3, 0xff, 0x0} },
1603 {WNI_CFG_EDCA_WME_ACVI,
1604 WNI_CFG_EDCA_WME_ACVI_LEN,
1605 17,
1606 {0x0, 0x2, 0x0, 0x7, 0x0, 0xf, 0x5e, 0x0, 0x7, 0x0, 0xf, 0xbc, 0x0, 0x7,
1607 0x0, 0xf, 0x5e} },
1608 {WNI_CFG_EDCA_WME_ACVO,
1609 WNI_CFG_EDCA_WME_ACVO_LEN,
1610 17,
1611 {0x0, 0x2, 0x0, 0x3, 0x0, 0x7, 0x2f, 0x0, 0x3, 0x0, 0x7, 0x66, 0x0, 0x3,
1612 0x0, 0x7, 0x2f} },
Prakash Dhavali7090c5f2015-11-02 17:55:19 -0800[diff] [blame]1613 {WNI_CFG_SCAN_CONTROL_LIST,
1614 WNI_CFG_SCAN_CONTROL_LIST_LEN,
1615 114,
1616 {0x1, 0x1, 0x2, 0x1, 0x3, 0x1, 0x4, 0x1, 0x5, 0x1, 0x6, 0x1, 0x7, 0x1,
1617 0x8, 0x1, 0x9, 0x1, 0xa, 0x1, 0xb, 0x1, 0xc, 0x1, 0xd, 0x1, 0xe, 0x1,
1618 0x22, 0x1, 0x24, 0x1, 0x26, 0x1, 0x28, 0x1, 0x2a, 0x1, 0x2c, 0x1, 0x2e,
1619 0x1, 0x30, 0x1, 0x32, 0x1, 0x34, 0x0, 0x36, 0x0, 0x38, 0x0, 0x3a, 0x0,
1620 0x3c, 0x0, 0x3e, 0x0, 0x40, 0x0, 0x64, 0x0, 0x68, 0x0, 0x6c, 0x0, 0x70,
1621 0x0, 0x74, 0x0, 0x78, 0x0, 0x7c, 0x0, 0x80, 0x0, 0x84, 0x0, 0x88, 0x0,
1622 0x8c, 0x0, 0x90, 0x0, 0x95, 0x1, 0x97, 0x1, 0x99, 0x1, 0x9b, 0x1, 0x9d,
1623 0x1, 0x9f, 0x1, 0xa1, 0x1, 0xa5, 0x1, 0xf0, 0x1, 0xf2, 0x1, 0xf4, 0x1,
1624 0xf6, 0x1, 0xf8, 0x1, 0xfa, 0x1, 0xfc, 0x1} },
1625 {WNI_CFG_SUPPORTED_MCS_SET,
1626 WNI_CFG_SUPPORTED_MCS_SET_LEN,
1627 16,
1628 {0xff, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
1629 0x0, 0x0} },
1630 {WNI_CFG_BASIC_MCS_SET,
1631 WNI_CFG_BASIC_MCS_SET_LEN,
1632 16,
1633 {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
1634 0x0, 0x0} },
1635 {WNI_CFG_CURRENT_MCS_SET,
1636 WNI_CFG_CURRENT_MCS_SET_LEN,
1637 16,
1638 {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
1639 0x0, 0x0} },
Prakash Dhavali7090c5f2015-11-02 17:55:19 -0800[diff] [blame]1640 {WNI_CFG_WPS_UUID,
1641 WNI_CFG_WPS_UUID_LEN,
1642 6,
Krishna Kumaar Natarajaned1efd92016-09-24 18:05:47 -0700[diff] [blame^]1643 {0xa, 0xb, 0xc, 0xd, 0xe, 0xf} },
1644 {WNI_CFG_HE_PPET,
1645 WNI_CFG_HE_PPET_LEN,
1646 WNI_CFG_HE_PPET_LEN,
1647 {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
1648 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0} }
Prakash Dhavali7090c5f2015-11-02 17:55:19 -0800[diff] [blame]1649};
1650
1651/*--------------------------------------------------------------------*/
1652/* Static function prototypes */
1653/*--------------------------------------------------------------------*/
1654static void proc_dnld_rsp(tpAniSirGlobal, uint16_t, uint32_t *);
1655static void proc_get_req(tpAniSirGlobal, uint16_t, uint32_t *);
1656static void proc_set_req(tpAniSirGlobal, uint16_t, uint32_t *);
1657static void proc_set_req_no_rsp(tpAniSirGlobal, uint16_t, uint32_t *);
1658
1659static uint8_t check_param(tpAniSirGlobal, uint16_t, uint32_t, uint32_t,
1660 uint32_t *);
1661static void get_str_value(uint8_t *, uint8_t *, uint32_t);
1662
1663/*--------------------------------------------------------------------*/
1664/* Module global variables */
1665/*--------------------------------------------------------------------*/
1666
1667/* CFG function table */
1668void (*g_cfg_func[])(tpAniSirGlobal, uint16_t, uint32_t *) = {
1669 proc_dnld_rsp, proc_get_req, proc_set_req, proc_set_req_no_rsp
1670};
1671
1672/**---------------------------------------------------------------------
1673 * cfg_process_mb_msg()
1674 *
1675 ***FUNCTION:
1676 * CFG mailbox message processing function.
1677 *
1678 ***LOGIC:
1679 *
1680 ***ASSUMPTIONS:
1681 * None.
1682 *
1683 ***NOTE:
1684 *
1685 * @param pMsg Message pointer
1686 *
1687 * @return None.
1688 *
1689 */
1690void cfg_process_mb_msg(tpAniSirGlobal pMac, tSirMbMsg *pMsg)
1691{
1692 uint16_t index;
1693 uint16_t len;
1694 uint32_t *pParam;
1695
1696 /* Use type[7:0] as index to function table */
1697 index = CFG_GET_FUNC_INDX(pMsg->type);
1698
Anurag Chouhan6d760662016-02-20 16:05:43 +0530[diff] [blame]1699 if (index >= QDF_ARRAY_SIZE(g_cfg_func)) {
Anurag Chouhan600c3a02016-03-01 10:33:54 +0530[diff] [blame]1700 qdf_mem_free(pMsg);
Prakash Dhavali7090c5f2015-11-02 17:55:19 -0800[diff] [blame]1701 return;
1702 }
1703 len = pMsg->msgLen - WNI_CFG_MB_HDR_LEN;
1704 pParam = ((uint32_t *) pMsg) + 1;
1705
1706 /* Call processing function */
1707 g_cfg_func[index] (pMac, len, pParam);
1708
1709 /* Free up buffer */
Anurag Chouhan600c3a02016-03-01 10:33:54 +0530[diff] [blame]1710 qdf_mem_free(pMsg);
Prakash Dhavali7090c5f2015-11-02 17:55:19 -0800[diff] [blame]1711
1712} /*** end cfg_process_mb_msg() ***/
1713
1714/**---------------------------------------------------------------------
1715 * proc_dnld_rsp()
1716 *
1717 * FUNCTION:
1718 * This function processes CFG_DNLD_RSP message from host.
1719 *
1720 * LOGIC:
1721 *
1722 * ASSUMPTIONS:
1723 *
1724 * NOTE:
1725 *
1726 * @param length: message length
1727 * @param pParam: parameter list pointer
1728 *
1729 * @return None
1730 *
1731 */
1732static void proc_dnld_rsp(tpAniSirGlobal pMac, uint16_t length, uint32_t *pParam)
1733{
1734 int32_t i;
1735
1736 uint32_t expLen, retVal, bufStart, bufEnd;
1737 uint32_t *pSrc, *pDst, *pDstEnd;
1738 uint32_t strSize, j;
1739 uint8_t pStr[CFG_MAX_STR_LEN];
1740 tpCfgBinHdr pHdr;
1741 uint32_t logLevel;
Rajeev Kumar416b73f2017-01-21 16:45:21 -0800[diff] [blame]1742 struct scheduler_msg mmhMsg;
Prakash Dhavali7090c5f2015-11-02 17:55:19 -0800[diff] [blame]1743
1744 /* First Dword must contain the AP or STA magic dword */
1745 PELOGW(cfg_log(pMac, LOGW, FL("CFG size %d bytes MAGIC dword is 0x%x"),
1746 length, sir_read_u32_n((uint8_t *) pParam));
1747 )
1748 /* if the string is not correct, return failure */
1749 if (*pParam == CFG_STA_MAGIC_DWORD) {
1750 }
1751
1752 else {
1753 PELOGE(cfg_log
1754 (pMac, LOGE, FL("Invalid magic dword 0x%x"),
1755 sir_read_u32_n((uint8_t *) pParam));
1756 )
1757 retVal = WNI_CFG_INVALID_LEN;
1758 goto end;
1759 }
1760
1761 pParam++;
1762 length -= 4;
1763
Prakash Dhavali7090c5f2015-11-02 17:55:19 -0800[diff] [blame]1764 /* Parse the Cfg header */
1765 pHdr = (tpCfgBinHdr) pParam;
1766 pParam += (sizeof(tCfgBinHdr) >> 2);
1767 PELOGW(cfg_log
1768 (pMac, LOGW,
1769 FL("CFG hdr totParams %d intParams %d strBufSize %d/%d"),
1770 pHdr->controlSize, pHdr->iBufSize, pHdr->sBufSize,
1771 pMac->cfg.gCfgMaxSBufSize);
1772 )
1773
1774 expLen =
1775 ((CFG_PARAM_MAX_NUM + 3 * pMac->cfg.gCfgMaxIBufSize) << 2) +
1776 pHdr->sBufSize + sizeof(tCfgBinHdr);
1777
1778 if (length != expLen) {
1779 PELOGE(cfg_log
1780 (pMac, LOGE,
1781 FL("<CFG> DNLD_RSP invalid length %d (exp %d)"), length,
1782 expLen);
1783 )
1784 retVal = WNI_CFG_INVALID_LEN;
1785 goto end;
1786 }
1787
1788 if (pHdr->controlSize != CFG_PARAM_MAX_NUM) {
1789 PELOGE(cfg_log
1790 (pMac, LOGE, FL("<CFG> Total parameter count mismatch"));
1791 )
1792 retVal = WNI_CFG_INVALID_LEN;
1793 goto end;
1794 }
1795
1796 if (pHdr->iBufSize != pMac->cfg.gCfgMaxIBufSize) {
1797 PELOGE(cfg_log
1798 (pMac, LOGE,
1799 FL("<CFG> Integer parameter count mismatch"));
1800 )
1801 retVal = WNI_CFG_INVALID_LEN;
1802 goto end;
1803 }
1804 /* Copy control array */
1805 pDst = (uint32_t *) pMac->cfg.gCfgEntry;
1806 pDstEnd = pDst + CFG_PARAM_MAX_NUM;
1807 pSrc = pParam;
1808 while (pDst < pDstEnd) {
1809 *pDst++ = *pSrc++;
1810 }
1811 /* Copy default values */
1812 pDst = pMac->cfg.gCfgIBuf;
1813 pDstEnd = pDst + pMac->cfg.gCfgMaxIBufSize;
1814 while (pDst < pDstEnd) {
1815 *pDst++ = *pSrc++;
1816 }
1817
1818 /* Copy min values */
1819 pDst = pMac->cfg.gCfgIBufMin;
1820 pDstEnd = pDst + pMac->cfg.gCfgMaxIBufSize;
1821 while (pDst < pDstEnd) {
1822 *pDst++ = *pSrc++;
1823 }
1824
1825 /* Copy max values */
1826 pDst = pMac->cfg.gCfgIBufMax;
1827 pDstEnd = pDst + pMac->cfg.gCfgMaxIBufSize;
1828 while (pDst < pDstEnd) {
1829 *pDst++ = *pSrc++;
1830 }
1831
1832 for (i = 0; i < pMac->cfg.gCfgMaxIBufSize; i++)
1833 if (pMac->cfg.gCfgIBuf[i] < pMac->cfg.gCfgIBufMin[i] ||
1834 pMac->cfg.gCfgIBuf[i] > pMac->cfg.gCfgIBufMax[i]) {
1835 PELOGE(cfg_log
1836 (pMac, LOGE,
1837 FL("cfg id %d Invalid def value %d "
1838 "min %d max %d"), i, pMac->cfg.gCfgIBuf[i],
1839 pMac->cfg.gCfgIBufMin[i],
1840 pMac->cfg.gCfgIBufMax[i]);
1841 )
1842 }
1843 /* Calculate max string buffer lengths for all string parameters */
1844 bufEnd = pMac->cfg.gCfgMaxSBufSize;
1845 for (i = CFG_PARAM_MAX_NUM - 1; i >= 0; i--) {
1846 if ((pMac->cfg.gCfgEntry[i].control & CFG_CTL_INT) != 0)
1847 continue;
1848
1849 if ((pMac->cfg.gCfgEntry[i].control & CFG_CTL_VALID) == 0)
1850 continue;
1851
1852 bufStart = pMac->cfg.gCfgEntry[i].control & CFG_BUF_INDX_MASK;
1853 pMac->cfg.gCfgSBuf[bufStart] =
1854 (uint8_t) (bufEnd - bufStart - 2);
1855
1856 PELOG1(cfg_log
1857 (pMac, LOG1, FL("id %d max %d bufStart %d bufEnd %d"), i,
1858 pMac->cfg.gCfgSBuf[bufStart], bufStart, bufEnd);
1859 )
1860
1861 bufEnd = bufStart;
1862 }
1863
1864 /* Initialize string defaults */
1865 strSize = pHdr->sBufSize;
1866 while (strSize) {
1867 uint32_t paramId, paramLen, paramLenCeil4;
1868
1869 if (strSize < 4) {
1870 PELOGE(cfg_log
1871 (pMac, LOGE,
1872 FL("Error parsing str defaults, rem %d bytes"),
1873 strSize);
1874 )
1875 retVal = WNI_CFG_INVALID_LEN;
1876 goto end;
1877 }
1878 paramId = *pSrc >> 16;
1879 paramLen = *pSrc & 0xff;
1880 pSrc++;
1881 strSize -= 4;
1882
1883 paramLenCeil4 = ((paramLen + 3) >> 2);
1884 if (strSize < paramLenCeil4 << 2) {
1885 PELOGE(cfg_log
1886 (pMac, LOGE,
1887 FL("Error parsing str defaults, rem %d bytes"),
1888 strSize);
1889 )
1890 PELOGE(cfg_log
1891 (pMac, LOGE, FL("param id %d len %d bytes"),
1892 paramId, paramLen);
1893 )
1894 retVal = WNI_CFG_INVALID_LEN;
1895 goto end;
1896 }
1897 for (j = 0; j < paramLenCeil4; j++) {
1898 pStr[4 * j] = (uint8_t) (*pSrc >> 24) & 0xff;
1899 pStr[4 * j + 1] = (uint8_t) (*pSrc >> 16) & 0xff;
1900 pStr[4 * j + 2] = (uint8_t) (*pSrc >> 8) & 0xff;
1901 pStr[4 * j + 3] = (uint8_t) (*pSrc) & 0xff;
1902
1903 pSrc++;
1904 strSize -= 4;
1905 }
1906
1907 PELOG1(cfg_log
1908 (pMac, LOG1, FL("set str id %d len %d"), paramId,
1909 paramLen);
1910 )
1911
1912 if (cfg_set_str(pMac, (uint16_t) paramId, pStr, paramLen) !=
1913 eSIR_SUCCESS) {
1914 PELOGE(cfg_log
1915 (pMac, LOGE,
1916 FL("Error setting str default param %d len %d"),
1917 paramId, paramLen);
1918 )
1919 retVal = WNI_CFG_INVALID_LEN;
1920 goto end;
1921 }
1922 }
1923
1924 /* Set the default log level based on config */
1925 wlan_cfg_get_int(pMac, WNI_CFG_LOG_LEVEL, &logLevel);
1926 for (i = 0; i < LOG_ENTRY_NUM; i++)
1927 pMac->utils.gLogEvtLevel[i] = pMac->utils.gLogDbgLevel[i] =
1928 logLevel;
1929
1930 /* Set status to READY */
1931 pMac->cfg.gCfgStatus = CFG_SUCCESS;
1932 retVal = WNI_CFG_SUCCESS;
1933 PELOG1(cfg_log(pMac, LOG1, "<CFG> Completed successfully");)
1934
1935end :
1936
1937 if (retVal != WNI_CFG_SUCCESS)
1938 pMac->cfg.gCfgStatus = CFG_FAILURE;
1939
1940 /* Send response message to host */
1941 pMac->cfg.gParamList[WNI_CFG_DNLD_CNF_RES] = retVal;
1942 cfg_send_host_msg(pMac, WNI_CFG_DNLD_CNF, WNI_CFG_DNLD_CNF_LEN,
1943 WNI_CFG_DNLD_CNF_NUM, pMac->cfg.gParamList, 0, 0);
1944
1945 /* notify WMA that the config has downloaded */
1946 mmhMsg.type = SIR_CFG_DOWNLOAD_COMPLETE_IND;
1947 mmhMsg.bodyptr = NULL;
1948 mmhMsg.bodyval = 0;
1949
1950 MTRACE(mac_trace_msg_tx(pMac, NO_SESSION, mmhMsg.type));
1951 if (wma_post_ctrl_msg(pMac, &mmhMsg) != eSIR_SUCCESS) {
1952 PELOGE(cfg_log(pMac, LOGE, FL("WMAPostMsgApi failed!"));)
1953 }
1954
1955} /*** end procDnldRsp() ***/
1956
1957/**---------------------------------------------------------------------
1958 * proc_get_req()
1959 *
1960 * FUNCTION:
1961 * This function processes CFG_GET_REQ message from host.
1962 *
1963 * LOGIC:
1964 *
1965 * ASSUMPTIONS:
1966 *
1967 * NOTE:
1968 * For every parameter ID specified on the list, CFG will send a separate
1969 * CFG_GET_RSP back to host.
1970 *
1971 * @param length: message length
1972 * @param pParam: parameter list pointer
1973 *
1974 * @return None
1975 *
1976 */
1977static void proc_get_req(tpAniSirGlobal pMac, uint16_t length, uint32_t *pParam)
1978{
1979 uint16_t cfgId, i;
1980 uint32_t value, valueLen, result;
1981 uint32_t *pValue;
1982
1983 PELOG1(cfg_log(pMac, LOG1, FL("Rcvd cfg get request %d bytes"), length);)
1984 for (i = 0; i < length / 4; i++)
1985 PELOG2(cfg_log(pMac, LOG2, FL("[%2d] 0x%08x"), i, pParam[i]);)
1986
1987 if (!pMac->cfg.gCfgStatus) {
1988 cfgId = (uint16_t) sir_read_u32_n((uint8_t *) pParam);
1989 PELOGE(cfg_log(pMac, LOGE, FL("CFG not ready, param %d"), cfgId);)
1990 pMac->cfg.gParamList[WNI_CFG_GET_RSP_RES] =
1991 WNI_CFG_NOT_READY;
1992 pMac->cfg.gParamList[WNI_CFG_GET_RSP_PID] = cfgId;
1993 pMac->cfg.gParamList[WNI_CFG_GET_RSP_PLEN] = 0;
1994 cfg_send_host_msg(pMac, WNI_CFG_GET_RSP,
1995 WNI_CFG_GET_RSP_PARTIAL_LEN, WNI_CFG_GET_RSP_NUM,
1996 pMac->cfg.gParamList, 0, 0);
1997 } else {
1998 /* Process all parameter ID's on the list */
1999 while (length >= sizeof(uint32_t)) {
2000 cfgId = (uint16_t) *pParam++;
2001 pValue = 0;
2002 valueLen = 0;
2003
2004 PELOG1(cfg_log
2005 (pMac, LOG1, FL("Cfg get param %d"), cfgId);
2006 )
2007 /* Check for valid parameter ID, etc... */
2008 if (check_param
2009 (pMac, cfgId, CFG_CTL_RE, WNI_CFG_WO_PARAM,
2010 &result)) {
2011 if ((pMac->cfg.gCfgEntry[cfgId].
2012 control & CFG_CTL_INT) != 0) {
2013 /* Get integer parameter */
2014 result =
2015 (wlan_cfg_get_int(pMac, cfgId, &value)
2016 ==
2017 eSIR_SUCCESS ? WNI_CFG_SUCCESS :
2018 WNI_CFG_OTHER_ERROR);
2019 pValue = &value;
2020 valueLen = sizeof(uint32_t);
2021 } else {
2022 /* Get string parameter */
2023 valueLen = sizeof(pMac->cfg.gSBuffer);
2024 result =
2025 (wlan_cfg_get_str
2026 (pMac, cfgId, pMac->cfg.gSBuffer,
2027 &valueLen)
2028 == eSIR_SUCCESS ? WNI_CFG_SUCCESS :
2029 WNI_CFG_OTHER_ERROR);
2030 pValue =
2031 (uint32_t *) pMac->cfg.gSBuffer;
2032 }
2033 } else {
2034 PELOGE(cfg_log
2035 (pMac, LOGE,
2036 FL("Check param failed, param %d"),
2037 cfgId);
2038 )
2039 result = WNI_CFG_INVALID_LEN;
2040 }
2041
2042 /* Send response message to host */
2043 pMac->cfg.gParamList[WNI_CFG_GET_RSP_RES] = result;
2044 pMac->cfg.gParamList[WNI_CFG_GET_RSP_PID] = cfgId;
2045 pMac->cfg.gParamList[WNI_CFG_GET_RSP_PLEN] = valueLen;
2046
2047 /* We need to round up buffer length to word-increment */
2048 valueLen = (((valueLen + 3) >> 2) << 2);
2049 cfg_send_host_msg(pMac, WNI_CFG_GET_RSP,
2050 WNI_CFG_GET_RSP_PARTIAL_LEN + valueLen,
2051 WNI_CFG_GET_RSP_NUM,
2052 pMac->cfg.gParamList, valueLen, pValue);
2053
2054 /* Decrement length */
2055 length -= sizeof(uint32_t);
2056 }
2057 }
2058
2059} /*** end procGetReq() ***/
2060
2061/**---------------------------------------------------------------------
2062 * proc_set_req_internal()
2063 *
2064 * FUNCTION:
2065 * This function processes CFG_SET_REQ message from host.
2066 *
2067 * LOGIC:
2068 *
2069 * ASSUMPTIONS:
2070 * - The message content is coded in TLV format.
2071 * - For string parameter, the length field is byte accurate. However,
2072 * the next TLV set will begin on the next word boundary.
2073 *
2074 * NOTE:
2075 * - For every parameter ID specified on the list, CFG will send a separate
2076 * CFG_SET_RSP back to host.
2077 *
2078 * @param length: message length
2079 * @param pParam: parameter list pointer
2080 * @param fRsp: whether to send response to host. true means sending.
2081 * @return None
2082 *
2083 */
2084static void
2085proc_set_req_internal(tpAniSirGlobal pMac, uint16_t length, uint32_t *pParam,
2086 bool fRsp)
2087{
2088 uint16_t cfgId, valueLen, valueLenRoundedUp4;
2089 uint32_t value, result;
2090
2091 PELOG1(cfg_log(pMac, LOGl, FL("Rcvd cfg set request %d bytes"), length);)
2092
2093 if (!pMac->cfg.gCfgStatus) {
2094 cfgId = (uint16_t) sir_read_u32_n((uint8_t *) pParam);
2095 PELOG1(cfg_log(pMac, LOGW, FL("CFG not ready, param %d"), cfgId);)
2096 pMac->cfg.gParamList[WNI_CFG_SET_CNF_RES] =
2097 WNI_CFG_NOT_READY;
2098 pMac->cfg.gParamList[WNI_CFG_SET_CNF_PID] = cfgId;
2099 if (fRsp) {
2100 cfg_send_host_msg(pMac, WNI_CFG_SET_CNF,
2101 WNI_CFG_SET_CNF_LEN, WNI_CFG_SET_CNF_NUM,
2102 pMac->cfg.gParamList, 0, 0);
2103 }
2104 } else {
2105 /* Process all TLVs in buffer */
2106 while (length >= (sizeof(uint32_t) * 2)) {
2107 cfgId = (uint16_t) *pParam++;
2108 valueLen = (uint16_t) *pParam++;
2109 length -= (sizeof(uint32_t) * 2);
2110 /* value length rounded up to a 4 byte multiple */
2111 valueLenRoundedUp4 = (((valueLen + 3) >> 2) << 2);
2112
2113 /* Check for valid request before proceeding */
2114 if (check_param
2115 (pMac, cfgId, CFG_CTL_WE, WNI_CFG_RO_PARAM,
2116 &result)) {
2117 PELOG1(cfg_log
2118 (pMac, LOGW,
2119 (char *)g_cfg_param_name[cfgId]);
2120 )
2121 /* Process integer parameter */
2122 if ((pMac->cfg.gCfgEntry[cfgId].
2123 control & CFG_CTL_INT) != 0) {
2124 /* Set VALUE */
2125 if (valueLen != sizeof(uint32_t)) {
2126 PELOGE(cfg_log
2127 (pMac, LOGE,
2128 FL
2129 ("Invalid value length %d in set param %d (tot %d)"),
2130 valueLen, cfgId,
2131 length);
2132 )
2133 result =
2134 WNI_CFG_INVALID_LEN;
2135 } else {
2136 value = *pParam;
2137 PELOG1(cfg_log
2138 (pMac, LOGW,
2139 FL
2140 ("Cfg set int %d len %d(%d) val %d"),
2141 cfgId, valueLen,
2142 valueLenRoundedUp4,
2143 value);
2144 )
2145 result =
2146 (cfg_set_int
2147 (pMac, cfgId,
2148 value) ==
2149 eSIR_SUCCESS ?
2150 WNI_CFG_SUCCESS :
2151 WNI_CFG_OTHER_ERROR);
2152 if (result == WNI_CFG_SUCCESS) {
2153 if (cfg_need_restart
2154 (pMac, cfgId)) {
2155 result =
2156 WNI_CFG_NEED_RESTART;
2157 } else
2158 if (cfg_need_reload
2159 (pMac, cfgId)) {
2160 result =
2161 WNI_CFG_NEED_RELOAD;
2162 }
2163 }
2164 }
2165 }
2166 /* Process string parameter */
2167 else {
2168 if (valueLenRoundedUp4 > length) {
2169 PELOGE(cfg_log
2170 (pMac, LOGE,
2171 FL
2172 ("Invalid string length %d"
2173 "in set param %d (tot %d)"),
2174 valueLen, cfgId,
2175 length);
2176 )
2177 result =
2178 WNI_CFG_INVALID_LEN;
2179 } else {
2180 get_str_value((uint8_t *) pParam,
2181 pMac->cfg.gSBuffer,
2182 valueLen);
2183 PELOG1(cfg_log
2184 (pMac, LOGW,
2185 FL
2186 ("Cfg set str %d len %d(%d) bytes"),
2187 cfgId, valueLen,
2188 valueLenRoundedUp4);
2189 )
2190 result =
2191 (cfg_set_str
2192 (pMac, cfgId,
2193 pMac->cfg.gSBuffer,
2194 valueLen) ==
2195 eSIR_SUCCESS ?
2196 WNI_CFG_SUCCESS :
2197 WNI_CFG_OTHER_ERROR);
2198 if (result == WNI_CFG_SUCCESS) {
2199 if (cfg_need_restart
2200 (pMac, cfgId)) {
2201 result =
2202 WNI_CFG_NEED_RESTART;
2203 } else
2204 if (cfg_need_reload
2205 (pMac, cfgId)) {
2206 result =
2207 WNI_CFG_NEED_RELOAD;
2208 }
2209 }
2210 }
2211 }
2212 } else {
2213 PELOGE(cfg_log
2214 (pMac, LOGE,
2215 FL("Check param failed, param %d"),
2216 cfgId);
2217 )
2218 result = WNI_CFG_INVALID_LEN;
2219 }
2220
2221 /* Send confirm message to host */
2222 pMac->cfg.gParamList[WNI_CFG_SET_CNF_RES] = result;
2223 pMac->cfg.gParamList[WNI_CFG_SET_CNF_PID] = cfgId;
2224 if (fRsp) {
2225 cfg_send_host_msg(pMac, WNI_CFG_SET_CNF,
2226 WNI_CFG_SET_CNF_LEN,
2227 WNI_CFG_SET_CNF_NUM,
2228 pMac->cfg.gParamList, 0, 0);
2229 } else {
2230 PELOGW(cfg_log
2231 (pMac, LOG2, " CFGID %d no rsp", cfgId);
2232 )
2233 }
2234
2235 if (valueLenRoundedUp4 > length)
2236 length = 0;
2237 else {
2238 length -= valueLenRoundedUp4;
2239 pParam += (valueLenRoundedUp4 >> 2);
2240 }
2241 }
2242 }
2243}
2244
2245static void proc_set_req(tpAniSirGlobal pMac, uint16_t length, uint32_t *pParam)
2246{
2247 proc_set_req_internal(pMac, length, pParam, true);
2248}
2249
2250static void
2251proc_set_req_no_rsp(tpAniSirGlobal pMac, uint16_t length, uint32_t *pParam)
2252{
2253 proc_set_req_internal(pMac, length, pParam, false);
2254}
2255
2256/**---------------------------------------------------------------------
2257 * check_param()
2258 *
2259 * FUNCTION:
2260 * This function is called to perform various check on a parameter.
2261 *
2262 * LOGIC:
2263 * - If cfgId is out of bound or parameter is not valid, result
2264 * WNI_CFG_INVALID_PID is returned at address specified in pResult.
2265 *
2266 * - If specified 'flag' is not set in the parameter control entry,
2267 * 'failedResult' is returned at address specified in pResult.
2268 *
2269 * ASSUMPTIONS:
2270 * Since this function is used internally, 'pResult' is always valid.
2271 *
2272 * NOTE:
2273 *
2274 * @param None
2275 *
2276 * @return true: Parameter is valid and matches checked condition \n
2277 * @return false: Parameter either is not valid or does not match
2278 * checked condition.
2279 *
2280 */
2281static uint8_t
2282check_param(tpAniSirGlobal pMac, uint16_t cfgId, uint32_t flag,
2283 uint32_t failedResult, uint32_t *pResult)
2284{
2285 /* Check if parameter ID is out of bound */
2286 if (cfgId >= CFG_PARAM_MAX_NUM) {
2287 PELOGE(cfg_log(pMac, LOGE, FL("Invalid param id %d"), cfgId);)
2288 * pResult = WNI_CFG_INVALID_PID;
2289 } else {
2290 /* Check if parameter is valid */
2291 if ((pMac->cfg.gCfgEntry[cfgId].control & CFG_CTL_VALID) == 0) {
2292 PELOGE(cfg_log
2293 (pMac, LOGE, FL("Param id %d not valid"), cfgId);
2294 )
2295 * pResult = WNI_CFG_INVALID_PID;
2296 } else {
2297 /* Check control field against flag */
2298 if ((pMac->cfg.gCfgEntry[cfgId].control & flag) == 0) {
2299 PELOGE(cfg_log
2300 (pMac, LOGE,
2301 FL("Param id %d wrong permissions %x"),
2302 cfgId,
2303 pMac->cfg.gCfgEntry[cfgId].control);
2304 )
2305 * pResult = failedResult;
2306 } else
2307 return true;
2308 }
2309 }
2310 return false;
2311
2312} /*** cfgParamCheck() ***/
2313
2314/**---------------------------------------------------------------------
2315 * get_str_value()
2316 *
2317 * FUNCTION:
2318 * This function copies a string value from the specified buffer.
2319 *
2320 * LOGIC:
2321 *
2322 * ASSUMPTIONS:
2323 *
2324 * NOTE:
2325 *
2326 * @param pBuf: input data buffer
2327 * @param pValue: address where data is returned
2328 * @param length: number of bytes to copy
2329 *
2330 * @return None
2331 *
2332 */
2333static void get_str_value(uint8_t *pBuf, uint8_t *pValue, uint32_t length)
2334{
2335 uint8_t *pEnd;
2336
2337 pEnd = pValue + length;
2338 while (pValue < pEnd)
2339 *pValue++ = *pBuf++;
2340} /*** end get_str_value() ***/
2341
2342/**---------------------------------------------------------------------
2343 * process_cfg_download_req()
2344 *
2345 * FUNCTION: This function does the Cfg Download and is invoked
2346 * only in the case of Prima or the Integrated SOC
2347 * solutions. Not applicable to Volans or Libra
2348 *
2349 * LOGIC:
2350 *
2351 * ASSUMPTIONS:
2352 *
2353 * NOTE:
2354 *
2355 * @param pMac: Pointer to Mac Structure
2356 *
2357 * @return None
2358 *
2359 */
2360
2361void
2362process_cfg_download_req(tpAniSirGlobal pMac)
2363{
2364 int32_t i;
2365 uint32_t index;
2366 uint8_t *pDstTest, *pSrcTest;
2367 uint8_t len;
Anurag Chouhan6d760662016-02-20 16:05:43 +0530[diff] [blame]2368 cfgstatic_string * pStrCfg;
Prakash Dhavali7090c5f2015-11-02 17:55:19 -0800[diff] [blame]2369 uint32_t bufStart, bufEnd;
2370 uint32_t logLevel, retVal;
2371 uint32_t iCount = 0;
2372 uint32_t sCount = 0;
2373
2374 for (i = 0; i < CFG_PARAM_MAX_NUM ; i++) {
2375 if ((cfg_static[i].control & CFG_CTL_VALID) != 0) {
2376 if (!(cfg_static[i].control & CFG_CTL_INT)) {
Anurag Chouhan6d760662016-02-20 16:05:43 +0530[diff] [blame]2377 pStrCfg = (cfgstatic_string*)cfg_static[i].
Prakash Dhavali7090c5f2015-11-02 17:55:19 -0800[diff] [blame]2378 pStrData;
2379 if (pStrCfg == NULL) {
2380 PELOGE(cfg_log(pMac, LOGE,
2381 FL("pStrCfg is NULL for CfigID : %d"),
2382 i);)
2383 continue;
2384 }
2385 index = sCount & CFG_BUF_INDX_MASK;
2386 sCount += pStrCfg->maxLen + 1 + 1;
2387 } else {
2388 index = iCount & CFG_BUF_INDX_MASK;
2389 iCount++;
2390 }
2391 } else {
2392 index = 0;
2393 }
2394 pMac->cfg.gCfgEntry[i].control = cfg_static[i].control | index;
2395 }
2396
2397 /*Fill the SBUF wih maxLength*/
2398 bufEnd = pMac->cfg.gCfgMaxSBufSize;
2399 for (i = CFG_PARAM_MAX_NUM - 1; i >= 0; i--) {
2400 if ((pMac->cfg.gCfgEntry[i].control & CFG_CTL_INT) != 0)
2401 continue;
2402
2403 if ((pMac->cfg.gCfgEntry[i].control & CFG_CTL_VALID) == 0)
2404 continue;
2405
2406 bufStart = pMac->cfg.gCfgEntry[i].control & CFG_BUF_INDX_MASK;
2407 pMac->cfg.gCfgSBuf[bufStart] = (uint8_t)(bufEnd - bufStart - 2);
2408
2409 PELOG1(cfgLog(pMac, LOG1, FL("id %d max %d bufStart %d bufEnd %d"),
2410 i, pMac->cfg.gCfgSBuf[bufStart],
2411 bufStart, bufEnd);)
2412 bufEnd = bufStart;
2413 }
2414
2415 for (i = 0; i < CFG_PARAM_MAX_NUM ; i++) {
2416 index = pMac->cfg.gCfgEntry[i].control & CFG_BUF_INDX_MASK;
2417
2418 if ((pMac->cfg.gCfgEntry[i].control & CFG_CTL_INT) != 0) {
2419 pMac->cfg.gCfgIBufMin[index] = cfg_static[i].cfgIMin;
2420 pMac->cfg.gCfgIBufMax[index] = cfg_static[i].cfgIMax;
2421 pMac->cfg.gCfgIBuf[index] = cfg_static[i].cfgIVal;
2422 } else {
2423 uint8_t maxSavedLen;
2424 if ((pMac->cfg.gCfgEntry[i].control & CFG_CTL_VALID) == 0)
2425 continue;
Naveen Rawat318fce92015-09-25 09:40:47 -0700[diff] [blame]2426 if (index >= pMac->cfg.gCfgMaxSBufSize)
Prakash Dhavali7090c5f2015-11-02 17:55:19 -0800[diff] [blame]2427 continue;
2428
2429 pDstTest = &pMac->cfg.gCfgSBuf[index];
Anurag Chouhan6d760662016-02-20 16:05:43 +0530[diff] [blame]2430 pStrCfg = (cfgstatic_string*)cfg_static[i].pStrData;
Prakash Dhavali7090c5f2015-11-02 17:55:19 -0800[diff] [blame]2431 pSrcTest = pStrCfg->data;
2432 if ((pDstTest == NULL) || (pStrCfg == NULL) ||
2433 (pSrcTest == NULL))
2434 continue;
2435 maxSavedLen = *pDstTest;
2436 len = pStrCfg->length;
2437 if (len > maxSavedLen)
2438 continue;
2439 *pDstTest++ = pStrCfg->maxLen;
2440 *pDstTest++ = len;
2441 while (len) {
2442 *pDstTest++ = *pSrcTest++;
2443 len--;
2444 }
2445 }
2446 }
2447
2448 /* Set the default log level based on config */
2449 wlan_cfg_get_int(pMac, WNI_CFG_LOG_LEVEL, &logLevel);
2450 for (i = 0; i < LOG_ENTRY_NUM; i++)
2451 pMac->utils.gLogEvtLevel[i] = pMac->utils.gLogDbgLevel[i] =
2452 logLevel;
2453
2454 /* Set status to READY */
2455 pMac->cfg.gCfgStatus = CFG_SUCCESS;
2456 retVal = WNI_CFG_SUCCESS;
2457 PELOG1(cfg_log(pMac, LOG1, "<CFG> Completed successfully");)
2458
2459 pMac->cfg.gParamList[WNI_CFG_DNLD_CNF_RES] = retVal;
2460
2461} /*** end ProcessDownloadReq() ***/