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gerrit-public.fairphone.software / toolchain / llvm-project / 00b7f95b122372d57b7d3f00ae435512024bb45e / . / llvm / test / CodeGen / Mips / fcmp.ll
blob: 8e83b0064ed9e3d374155e89af4958e6893244f5 [file] [log] [blame]
Daniel Sanders0fa60412014-06-12 13:39:06 +0000[diff] [blame]1; RUN: llc < %s -march=mipsel -mcpu=mips32 | FileCheck %s -check-prefix=ALL -check-prefix=32-C
2; RUN: llc < %s -march=mipsel -mcpu=mips32r2 | FileCheck %s -check-prefix=ALL -check-prefix=32-C
3; RUN: llc < %s -march=mipsel -mcpu=mips32r6 | FileCheck %s -check-prefix=ALL -check-prefix=32-CMP
4; RUN: llc < %s -march=mips64el -mcpu=mips4 | FileCheck %s -check-prefix=ALL -check-prefix=64-C
5; RUN: llc < %s -march=mips64el -mcpu=mips64 | FileCheck %s -check-prefix=ALL -check-prefix=64-C
6; RUN: llc < %s -march=mips64el -mcpu=mips64r2 | FileCheck %s -check-prefix=ALL -check-prefix=64-C
7; RUN: llc < %s -march=mips64el -mcpu=mips64r6 | FileCheck %s -check-prefix=ALL -check-prefix=64-CMP
8
9define i32 @false_f32(float %a, float %b) nounwind {
10; ALL-LABEL: false_f32:
11; ALL: addiu $2, $zero, 0
12
13 %1 = fcmp false float %a, %b
14 %2 = zext i1 %1 to i32
15 ret i32 %2
16}
17
18define i32 @oeq_f32(float %a, float %b) nounwind {
19; ALL-LABEL: oeq_f32:
20
21; 32-C-DAG: addiu $[[T0:2]], $zero, 0
22; 32-C-DAG: addiu $[[T1:[0-9]+]], $zero, 1
23; 32-C-DAG: c.eq.s $f12, $f14
24; 32-C-DAG: movt $[[T0]], $1, $fcc0
25
26; 64-C-DAG: addiu $[[T0:2]], $zero, 0
27; 64-C-DAG: addiu $[[T1:[0-9]+]], $zero, 1
28; 64-C-DAG: c.eq.s $f12, $f13
29; 64-C-DAG: movt $[[T0]], $1, $fcc0
30
31; 32-CMP-DAG: cmp.eq.s $[[T0:f[0-9]+]], $f12, $f14
Daniel Sanderscbd44c52014-07-10 10:18:12 +0000[diff] [blame]32; 32-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
33; 32-CMP-DAG: andi $2, $[[T1]], 1
Daniel Sanders0fa60412014-06-12 13:39:06 +0000[diff] [blame]34
35; 64-CMP-DAG: cmp.eq.s $[[T0:f[0-9]+]], $f12, $f13
Daniel Sanderscbd44c52014-07-10 10:18:12 +0000[diff] [blame]36; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
37; 64-CMP-DAG: andi $2, $[[T1]], 1
Daniel Sanders0fa60412014-06-12 13:39:06 +0000[diff] [blame]38
39 %1 = fcmp oeq float %a, %b
40 %2 = zext i1 %1 to i32
41 ret i32 %2
42}
43
44define i32 @ogt_f32(float %a, float %b) nounwind {
45; ALL-LABEL: ogt_f32:
46
47; 32-C-DAG: addiu $[[T0:2]], $zero, 0
48; 32-C-DAG: addiu $[[T1:[0-9]+]], $zero, 1
49; 32-C-DAG: c.ule.s $f12, $f14
50; 32-C-DAG: movf $[[T0]], $1, $fcc0
51
52; 64-C-DAG: addiu $[[T0:2]], $zero, 0
53; 64-C-DAG: addiu $[[T1:[0-9]+]], $zero, 1
54; 64-C-DAG: c.ule.s $f12, $f13
55; 64-C-DAG: movf $[[T0]], $1, $fcc0
56
Daniel Sandersdc067182014-07-09 10:40:20 +0000[diff] [blame]57; 32-CMP-DAG: cmp.lt.s $[[T0:f[0-9]+]], $f14, $f12
Daniel Sanderscbd44c52014-07-10 10:18:12 +0000[diff] [blame]58; 32-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
59; 32-CMP-DAG: andi $2, $[[T1]], 1
Daniel Sanders0fa60412014-06-12 13:39:06 +0000[diff] [blame]60
Daniel Sandersdc067182014-07-09 10:40:20 +0000[diff] [blame]61; 64-CMP-DAG: cmp.lt.s $[[T0:f[0-9]+]], $f13, $f12
Daniel Sanderscbd44c52014-07-10 10:18:12 +0000[diff] [blame]62; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
63; 64-CMP-DAG: andi $2, $[[T1]], 1
Daniel Sanders0fa60412014-06-12 13:39:06 +0000[diff] [blame]64
65 %1 = fcmp ogt float %a, %b
66 %2 = zext i1 %1 to i32
67 ret i32 %2
68}
69
70define i32 @oge_f32(float %a, float %b) nounwind {
71; ALL-LABEL: oge_f32:
72
73; 32-C-DAG: addiu $[[T0:2]], $zero, 0
74; 32-C-DAG: addiu $[[T1:[0-9]+]], $zero, 1
75; 32-C-DAG: c.ult.s $f12, $f14
76; 32-C-DAG: movf $[[T0]], $1, $fcc0
77
78; 64-C-DAG: addiu $[[T0:2]], $zero, 0
79; 64-C-DAG: addiu $[[T1:[0-9]+]], $zero, 1
80; 64-C-DAG: c.ult.s $f12, $f13
81; 64-C-DAG: movf $[[T0]], $1, $fcc0
82
Daniel Sandersdc067182014-07-09 10:40:20 +0000[diff] [blame]83; 32-CMP-DAG: cmp.le.s $[[T0:f[0-9]+]], $f14, $f12
Daniel Sanderscbd44c52014-07-10 10:18:12 +0000[diff] [blame]84; 32-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
85; 32-CMP-DAG: andi $2, $[[T1]], 1
Daniel Sanders0fa60412014-06-12 13:39:06 +0000[diff] [blame]86
Daniel Sandersdc067182014-07-09 10:40:20 +0000[diff] [blame]87; 64-CMP-DAG: cmp.le.s $[[T0:f[0-9]+]], $f13, $f12
Daniel Sanderscbd44c52014-07-10 10:18:12 +0000[diff] [blame]88; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
89; 64-CMP-DAG: andi $2, $[[T1]], 1
Daniel Sanders0fa60412014-06-12 13:39:06 +0000[diff] [blame]90
91 %1 = fcmp oge float %a, %b
92 %2 = zext i1 %1 to i32
93 ret i32 %2
94}
95
96define i32 @olt_f32(float %a, float %b) nounwind {
97; ALL-LABEL: olt_f32:
98
99; 32-C-DAG: addiu $[[T0:2]], $zero, 0
100; 32-C-DAG: addiu $[[T1:[0-9]+]], $zero, 1
101; 32-C-DAG: c.olt.s $f12, $f14
102; 32-C-DAG: movt $[[T0]], $1, $fcc0
103
104; 64-C-DAG: addiu $[[T0:2]], $zero, 0
105; 64-C-DAG: addiu $[[T1:[0-9]+]], $zero, 1
106; 64-C-DAG: c.olt.s $f12, $f13
107; 64-C-DAG: movt $[[T0]], $1, $fcc0
108
Daniel Sandersdc067182014-07-09 10:40:20 +0000[diff] [blame]109; 32-CMP-DAG: cmp.lt.s $[[T0:f[0-9]+]], $f12, $f14
Daniel Sanderscbd44c52014-07-10 10:18:12 +0000[diff] [blame]110; 32-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
111; 32-CMP-DAG: andi $2, $[[T1]], 1
Daniel Sanders0fa60412014-06-12 13:39:06 +0000[diff] [blame]112
Daniel Sandersdc067182014-07-09 10:40:20 +0000[diff] [blame]113; 64-CMP-DAG: cmp.lt.s $[[T0:f[0-9]+]], $f12, $f13
Daniel Sanderscbd44c52014-07-10 10:18:12 +0000[diff] [blame]114; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
115; 64-CMP-DAG: andi $2, $[[T1]], 1
Daniel Sanders0fa60412014-06-12 13:39:06 +0000[diff] [blame]116
117 %1 = fcmp olt float %a, %b
118 %2 = zext i1 %1 to i32
119 ret i32 %2
120}
121
122define i32 @ole_f32(float %a, float %b) nounwind {
123; ALL-LABEL: ole_f32:
124
125; 32-C-DAG: addiu $[[T0:2]], $zero, 0
126; 32-C-DAG: addiu $[[T1:[0-9]+]], $zero, 1
127; 32-C-DAG: c.ole.s $f12, $f14
128; 32-C-DAG: movt $[[T0]], $1, $fcc0
129
130; 64-C-DAG: addiu $[[T0:2]], $zero, 0
131; 64-C-DAG: addiu $[[T1:[0-9]+]], $zero, 1
132; 64-C-DAG: c.ole.s $f12, $f13
133; 64-C-DAG: movt $[[T0]], $1, $fcc0
134
Daniel Sandersdc067182014-07-09 10:40:20 +0000[diff] [blame]135; 32-CMP-DAG: cmp.le.s $[[T0:f[0-9]+]], $f12, $f14
Daniel Sanderscbd44c52014-07-10 10:18:12 +0000[diff] [blame]136; 32-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
137; 32-CMP-DAG: andi $2, $[[T1]], 1
Daniel Sanders0fa60412014-06-12 13:39:06 +0000[diff] [blame]138
Daniel Sandersdc067182014-07-09 10:40:20 +0000[diff] [blame]139; 64-CMP-DAG: cmp.le.s $[[T0:f[0-9]+]], $f12, $f13
Daniel Sanderscbd44c52014-07-10 10:18:12 +0000[diff] [blame]140; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
141; 64-CMP-DAG: andi $2, $[[T1]], 1
Daniel Sanders0fa60412014-06-12 13:39:06 +0000[diff] [blame]142
143 %1 = fcmp ole float %a, %b
144 %2 = zext i1 %1 to i32
145 ret i32 %2
146}
147
148define i32 @one_f32(float %a, float %b) nounwind {
149; ALL-LABEL: one_f32:
150
151; 32-C-DAG: addiu $[[T0:2]], $zero, 0
152; 32-C-DAG: addiu $[[T1:[0-9]+]], $zero, 1
153; 32-C-DAG: c.ueq.s $f12, $f14
154; 32-C-DAG: movf $[[T0]], $1, $fcc0
155
156; 64-C-DAG: addiu $[[T0:2]], $zero, 0
157; 64-C-DAG: addiu $[[T1:[0-9]+]], $zero, 1
158; 64-C-DAG: c.ueq.s $f12, $f13
159; 64-C-DAG: movf $[[T0]], $1, $fcc0
160
161; 32-CMP-DAG: cmp.ueq.s $[[T0:f[0-9]+]], $f12, $f14
162; 32-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
Daniel Sanderscbd44c52014-07-10 10:18:12 +0000[diff] [blame]163; 32-CMP-DAG: not $[[T2:[0-9]+]], $[[T1]]
164; 32-CMP-DAG: andi $2, $[[T2]], 1
Daniel Sanders0fa60412014-06-12 13:39:06 +0000[diff] [blame]165
166; 64-CMP-DAG: cmp.ueq.s $[[T0:f[0-9]+]], $f12, $f13
167; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
Daniel Sanderscbd44c52014-07-10 10:18:12 +0000[diff] [blame]168; 64-CMP-DAG: not $[[T2:[0-9]+]], $[[T1]]
169; 64-CMP-DAG: andi $2, $[[T2]], 1
Daniel Sanders0fa60412014-06-12 13:39:06 +0000[diff] [blame]170
171 %1 = fcmp one float %a, %b
172 %2 = zext i1 %1 to i32
173 ret i32 %2
174}
175
176define i32 @ord_f32(float %a, float %b) nounwind {
177; ALL-LABEL: ord_f32:
178
179; 32-C-DAG: addiu $[[T0:2]], $zero, 0
180; 32-C-DAG: addiu $[[T1:[0-9]+]], $zero, 1
181; 32-C-DAG: c.un.s $f12, $f14
182; 32-C-DAG: movf $[[T0]], $1, $fcc0
183
184; 64-C-DAG: addiu $[[T0:2]], $zero, 0
185; 64-C-DAG: addiu $[[T1:[0-9]+]], $zero, 1
186; 64-C-DAG: c.un.s $f12, $f13
187; 64-C-DAG: movf $[[T0]], $1, $fcc0
188
189; 32-CMP-DAG: cmp.un.s $[[T0:f[0-9]+]], $f12, $f14
190; 32-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
Daniel Sanderscbd44c52014-07-10 10:18:12 +0000[diff] [blame]191; 32-CMP-DAG: not $[[T2:[0-9]+]], $[[T1]]
192; 32-CMP-DAG: andi $2, $[[T2]], 1
Daniel Sanders0fa60412014-06-12 13:39:06 +0000[diff] [blame]193
194; 64-CMP-DAG: cmp.un.s $[[T0:f[0-9]+]], $f12, $f13
195; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
Daniel Sanderscbd44c52014-07-10 10:18:12 +0000[diff] [blame]196; 64-CMP-DAG: not $[[T2:[0-9]+]], $[[T1]]
197; 64-CMP-DAG: andi $2, $[[T2]], 1
Daniel Sanders0fa60412014-06-12 13:39:06 +0000[diff] [blame]198
199 %1 = fcmp ord float %a, %b
200 %2 = zext i1 %1 to i32
201 ret i32 %2
202}
203
204define i32 @ueq_f32(float %a, float %b) nounwind {
205; ALL-LABEL: ueq_f32:
206
207; 32-C-DAG: addiu $[[T0:2]], $zero, 0
208; 32-C-DAG: addiu $[[T1:[0-9]+]], $zero, 1
209; 32-C-DAG: c.ueq.s $f12, $f14
210; 32-C-DAG: movt $[[T0]], $1, $fcc0
211
212; 64-C-DAG: addiu $[[T0:2]], $zero, 0
213; 64-C-DAG: addiu $[[T1:[0-9]+]], $zero, 1
214; 64-C-DAG: c.ueq.s $f12, $f13
215; 64-C-DAG: movt $[[T0]], $1, $fcc0
216
217; 32-CMP-DAG: cmp.ueq.s $[[T0:f[0-9]+]], $f12, $f14
Daniel Sanderscbd44c52014-07-10 10:18:12 +0000[diff] [blame]218; 32-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
219; 32-CMP-DAG: andi $2, $[[T1]], 1
Daniel Sanders0fa60412014-06-12 13:39:06 +0000[diff] [blame]220
221; 64-CMP-DAG: cmp.ueq.s $[[T0:f[0-9]+]], $f12, $f13
Daniel Sanderscbd44c52014-07-10 10:18:12 +0000[diff] [blame]222; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
223; 64-CMP-DAG: andi $2, $[[T1]], 1
Daniel Sanders0fa60412014-06-12 13:39:06 +0000[diff] [blame]224
225 %1 = fcmp ueq float %a, %b
226 %2 = zext i1 %1 to i32
227 ret i32 %2
228}
229
230define i32 @ugt_f32(float %a, float %b) nounwind {
231; ALL-LABEL: ugt_f32:
232
233; 32-C-DAG: addiu $[[T0:2]], $zero, 0
234; 32-C-DAG: addiu $[[T1:[0-9]+]], $zero, 1
235; 32-C-DAG: c.ole.s $f12, $f14
236; 32-C-DAG: movf $[[T0]], $1, $fcc0
237
238; 64-C-DAG: addiu $[[T0:2]], $zero, 0
239; 64-C-DAG: addiu $[[T1:[0-9]+]], $zero, 1
240; 64-C-DAG: c.ole.s $f12, $f13
241; 64-C-DAG: movf $[[T0]], $1, $fcc0
242
243; 32-CMP-DAG: cmp.ult.s $[[T0:f[0-9]+]], $f14, $f12
Daniel Sanderscbd44c52014-07-10 10:18:12 +0000[diff] [blame]244; 32-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
245; 32-CMP-DAG: andi $2, $[[T1]], 1
Daniel Sanders0fa60412014-06-12 13:39:06 +0000[diff] [blame]246
247; 64-CMP-DAG: cmp.ult.s $[[T0:f[0-9]+]], $f13, $f12
Daniel Sanderscbd44c52014-07-10 10:18:12 +0000[diff] [blame]248; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
249; 64-CMP-DAG: andi $2, $[[T1]], 1
Daniel Sanders0fa60412014-06-12 13:39:06 +0000[diff] [blame]250
251 %1 = fcmp ugt float %a, %b
252 %2 = zext i1 %1 to i32
253 ret i32 %2
254}
255
256define i32 @uge_f32(float %a, float %b) nounwind {
257; ALL-LABEL: uge_f32:
258
259; 32-C-DAG: addiu $[[T0:2]], $zero, 0
260; 32-C-DAG: addiu $[[T1:[0-9]+]], $zero, 1
261; 32-C-DAG: c.olt.s $f12, $f14
262; 32-C-DAG: movf $[[T0]], $1, $fcc0
263
264; 64-C-DAG: addiu $[[T0:2]], $zero, 0
265; 64-C-DAG: addiu $[[T1:[0-9]+]], $zero, 1
266; 64-C-DAG: c.olt.s $f12, $f13
267; 64-C-DAG: movf $[[T0]], $1, $fcc0
268
269; 32-CMP-DAG: cmp.ule.s $[[T0:f[0-9]+]], $f14, $f12
Daniel Sanderscbd44c52014-07-10 10:18:12 +0000[diff] [blame]270; 32-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
271; 32-CMP-DAG: andi $2, $[[T1]], 1
Daniel Sanders0fa60412014-06-12 13:39:06 +0000[diff] [blame]272
273; 64-CMP-DAG: cmp.ule.s $[[T0:f[0-9]+]], $f13, $f12
Daniel Sanderscbd44c52014-07-10 10:18:12 +0000[diff] [blame]274; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
275; 64-CMP-DAG: andi $2, $[[T1]], 1
Daniel Sanders0fa60412014-06-12 13:39:06 +0000[diff] [blame]276
277 %1 = fcmp uge float %a, %b
278 %2 = zext i1 %1 to i32
279 ret i32 %2
280}
281
282define i32 @ult_f32(float %a, float %b) nounwind {
283; ALL-LABEL: ult_f32:
284
285; 32-C-DAG: addiu $[[T0:2]], $zero, 0
286; 32-C-DAG: addiu $[[T1:[0-9]+]], $zero, 1
287; 32-C-DAG: c.ult.s $f12, $f14
288; 32-C-DAG: movt $[[T0]], $1, $fcc0
289
290; 64-C-DAG: addiu $[[T0:2]], $zero, 0
291; 64-C-DAG: addiu $[[T1:[0-9]+]], $zero, 1
292; 64-C-DAG: c.ult.s $f12, $f13
293; 64-C-DAG: movt $[[T0]], $1, $fcc0
294
295; 32-CMP-DAG: cmp.ult.s $[[T0:f[0-9]+]], $f12, $f14
Daniel Sanderscbd44c52014-07-10 10:18:12 +0000[diff] [blame]296; 32-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
297; 32-CMP-DAG: andi $2, $[[T1]], 1
Daniel Sanders0fa60412014-06-12 13:39:06 +0000[diff] [blame]298
299; 64-CMP-DAG: cmp.ult.s $[[T0:f[0-9]+]], $f12, $f13
Daniel Sanderscbd44c52014-07-10 10:18:12 +0000[diff] [blame]300; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
301; 64-CMP-DAG: andi $2, $[[T1]], 1
Daniel Sanders0fa60412014-06-12 13:39:06 +0000[diff] [blame]302
303 %1 = fcmp ult float %a, %b
304 %2 = zext i1 %1 to i32
305 ret i32 %2
306}
307
308define i32 @ule_f32(float %a, float %b) nounwind {
309; ALL-LABEL: ule_f32:
310
311; 32-C-DAG: addiu $[[T0:2]], $zero, 0
312; 32-C-DAG: addiu $[[T1:[0-9]+]], $zero, 1
313; 32-C-DAG: c.ule.s $f12, $f14
314; 32-C-DAG: movt $[[T0]], $1, $fcc0
315
316; 64-C-DAG: addiu $[[T0:2]], $zero, 0
317; 64-C-DAG: addiu $[[T1:[0-9]+]], $zero, 1
318; 64-C-DAG: c.ule.s $f12, $f13
319; 64-C-DAG: movt $[[T0]], $1, $fcc0
320
321; 32-CMP-DAG: cmp.ule.s $[[T0:f[0-9]+]], $f12, $f14
Daniel Sanderscbd44c52014-07-10 10:18:12 +0000[diff] [blame]322; 32-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
323; 32-CMP-DAG: andi $2, $[[T1]], 1
Daniel Sanders0fa60412014-06-12 13:39:06 +0000[diff] [blame]324
325; 64-CMP-DAG: cmp.ule.s $[[T0:f[0-9]+]], $f12, $f13
Daniel Sanderscbd44c52014-07-10 10:18:12 +0000[diff] [blame]326; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
327; 64-CMP-DAG: andi $2, $[[T1]], 1
Daniel Sanders0fa60412014-06-12 13:39:06 +0000[diff] [blame]328
329 %1 = fcmp ule float %a, %b
330 %2 = zext i1 %1 to i32
331 ret i32 %2
332}
333
334define i32 @une_f32(float %a, float %b) nounwind {
335; ALL-LABEL: une_f32:
336
337; 32-C-DAG: addiu $[[T0:2]], $zero, 0
338; 32-C-DAG: addiu $[[T1:[0-9]+]], $zero, 1
339; 32-C-DAG: c.eq.s $f12, $f14
340; 32-C-DAG: movf $[[T0]], $1, $fcc0
341
342; 64-C-DAG: addiu $[[T0:2]], $zero, 0
343; 64-C-DAG: addiu $[[T1:[0-9]+]], $zero, 1
344; 64-C-DAG: c.eq.s $f12, $f13
345; 64-C-DAG: movf $[[T0]], $1, $fcc0
346
347; 32-CMP-DAG: cmp.eq.s $[[T0:f[0-9]+]], $f12, $f14
348; 32-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
Daniel Sanderscbd44c52014-07-10 10:18:12 +0000[diff] [blame]349; 32-CMP-DAG: not $[[T2:[0-9]+]], $[[T1]]
350; 32-CMP-DAG: andi $2, $[[T2]], 1
Daniel Sanders0fa60412014-06-12 13:39:06 +0000[diff] [blame]351
352; 64-CMP-DAG: cmp.eq.s $[[T0:f[0-9]+]], $f12, $f13
353; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
Daniel Sanderscbd44c52014-07-10 10:18:12 +0000[diff] [blame]354; 64-CMP-DAG: not $[[T2:[0-9]+]], $[[T1]]
355; 64-CMP-DAG: andi $2, $[[T2]], 1
Daniel Sanders0fa60412014-06-12 13:39:06 +0000[diff] [blame]356
357 %1 = fcmp une float %a, %b
358 %2 = zext i1 %1 to i32
359 ret i32 %2
360}
361
362define i32 @uno_f32(float %a, float %b) nounwind {
363; ALL-LABEL: uno_f32:
364
365; 32-C-DAG: addiu $[[T0:2]], $zero, 0
366; 32-C-DAG: addiu $[[T1:[0-9]+]], $zero, 1
367; 32-C-DAG: c.un.s $f12, $f14
368; 32-C-DAG: movt $[[T0]], $1, $fcc0
369
370; 64-C-DAG: addiu $[[T0:2]], $zero, 0
371; 64-C-DAG: addiu $[[T1:[0-9]+]], $zero, 1
372; 64-C-DAG: c.un.s $f12, $f13
373; 64-C-DAG: movt $[[T0]], $1, $fcc0
374
375; 32-CMP-DAG: cmp.un.s $[[T0:f[0-9]+]], $f12, $f14
Daniel Sanderscbd44c52014-07-10 10:18:12 +0000[diff] [blame]376; 32-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
377; 32-CMP-DAG: andi $2, $[[T1]], 1
Daniel Sanders0fa60412014-06-12 13:39:06 +0000[diff] [blame]378
379; 64-CMP-DAG: cmp.un.s $[[T0:f[0-9]+]], $f12, $f13
Daniel Sanderscbd44c52014-07-10 10:18:12 +0000[diff] [blame]380; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
381; 64-CMP-DAG: andi $2, $[[T1]], 1
Daniel Sanders0fa60412014-06-12 13:39:06 +0000[diff] [blame]382
383 %1 = fcmp uno float %a, %b
384 %2 = zext i1 %1 to i32
385 ret i32 %2
386}
387
388define i32 @true_f32(float %a, float %b) nounwind {
389; ALL-LABEL: true_f32:
390; ALL: addiu $2, $zero, 1
391
392 %1 = fcmp true float %a, %b
393 %2 = zext i1 %1 to i32
394 ret i32 %2
395}
396
397define i32 @false_f64(double %a, double %b) nounwind {
398; ALL-LABEL: false_f64:
399; ALL: addiu $2, $zero, 0
400
401 %1 = fcmp false double %a, %b
402 %2 = zext i1 %1 to i32
403 ret i32 %2
404}
405
406define i32 @oeq_f64(double %a, double %b) nounwind {
407; ALL-LABEL: oeq_f64:
408
409; 32-C-DAG: addiu $[[T0:2]], $zero, 0
410; 32-C-DAG: addiu $[[T1:[0-9]+]], $zero, 1
411; 32-C-DAG: c.eq.d $f12, $f14
412; 32-C-DAG: movt $[[T0]], $1, $fcc0
413
414; 64-C-DAG: addiu $[[T0:2]], $zero, 0
415; 64-C-DAG: addiu $[[T1:[0-9]+]], $zero, 1
416; 64-C-DAG: c.eq.d $f12, $f13
417; 64-C-DAG: movt $[[T0]], $1, $fcc0
418
419; 32-CMP-DAG: cmp.eq.d $[[T0:f[0-9]+]], $f12, $f14
Daniel Sanderscbd44c52014-07-10 10:18:12 +0000[diff] [blame]420; 32-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
421; 32-CMP-DAG: andi $2, $[[T1]], 1
Daniel Sanders0fa60412014-06-12 13:39:06 +0000[diff] [blame]422
423; 64-CMP-DAG: cmp.eq.d $[[T0:f[0-9]+]], $f12, $f13
Daniel Sanderscbd44c52014-07-10 10:18:12 +0000[diff] [blame]424; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
425; 64-CMP-DAG: andi $2, $[[T1]], 1
Daniel Sanders0fa60412014-06-12 13:39:06 +0000[diff] [blame]426
427 %1 = fcmp oeq double %a, %b
428 %2 = zext i1 %1 to i32
429 ret i32 %2
430}
431
432define i32 @ogt_f64(double %a, double %b) nounwind {
433; ALL-LABEL: ogt_f64:
434
435; 32-C-DAG: addiu $[[T0:2]], $zero, 0
436; 32-C-DAG: addiu $[[T1:[0-9]+]], $zero, 1
437; 32-C-DAG: c.ule.d $f12, $f14
438; 32-C-DAG: movf $[[T0]], $1, $fcc0
439
440; 64-C-DAG: addiu $[[T0:2]], $zero, 0
441; 64-C-DAG: addiu $[[T1:[0-9]+]], $zero, 1
442; 64-C-DAG: c.ule.d $f12, $f13
443; 64-C-DAG: movf $[[T0]], $1, $fcc0
444
Daniel Sandersdc067182014-07-09 10:40:20 +0000[diff] [blame]445; 32-CMP-DAG: cmp.lt.d $[[T0:f[0-9]+]], $f14, $f12
Daniel Sanderscbd44c52014-07-10 10:18:12 +0000[diff] [blame]446; 32-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
447; 32-CMP-DAG: andi $2, $[[T1]], 1
Daniel Sanders0fa60412014-06-12 13:39:06 +0000[diff] [blame]448
Daniel Sandersdc067182014-07-09 10:40:20 +0000[diff] [blame]449; 64-CMP-DAG: cmp.lt.d $[[T0:f[0-9]+]], $f13, $f12
Daniel Sanderscbd44c52014-07-10 10:18:12 +0000[diff] [blame]450; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
451; 64-CMP-DAG: andi $2, $[[T1]], 1
Daniel Sanders0fa60412014-06-12 13:39:06 +0000[diff] [blame]452
453 %1 = fcmp ogt double %a, %b
454 %2 = zext i1 %1 to i32
455 ret i32 %2
456}
457
458define i32 @oge_f64(double %a, double %b) nounwind {
459; ALL-LABEL: oge_f64:
460
461; 32-C-DAG: addiu $[[T0:2]], $zero, 0
462; 32-C-DAG: addiu $[[T1:[0-9]+]], $zero, 1
463; 32-C-DAG: c.ult.d $f12, $f14
464; 32-C-DAG: movf $[[T0]], $1, $fcc0
465
466; 64-C-DAG: addiu $[[T0:2]], $zero, 0
467; 64-C-DAG: addiu $[[T1:[0-9]+]], $zero, 1
468; 64-C-DAG: c.ult.d $f12, $f13
469; 64-C-DAG: movf $[[T0]], $1, $fcc0
470
Daniel Sandersdc067182014-07-09 10:40:20 +0000[diff] [blame]471; 32-CMP-DAG: cmp.le.d $[[T0:f[0-9]+]], $f14, $f12
Daniel Sanderscbd44c52014-07-10 10:18:12 +0000[diff] [blame]472; 32-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
473; 32-CMP-DAG: andi $2, $[[T1]], 1
Daniel Sanders0fa60412014-06-12 13:39:06 +0000[diff] [blame]474
Daniel Sandersdc067182014-07-09 10:40:20 +0000[diff] [blame]475; 64-CMP-DAG: cmp.le.d $[[T0:f[0-9]+]], $f13, $f12
Daniel Sanderscbd44c52014-07-10 10:18:12 +0000[diff] [blame]476; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
477; 64-CMP-DAG: andi $2, $[[T1]], 1
Daniel Sanders0fa60412014-06-12 13:39:06 +0000[diff] [blame]478
479 %1 = fcmp oge double %a, %b
480 %2 = zext i1 %1 to i32
481 ret i32 %2
482}
483
484define i32 @olt_f64(double %a, double %b) nounwind {
485; ALL-LABEL: olt_f64:
486
487; 32-C-DAG: addiu $[[T0:2]], $zero, 0
488; 32-C-DAG: addiu $[[T1:[0-9]+]], $zero, 1
489; 32-C-DAG: c.olt.d $f12, $f14
490; 32-C-DAG: movt $[[T0]], $1, $fcc0
491
492; 64-C-DAG: addiu $[[T0:2]], $zero, 0
493; 64-C-DAG: addiu $[[T1:[0-9]+]], $zero, 1
494; 64-C-DAG: c.olt.d $f12, $f13
495; 64-C-DAG: movt $[[T0]], $1, $fcc0
496
Daniel Sandersdc067182014-07-09 10:40:20 +0000[diff] [blame]497; 32-CMP-DAG: cmp.lt.d $[[T0:f[0-9]+]], $f12, $f14
Daniel Sanderscbd44c52014-07-10 10:18:12 +0000[diff] [blame]498; 32-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
499; 32-CMP-DAG: andi $2, $[[T1]], 1
Daniel Sanders0fa60412014-06-12 13:39:06 +0000[diff] [blame]500
Daniel Sandersdc067182014-07-09 10:40:20 +0000[diff] [blame]501; 64-CMP-DAG: cmp.lt.d $[[T0:f[0-9]+]], $f12, $f13
Daniel Sanderscbd44c52014-07-10 10:18:12 +0000[diff] [blame]502; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
503; 64-CMP-DAG: andi $2, $[[T1]], 1
Daniel Sanders0fa60412014-06-12 13:39:06 +0000[diff] [blame]504
505 %1 = fcmp olt double %a, %b
506 %2 = zext i1 %1 to i32
507 ret i32 %2
508}
509
510define i32 @ole_f64(double %a, double %b) nounwind {
511; ALL-LABEL: ole_f64:
512
513; 32-C-DAG: addiu $[[T0:2]], $zero, 0
514; 32-C-DAG: addiu $[[T1:[0-9]+]], $zero, 1
515; 32-C-DAG: c.ole.d $f12, $f14
516; 32-C-DAG: movt $[[T0]], $1, $fcc0
517
518; 64-C-DAG: addiu $[[T0:2]], $zero, 0
519; 64-C-DAG: addiu $[[T1:[0-9]+]], $zero, 1
520; 64-C-DAG: c.ole.d $f12, $f13
521; 64-C-DAG: movt $[[T0]], $1, $fcc0
522
Daniel Sandersdc067182014-07-09 10:40:20 +0000[diff] [blame]523; 32-CMP-DAG: cmp.le.d $[[T0:f[0-9]+]], $f12, $f14
Daniel Sanderscbd44c52014-07-10 10:18:12 +0000[diff] [blame]524; 32-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
525; 32-CMP-DAG: andi $2, $[[T1]], 1
Daniel Sanders0fa60412014-06-12 13:39:06 +0000[diff] [blame]526
Daniel Sandersdc067182014-07-09 10:40:20 +0000[diff] [blame]527; 64-CMP-DAG: cmp.le.d $[[T0:f[0-9]+]], $f12, $f13
Daniel Sanderscbd44c52014-07-10 10:18:12 +0000[diff] [blame]528; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
529; 64-CMP-DAG: andi $2, $[[T1]], 1
Daniel Sanders0fa60412014-06-12 13:39:06 +0000[diff] [blame]530
531 %1 = fcmp ole double %a, %b
532 %2 = zext i1 %1 to i32
533 ret i32 %2
534}
535
536define i32 @one_f64(double %a, double %b) nounwind {
537; ALL-LABEL: one_f64:
538
539; 32-C-DAG: addiu $[[T0:2]], $zero, 0
540; 32-C-DAG: addiu $[[T1:[0-9]+]], $zero, 1
541; 32-C-DAG: c.ueq.d $f12, $f14
542; 32-C-DAG: movf $[[T0]], $1, $fcc0
543
544; 64-C-DAG: addiu $[[T0:2]], $zero, 0
545; 64-C-DAG: addiu $[[T1:[0-9]+]], $zero, 1
546; 64-C-DAG: c.ueq.d $f12, $f13
547; 64-C-DAG: movf $[[T0]], $1, $fcc0
548
549; 32-CMP-DAG: cmp.ueq.d $[[T0:f[0-9]+]], $f12, $f14
550; 32-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
Daniel Sanderscbd44c52014-07-10 10:18:12 +0000[diff] [blame]551; 32-CMP-DAG: not $[[T2:[0-9]+]], $[[T1]]
552; 32-CMP-DAG: andi $2, $[[T2]], 1
Daniel Sanders0fa60412014-06-12 13:39:06 +0000[diff] [blame]553
554; 64-CMP-DAG: cmp.ueq.d $[[T0:f[0-9]+]], $f12, $f13
555; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
Daniel Sanderscbd44c52014-07-10 10:18:12 +0000[diff] [blame]556; 64-CMP-DAG: not $[[T2:[0-9]+]], $[[T1]]
557; 64-CMP-DAG: andi $2, $[[T2]], 1
Daniel Sanders0fa60412014-06-12 13:39:06 +0000[diff] [blame]558
559 %1 = fcmp one double %a, %b
560 %2 = zext i1 %1 to i32
561 ret i32 %2
562}
563
564define i32 @ord_f64(double %a, double %b) nounwind {
565; ALL-LABEL: ord_f64:
566
567; 32-C-DAG: addiu $[[T0:2]], $zero, 0
568; 32-C-DAG: addiu $[[T1:[0-9]+]], $zero, 1
569; 32-C-DAG: c.un.d $f12, $f14
570; 32-C-DAG: movf $[[T0]], $1, $fcc0
571
572; 64-C-DAG: addiu $[[T0:2]], $zero, 0
573; 64-C-DAG: addiu $[[T1:[0-9]+]], $zero, 1
574; 64-C-DAG: c.un.d $f12, $f13
575; 64-C-DAG: movf $[[T0]], $1, $fcc0
576
577; 32-CMP-DAG: cmp.un.d $[[T0:f[0-9]+]], $f12, $f14
578; 32-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
Daniel Sanderscbd44c52014-07-10 10:18:12 +0000[diff] [blame]579; 32-CMP-DAG: not $[[T2:[0-9]+]], $[[T1]]
580; 32-CMP-DAG: andi $2, $[[T2]], 1
Daniel Sanders0fa60412014-06-12 13:39:06 +0000[diff] [blame]581
582; 64-CMP-DAG: cmp.un.d $[[T0:f[0-9]+]], $f12, $f13
583; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
Daniel Sanderscbd44c52014-07-10 10:18:12 +0000[diff] [blame]584; 64-CMP-DAG: not $[[T2:[0-9]+]], $[[T1]]
585; 64-CMP-DAG: andi $2, $[[T2]], 1
Daniel Sanders0fa60412014-06-12 13:39:06 +0000[diff] [blame]586
587 %1 = fcmp ord double %a, %b
588 %2 = zext i1 %1 to i32
589 ret i32 %2
590}
591
592define i32 @ueq_f64(double %a, double %b) nounwind {
593; ALL-LABEL: ueq_f64:
594
595; 32-C-DAG: addiu $[[T0:2]], $zero, 0
596; 32-C-DAG: addiu $[[T1:[0-9]+]], $zero, 1
597; 32-C-DAG: c.ueq.d $f12, $f14
598; 32-C-DAG: movt $[[T0]], $1, $fcc0
599
600; 64-C-DAG: addiu $[[T0:2]], $zero, 0
601; 64-C-DAG: addiu $[[T1:[0-9]+]], $zero, 1
602; 64-C-DAG: c.ueq.d $f12, $f13
603; 64-C-DAG: movt $[[T0]], $1, $fcc0
604
605; 32-CMP-DAG: cmp.ueq.d $[[T0:f[0-9]+]], $f12, $f14
Daniel Sanderscbd44c52014-07-10 10:18:12 +0000[diff] [blame]606; 32-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
607; 32-CMP-DAG: andi $2, $[[T1]], 1
Daniel Sanders0fa60412014-06-12 13:39:06 +0000[diff] [blame]608
609; 64-CMP-DAG: cmp.ueq.d $[[T0:f[0-9]+]], $f12, $f13
Daniel Sanderscbd44c52014-07-10 10:18:12 +0000[diff] [blame]610; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
611; 64-CMP-DAG: andi $2, $[[T1]], 1
Daniel Sanders0fa60412014-06-12 13:39:06 +0000[diff] [blame]612
613 %1 = fcmp ueq double %a, %b
614 %2 = zext i1 %1 to i32
615 ret i32 %2
616}
617
618define i32 @ugt_f64(double %a, double %b) nounwind {
619; ALL-LABEL: ugt_f64:
620
621; 32-C-DAG: addiu $[[T0:2]], $zero, 0
622; 32-C-DAG: addiu $[[T1:[0-9]+]], $zero, 1
623; 32-C-DAG: c.ole.d $f12, $f14
624; 32-C-DAG: movf $[[T0]], $1, $fcc0
625
626; 64-C-DAG: addiu $[[T0:2]], $zero, 0
627; 64-C-DAG: addiu $[[T1:[0-9]+]], $zero, 1
628; 64-C-DAG: c.ole.d $f12, $f13
629; 64-C-DAG: movf $[[T0]], $1, $fcc0
630
631; 32-CMP-DAG: cmp.ult.d $[[T0:f[0-9]+]], $f14, $f12
Daniel Sanderscbd44c52014-07-10 10:18:12 +0000[diff] [blame]632; 32-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
633; 32-CMP-DAG: andi $2, $[[T1]], 1
Daniel Sanders0fa60412014-06-12 13:39:06 +0000[diff] [blame]634
635; 64-CMP-DAG: cmp.ult.d $[[T0:f[0-9]+]], $f13, $f12
Daniel Sanderscbd44c52014-07-10 10:18:12 +0000[diff] [blame]636; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
637; 64-CMP-DAG: andi $2, $[[T1]], 1
Daniel Sanders0fa60412014-06-12 13:39:06 +0000[diff] [blame]638
639 %1 = fcmp ugt double %a, %b
640 %2 = zext i1 %1 to i32
641 ret i32 %2
642}
643
644define i32 @uge_f64(double %a, double %b) nounwind {
645; ALL-LABEL: uge_f64:
646
647; 32-C-DAG: addiu $[[T0:2]], $zero, 0
648; 32-C-DAG: addiu $[[T1:[0-9]+]], $zero, 1
649; 32-C-DAG: c.olt.d $f12, $f14
650; 32-C-DAG: movf $[[T0]], $1, $fcc0
651
652; 64-C-DAG: addiu $[[T0:2]], $zero, 0
653; 64-C-DAG: addiu $[[T1:[0-9]+]], $zero, 1
654; 64-C-DAG: c.olt.d $f12, $f13
655; 64-C-DAG: movf $[[T0]], $1, $fcc0
656
657; 32-CMP-DAG: cmp.ule.d $[[T0:f[0-9]+]], $f14, $f12
Daniel Sanderscbd44c52014-07-10 10:18:12 +0000[diff] [blame]658; 32-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
659; 32-CMP-DAG: andi $2, $[[T1]], 1
Daniel Sanders0fa60412014-06-12 13:39:06 +0000[diff] [blame]660
661; 64-CMP-DAG: cmp.ule.d $[[T0:f[0-9]+]], $f13, $f12
Daniel Sanderscbd44c52014-07-10 10:18:12 +0000[diff] [blame]662; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
663; 64-CMP-DAG: andi $2, $[[T1]], 1
Daniel Sanders0fa60412014-06-12 13:39:06 +0000[diff] [blame]664
665 %1 = fcmp uge double %a, %b
666 %2 = zext i1 %1 to i32
667 ret i32 %2
668}
669
670define i32 @ult_f64(double %a, double %b) nounwind {
671; ALL-LABEL: ult_f64:
672
673; 32-C-DAG: addiu $[[T0:2]], $zero, 0
674; 32-C-DAG: addiu $[[T1:[0-9]+]], $zero, 1
675; 32-C-DAG: c.ult.d $f12, $f14
676; 32-C-DAG: movt $[[T0]], $1, $fcc0
677
678; 64-C-DAG: addiu $[[T0:2]], $zero, 0
679; 64-C-DAG: addiu $[[T1:[0-9]+]], $zero, 1
680; 64-C-DAG: c.ult.d $f12, $f13
681; 64-C-DAG: movt $[[T0]], $1, $fcc0
682
683; 32-CMP-DAG: cmp.ult.d $[[T0:f[0-9]+]], $f12, $f14
Daniel Sanderscbd44c52014-07-10 10:18:12 +0000[diff] [blame]684; 32-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
685; 32-CMP-DAG: andi $2, $[[T1]], 1
Daniel Sanders0fa60412014-06-12 13:39:06 +0000[diff] [blame]686
687; 64-CMP-DAG: cmp.ult.d $[[T0:f[0-9]+]], $f12, $f13
Daniel Sanderscbd44c52014-07-10 10:18:12 +0000[diff] [blame]688; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
689; 64-CMP-DAG: andi $2, $[[T1]], 1
Daniel Sanders0fa60412014-06-12 13:39:06 +0000[diff] [blame]690
691 %1 = fcmp ult double %a, %b
692 %2 = zext i1 %1 to i32
693 ret i32 %2
694}
695
696define i32 @ule_f64(double %a, double %b) nounwind {
697; ALL-LABEL: ule_f64:
698
699; 32-C-DAG: addiu $[[T0:2]], $zero, 0
700; 32-C-DAG: addiu $[[T1:[0-9]+]], $zero, 1
701; 32-C-DAG: c.ule.d $f12, $f14
702; 32-C-DAG: movt $[[T0]], $1, $fcc0
703
704; 64-C-DAG: addiu $[[T0:2]], $zero, 0
705; 64-C-DAG: addiu $[[T1:[0-9]+]], $zero, 1
706; 64-C-DAG: c.ule.d $f12, $f13
707; 64-C-DAG: movt $[[T0]], $1, $fcc0
708
709; 32-CMP-DAG: cmp.ule.d $[[T0:f[0-9]+]], $f12, $f14
Daniel Sanderscbd44c52014-07-10 10:18:12 +0000[diff] [blame]710; 32-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
711; 32-CMP-DAG: andi $2, $[[T1]], 1
Daniel Sanders0fa60412014-06-12 13:39:06 +0000[diff] [blame]712
713; 64-CMP-DAG: cmp.ule.d $[[T0:f[0-9]+]], $f12, $f13
Daniel Sanderscbd44c52014-07-10 10:18:12 +0000[diff] [blame]714; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
715; 64-CMP-DAG: andi $2, $[[T1]], 1
Daniel Sanders0fa60412014-06-12 13:39:06 +0000[diff] [blame]716
717 %1 = fcmp ule double %a, %b
718 %2 = zext i1 %1 to i32
719 ret i32 %2
720}
721
722define i32 @une_f64(double %a, double %b) nounwind {
723; ALL-LABEL: une_f64:
724
725; 32-C-DAG: addiu $[[T0:2]], $zero, 0
726; 32-C-DAG: addiu $[[T1:[0-9]+]], $zero, 1
727; 32-C-DAG: c.eq.d $f12, $f14
728; 32-C-DAG: movf $[[T0]], $1, $fcc0
729
730; 64-C-DAG: addiu $[[T0:2]], $zero, 0
731; 64-C-DAG: addiu $[[T1:[0-9]+]], $zero, 1
732; 64-C-DAG: c.eq.d $f12, $f13
733; 64-C-DAG: movf $[[T0]], $1, $fcc0
734
735; 32-CMP-DAG: cmp.eq.d $[[T0:f[0-9]+]], $f12, $f14
736; 32-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
Daniel Sanderscbd44c52014-07-10 10:18:12 +0000[diff] [blame]737; 32-CMP-DAG: not $[[T2:[0-9]+]], $[[T1]]
738; 32-CMP-DAG: andi $2, $[[T2]], 1
Daniel Sanders0fa60412014-06-12 13:39:06 +0000[diff] [blame]739
740; 64-CMP-DAG: cmp.eq.d $[[T0:f[0-9]+]], $f12, $f13
741; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
Daniel Sanderscbd44c52014-07-10 10:18:12 +0000[diff] [blame]742; 64-CMP-DAG: not $[[T2:[0-9]+]], $[[T1]]
743; 64-CMP-DAG: andi $2, $[[T2]], 1
Daniel Sanders0fa60412014-06-12 13:39:06 +0000[diff] [blame]744
745 %1 = fcmp une double %a, %b
746 %2 = zext i1 %1 to i32
747 ret i32 %2
748}
749
750define i32 @uno_f64(double %a, double %b) nounwind {
751; ALL-LABEL: uno_f64:
752
753; 32-C-DAG: addiu $[[T0:2]], $zero, 0
754; 32-C-DAG: addiu $[[T1:[0-9]+]], $zero, 1
755; 32-C-DAG: c.un.d $f12, $f14
756; 32-C-DAG: movt $[[T0]], $1, $fcc0
757
758; 64-C-DAG: addiu $[[T0:2]], $zero, 0
759; 64-C-DAG: addiu $[[T1:[0-9]+]], $zero, 1
760; 64-C-DAG: c.un.d $f12, $f13
761; 64-C-DAG: movt $[[T0]], $1, $fcc0
762
763; 32-CMP-DAG: cmp.un.d $[[T0:f[0-9]+]], $f12, $f14
Daniel Sanderscbd44c52014-07-10 10:18:12 +0000[diff] [blame]764; 32-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
765; 32-CMP-DAG: andi $2, $[[T1]], 1
Daniel Sanders0fa60412014-06-12 13:39:06 +0000[diff] [blame]766
767; 64-CMP-DAG: cmp.un.d $[[T0:f[0-9]+]], $f12, $f13
Daniel Sanderscbd44c52014-07-10 10:18:12 +0000[diff] [blame]768; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
769; 64-CMP-DAG: andi $2, $[[T1]], 1
Daniel Sanders0fa60412014-06-12 13:39:06 +0000[diff] [blame]770
771 %1 = fcmp uno double %a, %b
772 %2 = zext i1 %1 to i32
773 ret i32 %2
774}
775
776define i32 @true_f64(double %a, double %b) nounwind {
777; ALL-LABEL: true_f64:
778; ALL: addiu $2, $zero, 1
779
780 %1 = fcmp true double %a, %b
781 %2 = zext i1 %1 to i32
782 ret i32 %2
783}
Daniel Sanders023c8062015-01-15 15:41:03 +0000[diff] [blame]784
785; The optimizers sometimes produce setlt instead of setolt/setult.
786define float @bug1_f32(float %angle, float %at) #0 {
787entry:
788; ALL-LABEL: bug1_f32:
789
790; 32-C-DAG: add.s $[[T0:f[0-9]+]], $f14, $f12
791; 32-C-DAG: lwc1 $[[T1:f[0-9]+]], %lo($CPI32_0)(
792; 32-C-DAG: c.ole.s $[[T0]], $[[T1]]
793; 32-C-DAG: bc1t
794
795; 32-CMP-DAG: add.s $[[T0:f[0-9]+]], $f14, $f12
796; 32-CMP-DAG: lwc1 $[[T1:f[0-9]+]], %lo($CPI32_0)(
797; 32-CMP-DAG: cmp.le.s $[[T2:f[0-9]+]], $[[T0]], $[[T1]]
798; 32-CMP-DAG: mfc1 $[[T3:[0-9]+]], $[[T2]]
799; FIXME: This instruction is redundant.
800; 32-CMP-DAG: andi $[[T4:[0-9]+]], $[[T3]], 1
801; 32-CMP-DAG: bnez $[[T4]],
802
803; 64-C-DAG: add.s $[[T0:f[0-9]+]], $f13, $f12
804; 64-C-DAG: lwc1 $[[T1:f[0-9]+]], %got_ofst($CPI32_0)(
805; 64-C-DAG: c.ole.s $[[T0]], $[[T1]]
806; 64-C-DAG: bc1t
807
808; 64-CMP-DAG: add.s $[[T0:f[0-9]+]], $f13, $f12
809; 64-CMP-DAG: lwc1 $[[T1:f[0-9]+]], %got_ofst($CPI32_0)(
810; 64-CMP-DAG: cmp.le.s $[[T2:f[0-9]+]], $[[T0]], $[[T1]]
811; 64-CMP-DAG: mfc1 $[[T3:[0-9]+]], $[[T2]]
812; FIXME: This instruction is redundant.
813; 64-CMP-DAG: andi $[[T4:[0-9]+]], $[[T3]], 1
814; 64-CMP-DAG: bnez $[[T4]],
815
816 %add = fadd fast float %at, %angle
817 %cmp = fcmp ogt float %add, 1.000000e+00
818 br i1 %cmp, label %if.then, label %if.end
819
820if.then:
821 %sub = fadd fast float %add, -1.000000e+00
822 br label %if.end
823
824if.end:
825 %theta.0 = phi float [ %sub, %if.then ], [ %add, %entry ]
826 ret float %theta.0
827}
828
829; The optimizers sometimes produce setlt instead of setolt/setult.
830define double @bug1_f64(double %angle, double %at) #0 {
831entry:
832; ALL-LABEL: bug1_f64:
833
834; 32-C-DAG: add.d $[[T0:f[0-9]+]], $f14, $f12
835; 32-C-DAG: ldc1 $[[T1:f[0-9]+]], %lo($CPI33_0)(
836; 32-C-DAG: c.ole.d $[[T0]], $[[T1]]
837; 32-C-DAG: bc1t
838
839; 32-CMP-DAG: add.d $[[T0:f[0-9]+]], $f14, $f12
840; 32-CMP-DAG: ldc1 $[[T1:f[0-9]+]], %lo($CPI33_0)(
841; 32-CMP-DAG: cmp.le.d $[[T2:f[0-9]+]], $[[T0]], $[[T1]]
842; 32-CMP-DAG: mfc1 $[[T3:[0-9]+]], $[[T2]]
843; FIXME: This instruction is redundant.
844; 32-CMP-DAG: andi $[[T4:[0-9]+]], $[[T3]], 1
845; 32-CMP-DAG: bnez $[[T4]],
846
847; 64-C-DAG: add.d $[[T0:f[0-9]+]], $f13, $f12
848; 64-C-DAG: ldc1 $[[T1:f[0-9]+]], %got_ofst($CPI33_0)(
849; 64-C-DAG: c.ole.d $[[T0]], $[[T1]]
850; 64-C-DAG: bc1t
851
852; 64-CMP-DAG: add.d $[[T0:f[0-9]+]], $f13, $f12
853; 64-CMP-DAG: ldc1 $[[T1:f[0-9]+]], %got_ofst($CPI33_0)(
854; 64-CMP-DAG: cmp.le.d $[[T2:f[0-9]+]], $[[T0]], $[[T1]]
855; 64-CMP-DAG: mfc1 $[[T3:[0-9]+]], $[[T2]]
856; FIXME: This instruction is redundant.
857; 64-CMP-DAG: andi $[[T4:[0-9]+]], $[[T3]], 1
858; 64-CMP-DAG: bnez $[[T4]],
859
860 %add = fadd fast double %at, %angle
861 %cmp = fcmp ogt double %add, 1.000000e+00
862 br i1 %cmp, label %if.then, label %if.end
863
864if.then:
865 %sub = fadd fast double %add, -1.000000e+00
866 br label %if.end
867
868if.end:
869 %theta.0 = phi double [ %sub, %if.then ], [ %add, %entry ]
870 ret double %theta.0
871}
872
873attributes #0 = { nounwind readnone "no-nans-fp-math"="true" }