| Jia Liu | b22310f | 2012-02-18 12:03:15 +0000 | [diff] [blame] | 1 | //===-- Hexagon.td - Describe the Hexagon Target Machine --*- tablegen -*--===// |
| Tony Linthicum | 1213a7a | 2011-12-12 21:14:40 +0000 | [diff] [blame] | 2 | // |
| 3 | // The LLVM Compiler Infrastructure |
| 4 | // |
| 5 | // This file is distributed under the University of Illinois Open Source |
| 6 | // License. See LICENSE.TXT for details. |
| 7 | // |
| 8 | //===----------------------------------------------------------------------===// |
| 9 | // |
| Jia Liu | b22310f | 2012-02-18 12:03:15 +0000 | [diff] [blame] | 10 | // This is the top level entry point for the Hexagon target. |
| Tony Linthicum | 1213a7a | 2011-12-12 21:14:40 +0000 | [diff] [blame] | 11 | // |
| 12 | //===----------------------------------------------------------------------===// |
| 13 | |
| 14 | //===----------------------------------------------------------------------===// |
| 15 | // Target-independent interfaces which we are implementing |
| 16 | //===----------------------------------------------------------------------===// |
| 17 | |
| 18 | include "llvm/Target/Target.td" |
| 19 | |
| 20 | //===----------------------------------------------------------------------===// |
| 21 | // Hexagon Subtarget features. |
| Jia Liu | b22310f | 2012-02-18 12:03:15 +0000 | [diff] [blame] | 22 | //===----------------------------------------------------------------------===// |
| Tony Linthicum | 1213a7a | 2011-12-12 21:14:40 +0000 | [diff] [blame] | 23 | |
| Colin LeMahieu | 4fd203d | 2015-02-09 21:56:37 +0000 | [diff] [blame] | 24 | // Hexagon Architectures |
| 25 | def ArchV4: SubtargetFeature<"v4", "HexagonArchVersion", "V4", "Hexagon V4">; |
| 26 | def ArchV5: SubtargetFeature<"v5", "HexagonArchVersion", "V5", "Hexagon V5">; |
| Colin LeMahieu | 7c95871 | 2015-10-17 01:33:04 +0000 | [diff] [blame] | 27 | def ArchV55: SubtargetFeature<"v55", "HexagonArchVersion", "V55", "Hexagon V55">; |
| 28 | def ArchV60: SubtargetFeature<"v60", "HexagonArchVersion", "V60", "Hexagon V60">; |
| Tony Linthicum | 1213a7a | 2011-12-12 21:14:40 +0000 | [diff] [blame] | 29 | |
| Colin LeMahieu | 7c95871 | 2015-10-17 01:33:04 +0000 | [diff] [blame] | 30 | // Hexagon ISA Extensions |
| 31 | def ExtensionHVX: SubtargetFeature<"hvx", "UseHVXOps", |
| 32 | "true", "Hexagon HVX instructions">; |
| Tony Linthicum | 1213a7a | 2011-12-12 21:14:40 +0000 | [diff] [blame] | 33 | //===----------------------------------------------------------------------===// |
| Jyotsna Verma | efe4f55 | 2012-12-04 04:29:16 +0000 | [diff] [blame] | 34 | // Hexagon Instruction Predicate Definitions. |
| 35 | //===----------------------------------------------------------------------===// |
| Colin LeMahieu | 7c95871 | 2015-10-17 01:33:04 +0000 | [diff] [blame] | 36 | def HasV5T : Predicate<"HST->hasV5TOps()">; |
| 37 | def NoV5T : Predicate<"!HST->hasV5TOps()">; |
| 38 | def HasV55T : Predicate<"HST->hasV55TOps()">, |
| 39 | AssemblerPredicate<"ArchV55">; |
| 40 | def HasV60T : Predicate<"HST->hasV60TOps()">, |
| 41 | AssemblerPredicate<"ArchV60">; |
| 42 | def UseMEMOP : Predicate<"HST->useMemOps()">; |
| 43 | def IEEERndNearV5T : Predicate<"HST->modeIEEERndNear()">; |
| 44 | def UseHVXDbl : Predicate<"HST->useHVXDblOps()">, |
| 45 | AssemblerPredicate<"ExtensionHVXDbl">; |
| 46 | def UseHVXSgl : Predicate<"HST->useHVXSglOps()">; |
| 47 | |
| 48 | def UseHVX : Predicate<"HST->useHVXOps()">, |
| 49 | AssemblerPredicate<"ExtensionHVX">; |
| Jyotsna Verma | efe4f55 | 2012-12-04 04:29:16 +0000 | [diff] [blame] | 50 | |
| 51 | //===----------------------------------------------------------------------===// |
| 52 | // Classes used for relation maps. |
| 53 | //===----------------------------------------------------------------------===// |
| Colin LeMahieu | 9161d47 | 2014-12-30 18:58:47 +0000 | [diff] [blame] | 54 | |
| 55 | class ImmRegShl; |
| Jyotsna Verma | efe4f55 | 2012-12-04 04:29:16 +0000 | [diff] [blame] | 56 | // PredRel - Filter class used to relate non-predicated instructions with their |
| 57 | // predicated forms. |
| 58 | class PredRel; |
| 59 | // PredNewRel - Filter class used to relate predicated instructions with their |
| 60 | // predicate-new forms. |
| 61 | class PredNewRel: PredRel; |
| 62 | // ImmRegRel - Filter class used to relate instructions having reg-reg form |
| 63 | // with their reg-imm counterparts. |
| 64 | class ImmRegRel; |
| 65 | // NewValueRel - Filter class used to relate regular store instructions with |
| 66 | // their new-value store form. |
| 67 | class NewValueRel: PredNewRel; |
| 68 | // NewValueRel - Filter class used to relate load/store instructions having |
| 69 | // different addressing modes with each other. |
| 70 | class AddrModeRel: NewValueRel; |
| 71 | |
| 72 | //===----------------------------------------------------------------------===// |
| 73 | // Generate mapping table to relate non-predicate instructions with their |
| 74 | // predicated formats - true and false. |
| 75 | // |
| 76 | |
| 77 | def getPredOpcode : InstrMapping { |
| 78 | let FilterClass = "PredRel"; |
| 79 | // Instructions with the same BaseOpcode and isNVStore values form a row. |
| Colin LeMahieu | 7c95871 | 2015-10-17 01:33:04 +0000 | [diff] [blame] | 80 | let RowFields = ["BaseOpcode", "isNVStore", "PNewValue", "isNT"]; |
| Jyotsna Verma | efe4f55 | 2012-12-04 04:29:16 +0000 | [diff] [blame] | 81 | // Instructions with the same predicate sense form a column. |
| 82 | let ColFields = ["PredSense"]; |
| 83 | // The key column is the unpredicated instructions. |
| 84 | let KeyCol = [""]; |
| 85 | // Value columns are PredSense=true and PredSense=false |
| 86 | let ValueCols = [["true"], ["false"]]; |
| 87 | } |
| 88 | |
| 89 | //===----------------------------------------------------------------------===// |
| Jyotsna Verma | 84c4710 | 2013-05-06 18:49:23 +0000 | [diff] [blame] | 90 | // Generate mapping table to relate predicate-true instructions with their |
| 91 | // predicate-false forms |
| 92 | // |
| 93 | def getFalsePredOpcode : InstrMapping { |
| 94 | let FilterClass = "PredRel"; |
| Colin LeMahieu | 7c95871 | 2015-10-17 01:33:04 +0000 | [diff] [blame] | 95 | let RowFields = ["BaseOpcode", "PNewValue", "isNVStore", "isBrTaken", "isNT"]; |
| Jyotsna Verma | 84c4710 | 2013-05-06 18:49:23 +0000 | [diff] [blame] | 96 | let ColFields = ["PredSense"]; |
| 97 | let KeyCol = ["true"]; |
| 98 | let ValueCols = [["false"]]; |
| 99 | } |
| 100 | |
| 101 | //===----------------------------------------------------------------------===// |
| 102 | // Generate mapping table to relate predicate-false instructions with their |
| 103 | // predicate-true forms |
| 104 | // |
| 105 | def getTruePredOpcode : InstrMapping { |
| 106 | let FilterClass = "PredRel"; |
| Colin LeMahieu | 7c95871 | 2015-10-17 01:33:04 +0000 | [diff] [blame] | 107 | let RowFields = ["BaseOpcode", "PNewValue", "isNVStore", "isBrTaken", "isNT"]; |
| Jyotsna Verma | 84c4710 | 2013-05-06 18:49:23 +0000 | [diff] [blame] | 108 | let ColFields = ["PredSense"]; |
| 109 | let KeyCol = ["false"]; |
| 110 | let ValueCols = [["true"]]; |
| 111 | } |
| 112 | |
| 113 | //===----------------------------------------------------------------------===// |
| Jyotsna Verma | efe4f55 | 2012-12-04 04:29:16 +0000 | [diff] [blame] | 114 | // Generate mapping table to relate predicated instructions with their .new |
| 115 | // format. |
| 116 | // |
| 117 | def getPredNewOpcode : InstrMapping { |
| 118 | let FilterClass = "PredNewRel"; |
| Jyotsna Verma | 5ed5181 | 2013-05-01 21:37:34 +0000 | [diff] [blame] | 119 | let RowFields = ["BaseOpcode", "PredSense", "isNVStore", "isBrTaken"]; |
| Jyotsna Verma | efe4f55 | 2012-12-04 04:29:16 +0000 | [diff] [blame] | 120 | let ColFields = ["PNewValue"]; |
| 121 | let KeyCol = [""]; |
| 122 | let ValueCols = [["new"]]; |
| 123 | } |
| 124 | |
| 125 | //===----------------------------------------------------------------------===// |
| Jyotsna Verma | 438cec5 | 2013-05-10 20:58:11 +0000 | [diff] [blame] | 126 | // Generate mapping table to relate .new predicated instructions with their old |
| 127 | // format. |
| 128 | // |
| 129 | def getPredOldOpcode : InstrMapping { |
| 130 | let FilterClass = "PredNewRel"; |
| 131 | let RowFields = ["BaseOpcode", "PredSense", "isNVStore"]; |
| 132 | let ColFields = ["PNewValue"]; |
| 133 | let KeyCol = ["new"]; |
| 134 | let ValueCols = [[""]]; |
| 135 | } |
| 136 | |
| 137 | //===----------------------------------------------------------------------===// |
| Jyotsna Verma | efe4f55 | 2012-12-04 04:29:16 +0000 | [diff] [blame] | 138 | // Generate mapping table to relate store instructions with their new-value |
| 139 | // format. |
| 140 | // |
| 141 | def getNewValueOpcode : InstrMapping { |
| 142 | let FilterClass = "NewValueRel"; |
| Colin LeMahieu | 7c95871 | 2015-10-17 01:33:04 +0000 | [diff] [blame] | 143 | let RowFields = ["BaseOpcode", "PredSense", "PNewValue", "addrMode", "isNT"]; |
| Jyotsna Verma | 300f0b9 | 2013-05-10 20:27:34 +0000 | [diff] [blame] | 144 | let ColFields = ["NValueST"]; |
| 145 | let KeyCol = ["false"]; |
| 146 | let ValueCols = [["true"]]; |
| Jyotsna Verma | efe4f55 | 2012-12-04 04:29:16 +0000 | [diff] [blame] | 147 | } |
| 148 | |
| Jyotsna Verma | 438cec5 | 2013-05-10 20:58:11 +0000 | [diff] [blame] | 149 | //===----------------------------------------------------------------------===// |
| 150 | // Generate mapping table to relate new-value store instructions with their old |
| 151 | // format. |
| 152 | // |
| 153 | def getNonNVStore : InstrMapping { |
| 154 | let FilterClass = "NewValueRel"; |
| Colin LeMahieu | 7c95871 | 2015-10-17 01:33:04 +0000 | [diff] [blame] | 155 | let RowFields = ["BaseOpcode", "PredSense", "PNewValue", "addrMode", "isNT"]; |
| Jyotsna Verma | 438cec5 | 2013-05-10 20:58:11 +0000 | [diff] [blame] | 156 | let ColFields = ["NValueST"]; |
| 157 | let KeyCol = ["true"]; |
| 158 | let ValueCols = [["false"]]; |
| 159 | } |
| 160 | |
| Jyotsna Verma | efe4f55 | 2012-12-04 04:29:16 +0000 | [diff] [blame] | 161 | def getBasedWithImmOffset : InstrMapping { |
| 162 | let FilterClass = "AddrModeRel"; |
| 163 | let RowFields = ["CextOpcode", "PredSense", "PNewValue", "isNVStore", |
| Krzysztof Parzyszek | 05da79d | 2015-10-20 19:04:53 +0000 | [diff] [blame^] | 164 | "isFloat"]; |
| Jyotsna Verma | efe4f55 | 2012-12-04 04:29:16 +0000 | [diff] [blame] | 165 | let ColFields = ["addrMode"]; |
| 166 | let KeyCol = ["Absolute"]; |
| 167 | let ValueCols = [["BaseImmOffset"]]; |
| 168 | } |
| 169 | |
| 170 | def getBaseWithRegOffset : InstrMapping { |
| 171 | let FilterClass = "AddrModeRel"; |
| 172 | let RowFields = ["CextOpcode", "PredSense", "PNewValue", "isNVStore"]; |
| 173 | let ColFields = ["addrMode"]; |
| 174 | let KeyCol = ["BaseImmOffset"]; |
| 175 | let ValueCols = [["BaseRegOffset"]]; |
| 176 | } |
| 177 | |
| 178 | def getRegForm : InstrMapping { |
| 179 | let FilterClass = "ImmRegRel"; |
| 180 | let RowFields = ["CextOpcode", "PredSense", "PNewValue"]; |
| 181 | let ColFields = ["InputType"]; |
| 182 | let KeyCol = ["imm"]; |
| 183 | let ValueCols = [["reg"]]; |
| 184 | } |
| 185 | |
| 186 | //===----------------------------------------------------------------------===// |
| Tony Linthicum | 1213a7a | 2011-12-12 21:14:40 +0000 | [diff] [blame] | 187 | // Register File, Calling Conv, Instruction Descriptions |
| 188 | //===----------------------------------------------------------------------===// |
| 189 | include "HexagonSchedule.td" |
| 190 | include "HexagonRegisterInfo.td" |
| 191 | include "HexagonCallingConv.td" |
| 192 | include "HexagonInstrInfo.td" |
| 193 | include "HexagonIntrinsics.td" |
| 194 | include "HexagonIntrinsicsDerived.td" |
| 195 | |
| Evandro Menezes | 5cee621 | 2012-04-12 17:55:53 +0000 | [diff] [blame] | 196 | def HexagonInstrInfo : InstrInfo; |
| Tony Linthicum | 1213a7a | 2011-12-12 21:14:40 +0000 | [diff] [blame] | 197 | |
| 198 | //===----------------------------------------------------------------------===// |
| 199 | // Hexagon processors supported. |
| 200 | //===----------------------------------------------------------------------===// |
| 201 | |
| Andrew Trick | 87255e3 | 2012-07-07 04:00:00 +0000 | [diff] [blame] | 202 | class Proc<string Name, SchedMachineModel Model, |
| Tony Linthicum | 1213a7a | 2011-12-12 21:14:40 +0000 | [diff] [blame] | 203 | list<SubtargetFeature> Features> |
| Andrew Trick | 87255e3 | 2012-07-07 04:00:00 +0000 | [diff] [blame] | 204 | : ProcessorModel<Name, Model, Features>; |
| Tony Linthicum | 1213a7a | 2011-12-12 21:14:40 +0000 | [diff] [blame] | 205 | |
| Colin LeMahieu | 4fd203d | 2015-02-09 21:56:37 +0000 | [diff] [blame] | 206 | def : Proc<"hexagonv4", HexagonModelV4, |
| 207 | [ArchV4]>; |
| 208 | def : Proc<"hexagonv5", HexagonModelV4, |
| 209 | [ArchV4, ArchV5]>; |
| Sirish Pande | 69295b8 | 2012-05-10 20:20:25 +0000 | [diff] [blame] | 210 | |
| Tony Linthicum | 1213a7a | 2011-12-12 21:14:40 +0000 | [diff] [blame] | 211 | //===----------------------------------------------------------------------===// |
| 212 | // Declare the target which we are implementing |
| 213 | //===----------------------------------------------------------------------===// |
| 214 | |
| 215 | def Hexagon : Target { |
| 216 | // Pull in Instruction Info: |
| 217 | let InstructionSet = HexagonInstrInfo; |
| Tony Linthicum | 1213a7a | 2011-12-12 21:14:40 +0000 | [diff] [blame] | 218 | } |