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gerrit-public.fairphone.software / toolchain / llvm-project / 062a2baef02b0f2ed21aa5c5d61460ac02d2880b / . / llvm / lib / Target / NVPTX / NVPTXISelLowering.cpp
blob: 029dab30b32802b72162b79c20262c8b48eae4fe [file] [log] [blame]
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]1//
2// The LLVM Compiler Infrastructure
3//
4// This file is distributed under the University of Illinois Open Source
5// License. See LICENSE.TXT for details.
6//
7//===----------------------------------------------------------------------===//
8//
9// This file defines the interfaces that NVPTX uses to lower LLVM code into a
10// selection DAG.
11//
12//===----------------------------------------------------------------------===//
13
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]14#include "NVPTXISelLowering.h"
Chandler Carruthed0881b2012-12-03 16:50:05 +0000[diff] [blame]15#include "NVPTX.h"
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]16#include "NVPTXTargetMachine.h"
17#include "NVPTXTargetObjectFile.h"
18#include "NVPTXUtilities.h"
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]19#include "llvm/CodeGen/Analysis.h"
20#include "llvm/CodeGen/MachineFrameInfo.h"
21#include "llvm/CodeGen/MachineFunction.h"
22#include "llvm/CodeGen/MachineInstrBuilder.h"
23#include "llvm/CodeGen/MachineRegisterInfo.h"
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]24#include "llvm/CodeGen/TargetLoweringObjectFileImpl.h"
Chandler Carruth219b89b2014-03-04 11:01:28 +0000[diff] [blame]25#include "llvm/IR/CallSite.h"
Chandler Carruth9fb823b2013-01-02 11:36:10 +0000[diff] [blame]26#include "llvm/IR/DerivedTypes.h"
27#include "llvm/IR/Function.h"
28#include "llvm/IR/GlobalValue.h"
29#include "llvm/IR/IntrinsicInst.h"
30#include "llvm/IR/Intrinsics.h"
31#include "llvm/IR/Module.h"
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]32#include "llvm/MC/MCSectionELF.h"
Chandler Carruthed0881b2012-12-03 16:50:05 +0000[diff] [blame]33#include "llvm/Support/CommandLine.h"
34#include "llvm/Support/Debug.h"
35#include "llvm/Support/ErrorHandling.h"
36#include "llvm/Support/raw_ostream.h"
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]37#include <sstream>
38
39#undef DEBUG_TYPE
40#define DEBUG_TYPE "nvptx-lower"
41
42using namespace llvm;
43
44static unsigned int uniqueCallSite = 0;
45
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]46static cl::opt<bool> sched4reg(
47 "nvptx-sched4reg",
48 cl::desc("NVPTX Specific: schedule for register pressue"), cl::init(false));
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]49
Justin Holewinskibe8dc642013-02-12 14:18:49 +0000[diff] [blame]50static bool IsPTXVectorType(MVT VT) {
51 switch (VT.SimpleTy) {
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]52 default:
53 return false;
Justin Holewinskif8f70912013-06-28 17:57:59 +0000[diff] [blame]54 case MVT::v2i1:
55 case MVT::v4i1:
Justin Holewinskibe8dc642013-02-12 14:18:49 +0000[diff] [blame]56 case MVT::v2i8:
57 case MVT::v4i8:
58 case MVT::v2i16:
59 case MVT::v4i16:
60 case MVT::v2i32:
61 case MVT::v4i32:
62 case MVT::v2i64:
63 case MVT::v2f32:
64 case MVT::v4f32:
65 case MVT::v2f64:
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]66 return true;
Justin Holewinskibe8dc642013-02-12 14:18:49 +0000[diff] [blame]67 }
68}
69
Justin Holewinskif8f70912013-06-28 17:57:59 +0000[diff] [blame]70/// ComputePTXValueVTs - For the given Type \p Ty, returns the set of primitive
71/// EVTs that compose it. Unlike ComputeValueVTs, this will break apart vectors
72/// into their primitive components.
73/// NOTE: This is a band-aid for code that expects ComputeValueVTs to return the
74/// same number of types as the Ins/Outs arrays in LowerFormalArguments,
75/// LowerCall, and LowerReturn.
76static void ComputePTXValueVTs(const TargetLowering &TLI, Type *Ty,
77 SmallVectorImpl<EVT> &ValueVTs,
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame^]78 SmallVectorImpl<uint64_t> *Offsets = nullptr,
Justin Holewinskif8f70912013-06-28 17:57:59 +0000[diff] [blame]79 uint64_t StartingOffset = 0) {
80 SmallVector<EVT, 16> TempVTs;
81 SmallVector<uint64_t, 16> TempOffsets;
82
83 ComputeValueVTs(TLI, Ty, TempVTs, &TempOffsets, StartingOffset);
84 for (unsigned i = 0, e = TempVTs.size(); i != e; ++i) {
85 EVT VT = TempVTs[i];
86 uint64_t Off = TempOffsets[i];
87 if (VT.isVector())
88 for (unsigned j = 0, je = VT.getVectorNumElements(); j != je; ++j) {
89 ValueVTs.push_back(VT.getVectorElementType());
90 if (Offsets)
91 Offsets->push_back(Off+j*VT.getVectorElementType().getStoreSize());
92 }
93 else {
94 ValueVTs.push_back(VT);
95 if (Offsets)
96 Offsets->push_back(Off);
97 }
98 }
99}
100
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]101// NVPTXTargetLowering Constructor.
102NVPTXTargetLowering::NVPTXTargetLowering(NVPTXTargetMachine &TM)
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]103 : TargetLowering(TM, new NVPTXTargetObjectFile()), nvTM(&TM),
104 nvptxSubtarget(TM.getSubtarget<NVPTXSubtarget>()) {
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]105
106 // always lower memset, memcpy, and memmove intrinsics to load/store
107 // instructions, rather
108 // then generating calls to memset, mempcy or memmove.
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]109 MaxStoresPerMemset = (unsigned) 0xFFFFFFFF;
110 MaxStoresPerMemcpy = (unsigned) 0xFFFFFFFF;
111 MaxStoresPerMemmove = (unsigned) 0xFFFFFFFF;
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]112
113 setBooleanContents(ZeroOrNegativeOneBooleanContent);
114
115 // Jump is Expensive. Don't create extra control flow for 'and', 'or'
116 // condition branches.
117 setJumpIsExpensive(true);
118
119 // By default, use the Source scheduling
120 if (sched4reg)
121 setSchedulingPreference(Sched::RegPressure);
122 else
123 setSchedulingPreference(Sched::Source);
124
125 addRegisterClass(MVT::i1, &NVPTX::Int1RegsRegClass);
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]126 addRegisterClass(MVT::i16, &NVPTX::Int16RegsRegClass);
127 addRegisterClass(MVT::i32, &NVPTX::Int32RegsRegClass);
128 addRegisterClass(MVT::i64, &NVPTX::Int64RegsRegClass);
129 addRegisterClass(MVT::f32, &NVPTX::Float32RegsRegClass);
130 addRegisterClass(MVT::f64, &NVPTX::Float64RegsRegClass);
131
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]132 // Operations not directly supported by NVPTX.
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]133 setOperationAction(ISD::SELECT_CC, MVT::Other, Expand);
134 setOperationAction(ISD::BR_CC, MVT::f32, Expand);
135 setOperationAction(ISD::BR_CC, MVT::f64, Expand);
136 setOperationAction(ISD::BR_CC, MVT::i1, Expand);
137 setOperationAction(ISD::BR_CC, MVT::i8, Expand);
138 setOperationAction(ISD::BR_CC, MVT::i16, Expand);
139 setOperationAction(ISD::BR_CC, MVT::i32, Expand);
140 setOperationAction(ISD::BR_CC, MVT::i64, Expand);
Justin Holewinski318c6252013-07-01 12:58:56 +0000[diff] [blame]141 // Some SIGN_EXTEND_INREG can be done using cvt instruction.
142 // For others we will expand to a SHL/SRA pair.
143 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i64, Legal);
144 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Legal);
145 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Legal);
146 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Legal);
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]147 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]148
149 if (nvptxSubtarget.hasROT64()) {
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]150 setOperationAction(ISD::ROTL, MVT::i64, Legal);
151 setOperationAction(ISD::ROTR, MVT::i64, Legal);
152 } else {
153 setOperationAction(ISD::ROTL, MVT::i64, Expand);
154 setOperationAction(ISD::ROTR, MVT::i64, Expand);
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]155 }
156 if (nvptxSubtarget.hasROT32()) {
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]157 setOperationAction(ISD::ROTL, MVT::i32, Legal);
158 setOperationAction(ISD::ROTR, MVT::i32, Legal);
159 } else {
160 setOperationAction(ISD::ROTL, MVT::i32, Expand);
161 setOperationAction(ISD::ROTR, MVT::i32, Expand);
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]162 }
163
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]164 setOperationAction(ISD::ROTL, MVT::i16, Expand);
165 setOperationAction(ISD::ROTR, MVT::i16, Expand);
166 setOperationAction(ISD::ROTL, MVT::i8, Expand);
167 setOperationAction(ISD::ROTR, MVT::i8, Expand);
168 setOperationAction(ISD::BSWAP, MVT::i16, Expand);
169 setOperationAction(ISD::BSWAP, MVT::i32, Expand);
170 setOperationAction(ISD::BSWAP, MVT::i64, Expand);
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]171
172 // Indirect branch is not supported.
173 // This also disables Jump Table creation.
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]174 setOperationAction(ISD::BR_JT, MVT::Other, Expand);
175 setOperationAction(ISD::BRIND, MVT::Other, Expand);
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]176
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]177 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
178 setOperationAction(ISD::GlobalAddress, MVT::i64, Custom);
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]179
180 // We want to legalize constant related memmove and memcopy
181 // intrinsics.
182 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::Other, Custom);
183
184 // Turn FP extload into load/fextend
185 setLoadExtAction(ISD::EXTLOAD, MVT::f32, Expand);
186 // Turn FP truncstore into trunc + store.
187 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
188
189 // PTX does not support load / store predicate registers
Justin Holewinskic6462aa2012-11-14 19:19:16 +0000[diff] [blame]190 setOperationAction(ISD::LOAD, MVT::i1, Custom);
191 setOperationAction(ISD::STORE, MVT::i1, Custom);
192
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]193 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
194 setLoadExtAction(ISD::ZEXTLOAD, MVT::i1, Promote);
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]195 setTruncStoreAction(MVT::i64, MVT::i1, Expand);
196 setTruncStoreAction(MVT::i32, MVT::i1, Expand);
197 setTruncStoreAction(MVT::i16, MVT::i1, Expand);
198 setTruncStoreAction(MVT::i8, MVT::i1, Expand);
199
200 // This is legal in NVPTX
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]201 setOperationAction(ISD::ConstantFP, MVT::f64, Legal);
202 setOperationAction(ISD::ConstantFP, MVT::f32, Legal);
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]203
204 // TRAP can be lowered to PTX trap
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]205 setOperationAction(ISD::TRAP, MVT::Other, Legal);
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]206
Justin Holewinski51cb1342013-07-01 12:59:04 +0000[diff] [blame]207 setOperationAction(ISD::ADDC, MVT::i64, Expand);
208 setOperationAction(ISD::ADDE, MVT::i64, Expand);
209
Justin Holewinskibe8dc642013-02-12 14:18:49 +0000[diff] [blame]210 // Register custom handling for vector loads/stores
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]211 for (int i = MVT::FIRST_VECTOR_VALUETYPE; i <= MVT::LAST_VECTOR_VALUETYPE;
212 ++i) {
213 MVT VT = (MVT::SimpleValueType) i;
Justin Holewinskibe8dc642013-02-12 14:18:49 +0000[diff] [blame]214 if (IsPTXVectorType(VT)) {
215 setOperationAction(ISD::LOAD, VT, Custom);
216 setOperationAction(ISD::STORE, VT, Custom);
217 setOperationAction(ISD::INTRINSIC_W_CHAIN, VT, Custom);
218 }
219 }
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]220
Justin Holewinskif8f70912013-06-28 17:57:59 +0000[diff] [blame]221 // Custom handling for i8 intrinsics
222 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::i8, Custom);
223
Justin Holewinskidc372df2013-06-28 17:58:07 +0000[diff] [blame]224 setOperationAction(ISD::CTLZ, MVT::i16, Legal);
225 setOperationAction(ISD::CTLZ, MVT::i32, Legal);
226 setOperationAction(ISD::CTLZ, MVT::i64, Legal);
227 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i16, Legal);
228 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32, Legal);
229 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Legal);
230 setOperationAction(ISD::CTTZ, MVT::i16, Expand);
231 setOperationAction(ISD::CTTZ, MVT::i32, Expand);
232 setOperationAction(ISD::CTTZ, MVT::i64, Expand);
233 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i16, Expand);
234 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32, Expand);
235 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i64, Expand);
236 setOperationAction(ISD::CTPOP, MVT::i16, Legal);
237 setOperationAction(ISD::CTPOP, MVT::i32, Legal);
238 setOperationAction(ISD::CTPOP, MVT::i64, Legal);
239
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]240 // Now deduce the information based on the above mentioned
241 // actions
242 computeRegisterProperties();
243}
244
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]245const char *NVPTXTargetLowering::getTargetNodeName(unsigned Opcode) const {
246 switch (Opcode) {
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]247 default:
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame^]248 return nullptr;
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]249 case NVPTXISD::CALL:
250 return "NVPTXISD::CALL";
251 case NVPTXISD::RET_FLAG:
252 return "NVPTXISD::RET_FLAG";
253 case NVPTXISD::Wrapper:
254 return "NVPTXISD::Wrapper";
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]255 case NVPTXISD::DeclareParam:
256 return "NVPTXISD::DeclareParam";
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]257 case NVPTXISD::DeclareScalarParam:
258 return "NVPTXISD::DeclareScalarParam";
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]259 case NVPTXISD::DeclareRet:
260 return "NVPTXISD::DeclareRet";
261 case NVPTXISD::DeclareRetParam:
262 return "NVPTXISD::DeclareRetParam";
263 case NVPTXISD::PrintCall:
264 return "NVPTXISD::PrintCall";
265 case NVPTXISD::LoadParam:
266 return "NVPTXISD::LoadParam";
Justin Holewinskife44314f2013-06-28 17:57:51 +0000[diff] [blame]267 case NVPTXISD::LoadParamV2:
268 return "NVPTXISD::LoadParamV2";
269 case NVPTXISD::LoadParamV4:
270 return "NVPTXISD::LoadParamV4";
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]271 case NVPTXISD::StoreParam:
272 return "NVPTXISD::StoreParam";
Justin Holewinskife44314f2013-06-28 17:57:51 +0000[diff] [blame]273 case NVPTXISD::StoreParamV2:
274 return "NVPTXISD::StoreParamV2";
275 case NVPTXISD::StoreParamV4:
276 return "NVPTXISD::StoreParamV4";
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]277 case NVPTXISD::StoreParamS32:
278 return "NVPTXISD::StoreParamS32";
279 case NVPTXISD::StoreParamU32:
280 return "NVPTXISD::StoreParamU32";
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]281 case NVPTXISD::CallArgBegin:
282 return "NVPTXISD::CallArgBegin";
283 case NVPTXISD::CallArg:
284 return "NVPTXISD::CallArg";
285 case NVPTXISD::LastCallArg:
286 return "NVPTXISD::LastCallArg";
287 case NVPTXISD::CallArgEnd:
288 return "NVPTXISD::CallArgEnd";
289 case NVPTXISD::CallVoid:
290 return "NVPTXISD::CallVoid";
291 case NVPTXISD::CallVal:
292 return "NVPTXISD::CallVal";
293 case NVPTXISD::CallSymbol:
294 return "NVPTXISD::CallSymbol";
295 case NVPTXISD::Prototype:
296 return "NVPTXISD::Prototype";
297 case NVPTXISD::MoveParam:
298 return "NVPTXISD::MoveParam";
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]299 case NVPTXISD::StoreRetval:
300 return "NVPTXISD::StoreRetval";
Justin Holewinskife44314f2013-06-28 17:57:51 +0000[diff] [blame]301 case NVPTXISD::StoreRetvalV2:
302 return "NVPTXISD::StoreRetvalV2";
303 case NVPTXISD::StoreRetvalV4:
304 return "NVPTXISD::StoreRetvalV4";
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]305 case NVPTXISD::PseudoUseParam:
306 return "NVPTXISD::PseudoUseParam";
307 case NVPTXISD::RETURN:
308 return "NVPTXISD::RETURN";
309 case NVPTXISD::CallSeqBegin:
310 return "NVPTXISD::CallSeqBegin";
311 case NVPTXISD::CallSeqEnd:
312 return "NVPTXISD::CallSeqEnd";
Justin Holewinski3d49e5c2013-11-15 12:30:04 +0000[diff] [blame]313 case NVPTXISD::CallPrototype:
314 return "NVPTXISD::CallPrototype";
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]315 case NVPTXISD::LoadV2:
316 return "NVPTXISD::LoadV2";
317 case NVPTXISD::LoadV4:
318 return "NVPTXISD::LoadV4";
319 case NVPTXISD::LDGV2:
320 return "NVPTXISD::LDGV2";
321 case NVPTXISD::LDGV4:
322 return "NVPTXISD::LDGV4";
323 case NVPTXISD::LDUV2:
324 return "NVPTXISD::LDUV2";
325 case NVPTXISD::LDUV4:
326 return "NVPTXISD::LDUV4";
327 case NVPTXISD::StoreV2:
328 return "NVPTXISD::StoreV2";
329 case NVPTXISD::StoreV4:
330 return "NVPTXISD::StoreV4";
Justin Holewinski30d56a72014-04-09 15:39:15 +0000[diff] [blame]331 case NVPTXISD::Tex1DFloatI32: return "NVPTXISD::Tex1DFloatI32";
332 case NVPTXISD::Tex1DFloatFloat: return "NVPTXISD::Tex1DFloatFloat";
333 case NVPTXISD::Tex1DFloatFloatLevel:
334 return "NVPTXISD::Tex1DFloatFloatLevel";
335 case NVPTXISD::Tex1DFloatFloatGrad:
336 return "NVPTXISD::Tex1DFloatFloatGrad";
337 case NVPTXISD::Tex1DI32I32: return "NVPTXISD::Tex1DI32I32";
338 case NVPTXISD::Tex1DI32Float: return "NVPTXISD::Tex1DI32Float";
339 case NVPTXISD::Tex1DI32FloatLevel:
340 return "NVPTXISD::Tex1DI32FloatLevel";
341 case NVPTXISD::Tex1DI32FloatGrad:
342 return "NVPTXISD::Tex1DI32FloatGrad";
343 case NVPTXISD::Tex1DArrayFloatI32: return "NVPTXISD::Tex2DArrayFloatI32";
344 case NVPTXISD::Tex1DArrayFloatFloat: return "NVPTXISD::Tex2DArrayFloatFloat";
345 case NVPTXISD::Tex1DArrayFloatFloatLevel:
346 return "NVPTXISD::Tex2DArrayFloatFloatLevel";
347 case NVPTXISD::Tex1DArrayFloatFloatGrad:
348 return "NVPTXISD::Tex2DArrayFloatFloatGrad";
349 case NVPTXISD::Tex1DArrayI32I32: return "NVPTXISD::Tex2DArrayI32I32";
350 case NVPTXISD::Tex1DArrayI32Float: return "NVPTXISD::Tex2DArrayI32Float";
351 case NVPTXISD::Tex1DArrayI32FloatLevel:
352 return "NVPTXISD::Tex2DArrayI32FloatLevel";
353 case NVPTXISD::Tex1DArrayI32FloatGrad:
354 return "NVPTXISD::Tex2DArrayI32FloatGrad";
355 case NVPTXISD::Tex2DFloatI32: return "NVPTXISD::Tex2DFloatI32";
356 case NVPTXISD::Tex2DFloatFloat: return "NVPTXISD::Tex2DFloatFloat";
357 case NVPTXISD::Tex2DFloatFloatLevel:
358 return "NVPTXISD::Tex2DFloatFloatLevel";
359 case NVPTXISD::Tex2DFloatFloatGrad:
360 return "NVPTXISD::Tex2DFloatFloatGrad";
361 case NVPTXISD::Tex2DI32I32: return "NVPTXISD::Tex2DI32I32";
362 case NVPTXISD::Tex2DI32Float: return "NVPTXISD::Tex2DI32Float";
363 case NVPTXISD::Tex2DI32FloatLevel:
364 return "NVPTXISD::Tex2DI32FloatLevel";
365 case NVPTXISD::Tex2DI32FloatGrad:
366 return "NVPTXISD::Tex2DI32FloatGrad";
367 case NVPTXISD::Tex2DArrayFloatI32: return "NVPTXISD::Tex2DArrayFloatI32";
368 case NVPTXISD::Tex2DArrayFloatFloat: return "NVPTXISD::Tex2DArrayFloatFloat";
369 case NVPTXISD::Tex2DArrayFloatFloatLevel:
370 return "NVPTXISD::Tex2DArrayFloatFloatLevel";
371 case NVPTXISD::Tex2DArrayFloatFloatGrad:
372 return "NVPTXISD::Tex2DArrayFloatFloatGrad";
373 case NVPTXISD::Tex2DArrayI32I32: return "NVPTXISD::Tex2DArrayI32I32";
374 case NVPTXISD::Tex2DArrayI32Float: return "NVPTXISD::Tex2DArrayI32Float";
375 case NVPTXISD::Tex2DArrayI32FloatLevel:
376 return "NVPTXISD::Tex2DArrayI32FloatLevel";
377 case NVPTXISD::Tex2DArrayI32FloatGrad:
378 return "NVPTXISD::Tex2DArrayI32FloatGrad";
379 case NVPTXISD::Tex3DFloatI32: return "NVPTXISD::Tex3DFloatI32";
380 case NVPTXISD::Tex3DFloatFloat: return "NVPTXISD::Tex3DFloatFloat";
381 case NVPTXISD::Tex3DFloatFloatLevel:
382 return "NVPTXISD::Tex3DFloatFloatLevel";
383 case NVPTXISD::Tex3DFloatFloatGrad:
384 return "NVPTXISD::Tex3DFloatFloatGrad";
385 case NVPTXISD::Tex3DI32I32: return "NVPTXISD::Tex3DI32I32";
386 case NVPTXISD::Tex3DI32Float: return "NVPTXISD::Tex3DI32Float";
387 case NVPTXISD::Tex3DI32FloatLevel:
388 return "NVPTXISD::Tex3DI32FloatLevel";
389 case NVPTXISD::Tex3DI32FloatGrad:
390 return "NVPTXISD::Tex3DI32FloatGrad";
391
392 case NVPTXISD::Suld1DI8Trap: return "NVPTXISD::Suld1DI8Trap";
393 case NVPTXISD::Suld1DI16Trap: return "NVPTXISD::Suld1DI16Trap";
394 case NVPTXISD::Suld1DI32Trap: return "NVPTXISD::Suld1DI32Trap";
395 case NVPTXISD::Suld1DV2I8Trap: return "NVPTXISD::Suld1DV2I8Trap";
396 case NVPTXISD::Suld1DV2I16Trap: return "NVPTXISD::Suld1DV2I16Trap";
397 case NVPTXISD::Suld1DV2I32Trap: return "NVPTXISD::Suld1DV2I32Trap";
398 case NVPTXISD::Suld1DV4I8Trap: return "NVPTXISD::Suld1DV4I8Trap";
399 case NVPTXISD::Suld1DV4I16Trap: return "NVPTXISD::Suld1DV4I16Trap";
400 case NVPTXISD::Suld1DV4I32Trap: return "NVPTXISD::Suld1DV4I32Trap";
401
402 case NVPTXISD::Suld1DArrayI8Trap: return "NVPTXISD::Suld1DArrayI8Trap";
403 case NVPTXISD::Suld1DArrayI16Trap: return "NVPTXISD::Suld1DArrayI16Trap";
404 case NVPTXISD::Suld1DArrayI32Trap: return "NVPTXISD::Suld1DArrayI32Trap";
405 case NVPTXISD::Suld1DArrayV2I8Trap: return "NVPTXISD::Suld1DArrayV2I8Trap";
406 case NVPTXISD::Suld1DArrayV2I16Trap: return "NVPTXISD::Suld1DArrayV2I16Trap";
407 case NVPTXISD::Suld1DArrayV2I32Trap: return "NVPTXISD::Suld1DArrayV2I32Trap";
408 case NVPTXISD::Suld1DArrayV4I8Trap: return "NVPTXISD::Suld1DArrayV4I8Trap";
409 case NVPTXISD::Suld1DArrayV4I16Trap: return "NVPTXISD::Suld1DArrayV4I16Trap";
410 case NVPTXISD::Suld1DArrayV4I32Trap: return "NVPTXISD::Suld1DArrayV4I32Trap";
411
412 case NVPTXISD::Suld2DI8Trap: return "NVPTXISD::Suld2DI8Trap";
413 case NVPTXISD::Suld2DI16Trap: return "NVPTXISD::Suld2DI16Trap";
414 case NVPTXISD::Suld2DI32Trap: return "NVPTXISD::Suld2DI32Trap";
415 case NVPTXISD::Suld2DV2I8Trap: return "NVPTXISD::Suld2DV2I8Trap";
416 case NVPTXISD::Suld2DV2I16Trap: return "NVPTXISD::Suld2DV2I16Trap";
417 case NVPTXISD::Suld2DV2I32Trap: return "NVPTXISD::Suld2DV2I32Trap";
418 case NVPTXISD::Suld2DV4I8Trap: return "NVPTXISD::Suld2DV4I8Trap";
419 case NVPTXISD::Suld2DV4I16Trap: return "NVPTXISD::Suld2DV4I16Trap";
420 case NVPTXISD::Suld2DV4I32Trap: return "NVPTXISD::Suld2DV4I32Trap";
421
422 case NVPTXISD::Suld2DArrayI8Trap: return "NVPTXISD::Suld2DArrayI8Trap";
423 case NVPTXISD::Suld2DArrayI16Trap: return "NVPTXISD::Suld2DArrayI16Trap";
424 case NVPTXISD::Suld2DArrayI32Trap: return "NVPTXISD::Suld2DArrayI32Trap";
425 case NVPTXISD::Suld2DArrayV2I8Trap: return "NVPTXISD::Suld2DArrayV2I8Trap";
426 case NVPTXISD::Suld2DArrayV2I16Trap: return "NVPTXISD::Suld2DArrayV2I16Trap";
427 case NVPTXISD::Suld2DArrayV2I32Trap: return "NVPTXISD::Suld2DArrayV2I32Trap";
428 case NVPTXISD::Suld2DArrayV4I8Trap: return "NVPTXISD::Suld2DArrayV4I8Trap";
429 case NVPTXISD::Suld2DArrayV4I16Trap: return "NVPTXISD::Suld2DArrayV4I16Trap";
430 case NVPTXISD::Suld2DArrayV4I32Trap: return "NVPTXISD::Suld2DArrayV4I32Trap";
431
432 case NVPTXISD::Suld3DI8Trap: return "NVPTXISD::Suld3DI8Trap";
433 case NVPTXISD::Suld3DI16Trap: return "NVPTXISD::Suld3DI16Trap";
434 case NVPTXISD::Suld3DI32Trap: return "NVPTXISD::Suld3DI32Trap";
435 case NVPTXISD::Suld3DV2I8Trap: return "NVPTXISD::Suld3DV2I8Trap";
436 case NVPTXISD::Suld3DV2I16Trap: return "NVPTXISD::Suld3DV2I16Trap";
437 case NVPTXISD::Suld3DV2I32Trap: return "NVPTXISD::Suld3DV2I32Trap";
438 case NVPTXISD::Suld3DV4I8Trap: return "NVPTXISD::Suld3DV4I8Trap";
439 case NVPTXISD::Suld3DV4I16Trap: return "NVPTXISD::Suld3DV4I16Trap";
440 case NVPTXISD::Suld3DV4I32Trap: return "NVPTXISD::Suld3DV4I32Trap";
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]441 }
442}
443
Matt Arsenaultf751d622014-03-31 20:54:58 +0000[diff] [blame]444bool NVPTXTargetLowering::shouldSplitVectorType(EVT VT) const {
445 return VT.getScalarType() == MVT::i1;
Justin Holewinskibc451192012-11-29 14:26:24 +0000[diff] [blame]446}
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]447
448SDValue
449NVPTXTargetLowering::LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const {
Andrew Trickef9de2a2013-05-25 02:42:55 +0000[diff] [blame]450 SDLoc dl(Op);
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]451 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
452 Op = DAG.getTargetGlobalAddress(GV, dl, getPointerTy());
453 return DAG.getNode(NVPTXISD::Wrapper, dl, getPointerTy(), Op);
454}
455
Justin Holewinskif8f70912013-06-28 17:57:59 +0000[diff] [blame]456std::string
457NVPTXTargetLowering::getPrototype(Type *retTy, const ArgListTy &Args,
458 const SmallVectorImpl<ISD::OutputArg> &Outs,
459 unsigned retAlignment,
460 const ImmutableCallSite *CS) const {
461
462 bool isABI = (nvptxSubtarget.getSmVersion() >= 20);
463 assert(isABI && "Non-ABI compilation is not supported");
464 if (!isABI)
465 return "";
466
467 std::stringstream O;
468 O << "prototype_" << uniqueCallSite << " : .callprototype ";
469
470 if (retTy->getTypeID() == Type::VoidTyID) {
471 O << "()";
472 } else {
473 O << "(";
Rafael Espindola08013342013-12-07 19:34:20 +0000[diff] [blame]474 if (retTy->isFloatingPointTy() || retTy->isIntegerTy()) {
Justin Holewinskif8f70912013-06-28 17:57:59 +0000[diff] [blame]475 unsigned size = 0;
476 if (const IntegerType *ITy = dyn_cast<IntegerType>(retTy)) {
477 size = ITy->getBitWidth();
478 if (size < 32)
479 size = 32;
480 } else {
481 assert(retTy->isFloatingPointTy() &&
482 "Floating point type expected here");
483 size = retTy->getPrimitiveSizeInBits();
484 }
485
486 O << ".param .b" << size << " _";
487 } else if (isa<PointerType>(retTy)) {
488 O << ".param .b" << getPointerTy().getSizeInBits() << " _";
489 } else {
490 if ((retTy->getTypeID() == Type::StructTyID) || isa<VectorType>(retTy)) {
491 SmallVector<EVT, 16> vtparts;
492 ComputeValueVTs(*this, retTy, vtparts);
493 unsigned totalsz = 0;
494 for (unsigned i = 0, e = vtparts.size(); i != e; ++i) {
495 unsigned elems = 1;
496 EVT elemtype = vtparts[i];
497 if (vtparts[i].isVector()) {
498 elems = vtparts[i].getVectorNumElements();
499 elemtype = vtparts[i].getVectorElementType();
500 }
501 // TODO: no need to loop
502 for (unsigned j = 0, je = elems; j != je; ++j) {
503 unsigned sz = elemtype.getSizeInBits();
504 if (elemtype.isInteger() && (sz < 8))
505 sz = 8;
506 totalsz += sz / 8;
507 }
508 }
509 O << ".param .align " << retAlignment << " .b8 _[" << totalsz << "]";
510 } else {
511 assert(false && "Unknown return type");
512 }
513 }
514 O << ") ";
515 }
516 O << "_ (";
517
518 bool first = true;
519 MVT thePointerTy = getPointerTy();
520
521 unsigned OIdx = 0;
522 for (unsigned i = 0, e = Args.size(); i != e; ++i, ++OIdx) {
523 Type *Ty = Args[i].Ty;
524 if (!first) {
525 O << ", ";
526 }
527 first = false;
528
529 if (Outs[OIdx].Flags.isByVal() == false) {
530 if (Ty->isAggregateType() || Ty->isVectorTy()) {
531 unsigned align = 0;
532 const CallInst *CallI = cast<CallInst>(CS->getInstruction());
533 const DataLayout *TD = getDataLayout();
534 // +1 because index 0 is reserved for return type alignment
535 if (!llvm::getAlign(*CallI, i + 1, align))
536 align = TD->getABITypeAlignment(Ty);
537 unsigned sz = TD->getTypeAllocSize(Ty);
538 O << ".param .align " << align << " .b8 ";
539 O << "_";
540 O << "[" << sz << "]";
541 // update the index for Outs
542 SmallVector<EVT, 16> vtparts;
543 ComputeValueVTs(*this, Ty, vtparts);
544 if (unsigned len = vtparts.size())
545 OIdx += len - 1;
546 continue;
547 }
Justin Holewinskidff28d22013-07-01 12:59:01 +0000[diff] [blame]548 // i8 types in IR will be i16 types in SDAG
549 assert((getValueType(Ty) == Outs[OIdx].VT ||
550 (getValueType(Ty) == MVT::i8 && Outs[OIdx].VT == MVT::i16)) &&
Justin Holewinskif8f70912013-06-28 17:57:59 +0000[diff] [blame]551 "type mismatch between callee prototype and arguments");
552 // scalar type
553 unsigned sz = 0;
554 if (isa<IntegerType>(Ty)) {
555 sz = cast<IntegerType>(Ty)->getBitWidth();
556 if (sz < 32)
557 sz = 32;
558 } else if (isa<PointerType>(Ty))
559 sz = thePointerTy.getSizeInBits();
560 else
561 sz = Ty->getPrimitiveSizeInBits();
562 O << ".param .b" << sz << " ";
563 O << "_";
564 continue;
565 }
566 const PointerType *PTy = dyn_cast<PointerType>(Ty);
567 assert(PTy && "Param with byval attribute should be a pointer type");
568 Type *ETy = PTy->getElementType();
569
570 unsigned align = Outs[OIdx].Flags.getByValAlign();
571 unsigned sz = getDataLayout()->getTypeAllocSize(ETy);
572 O << ".param .align " << align << " .b8 ";
573 O << "_";
574 O << "[" << sz << "]";
575 }
576 O << ");";
577 return O.str();
578}
579
580unsigned
581NVPTXTargetLowering::getArgumentAlignment(SDValue Callee,
582 const ImmutableCallSite *CS,
583 Type *Ty,
584 unsigned Idx) const {
585 const DataLayout *TD = getDataLayout();
Justin Holewinski124e93d2013-11-11 19:28:19 +0000[diff] [blame]586 unsigned Align = 0;
587 const Value *DirectCallee = CS->getCalledFunction();
Justin Holewinskif8f70912013-06-28 17:57:59 +0000[diff] [blame]588
Justin Holewinski124e93d2013-11-11 19:28:19 +0000[diff] [blame]589 if (!DirectCallee) {
590 // We don't have a direct function symbol, but that may be because of
591 // constant cast instructions in the call.
592 const Instruction *CalleeI = CS->getInstruction();
593 assert(CalleeI && "Call target is not a function or derived value?");
594
595 // With bitcast'd call targets, the instruction will be the call
596 if (isa<CallInst>(CalleeI)) {
597 // Check if we have call alignment metadata
598 if (llvm::getAlign(*cast<CallInst>(CalleeI), Idx, Align))
599 return Align;
600
601 const Value *CalleeV = cast<CallInst>(CalleeI)->getCalledValue();
602 // Ignore any bitcast instructions
603 while(isa<ConstantExpr>(CalleeV)) {
604 const ConstantExpr *CE = cast<ConstantExpr>(CalleeV);
605 if (!CE->isCast())
606 break;
607 // Look through the bitcast
608 CalleeV = cast<ConstantExpr>(CalleeV)->getOperand(0);
609 }
610
611 // We have now looked past all of the bitcasts. Do we finally have a
612 // Function?
613 if (isa<Function>(CalleeV))
614 DirectCallee = CalleeV;
615 }
Justin Holewinskif8f70912013-06-28 17:57:59 +0000[diff] [blame]616 }
617
Justin Holewinski124e93d2013-11-11 19:28:19 +0000[diff] [blame]618 // Check for function alignment information if we found that the
619 // ultimate target is a Function
620 if (DirectCallee)
621 if (llvm::getAlign(*cast<Function>(DirectCallee), Idx, Align))
622 return Align;
623
624 // Call is indirect or alignment information is not available, fall back to
625 // the ABI type alignment
626 return TD->getABITypeAlignment(Ty);
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]627}
628
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]629SDValue NVPTXTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
630 SmallVectorImpl<SDValue> &InVals) const {
631 SelectionDAG &DAG = CLI.DAG;
Andrew Trickef9de2a2013-05-25 02:42:55 +0000[diff] [blame]632 SDLoc dl = CLI.DL;
Craig Topperb94011f2013-07-14 04:42:23 +0000[diff] [blame]633 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
634 SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;
635 SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins;
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]636 SDValue Chain = CLI.Chain;
637 SDValue Callee = CLI.Callee;
638 bool &isTailCall = CLI.IsTailCall;
639 ArgListTy &Args = CLI.Args;
640 Type *retTy = CLI.RetTy;
641 ImmutableCallSite *CS = CLI.CS;
Justin Holewinskiaa583972012-05-25 16:35:28 +0000[diff] [blame]642
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]643 bool isABI = (nvptxSubtarget.getSmVersion() >= 20);
Justin Holewinskif8f70912013-06-28 17:57:59 +0000[diff] [blame]644 assert(isABI && "Non-ABI compilation is not supported");
645 if (!isABI)
646 return Chain;
647 const DataLayout *TD = getDataLayout();
648 MachineFunction &MF = DAG.getMachineFunction();
649 const Function *F = MF.getFunction();
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]650
651 SDValue tempChain = Chain;
Justin Holewinskif8f70912013-06-28 17:57:59 +0000[diff] [blame]652 Chain =
653 DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(uniqueCallSite, true),
654 dl);
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]655 SDValue InFlag = Chain.getValue(1);
656
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]657 unsigned paramCount = 0;
Justin Holewinskif8f70912013-06-28 17:57:59 +0000[diff] [blame]658 // Args.size() and Outs.size() need not match.
659 // Outs.size() will be larger
660 // * if there is an aggregate argument with multiple fields (each field
661 // showing up separately in Outs)
662 // * if there is a vector argument with more than typical vector-length
663 // elements (generally if more than 4) where each vector element is
664 // individually present in Outs.
665 // So a different index should be used for indexing into Outs/OutVals.
666 // See similar issue in LowerFormalArguments.
667 unsigned OIdx = 0;
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]668 // Declare the .params or .reg need to pass values
669 // to the function
Justin Holewinskif8f70912013-06-28 17:57:59 +0000[diff] [blame]670 for (unsigned i = 0, e = Args.size(); i != e; ++i, ++OIdx) {
671 EVT VT = Outs[OIdx].VT;
672 Type *Ty = Args[i].Ty;
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]673
Justin Holewinskif8f70912013-06-28 17:57:59 +0000[diff] [blame]674 if (Outs[OIdx].Flags.isByVal() == false) {
675 if (Ty->isAggregateType()) {
676 // aggregate
677 SmallVector<EVT, 16> vtparts;
678 ComputeValueVTs(*this, Ty, vtparts);
679
680 unsigned align = getArgumentAlignment(Callee, CS, Ty, paramCount + 1);
681 // declare .param .align <align> .b8 .param<n>[<size>];
682 unsigned sz = TD->getTypeAllocSize(Ty);
683 SDVTList DeclareParamVTs = DAG.getVTList(MVT::Other, MVT::Glue);
684 SDValue DeclareParamOps[] = { Chain, DAG.getConstant(align, MVT::i32),
685 DAG.getConstant(paramCount, MVT::i32),
686 DAG.getConstant(sz, MVT::i32), InFlag };
687 Chain = DAG.getNode(NVPTXISD::DeclareParam, dl, DeclareParamVTs,
688 DeclareParamOps, 5);
689 InFlag = Chain.getValue(1);
690 unsigned curOffset = 0;
691 for (unsigned j = 0, je = vtparts.size(); j != je; ++j) {
692 unsigned elems = 1;
693 EVT elemtype = vtparts[j];
694 if (vtparts[j].isVector()) {
695 elems = vtparts[j].getVectorNumElements();
696 elemtype = vtparts[j].getVectorElementType();
697 }
698 for (unsigned k = 0, ke = elems; k != ke; ++k) {
699 unsigned sz = elemtype.getSizeInBits();
700 if (elemtype.isInteger() && (sz < 8))
701 sz = 8;
702 SDValue StVal = OutVals[OIdx];
703 if (elemtype.getSizeInBits() < 16) {
Justin Holewinskia2911282013-07-01 12:58:58 +0000[diff] [blame]704 StVal = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i16, StVal);
Justin Holewinskif8f70912013-06-28 17:57:59 +0000[diff] [blame]705 }
706 SDVTList CopyParamVTs = DAG.getVTList(MVT::Other, MVT::Glue);
707 SDValue CopyParamOps[] = { Chain,
708 DAG.getConstant(paramCount, MVT::i32),
709 DAG.getConstant(curOffset, MVT::i32),
710 StVal, InFlag };
711 Chain = DAG.getMemIntrinsicNode(NVPTXISD::StoreParam, dl,
712 CopyParamVTs, &CopyParamOps[0], 5,
713 elemtype, MachinePointerInfo());
714 InFlag = Chain.getValue(1);
715 curOffset += sz / 8;
716 ++OIdx;
717 }
718 }
719 if (vtparts.size() > 0)
720 --OIdx;
721 ++paramCount;
722 continue;
723 }
724 if (Ty->isVectorTy()) {
725 EVT ObjectVT = getValueType(Ty);
726 unsigned align = getArgumentAlignment(Callee, CS, Ty, paramCount + 1);
727 // declare .param .align <align> .b8 .param<n>[<size>];
728 unsigned sz = TD->getTypeAllocSize(Ty);
729 SDVTList DeclareParamVTs = DAG.getVTList(MVT::Other, MVT::Glue);
730 SDValue DeclareParamOps[] = { Chain, DAG.getConstant(align, MVT::i32),
731 DAG.getConstant(paramCount, MVT::i32),
732 DAG.getConstant(sz, MVT::i32), InFlag };
733 Chain = DAG.getNode(NVPTXISD::DeclareParam, dl, DeclareParamVTs,
734 DeclareParamOps, 5);
735 InFlag = Chain.getValue(1);
736 unsigned NumElts = ObjectVT.getVectorNumElements();
737 EVT EltVT = ObjectVT.getVectorElementType();
738 EVT MemVT = EltVT;
739 bool NeedExtend = false;
740 if (EltVT.getSizeInBits() < 16) {
741 NeedExtend = true;
742 EltVT = MVT::i16;
743 }
744
745 // V1 store
746 if (NumElts == 1) {
747 SDValue Elt = OutVals[OIdx++];
748 if (NeedExtend)
749 Elt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, Elt);
750
751 SDVTList CopyParamVTs = DAG.getVTList(MVT::Other, MVT::Glue);
752 SDValue CopyParamOps[] = { Chain,
753 DAG.getConstant(paramCount, MVT::i32),
754 DAG.getConstant(0, MVT::i32), Elt,
755 InFlag };
756 Chain = DAG.getMemIntrinsicNode(NVPTXISD::StoreParam, dl,
757 CopyParamVTs, &CopyParamOps[0], 5,
758 MemVT, MachinePointerInfo());
759 InFlag = Chain.getValue(1);
760 } else if (NumElts == 2) {
761 SDValue Elt0 = OutVals[OIdx++];
762 SDValue Elt1 = OutVals[OIdx++];
763 if (NeedExtend) {
764 Elt0 = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, Elt0);
765 Elt1 = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, Elt1);
766 }
767
768 SDVTList CopyParamVTs = DAG.getVTList(MVT::Other, MVT::Glue);
769 SDValue CopyParamOps[] = { Chain,
770 DAG.getConstant(paramCount, MVT::i32),
771 DAG.getConstant(0, MVT::i32), Elt0, Elt1,
772 InFlag };
773 Chain = DAG.getMemIntrinsicNode(NVPTXISD::StoreParamV2, dl,
774 CopyParamVTs, &CopyParamOps[0], 6,
775 MemVT, MachinePointerInfo());
776 InFlag = Chain.getValue(1);
777 } else {
778 unsigned curOffset = 0;
779 // V4 stores
780 // We have at least 4 elements (<3 x Ty> expands to 4 elements) and
781 // the
782 // vector will be expanded to a power of 2 elements, so we know we can
783 // always round up to the next multiple of 4 when creating the vector
784 // stores.
785 // e.g. 4 elem => 1 st.v4
786 // 6 elem => 2 st.v4
787 // 8 elem => 2 st.v4
788 // 11 elem => 3 st.v4
789 unsigned VecSize = 4;
790 if (EltVT.getSizeInBits() == 64)
791 VecSize = 2;
792
793 // This is potentially only part of a vector, so assume all elements
794 // are packed together.
795 unsigned PerStoreOffset = MemVT.getStoreSizeInBits() / 8 * VecSize;
796
797 for (unsigned i = 0; i < NumElts; i += VecSize) {
798 // Get values
799 SDValue StoreVal;
800 SmallVector<SDValue, 8> Ops;
801 Ops.push_back(Chain);
802 Ops.push_back(DAG.getConstant(paramCount, MVT::i32));
803 Ops.push_back(DAG.getConstant(curOffset, MVT::i32));
804
805 unsigned Opc = NVPTXISD::StoreParamV2;
806
807 StoreVal = OutVals[OIdx++];
808 if (NeedExtend)
809 StoreVal = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, StoreVal);
810 Ops.push_back(StoreVal);
811
812 if (i + 1 < NumElts) {
813 StoreVal = OutVals[OIdx++];
814 if (NeedExtend)
815 StoreVal =
816 DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, StoreVal);
817 } else {
818 StoreVal = DAG.getUNDEF(EltVT);
819 }
820 Ops.push_back(StoreVal);
821
822 if (VecSize == 4) {
823 Opc = NVPTXISD::StoreParamV4;
824 if (i + 2 < NumElts) {
825 StoreVal = OutVals[OIdx++];
826 if (NeedExtend)
827 StoreVal =
828 DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, StoreVal);
829 } else {
830 StoreVal = DAG.getUNDEF(EltVT);
831 }
832 Ops.push_back(StoreVal);
833
834 if (i + 3 < NumElts) {
835 StoreVal = OutVals[OIdx++];
836 if (NeedExtend)
837 StoreVal =
838 DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, StoreVal);
839 } else {
840 StoreVal = DAG.getUNDEF(EltVT);
841 }
842 Ops.push_back(StoreVal);
843 }
844
Justin Holewinskidff28d22013-07-01 12:59:01 +0000[diff] [blame]845 Ops.push_back(InFlag);
846
Justin Holewinskif8f70912013-06-28 17:57:59 +0000[diff] [blame]847 SDVTList CopyParamVTs = DAG.getVTList(MVT::Other, MVT::Glue);
848 Chain = DAG.getMemIntrinsicNode(Opc, dl, CopyParamVTs, &Ops[0],
849 Ops.size(), MemVT,
850 MachinePointerInfo());
851 InFlag = Chain.getValue(1);
852 curOffset += PerStoreOffset;
853 }
854 }
855 ++paramCount;
856 --OIdx;
857 continue;
858 }
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]859 // Plain scalar
860 // for ABI, declare .param .b<size> .param<n>;
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]861 unsigned sz = VT.getSizeInBits();
Justin Holewinskif8f70912013-06-28 17:57:59 +0000[diff] [blame]862 bool needExtend = false;
863 if (VT.isInteger()) {
864 if (sz < 16)
865 needExtend = true;
866 if (sz < 32)
867 sz = 32;
868 }
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]869 SDVTList DeclareParamVTs = DAG.getVTList(MVT::Other, MVT::Glue);
870 SDValue DeclareParamOps[] = { Chain,
871 DAG.getConstant(paramCount, MVT::i32),
872 DAG.getConstant(sz, MVT::i32),
Justin Holewinskif8f70912013-06-28 17:57:59 +0000[diff] [blame]873 DAG.getConstant(0, MVT::i32), InFlag };
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]874 Chain = DAG.getNode(NVPTXISD::DeclareScalarParam, dl, DeclareParamVTs,
875 DeclareParamOps, 5);
876 InFlag = Chain.getValue(1);
Justin Holewinskif8f70912013-06-28 17:57:59 +0000[diff] [blame]877 SDValue OutV = OutVals[OIdx];
878 if (needExtend) {
879 // zext/sext i1 to i16
880 unsigned opc = ISD::ZERO_EXTEND;
881 if (Outs[OIdx].Flags.isSExt())
882 opc = ISD::SIGN_EXTEND;
883 OutV = DAG.getNode(opc, dl, MVT::i16, OutV);
884 }
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]885 SDVTList CopyParamVTs = DAG.getVTList(MVT::Other, MVT::Glue);
886 SDValue CopyParamOps[] = { Chain, DAG.getConstant(paramCount, MVT::i32),
Justin Holewinskif8f70912013-06-28 17:57:59 +0000[diff] [blame]887 DAG.getConstant(0, MVT::i32), OutV, InFlag };
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]888
889 unsigned opcode = NVPTXISD::StoreParam;
Justin Holewinskif8f70912013-06-28 17:57:59 +0000[diff] [blame]890 if (Outs[OIdx].Flags.isZExt())
891 opcode = NVPTXISD::StoreParamU32;
892 else if (Outs[OIdx].Flags.isSExt())
893 opcode = NVPTXISD::StoreParamS32;
894 Chain = DAG.getMemIntrinsicNode(opcode, dl, CopyParamVTs, CopyParamOps, 5,
895 VT, MachinePointerInfo());
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]896
897 InFlag = Chain.getValue(1);
898 ++paramCount;
899 continue;
900 }
901 // struct or vector
902 SmallVector<EVT, 16> vtparts;
903 const PointerType *PTy = dyn_cast<PointerType>(Args[i].Ty);
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]904 assert(PTy && "Type of a byval parameter should be pointer");
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]905 ComputeValueVTs(*this, PTy->getElementType(), vtparts);
906
Justin Holewinskif8f70912013-06-28 17:57:59 +0000[diff] [blame]907 // declare .param .align <align> .b8 .param<n>[<size>];
908 unsigned sz = Outs[OIdx].Flags.getByValSize();
909 SDVTList DeclareParamVTs = DAG.getVTList(MVT::Other, MVT::Glue);
910 // The ByValAlign in the Outs[OIdx].Flags is alway set at this point,
911 // so we don't need to worry about natural alignment or not.
912 // See TargetLowering::LowerCallTo().
913 SDValue DeclareParamOps[] = {
914 Chain, DAG.getConstant(Outs[OIdx].Flags.getByValAlign(), MVT::i32),
915 DAG.getConstant(paramCount, MVT::i32), DAG.getConstant(sz, MVT::i32),
916 InFlag
917 };
918 Chain = DAG.getNode(NVPTXISD::DeclareParam, dl, DeclareParamVTs,
919 DeclareParamOps, 5);
920 InFlag = Chain.getValue(1);
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]921 unsigned curOffset = 0;
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]922 for (unsigned j = 0, je = vtparts.size(); j != je; ++j) {
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]923 unsigned elems = 1;
924 EVT elemtype = vtparts[j];
925 if (vtparts[j].isVector()) {
926 elems = vtparts[j].getVectorNumElements();
927 elemtype = vtparts[j].getVectorElementType();
928 }
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]929 for (unsigned k = 0, ke = elems; k != ke; ++k) {
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]930 unsigned sz = elemtype.getSizeInBits();
Justin Holewinskif8f70912013-06-28 17:57:59 +0000[diff] [blame]931 if (elemtype.isInteger() && (sz < 8))
932 sz = 8;
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]933 SDValue srcAddr =
Justin Holewinskif8f70912013-06-28 17:57:59 +0000[diff] [blame]934 DAG.getNode(ISD::ADD, dl, getPointerTy(), OutVals[OIdx],
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]935 DAG.getConstant(curOffset, getPointerTy()));
Justin Holewinskif8f70912013-06-28 17:57:59 +0000[diff] [blame]936 SDValue theVal = DAG.getLoad(elemtype, dl, tempChain, srcAddr,
937 MachinePointerInfo(), false, false, false,
938 0);
939 if (elemtype.getSizeInBits() < 16) {
Justin Holewinskia2911282013-07-01 12:58:58 +0000[diff] [blame]940 theVal = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i16, theVal);
Justin Holewinskif8f70912013-06-28 17:57:59 +0000[diff] [blame]941 }
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]942 SDVTList CopyParamVTs = DAG.getVTList(MVT::Other, MVT::Glue);
943 SDValue CopyParamOps[] = { Chain, DAG.getConstant(paramCount, MVT::i32),
Justin Holewinskif8f70912013-06-28 17:57:59 +0000[diff] [blame]944 DAG.getConstant(curOffset, MVT::i32), theVal,
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]945 InFlag };
Justin Holewinskif8f70912013-06-28 17:57:59 +0000[diff] [blame]946 Chain = DAG.getMemIntrinsicNode(NVPTXISD::StoreParam, dl, CopyParamVTs,
947 CopyParamOps, 5, elemtype,
948 MachinePointerInfo());
949
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]950 InFlag = Chain.getValue(1);
Justin Holewinskif8f70912013-06-28 17:57:59 +0000[diff] [blame]951 curOffset += sz / 8;
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]952 }
953 }
Justin Holewinskif8f70912013-06-28 17:57:59 +0000[diff] [blame]954 ++paramCount;
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]955 }
956
957 GlobalAddressSDNode *Func = dyn_cast<GlobalAddressSDNode>(Callee.getNode());
958 unsigned retAlignment = 0;
959
960 // Handle Result
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]961 if (Ins.size() > 0) {
962 SmallVector<EVT, 16> resvtparts;
963 ComputeValueVTs(*this, retTy, resvtparts);
964
Justin Holewinskif8f70912013-06-28 17:57:59 +0000[diff] [blame]965 // Declare
966 // .param .align 16 .b8 retval0[<size-in-bytes>], or
967 // .param .b<size-in-bits> retval0
968 unsigned resultsz = TD->getTypeAllocSizeInBits(retTy);
Rafael Espindola08013342013-12-07 19:34:20 +0000[diff] [blame]969 if (retTy->isSingleValueType()) {
Justin Holewinskif8f70912013-06-28 17:57:59 +0000[diff] [blame]970 // Scalar needs to be at least 32bit wide
971 if (resultsz < 32)
972 resultsz = 32;
973 SDVTList DeclareRetVTs = DAG.getVTList(MVT::Other, MVT::Glue);
974 SDValue DeclareRetOps[] = { Chain, DAG.getConstant(1, MVT::i32),
975 DAG.getConstant(resultsz, MVT::i32),
976 DAG.getConstant(0, MVT::i32), InFlag };
977 Chain = DAG.getNode(NVPTXISD::DeclareRet, dl, DeclareRetVTs,
978 DeclareRetOps, 5);
979 InFlag = Chain.getValue(1);
980 } else {
981 retAlignment = getArgumentAlignment(Callee, CS, retTy, 0);
982 SDVTList DeclareRetVTs = DAG.getVTList(MVT::Other, MVT::Glue);
983 SDValue DeclareRetOps[] = { Chain,
984 DAG.getConstant(retAlignment, MVT::i32),
985 DAG.getConstant(resultsz / 8, MVT::i32),
986 DAG.getConstant(0, MVT::i32), InFlag };
987 Chain = DAG.getNode(NVPTXISD::DeclareRetParam, dl, DeclareRetVTs,
988 DeclareRetOps, 5);
989 InFlag = Chain.getValue(1);
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]990 }
991 }
992
993 if (!Func) {
994 // This is indirect function call case : PTX requires a prototype of the
995 // form
996 // proto_0 : .callprototype(.param .b32 _) _ (.param .b32 _);
997 // to be emitted, and the label has to used as the last arg of call
998 // instruction.
Justin Holewinski3d49e5c2013-11-15 12:30:04 +0000[diff] [blame]999 // The prototype is embedded in a string and put as the operand for a
1000 // CallPrototype SDNode which will print out to the value of the string.
1001 SDVTList ProtoVTs = DAG.getVTList(MVT::Other, MVT::Glue);
1002 std::string Proto = getPrototype(retTy, Args, Outs, retAlignment, CS);
1003 const char *ProtoStr =
1004 nvTM->getManagedStrPool()->getManagedString(Proto.c_str())->c_str();
1005 SDValue ProtoOps[] = {
1006 Chain, DAG.getTargetExternalSymbol(ProtoStr, MVT::i32), InFlag,
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]1007 };
Justin Holewinski3d49e5c2013-11-15 12:30:04 +0000[diff] [blame]1008 Chain = DAG.getNode(NVPTXISD::CallPrototype, dl, ProtoVTs, &ProtoOps[0], 3);
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]1009 InFlag = Chain.getValue(1);
1010 }
1011 // Op to just print "call"
1012 SDVTList PrintCallVTs = DAG.getVTList(MVT::Other, MVT::Glue);
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]1013 SDValue PrintCallOps[] = {
Justin Holewinskif8f70912013-06-28 17:57:59 +0000[diff] [blame]1014 Chain, DAG.getConstant((Ins.size() == 0) ? 0 : 1, MVT::i32), InFlag
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]1015 };
1016 Chain = DAG.getNode(Func ? (NVPTXISD::PrintCallUni) : (NVPTXISD::PrintCall),
1017 dl, PrintCallVTs, PrintCallOps, 3);
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]1018 InFlag = Chain.getValue(1);
1019
1020 // Ops to print out the function name
1021 SDVTList CallVoidVTs = DAG.getVTList(MVT::Other, MVT::Glue);
1022 SDValue CallVoidOps[] = { Chain, Callee, InFlag };
1023 Chain = DAG.getNode(NVPTXISD::CallVoid, dl, CallVoidVTs, CallVoidOps, 3);
1024 InFlag = Chain.getValue(1);
1025
1026 // Ops to print out the param list
1027 SDVTList CallArgBeginVTs = DAG.getVTList(MVT::Other, MVT::Glue);
1028 SDValue CallArgBeginOps[] = { Chain, InFlag };
1029 Chain = DAG.getNode(NVPTXISD::CallArgBegin, dl, CallArgBeginVTs,
1030 CallArgBeginOps, 2);
1031 InFlag = Chain.getValue(1);
1032
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]1033 for (unsigned i = 0, e = paramCount; i != e; ++i) {
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]1034 unsigned opcode;
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]1035 if (i == (e - 1))
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]1036 opcode = NVPTXISD::LastCallArg;
1037 else
1038 opcode = NVPTXISD::CallArg;
1039 SDVTList CallArgVTs = DAG.getVTList(MVT::Other, MVT::Glue);
1040 SDValue CallArgOps[] = { Chain, DAG.getConstant(1, MVT::i32),
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]1041 DAG.getConstant(i, MVT::i32), InFlag };
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]1042 Chain = DAG.getNode(opcode, dl, CallArgVTs, CallArgOps, 4);
1043 InFlag = Chain.getValue(1);
1044 }
1045 SDVTList CallArgEndVTs = DAG.getVTList(MVT::Other, MVT::Glue);
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]1046 SDValue CallArgEndOps[] = { Chain, DAG.getConstant(Func ? 1 : 0, MVT::i32),
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]1047 InFlag };
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]1048 Chain =
1049 DAG.getNode(NVPTXISD::CallArgEnd, dl, CallArgEndVTs, CallArgEndOps, 3);
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]1050 InFlag = Chain.getValue(1);
1051
1052 if (!Func) {
1053 SDVTList PrototypeVTs = DAG.getVTList(MVT::Other, MVT::Glue);
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]1054 SDValue PrototypeOps[] = { Chain, DAG.getConstant(uniqueCallSite, MVT::i32),
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]1055 InFlag };
1056 Chain = DAG.getNode(NVPTXISD::Prototype, dl, PrototypeVTs, PrototypeOps, 3);
1057 InFlag = Chain.getValue(1);
1058 }
1059
1060 // Generate loads from param memory/moves from registers for result
1061 if (Ins.size() > 0) {
Justin Holewinskif8f70912013-06-28 17:57:59 +0000[diff] [blame]1062 unsigned resoffset = 0;
1063 if (retTy && retTy->isVectorTy()) {
1064 EVT ObjectVT = getValueType(retTy);
1065 unsigned NumElts = ObjectVT.getVectorNumElements();
1066 EVT EltVT = ObjectVT.getVectorElementType();
Benjamin Kramer3cc579a2013-06-29 22:51:12 +0000[diff] [blame]1067 assert(nvTM->getTargetLowering()->getNumRegisters(F->getContext(),
1068 ObjectVT) == NumElts &&
Justin Holewinskif8f70912013-06-28 17:57:59 +0000[diff] [blame]1069 "Vector was not scalarized");
1070 unsigned sz = EltVT.getSizeInBits();
1071 bool needTruncate = sz < 16 ? true : false;
1072
1073 if (NumElts == 1) {
1074 // Just a simple load
1075 std::vector<EVT> LoadRetVTs;
1076 if (needTruncate) {
1077 // If loading i1 result, generate
1078 // load i16
1079 // trunc i16 to i1
1080 LoadRetVTs.push_back(MVT::i16);
1081 } else
1082 LoadRetVTs.push_back(EltVT);
1083 LoadRetVTs.push_back(MVT::Other);
1084 LoadRetVTs.push_back(MVT::Glue);
1085 std::vector<SDValue> LoadRetOps;
1086 LoadRetOps.push_back(Chain);
1087 LoadRetOps.push_back(DAG.getConstant(1, MVT::i32));
1088 LoadRetOps.push_back(DAG.getConstant(0, MVT::i32));
1089 LoadRetOps.push_back(InFlag);
1090 SDValue retval = DAG.getMemIntrinsicNode(
1091 NVPTXISD::LoadParam, dl,
Craig Topperabb4ac72014-04-16 06:10:51 +0000[diff] [blame]1092 DAG.getVTList(LoadRetVTs), &LoadRetOps[0],
Justin Holewinskif8f70912013-06-28 17:57:59 +0000[diff] [blame]1093 LoadRetOps.size(), EltVT, MachinePointerInfo());
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]1094 Chain = retval.getValue(1);
1095 InFlag = retval.getValue(2);
Justin Holewinskif8f70912013-06-28 17:57:59 +0000[diff] [blame]1096 SDValue Ret0 = retval;
1097 if (needTruncate)
1098 Ret0 = DAG.getNode(ISD::TRUNCATE, dl, EltVT, Ret0);
1099 InVals.push_back(Ret0);
1100 } else if (NumElts == 2) {
1101 // LoadV2
1102 std::vector<EVT> LoadRetVTs;
1103 if (needTruncate) {
1104 // If loading i1 result, generate
1105 // load i16
1106 // trunc i16 to i1
1107 LoadRetVTs.push_back(MVT::i16);
1108 LoadRetVTs.push_back(MVT::i16);
1109 } else {
1110 LoadRetVTs.push_back(EltVT);
1111 LoadRetVTs.push_back(EltVT);
1112 }
1113 LoadRetVTs.push_back(MVT::Other);
1114 LoadRetVTs.push_back(MVT::Glue);
1115 std::vector<SDValue> LoadRetOps;
1116 LoadRetOps.push_back(Chain);
1117 LoadRetOps.push_back(DAG.getConstant(1, MVT::i32));
1118 LoadRetOps.push_back(DAG.getConstant(0, MVT::i32));
1119 LoadRetOps.push_back(InFlag);
1120 SDValue retval = DAG.getMemIntrinsicNode(
1121 NVPTXISD::LoadParamV2, dl,
Craig Topperabb4ac72014-04-16 06:10:51 +0000[diff] [blame]1122 DAG.getVTList(LoadRetVTs), &LoadRetOps[0],
Justin Holewinskif8f70912013-06-28 17:57:59 +0000[diff] [blame]1123 LoadRetOps.size(), EltVT, MachinePointerInfo());
1124 Chain = retval.getValue(2);
1125 InFlag = retval.getValue(3);
1126 SDValue Ret0 = retval.getValue(0);
1127 SDValue Ret1 = retval.getValue(1);
1128 if (needTruncate) {
1129 Ret0 = DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, Ret0);
1130 InVals.push_back(Ret0);
1131 Ret1 = DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, Ret1);
1132 InVals.push_back(Ret1);
1133 } else {
1134 InVals.push_back(Ret0);
1135 InVals.push_back(Ret1);
1136 }
1137 } else {
1138 // Split into N LoadV4
1139 unsigned Ofst = 0;
1140 unsigned VecSize = 4;
1141 unsigned Opc = NVPTXISD::LoadParamV4;
1142 if (EltVT.getSizeInBits() == 64) {
1143 VecSize = 2;
1144 Opc = NVPTXISD::LoadParamV2;
1145 }
1146 EVT VecVT = EVT::getVectorVT(F->getContext(), EltVT, VecSize);
1147 for (unsigned i = 0; i < NumElts; i += VecSize) {
1148 SmallVector<EVT, 8> LoadRetVTs;
1149 if (needTruncate) {
1150 // If loading i1 result, generate
1151 // load i16
1152 // trunc i16 to i1
1153 for (unsigned j = 0; j < VecSize; ++j)
1154 LoadRetVTs.push_back(MVT::i16);
1155 } else {
1156 for (unsigned j = 0; j < VecSize; ++j)
1157 LoadRetVTs.push_back(EltVT);
1158 }
1159 LoadRetVTs.push_back(MVT::Other);
1160 LoadRetVTs.push_back(MVT::Glue);
1161 SmallVector<SDValue, 4> LoadRetOps;
1162 LoadRetOps.push_back(Chain);
1163 LoadRetOps.push_back(DAG.getConstant(1, MVT::i32));
1164 LoadRetOps.push_back(DAG.getConstant(Ofst, MVT::i32));
1165 LoadRetOps.push_back(InFlag);
1166 SDValue retval = DAG.getMemIntrinsicNode(
Craig Topperabb4ac72014-04-16 06:10:51 +0000[diff] [blame]1167 Opc, dl, DAG.getVTList(LoadRetVTs),
Justin Holewinskif8f70912013-06-28 17:57:59 +0000[diff] [blame]1168 &LoadRetOps[0], LoadRetOps.size(), EltVT, MachinePointerInfo());
1169 if (VecSize == 2) {
1170 Chain = retval.getValue(2);
1171 InFlag = retval.getValue(3);
1172 } else {
1173 Chain = retval.getValue(4);
1174 InFlag = retval.getValue(5);
1175 }
1176
1177 for (unsigned j = 0; j < VecSize; ++j) {
1178 if (i + j >= NumElts)
1179 break;
1180 SDValue Elt = retval.getValue(j);
1181 if (needTruncate)
1182 Elt = DAG.getNode(ISD::TRUNCATE, dl, EltVT, Elt);
1183 InVals.push_back(Elt);
1184 }
1185 Ofst += TD->getTypeAllocSize(VecVT.getTypeForEVT(F->getContext()));
1186 }
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]1187 }
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]1188 } else {
Justin Holewinskif8f70912013-06-28 17:57:59 +0000[diff] [blame]1189 SmallVector<EVT, 16> VTs;
1190 ComputePTXValueVTs(*this, retTy, VTs);
1191 assert(VTs.size() == Ins.size() && "Bad value decomposition");
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]1192 for (unsigned i = 0, e = Ins.size(); i != e; ++i) {
Justin Holewinskif8f70912013-06-28 17:57:59 +0000[diff] [blame]1193 unsigned sz = VTs[i].getSizeInBits();
1194 bool needTruncate = sz < 8 ? true : false;
1195 if (VTs[i].isInteger() && (sz < 8))
1196 sz = 8;
1197
1198 SmallVector<EVT, 4> LoadRetVTs;
Justin Holewinskie04e4bd2013-06-28 17:58:10 +0000[diff] [blame]1199 EVT TheLoadType = VTs[i];
1200 if (retTy->isIntegerTy() &&
1201 TD->getTypeAllocSizeInBits(retTy) < 32) {
1202 // This is for integer types only, and specifically not for
1203 // aggregates.
1204 LoadRetVTs.push_back(MVT::i32);
1205 TheLoadType = MVT::i32;
1206 } else if (sz < 16) {
Justin Holewinskif8f70912013-06-28 17:57:59 +0000[diff] [blame]1207 // If loading i1/i8 result, generate
1208 // load i8 (-> i16)
1209 // trunc i16 to i1/i8
1210 LoadRetVTs.push_back(MVT::i16);
1211 } else
1212 LoadRetVTs.push_back(Ins[i].VT);
1213 LoadRetVTs.push_back(MVT::Other);
1214 LoadRetVTs.push_back(MVT::Glue);
1215
1216 SmallVector<SDValue, 4> LoadRetOps;
1217 LoadRetOps.push_back(Chain);
1218 LoadRetOps.push_back(DAG.getConstant(1, MVT::i32));
1219 LoadRetOps.push_back(DAG.getConstant(resoffset, MVT::i32));
1220 LoadRetOps.push_back(InFlag);
1221 SDValue retval = DAG.getMemIntrinsicNode(
1222 NVPTXISD::LoadParam, dl,
Craig Topperabb4ac72014-04-16 06:10:51 +0000[diff] [blame]1223 DAG.getVTList(LoadRetVTs), &LoadRetOps[0],
Justin Holewinskie04e4bd2013-06-28 17:58:10 +0000[diff] [blame]1224 LoadRetOps.size(), TheLoadType, MachinePointerInfo());
Justin Holewinskif8f70912013-06-28 17:57:59 +0000[diff] [blame]1225 Chain = retval.getValue(1);
1226 InFlag = retval.getValue(2);
1227 SDValue Ret0 = retval.getValue(0);
1228 if (needTruncate)
1229 Ret0 = DAG.getNode(ISD::TRUNCATE, dl, Ins[i].VT, Ret0);
1230 InVals.push_back(Ret0);
1231 resoffset += sz / 8;
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]1232 }
1233 }
1234 }
Justin Holewinskif8f70912013-06-28 17:57:59 +0000[diff] [blame]1235
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]1236 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(uniqueCallSite, true),
1237 DAG.getIntPtrConstant(uniqueCallSite + 1, true),
Andrew Trickad6d08a2013-05-29 22:03:55 +0000[diff] [blame]1238 InFlag, dl);
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]1239 uniqueCallSite++;
1240
1241 // set isTailCall to false for now, until we figure out how to express
1242 // tail call optimization in PTX
1243 isTailCall = false;
1244 return Chain;
1245}
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]1246
1247// By default CONCAT_VECTORS is lowered by ExpandVectorBuildThroughStack()
1248// (see LegalizeDAG.cpp). This is slow and uses local memory.
1249// We use extract/insert/build vector just as what LegalizeOp() does in llvm 2.5
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]1250SDValue
1251NVPTXTargetLowering::LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) const {
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]1252 SDNode *Node = Op.getNode();
Andrew Trickef9de2a2013-05-25 02:42:55 +0000[diff] [blame]1253 SDLoc dl(Node);
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]1254 SmallVector<SDValue, 8> Ops;
1255 unsigned NumOperands = Node->getNumOperands();
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]1256 for (unsigned i = 0; i < NumOperands; ++i) {
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]1257 SDValue SubOp = Node->getOperand(i);
1258 EVT VVT = SubOp.getNode()->getValueType(0);
1259 EVT EltVT = VVT.getVectorElementType();
1260 unsigned NumSubElem = VVT.getVectorNumElements();
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]1261 for (unsigned j = 0; j < NumSubElem; ++j) {
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]1262 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, SubOp,
1263 DAG.getIntPtrConstant(j)));
1264 }
1265 }
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]1266 return DAG.getNode(ISD::BUILD_VECTOR, dl, Node->getValueType(0), &Ops[0],
1267 Ops.size());
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]1268}
1269
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]1270SDValue
1271NVPTXTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]1272 switch (Op.getOpcode()) {
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]1273 case ISD::RETURNADDR:
1274 return SDValue();
1275 case ISD::FRAMEADDR:
1276 return SDValue();
1277 case ISD::GlobalAddress:
1278 return LowerGlobalAddress(Op, DAG);
1279 case ISD::INTRINSIC_W_CHAIN:
1280 return Op;
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]1281 case ISD::BUILD_VECTOR:
1282 case ISD::EXTRACT_SUBVECTOR:
1283 return Op;
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]1284 case ISD::CONCAT_VECTORS:
1285 return LowerCONCAT_VECTORS(Op, DAG);
1286 case ISD::STORE:
1287 return LowerSTORE(Op, DAG);
1288 case ISD::LOAD:
1289 return LowerLOAD(Op, DAG);
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]1290 default:
David Blaikie891d0a32012-05-04 22:34:16 +0000[diff] [blame]1291 llvm_unreachable("Custom lowering not defined for operation");
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]1292 }
1293}
1294
Justin Holewinskibe8dc642013-02-12 14:18:49 +0000[diff] [blame]1295SDValue NVPTXTargetLowering::LowerLOAD(SDValue Op, SelectionDAG &DAG) const {
1296 if (Op.getValueType() == MVT::i1)
1297 return LowerLOADi1(Op, DAG);
1298 else
1299 return SDValue();
1300}
1301
Justin Holewinskic6462aa2012-11-14 19:19:16 +0000[diff] [blame]1302// v = ld i1* addr
1303// =>
Justin Holewinskif8f70912013-06-28 17:57:59 +0000[diff] [blame]1304// v1 = ld i8* addr (-> i16)
1305// v = trunc i16 to i1
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]1306SDValue NVPTXTargetLowering::LowerLOADi1(SDValue Op, SelectionDAG &DAG) const {
Justin Holewinskic6462aa2012-11-14 19:19:16 +0000[diff] [blame]1307 SDNode *Node = Op.getNode();
1308 LoadSDNode *LD = cast<LoadSDNode>(Node);
Andrew Trickef9de2a2013-05-25 02:42:55 +0000[diff] [blame]1309 SDLoc dl(Node);
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]1310 assert(LD->getExtensionType() == ISD::NON_EXTLOAD);
NAKAMURA Takumi5bbe0e12012-11-14 23:46:15 +0000[diff] [blame]1311 assert(Node->getValueType(0) == MVT::i1 &&
1312 "Custom lowering for i1 load only");
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]1313 SDValue newLD =
Justin Holewinskif8f70912013-06-28 17:57:59 +0000[diff] [blame]1314 DAG.getLoad(MVT::i16, dl, LD->getChain(), LD->getBasePtr(),
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]1315 LD->getPointerInfo(), LD->isVolatile(), LD->isNonTemporal(),
1316 LD->isInvariant(), LD->getAlignment());
Justin Holewinskic6462aa2012-11-14 19:19:16 +0000[diff] [blame]1317 SDValue result = DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, newLD);
1318 // The legalizer (the caller) is expecting two values from the legalized
1319 // load, so we build a MergeValues node for it. See ExpandUnalignedLoad()
1320 // in LegalizeDAG.cpp which also uses MergeValues.
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]1321 SDValue Ops[] = { result, LD->getChain() };
Justin Holewinskic6462aa2012-11-14 19:19:16 +0000[diff] [blame]1322 return DAG.getMergeValues(Ops, 2, dl);
1323}
1324
Justin Holewinskibe8dc642013-02-12 14:18:49 +0000[diff] [blame]1325SDValue NVPTXTargetLowering::LowerSTORE(SDValue Op, SelectionDAG &DAG) const {
1326 EVT ValVT = Op.getOperand(1).getValueType();
1327 if (ValVT == MVT::i1)
1328 return LowerSTOREi1(Op, DAG);
1329 else if (ValVT.isVector())
1330 return LowerSTOREVector(Op, DAG);
1331 else
1332 return SDValue();
1333}
1334
1335SDValue
1336NVPTXTargetLowering::LowerSTOREVector(SDValue Op, SelectionDAG &DAG) const {
1337 SDNode *N = Op.getNode();
1338 SDValue Val = N->getOperand(1);
Andrew Trickef9de2a2013-05-25 02:42:55 +0000[diff] [blame]1339 SDLoc DL(N);
Justin Holewinskibe8dc642013-02-12 14:18:49 +0000[diff] [blame]1340 EVT ValVT = Val.getValueType();
1341
1342 if (ValVT.isVector()) {
1343 // We only handle "native" vector sizes for now, e.g. <4 x double> is not
1344 // legal. We can (and should) split that into 2 stores of <2 x double> here
1345 // but I'm leaving that as a TODO for now.
1346 if (!ValVT.isSimple())
1347 return SDValue();
1348 switch (ValVT.getSimpleVT().SimpleTy) {
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]1349 default:
1350 return SDValue();
Justin Holewinskibe8dc642013-02-12 14:18:49 +0000[diff] [blame]1351 case MVT::v2i8:
1352 case MVT::v2i16:
1353 case MVT::v2i32:
1354 case MVT::v2i64:
1355 case MVT::v2f32:
1356 case MVT::v2f64:
1357 case MVT::v4i8:
1358 case MVT::v4i16:
1359 case MVT::v4i32:
1360 case MVT::v4f32:
1361 // This is a "native" vector type
1362 break;
1363 }
1364
1365 unsigned Opcode = 0;
1366 EVT EltVT = ValVT.getVectorElementType();
1367 unsigned NumElts = ValVT.getVectorNumElements();
1368
1369 // Since StoreV2 is a target node, we cannot rely on DAG type legalization.
1370 // Therefore, we must ensure the type is legal. For i1 and i8, we set the
Alp Tokercb402912014-01-24 17:20:08 +0000[diff] [blame]1371 // stored type to i16 and propagate the "real" type as the memory type.
Justin Holewinskia2911282013-07-01 12:58:58 +0000[diff] [blame]1372 bool NeedExt = false;
Justin Holewinskibe8dc642013-02-12 14:18:49 +0000[diff] [blame]1373 if (EltVT.getSizeInBits() < 16)
Justin Holewinskia2911282013-07-01 12:58:58 +0000[diff] [blame]1374 NeedExt = true;
Justin Holewinskibe8dc642013-02-12 14:18:49 +0000[diff] [blame]1375
1376 switch (NumElts) {
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]1377 default:
1378 return SDValue();
Justin Holewinskibe8dc642013-02-12 14:18:49 +0000[diff] [blame]1379 case 2:
1380 Opcode = NVPTXISD::StoreV2;
1381 break;
1382 case 4: {
1383 Opcode = NVPTXISD::StoreV4;
1384 break;
1385 }
1386 }
1387
1388 SmallVector<SDValue, 8> Ops;
1389
1390 // First is the chain
1391 Ops.push_back(N->getOperand(0));
1392
1393 // Then the split values
1394 for (unsigned i = 0; i < NumElts; ++i) {
1395 SDValue ExtVal = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, EltVT, Val,
1396 DAG.getIntPtrConstant(i));
Justin Holewinskia2911282013-07-01 12:58:58 +0000[diff] [blame]1397 if (NeedExt)
1398 ExtVal = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i16, ExtVal);
Justin Holewinskibe8dc642013-02-12 14:18:49 +0000[diff] [blame]1399 Ops.push_back(ExtVal);
1400 }
1401
1402 // Then any remaining arguments
1403 for (unsigned i = 2, e = N->getNumOperands(); i != e; ++i) {
1404 Ops.push_back(N->getOperand(i));
1405 }
1406
1407 MemSDNode *MemSD = cast<MemSDNode>(N);
1408
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]1409 SDValue NewSt = DAG.getMemIntrinsicNode(
1410 Opcode, DL, DAG.getVTList(MVT::Other), &Ops[0], Ops.size(),
1411 MemSD->getMemoryVT(), MemSD->getMemOperand());
Justin Holewinskibe8dc642013-02-12 14:18:49 +0000[diff] [blame]1412
1413 //return DCI.CombineTo(N, NewSt, true);
1414 return NewSt;
1415 }
1416
1417 return SDValue();
1418}
1419
Justin Holewinskic6462aa2012-11-14 19:19:16 +0000[diff] [blame]1420// st i1 v, addr
1421// =>
Justin Holewinskif8f70912013-06-28 17:57:59 +0000[diff] [blame]1422// v1 = zxt v to i16
1423// st.u8 i16, addr
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]1424SDValue NVPTXTargetLowering::LowerSTOREi1(SDValue Op, SelectionDAG &DAG) const {
Justin Holewinskic6462aa2012-11-14 19:19:16 +0000[diff] [blame]1425 SDNode *Node = Op.getNode();
Andrew Trickef9de2a2013-05-25 02:42:55 +0000[diff] [blame]1426 SDLoc dl(Node);
Justin Holewinskic6462aa2012-11-14 19:19:16 +0000[diff] [blame]1427 StoreSDNode *ST = cast<StoreSDNode>(Node);
1428 SDValue Tmp1 = ST->getChain();
1429 SDValue Tmp2 = ST->getBasePtr();
1430 SDValue Tmp3 = ST->getValue();
NAKAMURA Takumi5bbe0e12012-11-14 23:46:15 +0000[diff] [blame]1431 assert(Tmp3.getValueType() == MVT::i1 && "Custom lowering for i1 store only");
Justin Holewinskic6462aa2012-11-14 19:19:16 +0000[diff] [blame]1432 unsigned Alignment = ST->getAlignment();
1433 bool isVolatile = ST->isVolatile();
1434 bool isNonTemporal = ST->isNonTemporal();
Justin Holewinskif8f70912013-06-28 17:57:59 +0000[diff] [blame]1435 Tmp3 = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, Tmp3);
1436 SDValue Result = DAG.getTruncStore(Tmp1, dl, Tmp3, Tmp2,
1437 ST->getPointerInfo(), MVT::i8, isNonTemporal,
1438 isVolatile, Alignment);
Justin Holewinskic6462aa2012-11-14 19:19:16 +0000[diff] [blame]1439 return Result;
1440}
1441
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]1442SDValue NVPTXTargetLowering::getExtSymb(SelectionDAG &DAG, const char *inname,
1443 int idx, EVT v) const {
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]1444 std::string *name = nvTM->getManagedStrPool()->getManagedString(inname);
1445 std::stringstream suffix;
1446 suffix << idx;
1447 *name += suffix.str();
1448 return DAG.getTargetExternalSymbol(name->c_str(), v);
1449}
1450
1451SDValue
1452NVPTXTargetLowering::getParamSymbol(SelectionDAG &DAG, int idx, EVT v) const {
Justin Holewinskia2a63d22013-08-06 14:13:27 +0000[diff] [blame]1453 std::string ParamSym;
1454 raw_string_ostream ParamStr(ParamSym);
1455
1456 ParamStr << DAG.getMachineFunction().getName() << "_param_" << idx;
1457 ParamStr.flush();
1458
1459 std::string *SavedStr =
1460 nvTM->getManagedStrPool()->getManagedString(ParamSym.c_str());
1461 return DAG.getTargetExternalSymbol(SavedStr->c_str(), v);
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]1462}
1463
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]1464SDValue NVPTXTargetLowering::getParamHelpSymbol(SelectionDAG &DAG, int idx) {
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]1465 return getExtSymb(DAG, ".HLPPARAM", idx);
1466}
1467
1468// Check to see if the kernel argument is image*_t or sampler_t
1469
1470bool llvm::isImageOrSamplerVal(const Value *arg, const Module *context) {
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]1471 static const char *const specialTypes[] = { "struct._image2d_t",
1472 "struct._image3d_t",
1473 "struct._sampler_t" };
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]1474
1475 const Type *Ty = arg->getType();
1476 const PointerType *PTy = dyn_cast<PointerType>(Ty);
1477
1478 if (!PTy)
1479 return false;
1480
1481 if (!context)
1482 return false;
1483
1484 const StructType *STy = dyn_cast<StructType>(PTy->getElementType());
Justin Holewinskifb711152012-12-05 20:50:28 +0000[diff] [blame]1485 const std::string TypeName = STy && !STy->isLiteral() ? STy->getName() : "";
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]1486
Craig Toppere4260f92012-05-24 04:22:05 +0000[diff] [blame]1487 for (int i = 0, e = array_lengthof(specialTypes); i != e; ++i)
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]1488 if (TypeName == specialTypes[i])
1489 return true;
1490
1491 return false;
1492}
1493
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]1494SDValue NVPTXTargetLowering::LowerFormalArguments(
1495 SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
Andrew Trickef9de2a2013-05-25 02:42:55 +0000[diff] [blame]1496 const SmallVectorImpl<ISD::InputArg> &Ins, SDLoc dl, SelectionDAG &DAG,
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]1497 SmallVectorImpl<SDValue> &InVals) const {
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]1498 MachineFunction &MF = DAG.getMachineFunction();
Micah Villmowcdfe20b2012-10-08 16:38:25 +0000[diff] [blame]1499 const DataLayout *TD = getDataLayout();
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]1500
1501 const Function *F = MF.getFunction();
Bill Wendlinge94d8432012-12-07 23:16:57 +0000[diff] [blame]1502 const AttributeSet &PAL = F->getAttributes();
Justin Holewinski44f5c602013-06-28 17:57:53 +0000[diff] [blame]1503 const TargetLowering *TLI = nvTM->getTargetLowering();
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]1504
1505 SDValue Root = DAG.getRoot();
1506 std::vector<SDValue> OutChains;
1507
1508 bool isKernel = llvm::isKernelFunction(*F);
1509 bool isABI = (nvptxSubtarget.getSmVersion() >= 20);
Justin Holewinski44f5c602013-06-28 17:57:53 +0000[diff] [blame]1510 assert(isABI && "Non-ABI compilation is not supported");
1511 if (!isABI)
1512 return Chain;
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]1513
1514 std::vector<Type *> argTypes;
1515 std::vector<const Argument *> theArgs;
1516 for (Function::const_arg_iterator I = F->arg_begin(), E = F->arg_end();
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]1517 I != E; ++I) {
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]1518 theArgs.push_back(I);
1519 argTypes.push_back(I->getType());
1520 }
Justin Holewinski44f5c602013-06-28 17:57:53 +0000[diff] [blame]1521 // argTypes.size() (or theArgs.size()) and Ins.size() need not match.
1522 // Ins.size() will be larger
1523 // * if there is an aggregate argument with multiple fields (each field
1524 // showing up separately in Ins)
1525 // * if there is a vector argument with more than typical vector-length
1526 // elements (generally if more than 4) where each vector element is
1527 // individually present in Ins.
1528 // So a different index should be used for indexing into Ins.
1529 // See similar issue in LowerCall.
1530 unsigned InsIdx = 0;
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]1531
1532 int idx = 0;
Justin Holewinski44f5c602013-06-28 17:57:53 +0000[diff] [blame]1533 for (unsigned i = 0, e = theArgs.size(); i != e; ++i, ++idx, ++InsIdx) {
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]1534 Type *Ty = argTypes[i];
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]1535
1536 // If the kernel argument is image*_t or sampler_t, convert it to
1537 // a i32 constant holding the parameter position. This can later
1538 // matched in the AsmPrinter to output the correct mangled name.
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]1539 if (isImageOrSamplerVal(
1540 theArgs[i],
1541 (theArgs[i]->getParent() ? theArgs[i]->getParent()->getParent()
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame^]1542 : nullptr))) {
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]1543 assert(isKernel && "Only kernels can have image/sampler params");
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]1544 InVals.push_back(DAG.getConstant(i + 1, MVT::i32));
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]1545 continue;
1546 }
1547
1548 if (theArgs[i]->use_empty()) {
1549 // argument is dead
Justin Holewinski44f5c602013-06-28 17:57:53 +0000[diff] [blame]1550 if (Ty->isAggregateType()) {
1551 SmallVector<EVT, 16> vtparts;
1552
Justin Holewinskif8f70912013-06-28 17:57:59 +0000[diff] [blame]1553 ComputePTXValueVTs(*this, Ty, vtparts);
Justin Holewinski44f5c602013-06-28 17:57:53 +0000[diff] [blame]1554 assert(vtparts.size() > 0 && "empty aggregate type not expected");
1555 for (unsigned parti = 0, parte = vtparts.size(); parti != parte;
1556 ++parti) {
1557 EVT partVT = vtparts[parti];
1558 InVals.push_back(DAG.getNode(ISD::UNDEF, dl, partVT));
1559 ++InsIdx;
Justin Holewinskie9884092013-03-24 21:17:47 +0000[diff] [blame]1560 }
Justin Holewinski44f5c602013-06-28 17:57:53 +0000[diff] [blame]1561 if (vtparts.size() > 0)
1562 --InsIdx;
1563 continue;
Justin Holewinskie9884092013-03-24 21:17:47 +0000[diff] [blame]1564 }
Justin Holewinski44f5c602013-06-28 17:57:53 +0000[diff] [blame]1565 if (Ty->isVectorTy()) {
1566 EVT ObjectVT = getValueType(Ty);
1567 unsigned NumRegs = TLI->getNumRegisters(F->getContext(), ObjectVT);
1568 for (unsigned parti = 0; parti < NumRegs; ++parti) {
1569 InVals.push_back(DAG.getNode(ISD::UNDEF, dl, Ins[InsIdx].VT));
1570 ++InsIdx;
1571 }
1572 if (NumRegs > 0)
1573 --InsIdx;
1574 continue;
1575 }
1576 InVals.push_back(DAG.getNode(ISD::UNDEF, dl, Ins[InsIdx].VT));
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]1577 continue;
1578 }
1579
1580 // In the following cases, assign a node order of "idx+1"
Justin Holewinski44f5c602013-06-28 17:57:53 +0000[diff] [blame]1581 // to newly created nodes. The SDNodes for params have to
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]1582 // appear in the same order as their order of appearance
1583 // in the original function. "idx+1" holds that order.
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]1584 if (PAL.hasAttribute(i + 1, Attribute::ByVal) == false) {
Justin Holewinski44f5c602013-06-28 17:57:53 +0000[diff] [blame]1585 if (Ty->isAggregateType()) {
1586 SmallVector<EVT, 16> vtparts;
1587 SmallVector<uint64_t, 16> offsets;
1588
Justin Holewinskif8f70912013-06-28 17:57:59 +0000[diff] [blame]1589 // NOTE: Here, we lose the ability to issue vector loads for vectors
1590 // that are a part of a struct. This should be investigated in the
1591 // future.
1592 ComputePTXValueVTs(*this, Ty, vtparts, &offsets, 0);
Justin Holewinski44f5c602013-06-28 17:57:53 +0000[diff] [blame]1593 assert(vtparts.size() > 0 && "empty aggregate type not expected");
1594 bool aggregateIsPacked = false;
1595 if (StructType *STy = llvm::dyn_cast<StructType>(Ty))
1596 aggregateIsPacked = STy->isPacked();
1597
1598 SDValue Arg = getParamSymbol(DAG, idx, getPointerTy());
1599 for (unsigned parti = 0, parte = vtparts.size(); parti != parte;
1600 ++parti) {
1601 EVT partVT = vtparts[parti];
1602 Value *srcValue = Constant::getNullValue(
1603 PointerType::get(partVT.getTypeForEVT(F->getContext()),
1604 llvm::ADDRESS_SPACE_PARAM));
1605 SDValue srcAddr =
1606 DAG.getNode(ISD::ADD, dl, getPointerTy(), Arg,
1607 DAG.getConstant(offsets[parti], getPointerTy()));
1608 unsigned partAlign =
1609 aggregateIsPacked ? 1
1610 : TD->getABITypeAlignment(
1611 partVT.getTypeForEVT(F->getContext()));
Justin Holewinskia2911282013-07-01 12:58:58 +0000[diff] [blame]1612 SDValue p;
1613 if (Ins[InsIdx].VT.getSizeInBits() > partVT.getSizeInBits()) {
1614 ISD::LoadExtType ExtOp = Ins[InsIdx].Flags.isSExt() ?
1615 ISD::SEXTLOAD : ISD::ZEXTLOAD;
1616 p = DAG.getExtLoad(ExtOp, dl, Ins[InsIdx].VT, Root, srcAddr,
Justin Holewinskif8f70912013-06-28 17:57:59 +0000[diff] [blame]1617 MachinePointerInfo(srcValue), partVT, false,
1618 false, partAlign);
Justin Holewinskia2911282013-07-01 12:58:58 +0000[diff] [blame]1619 } else {
Justin Holewinskif8f70912013-06-28 17:57:59 +0000[diff] [blame]1620 p = DAG.getLoad(partVT, dl, Root, srcAddr,
1621 MachinePointerInfo(srcValue), false, false, false,
1622 partAlign);
Justin Holewinskia2911282013-07-01 12:58:58 +0000[diff] [blame]1623 }
Justin Holewinski44f5c602013-06-28 17:57:53 +0000[diff] [blame]1624 if (p.getNode())
1625 p.getNode()->setIROrder(idx + 1);
1626 InVals.push_back(p);
1627 ++InsIdx;
Justin Holewinskie9884092013-03-24 21:17:47 +0000[diff] [blame]1628 }
Justin Holewinski44f5c602013-06-28 17:57:53 +0000[diff] [blame]1629 if (vtparts.size() > 0)
1630 --InsIdx;
Justin Holewinskie9884092013-03-24 21:17:47 +0000[diff] [blame]1631 continue;
1632 }
Justin Holewinski44f5c602013-06-28 17:57:53 +0000[diff] [blame]1633 if (Ty->isVectorTy()) {
1634 EVT ObjectVT = getValueType(Ty);
Justin Holewinskiaaaf2892013-06-25 12:22:21 +0000[diff] [blame]1635 SDValue Arg = getParamSymbol(DAG, idx, getPointerTy());
Justin Holewinski44f5c602013-06-28 17:57:53 +0000[diff] [blame]1636 unsigned NumElts = ObjectVT.getVectorNumElements();
1637 assert(TLI->getNumRegisters(F->getContext(), ObjectVT) == NumElts &&
1638 "Vector was not scalarized");
1639 unsigned Ofst = 0;
1640 EVT EltVT = ObjectVT.getVectorElementType();
1641
1642 // V1 load
1643 // f32 = load ...
1644 if (NumElts == 1) {
1645 // We only have one element, so just directly load it
1646 Value *SrcValue = Constant::getNullValue(PointerType::get(
1647 EltVT.getTypeForEVT(F->getContext()), llvm::ADDRESS_SPACE_PARAM));
1648 SDValue SrcAddr = DAG.getNode(ISD::ADD, dl, getPointerTy(), Arg,
1649 DAG.getConstant(Ofst, getPointerTy()));
1650 SDValue P = DAG.getLoad(
1651 EltVT, dl, Root, SrcAddr, MachinePointerInfo(SrcValue), false,
1652 false, true,
1653 TD->getABITypeAlignment(EltVT.getTypeForEVT(F->getContext())));
1654 if (P.getNode())
1655 P.getNode()->setIROrder(idx + 1);
1656
Justin Holewinskif8f70912013-06-28 17:57:59 +0000[diff] [blame]1657 if (Ins[InsIdx].VT.getSizeInBits() > EltVT.getSizeInBits())
Justin Holewinskia2911282013-07-01 12:58:58 +0000[diff] [blame]1658 P = DAG.getNode(ISD::ANY_EXTEND, dl, Ins[InsIdx].VT, P);
Justin Holewinski44f5c602013-06-28 17:57:53 +0000[diff] [blame]1659 InVals.push_back(P);
1660 Ofst += TD->getTypeAllocSize(EltVT.getTypeForEVT(F->getContext()));
1661 ++InsIdx;
1662 } else if (NumElts == 2) {
1663 // V2 load
1664 // f32,f32 = load ...
1665 EVT VecVT = EVT::getVectorVT(F->getContext(), EltVT, 2);
1666 Value *SrcValue = Constant::getNullValue(PointerType::get(
1667 VecVT.getTypeForEVT(F->getContext()), llvm::ADDRESS_SPACE_PARAM));
1668 SDValue SrcAddr = DAG.getNode(ISD::ADD, dl, getPointerTy(), Arg,
1669 DAG.getConstant(Ofst, getPointerTy()));
1670 SDValue P = DAG.getLoad(
1671 VecVT, dl, Root, SrcAddr, MachinePointerInfo(SrcValue), false,
1672 false, true,
1673 TD->getABITypeAlignment(VecVT.getTypeForEVT(F->getContext())));
1674 if (P.getNode())
1675 P.getNode()->setIROrder(idx + 1);
1676
1677 SDValue Elt0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, P,
1678 DAG.getIntPtrConstant(0));
1679 SDValue Elt1 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, P,
1680 DAG.getIntPtrConstant(1));
Justin Holewinskif8f70912013-06-28 17:57:59 +0000[diff] [blame]1681
1682 if (Ins[InsIdx].VT.getSizeInBits() > EltVT.getSizeInBits()) {
Justin Holewinskia2911282013-07-01 12:58:58 +0000[diff] [blame]1683 Elt0 = DAG.getNode(ISD::ANY_EXTEND, dl, Ins[InsIdx].VT, Elt0);
1684 Elt1 = DAG.getNode(ISD::ANY_EXTEND, dl, Ins[InsIdx].VT, Elt1);
Justin Holewinskif8f70912013-06-28 17:57:59 +0000[diff] [blame]1685 }
1686
Justin Holewinski44f5c602013-06-28 17:57:53 +0000[diff] [blame]1687 InVals.push_back(Elt0);
1688 InVals.push_back(Elt1);
1689 Ofst += TD->getTypeAllocSize(VecVT.getTypeForEVT(F->getContext()));
1690 InsIdx += 2;
1691 } else {
1692 // V4 loads
1693 // We have at least 4 elements (<3 x Ty> expands to 4 elements) and
1694 // the
1695 // vector will be expanded to a power of 2 elements, so we know we can
1696 // always round up to the next multiple of 4 when creating the vector
1697 // loads.
1698 // e.g. 4 elem => 1 ld.v4
1699 // 6 elem => 2 ld.v4
1700 // 8 elem => 2 ld.v4
1701 // 11 elem => 3 ld.v4
1702 unsigned VecSize = 4;
1703 if (EltVT.getSizeInBits() == 64) {
1704 VecSize = 2;
1705 }
1706 EVT VecVT = EVT::getVectorVT(F->getContext(), EltVT, VecSize);
1707 for (unsigned i = 0; i < NumElts; i += VecSize) {
1708 Value *SrcValue = Constant::getNullValue(
1709 PointerType::get(VecVT.getTypeForEVT(F->getContext()),
1710 llvm::ADDRESS_SPACE_PARAM));
1711 SDValue SrcAddr =
1712 DAG.getNode(ISD::ADD, dl, getPointerTy(), Arg,
1713 DAG.getConstant(Ofst, getPointerTy()));
1714 SDValue P = DAG.getLoad(
1715 VecVT, dl, Root, SrcAddr, MachinePointerInfo(SrcValue), false,
1716 false, true,
1717 TD->getABITypeAlignment(VecVT.getTypeForEVT(F->getContext())));
1718 if (P.getNode())
1719 P.getNode()->setIROrder(idx + 1);
1720
1721 for (unsigned j = 0; j < VecSize; ++j) {
1722 if (i + j >= NumElts)
1723 break;
1724 SDValue Elt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, P,
1725 DAG.getIntPtrConstant(j));
Justin Holewinskif8f70912013-06-28 17:57:59 +0000[diff] [blame]1726 if (Ins[InsIdx].VT.getSizeInBits() > EltVT.getSizeInBits())
Justin Holewinskia2911282013-07-01 12:58:58 +0000[diff] [blame]1727 Elt = DAG.getNode(ISD::ANY_EXTEND, dl, Ins[InsIdx].VT, Elt);
Justin Holewinski44f5c602013-06-28 17:57:53 +0000[diff] [blame]1728 InVals.push_back(Elt);
1729 }
1730 Ofst += TD->getTypeAllocSize(VecVT.getTypeForEVT(F->getContext()));
Justin Holewinski44f5c602013-06-28 17:57:53 +0000[diff] [blame]1731 }
Justin Holewinski4f5bc9b2013-11-11 19:28:16 +0000[diff] [blame]1732 InsIdx += NumElts;
Justin Holewinski44f5c602013-06-28 17:57:53 +0000[diff] [blame]1733 }
1734
1735 if (NumElts > 0)
1736 --InsIdx;
1737 continue;
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]1738 }
Justin Holewinski44f5c602013-06-28 17:57:53 +0000[diff] [blame]1739 // A plain scalar.
1740 EVT ObjectVT = getValueType(Ty);
Justin Holewinski44f5c602013-06-28 17:57:53 +0000[diff] [blame]1741 // If ABI, load from the param symbol
1742 SDValue Arg = getParamSymbol(DAG, idx, getPointerTy());
1743 Value *srcValue = Constant::getNullValue(PointerType::get(
1744 ObjectVT.getTypeForEVT(F->getContext()), llvm::ADDRESS_SPACE_PARAM));
Justin Holewinskif8f70912013-06-28 17:57:59 +0000[diff] [blame]1745 SDValue p;
Justin Holewinskia2911282013-07-01 12:58:58 +0000[diff] [blame]1746 if (ObjectVT.getSizeInBits() < Ins[InsIdx].VT.getSizeInBits()) {
1747 ISD::LoadExtType ExtOp = Ins[InsIdx].Flags.isSExt() ?
1748 ISD::SEXTLOAD : ISD::ZEXTLOAD;
1749 p = DAG.getExtLoad(ExtOp, dl, Ins[InsIdx].VT, Root, Arg,
Justin Holewinskif8f70912013-06-28 17:57:59 +0000[diff] [blame]1750 MachinePointerInfo(srcValue), ObjectVT, false, false,
Justin Holewinskia2911282013-07-01 12:58:58 +0000[diff] [blame]1751 TD->getABITypeAlignment(ObjectVT.getTypeForEVT(F->getContext())));
1752 } else {
Justin Holewinskif8f70912013-06-28 17:57:59 +0000[diff] [blame]1753 p = DAG.getLoad(Ins[InsIdx].VT, dl, Root, Arg,
1754 MachinePointerInfo(srcValue), false, false, false,
Justin Holewinskia2911282013-07-01 12:58:58 +0000[diff] [blame]1755 TD->getABITypeAlignment(ObjectVT.getTypeForEVT(F->getContext())));
1756 }
Justin Holewinski44f5c602013-06-28 17:57:53 +0000[diff] [blame]1757 if (p.getNode())
1758 p.getNode()->setIROrder(idx + 1);
1759 InVals.push_back(p);
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]1760 continue;
1761 }
1762
1763 // Param has ByVal attribute
Justin Holewinski44f5c602013-06-28 17:57:53 +0000[diff] [blame]1764 // Return MoveParam(param symbol).
1765 // Ideally, the param symbol can be returned directly,
1766 // but when SDNode builder decides to use it in a CopyToReg(),
1767 // machine instruction fails because TargetExternalSymbol
1768 // (not lowered) is target dependent, and CopyToReg assumes
1769 // the source is lowered.
1770 EVT ObjectVT = getValueType(Ty);
1771 assert(ObjectVT == Ins[InsIdx].VT &&
1772 "Ins type did not match function type");
1773 SDValue Arg = getParamSymbol(DAG, idx, getPointerTy());
1774 SDValue p = DAG.getNode(NVPTXISD::MoveParam, dl, ObjectVT, Arg);
1775 if (p.getNode())
1776 p.getNode()->setIROrder(idx + 1);
1777 if (isKernel)
1778 InVals.push_back(p);
1779 else {
1780 SDValue p2 = DAG.getNode(
1781 ISD::INTRINSIC_WO_CHAIN, dl, ObjectVT,
1782 DAG.getConstant(Intrinsic::nvvm_ptr_local_to_gen, MVT::i32), p);
1783 InVals.push_back(p2);
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]1784 }
1785 }
1786
1787 // Clang will check explicit VarArg and issue error if any. However, Clang
1788 // will let code with
Justin Holewinski44f5c602013-06-28 17:57:53 +0000[diff] [blame]1789 // implicit var arg like f() pass. See bug 617733.
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]1790 // We treat this case as if the arg list is empty.
Justin Holewinski44f5c602013-06-28 17:57:53 +0000[diff] [blame]1791 // if (F.isVarArg()) {
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]1792 // assert(0 && "VarArg not supported yet!");
1793 //}
1794
1795 if (!OutChains.empty())
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]1796 DAG.setRoot(DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &OutChains[0],
1797 OutChains.size()));
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]1798
1799 return Chain;
1800}
1801
Justin Holewinski44f5c602013-06-28 17:57:53 +0000[diff] [blame]1802
Justin Holewinski120baee2013-06-28 17:57:55 +0000[diff] [blame]1803SDValue
1804NVPTXTargetLowering::LowerReturn(SDValue Chain, CallingConv::ID CallConv,
1805 bool isVarArg,
1806 const SmallVectorImpl<ISD::OutputArg> &Outs,
1807 const SmallVectorImpl<SDValue> &OutVals,
1808 SDLoc dl, SelectionDAG &DAG) const {
1809 MachineFunction &MF = DAG.getMachineFunction();
1810 const Function *F = MF.getFunction();
Justin Holewinskie04e4bd2013-06-28 17:58:10 +0000[diff] [blame]1811 Type *RetTy = F->getReturnType();
Justin Holewinski120baee2013-06-28 17:57:55 +0000[diff] [blame]1812 const DataLayout *TD = getDataLayout();
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]1813
1814 bool isABI = (nvptxSubtarget.getSmVersion() >= 20);
Justin Holewinski120baee2013-06-28 17:57:55 +0000[diff] [blame]1815 assert(isABI && "Non-ABI compilation is not supported");
1816 if (!isABI)
1817 return Chain;
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]1818
Justin Holewinskie04e4bd2013-06-28 17:58:10 +0000[diff] [blame]1819 if (VectorType *VTy = dyn_cast<VectorType>(RetTy)) {
Justin Holewinski120baee2013-06-28 17:57:55 +0000[diff] [blame]1820 // If we have a vector type, the OutVals array will be the scalarized
1821 // components and we have combine them into 1 or more vector stores.
1822 unsigned NumElts = VTy->getNumElements();
1823 assert(NumElts == Outs.size() && "Bad scalarization of return value");
1824
Justin Holewinskif8f70912013-06-28 17:57:59 +0000[diff] [blame]1825 // const_cast can be removed in later LLVM versions
Justin Holewinskie04e4bd2013-06-28 17:58:10 +0000[diff] [blame]1826 EVT EltVT = getValueType(RetTy).getVectorElementType();
Justin Holewinskif8f70912013-06-28 17:57:59 +0000[diff] [blame]1827 bool NeedExtend = false;
1828 if (EltVT.getSizeInBits() < 16)
1829 NeedExtend = true;
1830
Justin Holewinski120baee2013-06-28 17:57:55 +0000[diff] [blame]1831 // V1 store
1832 if (NumElts == 1) {
1833 SDValue StoreVal = OutVals[0];
1834 // We only have one element, so just directly store it
Justin Holewinskif8f70912013-06-28 17:57:59 +0000[diff] [blame]1835 if (NeedExtend)
1836 StoreVal = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, StoreVal);
1837 SDValue Ops[] = { Chain, DAG.getConstant(0, MVT::i32), StoreVal };
1838 Chain = DAG.getMemIntrinsicNode(NVPTXISD::StoreRetval, dl,
1839 DAG.getVTList(MVT::Other), &Ops[0], 3,
1840 EltVT, MachinePointerInfo());
1841
Justin Holewinski120baee2013-06-28 17:57:55 +0000[diff] [blame]1842 } else if (NumElts == 2) {
1843 // V2 store
1844 SDValue StoreVal0 = OutVals[0];
1845 SDValue StoreVal1 = OutVals[1];
1846
Justin Holewinskif8f70912013-06-28 17:57:59 +0000[diff] [blame]1847 if (NeedExtend) {
1848 StoreVal0 = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, StoreVal0);
1849 StoreVal1 = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, StoreVal1);
Justin Holewinski120baee2013-06-28 17:57:55 +0000[diff] [blame]1850 }
1851
Justin Holewinskif8f70912013-06-28 17:57:59 +0000[diff] [blame]1852 SDValue Ops[] = { Chain, DAG.getConstant(0, MVT::i32), StoreVal0,
1853 StoreVal1 };
1854 Chain = DAG.getMemIntrinsicNode(NVPTXISD::StoreRetvalV2, dl,
1855 DAG.getVTList(MVT::Other), &Ops[0], 4,
1856 EltVT, MachinePointerInfo());
Justin Holewinski120baee2013-06-28 17:57:55 +0000[diff] [blame]1857 } else {
1858 // V4 stores
1859 // We have at least 4 elements (<3 x Ty> expands to 4 elements) and the
1860 // vector will be expanded to a power of 2 elements, so we know we can
1861 // always round up to the next multiple of 4 when creating the vector
1862 // stores.
1863 // e.g. 4 elem => 1 st.v4
1864 // 6 elem => 2 st.v4
1865 // 8 elem => 2 st.v4
1866 // 11 elem => 3 st.v4
1867
1868 unsigned VecSize = 4;
1869 if (OutVals[0].getValueType().getSizeInBits() == 64)
1870 VecSize = 2;
1871
1872 unsigned Offset = 0;
1873
1874 EVT VecVT =
1875 EVT::getVectorVT(F->getContext(), OutVals[0].getValueType(), VecSize);
1876 unsigned PerStoreOffset =
1877 TD->getTypeAllocSize(VecVT.getTypeForEVT(F->getContext()));
1878
Justin Holewinski120baee2013-06-28 17:57:55 +0000[diff] [blame]1879 for (unsigned i = 0; i < NumElts; i += VecSize) {
1880 // Get values
1881 SDValue StoreVal;
1882 SmallVector<SDValue, 8> Ops;
1883 Ops.push_back(Chain);
1884 Ops.push_back(DAG.getConstant(Offset, MVT::i32));
1885 unsigned Opc = NVPTXISD::StoreRetvalV2;
Justin Holewinskif8f70912013-06-28 17:57:59 +0000[diff] [blame]1886 EVT ExtendedVT = (NeedExtend) ? MVT::i16 : OutVals[0].getValueType();
Justin Holewinski120baee2013-06-28 17:57:55 +0000[diff] [blame]1887
1888 StoreVal = OutVals[i];
Justin Holewinskif8f70912013-06-28 17:57:59 +0000[diff] [blame]1889 if (NeedExtend)
1890 StoreVal = DAG.getNode(ISD::ZERO_EXTEND, dl, ExtendedVT, StoreVal);
Justin Holewinski120baee2013-06-28 17:57:55 +0000[diff] [blame]1891 Ops.push_back(StoreVal);
1892
1893 if (i + 1 < NumElts) {
1894 StoreVal = OutVals[i + 1];
Justin Holewinskif8f70912013-06-28 17:57:59 +0000[diff] [blame]1895 if (NeedExtend)
1896 StoreVal = DAG.getNode(ISD::ZERO_EXTEND, dl, ExtendedVT, StoreVal);
Justin Holewinski120baee2013-06-28 17:57:55 +0000[diff] [blame]1897 } else {
1898 StoreVal = DAG.getUNDEF(ExtendedVT);
1899 }
1900 Ops.push_back(StoreVal);
1901
1902 if (VecSize == 4) {
1903 Opc = NVPTXISD::StoreRetvalV4;
1904 if (i + 2 < NumElts) {
1905 StoreVal = OutVals[i + 2];
Justin Holewinskif8f70912013-06-28 17:57:59 +0000[diff] [blame]1906 if (NeedExtend)
1907 StoreVal =
1908 DAG.getNode(ISD::ZERO_EXTEND, dl, ExtendedVT, StoreVal);
Justin Holewinski120baee2013-06-28 17:57:55 +0000[diff] [blame]1909 } else {
1910 StoreVal = DAG.getUNDEF(ExtendedVT);
1911 }
1912 Ops.push_back(StoreVal);
1913
1914 if (i + 3 < NumElts) {
1915 StoreVal = OutVals[i + 3];
Justin Holewinskif8f70912013-06-28 17:57:59 +0000[diff] [blame]1916 if (NeedExtend)
1917 StoreVal =
1918 DAG.getNode(ISD::ZERO_EXTEND, dl, ExtendedVT, StoreVal);
Justin Holewinski120baee2013-06-28 17:57:55 +0000[diff] [blame]1919 } else {
1920 StoreVal = DAG.getUNDEF(ExtendedVT);
1921 }
1922 Ops.push_back(StoreVal);
1923 }
1924
Justin Holewinskif8f70912013-06-28 17:57:59 +0000[diff] [blame]1925 // Chain = DAG.getNode(Opc, dl, MVT::Other, &Ops[0], Ops.size());
1926 Chain =
1927 DAG.getMemIntrinsicNode(Opc, dl, DAG.getVTList(MVT::Other), &Ops[0],
1928 Ops.size(), EltVT, MachinePointerInfo());
Justin Holewinski120baee2013-06-28 17:57:55 +0000[diff] [blame]1929 Offset += PerStoreOffset;
1930 }
1931 }
1932 } else {
Justin Holewinskif8f70912013-06-28 17:57:59 +0000[diff] [blame]1933 SmallVector<EVT, 16> ValVTs;
1934 // const_cast is necessary since we are still using an LLVM version from
1935 // before the type system re-write.
Justin Holewinskie04e4bd2013-06-28 17:58:10 +0000[diff] [blame]1936 ComputePTXValueVTs(*this, RetTy, ValVTs);
Justin Holewinskif8f70912013-06-28 17:57:59 +0000[diff] [blame]1937 assert(ValVTs.size() == OutVals.size() && "Bad return value decomposition");
1938
Justin Holewinskie04e4bd2013-06-28 17:58:10 +0000[diff] [blame]1939 unsigned SizeSoFar = 0;
Justin Holewinski120baee2013-06-28 17:57:55 +0000[diff] [blame]1940 for (unsigned i = 0, e = Outs.size(); i != e; ++i) {
1941 SDValue theVal = OutVals[i];
Justin Holewinskie04e4bd2013-06-28 17:58:10 +0000[diff] [blame]1942 EVT TheValType = theVal.getValueType();
Justin Holewinski120baee2013-06-28 17:57:55 +0000[diff] [blame]1943 unsigned numElems = 1;
Justin Holewinskie04e4bd2013-06-28 17:58:10 +0000[diff] [blame]1944 if (TheValType.isVector())
1945 numElems = TheValType.getVectorNumElements();
Justin Holewinski120baee2013-06-28 17:57:55 +0000[diff] [blame]1946 for (unsigned j = 0, je = numElems; j != je; ++j) {
Justin Holewinskie04e4bd2013-06-28 17:58:10 +0000[diff] [blame]1947 SDValue TmpVal = theVal;
1948 if (TheValType.isVector())
1949 TmpVal = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
1950 TheValType.getVectorElementType(), TmpVal,
Justin Holewinski120baee2013-06-28 17:57:55 +0000[diff] [blame]1951 DAG.getIntPtrConstant(j));
Justin Holewinskie04e4bd2013-06-28 17:58:10 +0000[diff] [blame]1952 EVT TheStoreType = ValVTs[i];
1953 if (RetTy->isIntegerTy() &&
1954 TD->getTypeAllocSizeInBits(RetTy) < 32) {
1955 // The following zero-extension is for integer types only, and
1956 // specifically not for aggregates.
1957 TmpVal = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, TmpVal);
1958 TheStoreType = MVT::i32;
1959 }
1960 else if (TmpVal.getValueType().getSizeInBits() < 16)
1961 TmpVal = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i16, TmpVal);
1962
1963 SDValue Ops[] = { Chain, DAG.getConstant(SizeSoFar, MVT::i32), TmpVal };
Justin Holewinskif8f70912013-06-28 17:57:59 +0000[diff] [blame]1964 Chain = DAG.getMemIntrinsicNode(NVPTXISD::StoreRetval, dl,
Justin Holewinskie04e4bd2013-06-28 17:58:10 +0000[diff] [blame]1965 DAG.getVTList(MVT::Other), &Ops[0],
1966 3, TheStoreType,
1967 MachinePointerInfo());
1968 if(TheValType.isVector())
1969 SizeSoFar +=
1970 TheStoreType.getVectorElementType().getStoreSizeInBits() / 8;
Justin Holewinski120baee2013-06-28 17:57:55 +0000[diff] [blame]1971 else
Justin Holewinskie04e4bd2013-06-28 17:58:10 +0000[diff] [blame]1972 SizeSoFar += TheStoreType.getStoreSizeInBits()/8;
Justin Holewinski120baee2013-06-28 17:57:55 +0000[diff] [blame]1973 }
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]1974 }
1975 }
1976
1977 return DAG.getNode(NVPTXISD::RET_FLAG, dl, MVT::Other, Chain);
1978}
1979
Justin Holewinskif8f70912013-06-28 17:57:59 +0000[diff] [blame]1980
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]1981void NVPTXTargetLowering::LowerAsmOperandForConstraint(
1982 SDValue Op, std::string &Constraint, std::vector<SDValue> &Ops,
1983 SelectionDAG &DAG) const {
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]1984 if (Constraint.length() > 1)
1985 return;
1986 else
1987 TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
1988}
1989
1990// NVPTX suuport vector of legal types of any length in Intrinsics because the
1991// NVPTX specific type legalizer
1992// will legalize them to the PTX supported length.
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]1993bool NVPTXTargetLowering::isTypeSupportedInIntrinsic(MVT VT) const {
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]1994 if (isTypeLegal(VT))
1995 return true;
1996 if (VT.isVector()) {
1997 MVT eVT = VT.getVectorElementType();
1998 if (isTypeLegal(eVT))
1999 return true;
2000 }
2001 return false;
2002}
2003
Justin Holewinski30d56a72014-04-09 15:39:15 +0000[diff] [blame]2004static unsigned getOpcForTextureInstr(unsigned Intrinsic) {
2005 switch (Intrinsic) {
2006 default:
2007 return 0;
2008
2009 case Intrinsic::nvvm_tex_1d_v4f32_i32:
2010 return NVPTXISD::Tex1DFloatI32;
2011 case Intrinsic::nvvm_tex_1d_v4f32_f32:
2012 return NVPTXISD::Tex1DFloatFloat;
2013 case Intrinsic::nvvm_tex_1d_level_v4f32_f32:
2014 return NVPTXISD::Tex1DFloatFloatLevel;
2015 case Intrinsic::nvvm_tex_1d_grad_v4f32_f32:
2016 return NVPTXISD::Tex1DFloatFloatGrad;
2017 case Intrinsic::nvvm_tex_1d_v4i32_i32:
2018 return NVPTXISD::Tex1DI32I32;
2019 case Intrinsic::nvvm_tex_1d_v4i32_f32:
2020 return NVPTXISD::Tex1DI32Float;
2021 case Intrinsic::nvvm_tex_1d_level_v4i32_f32:
2022 return NVPTXISD::Tex1DI32FloatLevel;
2023 case Intrinsic::nvvm_tex_1d_grad_v4i32_f32:
2024 return NVPTXISD::Tex1DI32FloatGrad;
2025
2026 case Intrinsic::nvvm_tex_1d_array_v4f32_i32:
2027 return NVPTXISD::Tex1DArrayFloatI32;
2028 case Intrinsic::nvvm_tex_1d_array_v4f32_f32:
2029 return NVPTXISD::Tex1DArrayFloatFloat;
2030 case Intrinsic::nvvm_tex_1d_array_level_v4f32_f32:
2031 return NVPTXISD::Tex1DArrayFloatFloatLevel;
2032 case Intrinsic::nvvm_tex_1d_array_grad_v4f32_f32:
2033 return NVPTXISD::Tex1DArrayFloatFloatGrad;
2034 case Intrinsic::nvvm_tex_1d_array_v4i32_i32:
2035 return NVPTXISD::Tex1DArrayI32I32;
2036 case Intrinsic::nvvm_tex_1d_array_v4i32_f32:
2037 return NVPTXISD::Tex1DArrayI32Float;
2038 case Intrinsic::nvvm_tex_1d_array_level_v4i32_f32:
2039 return NVPTXISD::Tex1DArrayI32FloatLevel;
2040 case Intrinsic::nvvm_tex_1d_array_grad_v4i32_f32:
2041 return NVPTXISD::Tex1DArrayI32FloatGrad;
2042
2043 case Intrinsic::nvvm_tex_2d_v4f32_i32:
2044 return NVPTXISD::Tex2DFloatI32;
2045 case Intrinsic::nvvm_tex_2d_v4f32_f32:
2046 return NVPTXISD::Tex2DFloatFloat;
2047 case Intrinsic::nvvm_tex_2d_level_v4f32_f32:
2048 return NVPTXISD::Tex2DFloatFloatLevel;
2049 case Intrinsic::nvvm_tex_2d_grad_v4f32_f32:
2050 return NVPTXISD::Tex2DFloatFloatGrad;
2051 case Intrinsic::nvvm_tex_2d_v4i32_i32:
2052 return NVPTXISD::Tex2DI32I32;
2053 case Intrinsic::nvvm_tex_2d_v4i32_f32:
2054 return NVPTXISD::Tex2DI32Float;
2055 case Intrinsic::nvvm_tex_2d_level_v4i32_f32:
2056 return NVPTXISD::Tex2DI32FloatLevel;
2057 case Intrinsic::nvvm_tex_2d_grad_v4i32_f32:
2058 return NVPTXISD::Tex2DI32FloatGrad;
2059
2060 case Intrinsic::nvvm_tex_2d_array_v4f32_i32:
2061 return NVPTXISD::Tex2DArrayFloatI32;
2062 case Intrinsic::nvvm_tex_2d_array_v4f32_f32:
2063 return NVPTXISD::Tex2DArrayFloatFloat;
2064 case Intrinsic::nvvm_tex_2d_array_level_v4f32_f32:
2065 return NVPTXISD::Tex2DArrayFloatFloatLevel;
2066 case Intrinsic::nvvm_tex_2d_array_grad_v4f32_f32:
2067 return NVPTXISD::Tex2DArrayFloatFloatGrad;
2068 case Intrinsic::nvvm_tex_2d_array_v4i32_i32:
2069 return NVPTXISD::Tex2DArrayI32I32;
2070 case Intrinsic::nvvm_tex_2d_array_v4i32_f32:
2071 return NVPTXISD::Tex2DArrayI32Float;
2072 case Intrinsic::nvvm_tex_2d_array_level_v4i32_f32:
2073 return NVPTXISD::Tex2DArrayI32FloatLevel;
2074 case Intrinsic::nvvm_tex_2d_array_grad_v4i32_f32:
2075 return NVPTXISD::Tex2DArrayI32FloatGrad;
2076
2077 case Intrinsic::nvvm_tex_3d_v4f32_i32:
2078 return NVPTXISD::Tex3DFloatI32;
2079 case Intrinsic::nvvm_tex_3d_v4f32_f32:
2080 return NVPTXISD::Tex3DFloatFloat;
2081 case Intrinsic::nvvm_tex_3d_level_v4f32_f32:
2082 return NVPTXISD::Tex3DFloatFloatLevel;
2083 case Intrinsic::nvvm_tex_3d_grad_v4f32_f32:
2084 return NVPTXISD::Tex3DFloatFloatGrad;
2085 case Intrinsic::nvvm_tex_3d_v4i32_i32:
2086 return NVPTXISD::Tex3DI32I32;
2087 case Intrinsic::nvvm_tex_3d_v4i32_f32:
2088 return NVPTXISD::Tex3DI32Float;
2089 case Intrinsic::nvvm_tex_3d_level_v4i32_f32:
2090 return NVPTXISD::Tex3DI32FloatLevel;
2091 case Intrinsic::nvvm_tex_3d_grad_v4i32_f32:
2092 return NVPTXISD::Tex3DI32FloatGrad;
2093 }
2094}
2095
2096static unsigned getOpcForSurfaceInstr(unsigned Intrinsic) {
2097 switch (Intrinsic) {
2098 default:
2099 return 0;
2100 case Intrinsic::nvvm_suld_1d_i8_trap:
2101 return NVPTXISD::Suld1DI8Trap;
2102 case Intrinsic::nvvm_suld_1d_i16_trap:
2103 return NVPTXISD::Suld1DI16Trap;
2104 case Intrinsic::nvvm_suld_1d_i32_trap:
2105 return NVPTXISD::Suld1DI32Trap;
2106 case Intrinsic::nvvm_suld_1d_v2i8_trap:
2107 return NVPTXISD::Suld1DV2I8Trap;
2108 case Intrinsic::nvvm_suld_1d_v2i16_trap:
2109 return NVPTXISD::Suld1DV2I16Trap;
2110 case Intrinsic::nvvm_suld_1d_v2i32_trap:
2111 return NVPTXISD::Suld1DV2I32Trap;
2112 case Intrinsic::nvvm_suld_1d_v4i8_trap:
2113 return NVPTXISD::Suld1DV4I8Trap;
2114 case Intrinsic::nvvm_suld_1d_v4i16_trap:
2115 return NVPTXISD::Suld1DV4I16Trap;
2116 case Intrinsic::nvvm_suld_1d_v4i32_trap:
2117 return NVPTXISD::Suld1DV4I32Trap;
2118 case Intrinsic::nvvm_suld_1d_array_i8_trap:
2119 return NVPTXISD::Suld1DArrayI8Trap;
2120 case Intrinsic::nvvm_suld_1d_array_i16_trap:
2121 return NVPTXISD::Suld1DArrayI16Trap;
2122 case Intrinsic::nvvm_suld_1d_array_i32_trap:
2123 return NVPTXISD::Suld1DArrayI32Trap;
2124 case Intrinsic::nvvm_suld_1d_array_v2i8_trap:
2125 return NVPTXISD::Suld1DArrayV2I8Trap;
2126 case Intrinsic::nvvm_suld_1d_array_v2i16_trap:
2127 return NVPTXISD::Suld1DArrayV2I16Trap;
2128 case Intrinsic::nvvm_suld_1d_array_v2i32_trap:
2129 return NVPTXISD::Suld1DArrayV2I32Trap;
2130 case Intrinsic::nvvm_suld_1d_array_v4i8_trap:
2131 return NVPTXISD::Suld1DArrayV4I8Trap;
2132 case Intrinsic::nvvm_suld_1d_array_v4i16_trap:
2133 return NVPTXISD::Suld1DArrayV4I16Trap;
2134 case Intrinsic::nvvm_suld_1d_array_v4i32_trap:
2135 return NVPTXISD::Suld1DArrayV4I32Trap;
2136 case Intrinsic::nvvm_suld_2d_i8_trap:
2137 return NVPTXISD::Suld2DI8Trap;
2138 case Intrinsic::nvvm_suld_2d_i16_trap:
2139 return NVPTXISD::Suld2DI16Trap;
2140 case Intrinsic::nvvm_suld_2d_i32_trap:
2141 return NVPTXISD::Suld2DI32Trap;
2142 case Intrinsic::nvvm_suld_2d_v2i8_trap:
2143 return NVPTXISD::Suld2DV2I8Trap;
2144 case Intrinsic::nvvm_suld_2d_v2i16_trap:
2145 return NVPTXISD::Suld2DV2I16Trap;
2146 case Intrinsic::nvvm_suld_2d_v2i32_trap:
2147 return NVPTXISD::Suld2DV2I32Trap;
2148 case Intrinsic::nvvm_suld_2d_v4i8_trap:
2149 return NVPTXISD::Suld2DV4I8Trap;
2150 case Intrinsic::nvvm_suld_2d_v4i16_trap:
2151 return NVPTXISD::Suld2DV4I16Trap;
2152 case Intrinsic::nvvm_suld_2d_v4i32_trap:
2153 return NVPTXISD::Suld2DV4I32Trap;
2154 case Intrinsic::nvvm_suld_2d_array_i8_trap:
2155 return NVPTXISD::Suld2DArrayI8Trap;
2156 case Intrinsic::nvvm_suld_2d_array_i16_trap:
2157 return NVPTXISD::Suld2DArrayI16Trap;
2158 case Intrinsic::nvvm_suld_2d_array_i32_trap:
2159 return NVPTXISD::Suld2DArrayI32Trap;
2160 case Intrinsic::nvvm_suld_2d_array_v2i8_trap:
2161 return NVPTXISD::Suld2DArrayV2I8Trap;
2162 case Intrinsic::nvvm_suld_2d_array_v2i16_trap:
2163 return NVPTXISD::Suld2DArrayV2I16Trap;
2164 case Intrinsic::nvvm_suld_2d_array_v2i32_trap:
2165 return NVPTXISD::Suld2DArrayV2I32Trap;
2166 case Intrinsic::nvvm_suld_2d_array_v4i8_trap:
2167 return NVPTXISD::Suld2DArrayV4I8Trap;
2168 case Intrinsic::nvvm_suld_2d_array_v4i16_trap:
2169 return NVPTXISD::Suld2DArrayV4I16Trap;
2170 case Intrinsic::nvvm_suld_2d_array_v4i32_trap:
2171 return NVPTXISD::Suld2DArrayV4I32Trap;
2172 case Intrinsic::nvvm_suld_3d_i8_trap:
2173 return NVPTXISD::Suld3DI8Trap;
2174 case Intrinsic::nvvm_suld_3d_i16_trap:
2175 return NVPTXISD::Suld3DI16Trap;
2176 case Intrinsic::nvvm_suld_3d_i32_trap:
2177 return NVPTXISD::Suld3DI32Trap;
2178 case Intrinsic::nvvm_suld_3d_v2i8_trap:
2179 return NVPTXISD::Suld3DV2I8Trap;
2180 case Intrinsic::nvvm_suld_3d_v2i16_trap:
2181 return NVPTXISD::Suld3DV2I16Trap;
2182 case Intrinsic::nvvm_suld_3d_v2i32_trap:
2183 return NVPTXISD::Suld3DV2I32Trap;
2184 case Intrinsic::nvvm_suld_3d_v4i8_trap:
2185 return NVPTXISD::Suld3DV4I8Trap;
2186 case Intrinsic::nvvm_suld_3d_v4i16_trap:
2187 return NVPTXISD::Suld3DV4I16Trap;
2188 case Intrinsic::nvvm_suld_3d_v4i32_trap:
2189 return NVPTXISD::Suld3DV4I32Trap;
2190 }
2191}
2192
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]2193// llvm.ptx.memcpy.const and llvm.ptx.memmove.const need to be modeled as
2194// TgtMemIntrinsic
2195// because we need the information that is only available in the "Value" type
2196// of destination
2197// pointer. In particular, the address space information.
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]2198bool NVPTXTargetLowering::getTgtMemIntrinsic(
2199 IntrinsicInfo &Info, const CallInst &I, unsigned Intrinsic) const {
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]2200 switch (Intrinsic) {
2201 default:
2202 return false;
2203
2204 case Intrinsic::nvvm_atomic_load_add_f32:
2205 Info.opc = ISD::INTRINSIC_W_CHAIN;
2206 Info.memVT = MVT::f32;
2207 Info.ptrVal = I.getArgOperand(0);
2208 Info.offset = 0;
2209 Info.vol = 0;
2210 Info.readMem = true;
2211 Info.writeMem = true;
2212 Info.align = 0;
2213 return true;
2214
2215 case Intrinsic::nvvm_atomic_load_inc_32:
2216 case Intrinsic::nvvm_atomic_load_dec_32:
2217 Info.opc = ISD::INTRINSIC_W_CHAIN;
2218 Info.memVT = MVT::i32;
2219 Info.ptrVal = I.getArgOperand(0);
2220 Info.offset = 0;
2221 Info.vol = 0;
2222 Info.readMem = true;
2223 Info.writeMem = true;
2224 Info.align = 0;
2225 return true;
2226
2227 case Intrinsic::nvvm_ldu_global_i:
2228 case Intrinsic::nvvm_ldu_global_f:
2229 case Intrinsic::nvvm_ldu_global_p:
2230
2231 Info.opc = ISD::INTRINSIC_W_CHAIN;
2232 if (Intrinsic == Intrinsic::nvvm_ldu_global_i)
Justin Holewinskif8f70912013-06-28 17:57:59 +0000[diff] [blame]2233 Info.memVT = getValueType(I.getType());
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]2234 else if (Intrinsic == Intrinsic::nvvm_ldu_global_p)
Justin Holewinskif8f70912013-06-28 17:57:59 +0000[diff] [blame]2235 Info.memVT = getValueType(I.getType());
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]2236 else
2237 Info.memVT = MVT::f32;
2238 Info.ptrVal = I.getArgOperand(0);
2239 Info.offset = 0;
2240 Info.vol = 0;
2241 Info.readMem = true;
2242 Info.writeMem = false;
2243 Info.align = 0;
2244 return true;
2245
Justin Holewinski30d56a72014-04-09 15:39:15 +0000[diff] [blame]2246 case Intrinsic::nvvm_tex_1d_v4f32_i32:
2247 case Intrinsic::nvvm_tex_1d_v4f32_f32:
2248 case Intrinsic::nvvm_tex_1d_level_v4f32_f32:
2249 case Intrinsic::nvvm_tex_1d_grad_v4f32_f32:
2250 case Intrinsic::nvvm_tex_1d_array_v4f32_i32:
2251 case Intrinsic::nvvm_tex_1d_array_v4f32_f32:
2252 case Intrinsic::nvvm_tex_1d_array_level_v4f32_f32:
2253 case Intrinsic::nvvm_tex_1d_array_grad_v4f32_f32:
2254 case Intrinsic::nvvm_tex_2d_v4f32_i32:
2255 case Intrinsic::nvvm_tex_2d_v4f32_f32:
2256 case Intrinsic::nvvm_tex_2d_level_v4f32_f32:
2257 case Intrinsic::nvvm_tex_2d_grad_v4f32_f32:
2258 case Intrinsic::nvvm_tex_2d_array_v4f32_i32:
2259 case Intrinsic::nvvm_tex_2d_array_v4f32_f32:
2260 case Intrinsic::nvvm_tex_2d_array_level_v4f32_f32:
2261 case Intrinsic::nvvm_tex_2d_array_grad_v4f32_f32:
2262 case Intrinsic::nvvm_tex_3d_v4f32_i32:
2263 case Intrinsic::nvvm_tex_3d_v4f32_f32:
2264 case Intrinsic::nvvm_tex_3d_level_v4f32_f32:
2265 case Intrinsic::nvvm_tex_3d_grad_v4f32_f32: {
2266 Info.opc = getOpcForTextureInstr(Intrinsic);
2267 Info.memVT = MVT::f32;
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame^]2268 Info.ptrVal = nullptr;
Justin Holewinski30d56a72014-04-09 15:39:15 +0000[diff] [blame]2269 Info.offset = 0;
2270 Info.vol = 0;
2271 Info.readMem = true;
2272 Info.writeMem = false;
2273 Info.align = 16;
2274 return true;
2275 }
2276 case Intrinsic::nvvm_tex_1d_v4i32_i32:
2277 case Intrinsic::nvvm_tex_1d_v4i32_f32:
2278 case Intrinsic::nvvm_tex_1d_level_v4i32_f32:
2279 case Intrinsic::nvvm_tex_1d_grad_v4i32_f32:
2280 case Intrinsic::nvvm_tex_1d_array_v4i32_i32:
2281 case Intrinsic::nvvm_tex_1d_array_v4i32_f32:
2282 case Intrinsic::nvvm_tex_1d_array_level_v4i32_f32:
2283 case Intrinsic::nvvm_tex_1d_array_grad_v4i32_f32:
2284 case Intrinsic::nvvm_tex_2d_v4i32_i32:
2285 case Intrinsic::nvvm_tex_2d_v4i32_f32:
2286 case Intrinsic::nvvm_tex_2d_level_v4i32_f32:
2287 case Intrinsic::nvvm_tex_2d_grad_v4i32_f32:
2288 case Intrinsic::nvvm_tex_2d_array_v4i32_i32:
2289 case Intrinsic::nvvm_tex_2d_array_v4i32_f32:
2290 case Intrinsic::nvvm_tex_2d_array_level_v4i32_f32:
2291 case Intrinsic::nvvm_tex_2d_array_grad_v4i32_f32:
2292 case Intrinsic::nvvm_tex_3d_v4i32_i32:
2293 case Intrinsic::nvvm_tex_3d_v4i32_f32:
2294 case Intrinsic::nvvm_tex_3d_level_v4i32_f32:
2295 case Intrinsic::nvvm_tex_3d_grad_v4i32_f32: {
2296 Info.opc = getOpcForTextureInstr(Intrinsic);
2297 Info.memVT = MVT::i32;
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame^]2298 Info.ptrVal = nullptr;
Justin Holewinski30d56a72014-04-09 15:39:15 +0000[diff] [blame]2299 Info.offset = 0;
2300 Info.vol = 0;
2301 Info.readMem = true;
2302 Info.writeMem = false;
2303 Info.align = 16;
2304 return true;
2305 }
2306 case Intrinsic::nvvm_suld_1d_i8_trap:
2307 case Intrinsic::nvvm_suld_1d_v2i8_trap:
2308 case Intrinsic::nvvm_suld_1d_v4i8_trap:
2309 case Intrinsic::nvvm_suld_1d_array_i8_trap:
2310 case Intrinsic::nvvm_suld_1d_array_v2i8_trap:
2311 case Intrinsic::nvvm_suld_1d_array_v4i8_trap:
2312 case Intrinsic::nvvm_suld_2d_i8_trap:
2313 case Intrinsic::nvvm_suld_2d_v2i8_trap:
2314 case Intrinsic::nvvm_suld_2d_v4i8_trap:
2315 case Intrinsic::nvvm_suld_2d_array_i8_trap:
2316 case Intrinsic::nvvm_suld_2d_array_v2i8_trap:
2317 case Intrinsic::nvvm_suld_2d_array_v4i8_trap:
2318 case Intrinsic::nvvm_suld_3d_i8_trap:
2319 case Intrinsic::nvvm_suld_3d_v2i8_trap:
2320 case Intrinsic::nvvm_suld_3d_v4i8_trap: {
2321 Info.opc = getOpcForSurfaceInstr(Intrinsic);
2322 Info.memVT = MVT::i8;
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame^]2323 Info.ptrVal = nullptr;
Justin Holewinski30d56a72014-04-09 15:39:15 +0000[diff] [blame]2324 Info.offset = 0;
2325 Info.vol = 0;
2326 Info.readMem = true;
2327 Info.writeMem = false;
2328 Info.align = 16;
2329 return true;
2330 }
2331 case Intrinsic::nvvm_suld_1d_i16_trap:
2332 case Intrinsic::nvvm_suld_1d_v2i16_trap:
2333 case Intrinsic::nvvm_suld_1d_v4i16_trap:
2334 case Intrinsic::nvvm_suld_1d_array_i16_trap:
2335 case Intrinsic::nvvm_suld_1d_array_v2i16_trap:
2336 case Intrinsic::nvvm_suld_1d_array_v4i16_trap:
2337 case Intrinsic::nvvm_suld_2d_i16_trap:
2338 case Intrinsic::nvvm_suld_2d_v2i16_trap:
2339 case Intrinsic::nvvm_suld_2d_v4i16_trap:
2340 case Intrinsic::nvvm_suld_2d_array_i16_trap:
2341 case Intrinsic::nvvm_suld_2d_array_v2i16_trap:
2342 case Intrinsic::nvvm_suld_2d_array_v4i16_trap:
2343 case Intrinsic::nvvm_suld_3d_i16_trap:
2344 case Intrinsic::nvvm_suld_3d_v2i16_trap:
2345 case Intrinsic::nvvm_suld_3d_v4i16_trap: {
2346 Info.opc = getOpcForSurfaceInstr(Intrinsic);
2347 Info.memVT = MVT::i16;
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame^]2348 Info.ptrVal = nullptr;
Justin Holewinski30d56a72014-04-09 15:39:15 +0000[diff] [blame]2349 Info.offset = 0;
2350 Info.vol = 0;
2351 Info.readMem = true;
2352 Info.writeMem = false;
2353 Info.align = 16;
2354 return true;
2355 }
2356 case Intrinsic::nvvm_suld_1d_i32_trap:
2357 case Intrinsic::nvvm_suld_1d_v2i32_trap:
2358 case Intrinsic::nvvm_suld_1d_v4i32_trap:
2359 case Intrinsic::nvvm_suld_1d_array_i32_trap:
2360 case Intrinsic::nvvm_suld_1d_array_v2i32_trap:
2361 case Intrinsic::nvvm_suld_1d_array_v4i32_trap:
2362 case Intrinsic::nvvm_suld_2d_i32_trap:
2363 case Intrinsic::nvvm_suld_2d_v2i32_trap:
2364 case Intrinsic::nvvm_suld_2d_v4i32_trap:
2365 case Intrinsic::nvvm_suld_2d_array_i32_trap:
2366 case Intrinsic::nvvm_suld_2d_array_v2i32_trap:
2367 case Intrinsic::nvvm_suld_2d_array_v4i32_trap:
2368 case Intrinsic::nvvm_suld_3d_i32_trap:
2369 case Intrinsic::nvvm_suld_3d_v2i32_trap:
2370 case Intrinsic::nvvm_suld_3d_v4i32_trap: {
2371 Info.opc = getOpcForSurfaceInstr(Intrinsic);
2372 Info.memVT = MVT::i32;
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame^]2373 Info.ptrVal = nullptr;
Justin Holewinski30d56a72014-04-09 15:39:15 +0000[diff] [blame]2374 Info.offset = 0;
2375 Info.vol = 0;
2376 Info.readMem = true;
2377 Info.writeMem = false;
2378 Info.align = 16;
2379 return true;
2380 }
2381
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]2382 }
2383 return false;
2384}
2385
2386/// isLegalAddressingMode - Return true if the addressing mode represented
2387/// by AM is legal for this target, for a load/store of the specified type.
2388/// Used to guide target specific optimizations, like loop strength reduction
2389/// (LoopStrengthReduce.cpp) and memory optimization for address mode
2390/// (CodeGenPrepare.cpp)
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]2391bool NVPTXTargetLowering::isLegalAddressingMode(const AddrMode &AM,
2392 Type *Ty) const {
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]2393
2394 // AddrMode - This represents an addressing mode of:
2395 // BaseGV + BaseOffs + BaseReg + Scale*ScaleReg
2396 //
2397 // The legal address modes are
2398 // - [avar]
2399 // - [areg]
2400 // - [areg+immoff]
2401 // - [immAddr]
2402
2403 if (AM.BaseGV) {
2404 if (AM.BaseOffs || AM.HasBaseReg || AM.Scale)
2405 return false;
2406 return true;
2407 }
2408
2409 switch (AM.Scale) {
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]2410 case 0: // "r", "r+i" or "i" is allowed
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]2411 break;
2412 case 1:
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]2413 if (AM.HasBaseReg) // "r+r+i" or "r+r" is not allowed.
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]2414 return false;
2415 // Otherwise we have r+i.
2416 break;
2417 default:
2418 // No scale > 1 is allowed
2419 return false;
2420 }
2421 return true;
2422}
2423
2424//===----------------------------------------------------------------------===//
2425// NVPTX Inline Assembly Support
2426//===----------------------------------------------------------------------===//
2427
2428/// getConstraintType - Given a constraint letter, return the type of
2429/// constraint it is for this target.
2430NVPTXTargetLowering::ConstraintType
2431NVPTXTargetLowering::getConstraintType(const std::string &Constraint) const {
2432 if (Constraint.size() == 1) {
2433 switch (Constraint[0]) {
2434 default:
2435 break;
2436 case 'r':
2437 case 'h':
2438 case 'c':
2439 case 'l':
2440 case 'f':
2441 case 'd':
2442 case '0':
2443 case 'N':
2444 return C_RegisterClass;
2445 }
2446 }
2447 return TargetLowering::getConstraintType(Constraint);
2448}
2449
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]2450std::pair<unsigned, const TargetRegisterClass *>
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]2451NVPTXTargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
Chad Rosier295bd432013-06-22 18:37:38 +0000[diff] [blame]2452 MVT VT) const {
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]2453 if (Constraint.size() == 1) {
2454 switch (Constraint[0]) {
2455 case 'c':
Justin Holewinskif8f70912013-06-28 17:57:59 +0000[diff] [blame]2456 return std::make_pair(0U, &NVPTX::Int16RegsRegClass);
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]2457 case 'h':
2458 return std::make_pair(0U, &NVPTX::Int16RegsRegClass);
2459 case 'r':
2460 return std::make_pair(0U, &NVPTX::Int32RegsRegClass);
2461 case 'l':
2462 case 'N':
2463 return std::make_pair(0U, &NVPTX::Int64RegsRegClass);
2464 case 'f':
2465 return std::make_pair(0U, &NVPTX::Float32RegsRegClass);
2466 case 'd':
2467 return std::make_pair(0U, &NVPTX::Float64RegsRegClass);
2468 }
2469 }
2470 return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
2471}
2472
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]2473/// getFunctionAlignment - Return the Log2 alignment of this function.
2474unsigned NVPTXTargetLowering::getFunctionAlignment(const Function *) const {
2475 return 4;
2476}
Justin Holewinskibe8dc642013-02-12 14:18:49 +0000[diff] [blame]2477
2478/// ReplaceVectorLoad - Convert vector loads into multi-output scalar loads.
2479static void ReplaceLoadVector(SDNode *N, SelectionDAG &DAG,
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]2480 SmallVectorImpl<SDValue> &Results) {
Justin Holewinskibe8dc642013-02-12 14:18:49 +0000[diff] [blame]2481 EVT ResVT = N->getValueType(0);
Andrew Trickef9de2a2013-05-25 02:42:55 +0000[diff] [blame]2482 SDLoc DL(N);
Justin Holewinskibe8dc642013-02-12 14:18:49 +0000[diff] [blame]2483
2484 assert(ResVT.isVector() && "Vector load must have vector type");
2485
2486 // We only handle "native" vector sizes for now, e.g. <4 x double> is not
2487 // legal. We can (and should) split that into 2 loads of <2 x double> here
2488 // but I'm leaving that as a TODO for now.
2489 assert(ResVT.isSimple() && "Can only handle simple types");
2490 switch (ResVT.getSimpleVT().SimpleTy) {
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]2491 default:
2492 return;
Justin Holewinskibe8dc642013-02-12 14:18:49 +0000[diff] [blame]2493 case MVT::v2i8:
2494 case MVT::v2i16:
2495 case MVT::v2i32:
2496 case MVT::v2i64:
2497 case MVT::v2f32:
2498 case MVT::v2f64:
2499 case MVT::v4i8:
2500 case MVT::v4i16:
2501 case MVT::v4i32:
2502 case MVT::v4f32:
2503 // This is a "native" vector type
2504 break;
2505 }
2506
2507 EVT EltVT = ResVT.getVectorElementType();
2508 unsigned NumElts = ResVT.getVectorNumElements();
2509
2510 // Since LoadV2 is a target node, we cannot rely on DAG type legalization.
2511 // Therefore, we must ensure the type is legal. For i1 and i8, we set the
Alp Tokercb402912014-01-24 17:20:08 +0000[diff] [blame]2512 // loaded type to i16 and propagate the "real" type as the memory type.
Justin Holewinskibe8dc642013-02-12 14:18:49 +0000[diff] [blame]2513 bool NeedTrunc = false;
2514 if (EltVT.getSizeInBits() < 16) {
2515 EltVT = MVT::i16;
2516 NeedTrunc = true;
2517 }
2518
2519 unsigned Opcode = 0;
2520 SDVTList LdResVTs;
2521
2522 switch (NumElts) {
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]2523 default:
2524 return;
Justin Holewinskibe8dc642013-02-12 14:18:49 +0000[diff] [blame]2525 case 2:
2526 Opcode = NVPTXISD::LoadV2;
2527 LdResVTs = DAG.getVTList(EltVT, EltVT, MVT::Other);
2528 break;
2529 case 4: {
2530 Opcode = NVPTXISD::LoadV4;
2531 EVT ListVTs[] = { EltVT, EltVT, EltVT, EltVT, MVT::Other };
Craig Topperabb4ac72014-04-16 06:10:51 +0000[diff] [blame]2532 LdResVTs = DAG.getVTList(ListVTs);
Justin Holewinskibe8dc642013-02-12 14:18:49 +0000[diff] [blame]2533 break;
2534 }
2535 }
2536
2537 SmallVector<SDValue, 8> OtherOps;
2538
2539 // Copy regular operands
2540 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
2541 OtherOps.push_back(N->getOperand(i));
2542
2543 LoadSDNode *LD = cast<LoadSDNode>(N);
2544
2545 // The select routine does not have access to the LoadSDNode instance, so
2546 // pass along the extension information
2547 OtherOps.push_back(DAG.getIntPtrConstant(LD->getExtensionType()));
2548
2549 SDValue NewLD = DAG.getMemIntrinsicNode(Opcode, DL, LdResVTs, &OtherOps[0],
2550 OtherOps.size(), LD->getMemoryVT(),
2551 LD->getMemOperand());
2552
2553 SmallVector<SDValue, 4> ScalarRes;
2554
2555 for (unsigned i = 0; i < NumElts; ++i) {
2556 SDValue Res = NewLD.getValue(i);
2557 if (NeedTrunc)
2558 Res = DAG.getNode(ISD::TRUNCATE, DL, ResVT.getVectorElementType(), Res);
2559 ScalarRes.push_back(Res);
2560 }
2561
2562 SDValue LoadChain = NewLD.getValue(NumElts);
2563
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]2564 SDValue BuildVec =
2565 DAG.getNode(ISD::BUILD_VECTOR, DL, ResVT, &ScalarRes[0], NumElts);
Justin Holewinskibe8dc642013-02-12 14:18:49 +0000[diff] [blame]2566
2567 Results.push_back(BuildVec);
2568 Results.push_back(LoadChain);
2569}
2570
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]2571static void ReplaceINTRINSIC_W_CHAIN(SDNode *N, SelectionDAG &DAG,
Justin Holewinskibe8dc642013-02-12 14:18:49 +0000[diff] [blame]2572 SmallVectorImpl<SDValue> &Results) {
2573 SDValue Chain = N->getOperand(0);
2574 SDValue Intrin = N->getOperand(1);
Andrew Trickef9de2a2013-05-25 02:42:55 +0000[diff] [blame]2575 SDLoc DL(N);
Justin Holewinskibe8dc642013-02-12 14:18:49 +0000[diff] [blame]2576
2577 // Get the intrinsic ID
2578 unsigned IntrinNo = cast<ConstantSDNode>(Intrin.getNode())->getZExtValue();
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]2579 switch (IntrinNo) {
2580 default:
2581 return;
Justin Holewinskibe8dc642013-02-12 14:18:49 +0000[diff] [blame]2582 case Intrinsic::nvvm_ldg_global_i:
2583 case Intrinsic::nvvm_ldg_global_f:
2584 case Intrinsic::nvvm_ldg_global_p:
2585 case Intrinsic::nvvm_ldu_global_i:
2586 case Intrinsic::nvvm_ldu_global_f:
2587 case Intrinsic::nvvm_ldu_global_p: {
2588 EVT ResVT = N->getValueType(0);
2589
2590 if (ResVT.isVector()) {
2591 // Vector LDG/LDU
2592
2593 unsigned NumElts = ResVT.getVectorNumElements();
2594 EVT EltVT = ResVT.getVectorElementType();
2595
Justin Holewinskif8f70912013-06-28 17:57:59 +0000[diff] [blame]2596 // Since LDU/LDG are target nodes, we cannot rely on DAG type
2597 // legalization.
Justin Holewinskibe8dc642013-02-12 14:18:49 +0000[diff] [blame]2598 // Therefore, we must ensure the type is legal. For i1 and i8, we set the
Alp Tokercb402912014-01-24 17:20:08 +0000[diff] [blame]2599 // loaded type to i16 and propagate the "real" type as the memory type.
Justin Holewinskibe8dc642013-02-12 14:18:49 +0000[diff] [blame]2600 bool NeedTrunc = false;
2601 if (EltVT.getSizeInBits() < 16) {
2602 EltVT = MVT::i16;
2603 NeedTrunc = true;
2604 }
2605
2606 unsigned Opcode = 0;
2607 SDVTList LdResVTs;
2608
2609 switch (NumElts) {
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]2610 default:
2611 return;
Justin Holewinskibe8dc642013-02-12 14:18:49 +0000[diff] [blame]2612 case 2:
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]2613 switch (IntrinNo) {
2614 default:
2615 return;
Justin Holewinskibe8dc642013-02-12 14:18:49 +0000[diff] [blame]2616 case Intrinsic::nvvm_ldg_global_i:
2617 case Intrinsic::nvvm_ldg_global_f:
2618 case Intrinsic::nvvm_ldg_global_p:
2619 Opcode = NVPTXISD::LDGV2;
2620 break;
2621 case Intrinsic::nvvm_ldu_global_i:
2622 case Intrinsic::nvvm_ldu_global_f:
2623 case Intrinsic::nvvm_ldu_global_p:
2624 Opcode = NVPTXISD::LDUV2;
2625 break;
2626 }
2627 LdResVTs = DAG.getVTList(EltVT, EltVT, MVT::Other);
2628 break;
2629 case 4: {
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]2630 switch (IntrinNo) {
2631 default:
2632 return;
Justin Holewinskibe8dc642013-02-12 14:18:49 +0000[diff] [blame]2633 case Intrinsic::nvvm_ldg_global_i:
2634 case Intrinsic::nvvm_ldg_global_f:
2635 case Intrinsic::nvvm_ldg_global_p:
2636 Opcode = NVPTXISD::LDGV4;
2637 break;
2638 case Intrinsic::nvvm_ldu_global_i:
2639 case Intrinsic::nvvm_ldu_global_f:
2640 case Intrinsic::nvvm_ldu_global_p:
2641 Opcode = NVPTXISD::LDUV4;
2642 break;
2643 }
2644 EVT ListVTs[] = { EltVT, EltVT, EltVT, EltVT, MVT::Other };
Craig Topperabb4ac72014-04-16 06:10:51 +0000[diff] [blame]2645 LdResVTs = DAG.getVTList(ListVTs);
Justin Holewinskibe8dc642013-02-12 14:18:49 +0000[diff] [blame]2646 break;
2647 }
2648 }
2649
2650 SmallVector<SDValue, 8> OtherOps;
2651
2652 // Copy regular operands
2653
2654 OtherOps.push_back(Chain); // Chain
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]2655 // Skip operand 1 (intrinsic ID)
Justin Holewinskif8f70912013-06-28 17:57:59 +0000[diff] [blame]2656 // Others
Justin Holewinskibe8dc642013-02-12 14:18:49 +0000[diff] [blame]2657 for (unsigned i = 2, e = N->getNumOperands(); i != e; ++i)
2658 OtherOps.push_back(N->getOperand(i));
2659
2660 MemIntrinsicSDNode *MemSD = cast<MemIntrinsicSDNode>(N);
2661
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]2662 SDValue NewLD = DAG.getMemIntrinsicNode(
2663 Opcode, DL, LdResVTs, &OtherOps[0], OtherOps.size(),
2664 MemSD->getMemoryVT(), MemSD->getMemOperand());
Justin Holewinskibe8dc642013-02-12 14:18:49 +0000[diff] [blame]2665
2666 SmallVector<SDValue, 4> ScalarRes;
2667
2668 for (unsigned i = 0; i < NumElts; ++i) {
2669 SDValue Res = NewLD.getValue(i);
2670 if (NeedTrunc)
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]2671 Res =
2672 DAG.getNode(ISD::TRUNCATE, DL, ResVT.getVectorElementType(), Res);
Justin Holewinskibe8dc642013-02-12 14:18:49 +0000[diff] [blame]2673 ScalarRes.push_back(Res);
2674 }
2675
2676 SDValue LoadChain = NewLD.getValue(NumElts);
2677
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]2678 SDValue BuildVec =
2679 DAG.getNode(ISD::BUILD_VECTOR, DL, ResVT, &ScalarRes[0], NumElts);
Justin Holewinskibe8dc642013-02-12 14:18:49 +0000[diff] [blame]2680
2681 Results.push_back(BuildVec);
2682 Results.push_back(LoadChain);
2683 } else {
2684 // i8 LDG/LDU
2685 assert(ResVT.isSimple() && ResVT.getSimpleVT().SimpleTy == MVT::i8 &&
2686 "Custom handling of non-i8 ldu/ldg?");
2687
2688 // Just copy all operands as-is
2689 SmallVector<SDValue, 4> Ops;
2690 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
2691 Ops.push_back(N->getOperand(i));
2692
2693 // Force output to i16
2694 SDVTList LdResVTs = DAG.getVTList(MVT::i16, MVT::Other);
2695
2696 MemIntrinsicSDNode *MemSD = cast<MemIntrinsicSDNode>(N);
2697
2698 // We make sure the memory type is i8, which will be used during isel
2699 // to select the proper instruction.
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]2700 SDValue NewLD =
2701 DAG.getMemIntrinsicNode(ISD::INTRINSIC_W_CHAIN, DL, LdResVTs, &Ops[0],
2702 Ops.size(), MVT::i8, MemSD->getMemOperand());
Justin Holewinskibe8dc642013-02-12 14:18:49 +0000[diff] [blame]2703
Justin Holewinskie8c93e32013-07-01 12:58:48 +0000[diff] [blame]2704 Results.push_back(DAG.getNode(ISD::TRUNCATE, DL, MVT::i8,
2705 NewLD.getValue(0)));
Justin Holewinskibe8dc642013-02-12 14:18:49 +0000[diff] [blame]2706 Results.push_back(NewLD.getValue(1));
2707 }
2708 }
2709 }
2710}
2711
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]2712void NVPTXTargetLowering::ReplaceNodeResults(
2713 SDNode *N, SmallVectorImpl<SDValue> &Results, SelectionDAG &DAG) const {
Justin Holewinskibe8dc642013-02-12 14:18:49 +0000[diff] [blame]2714 switch (N->getOpcode()) {
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]2715 default:
2716 report_fatal_error("Unhandled custom legalization");
Justin Holewinskibe8dc642013-02-12 14:18:49 +0000[diff] [blame]2717 case ISD::LOAD:
2718 ReplaceLoadVector(N, DAG, Results);
2719 return;
2720 case ISD::INTRINSIC_W_CHAIN:
2721 ReplaceINTRINSIC_W_CHAIN(N, DAG, Results);
2722 return;
2723 }
2724}
Juergen Ributzkad12ccbd2013-11-19 00:57:56 +0000[diff] [blame]2725
2726// Pin NVPTXSection's and NVPTXTargetObjectFile's vtables to this file.
2727void NVPTXSection::anchor() {}
2728
2729NVPTXTargetObjectFile::~NVPTXTargetObjectFile() {
2730 delete TextSection;
2731 delete DataSection;
2732 delete BSSSection;
2733 delete ReadOnlySection;
2734
2735 delete StaticCtorSection;
2736 delete StaticDtorSection;
2737 delete LSDASection;
2738 delete EHFrameSection;
2739 delete DwarfAbbrevSection;
2740 delete DwarfInfoSection;
2741 delete DwarfLineSection;
2742 delete DwarfFrameSection;
2743 delete DwarfPubTypesSection;
2744 delete DwarfDebugInlineSection;
2745 delete DwarfStrSection;
2746 delete DwarfLocSection;
2747 delete DwarfARangesSection;
2748 delete DwarfRangesSection;
2749 delete DwarfMacroInfoSection;
2750}