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gerrit-public.fairphone.software / toolchain / llvm-project / 067c81567bf35e04b2c9b3d360a6f15dedbfe8aa / . / llvm / lib / Target / R600 / SIISelLowering.h
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Tom Stellard75aadc22012-12-11 21:25:42 +0000[diff] [blame]1//===-- SIISelLowering.h - SI DAG Lowering Interface ------------*- C++ -*-===//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10/// \file
11/// \brief SI DAG Lowering interface definition
12//
13//===----------------------------------------------------------------------===//
14
15#ifndef SIISELLOWERING_H
16#define SIISELLOWERING_H
17
18#include "AMDGPUISelLowering.h"
19#include "SIInstrInfo.h"
20
21namespace llvm {
22
23class SITargetLowering : public AMDGPUTargetLowering {
Tom Stellardaf775432013-10-23 00:44:32 +0000[diff] [blame]24 SDValue LowerParameter(SelectionDAG &DAG, EVT VT, EVT MemVT, SDLoc DL,
Matt Arsenaulte1f030c2014-04-11 20:59:54 +0000[diff] [blame]25 SDValue Chain, unsigned Offset, bool Signed) const;
Tom Stellard9fa17912013-08-14 23:24:45 +0000[diff] [blame]26 SDValue LowerSampleIntrinsic(unsigned Opcode, const SDValue &Op,
27 SelectionDAG &DAG) const;
Tom Stellard067c8152014-07-21 14:01:14 +0000[diff] [blame^]28 SDValue LowerGlobalAddress(AMDGPUMachineFunction *MFI, SDValue Op,
29 SelectionDAG &DAG) const override;
Tom Stellard81d871d2013-11-13 23:36:50 +0000[diff] [blame]30 SDValue LowerLOAD(SDValue Op, SelectionDAG &DAG) const;
Tom Stellard0ec134f2014-02-04 17:18:40 +0000[diff] [blame]31 SDValue LowerSELECT(SDValue Op, SelectionDAG &DAG) const;
Matt Arsenault22ca3f82014-07-15 23:50:10 +0000[diff] [blame]32 SDValue LowerFastFDIV(SDValue Op, SelectionDAG &DAG) const;
Matt Arsenaulte9fa3b82014-07-15 20:18:31 +0000[diff] [blame]33 SDValue LowerFDIV32(SDValue Op, SelectionDAG &DAG) const;
34 SDValue LowerFDIV64(SDValue Op, SelectionDAG &DAG) const;
35 SDValue LowerFDIV(SDValue Op, SelectionDAG &DAG) const;
Tom Stellard81d871d2013-11-13 23:36:50 +0000[diff] [blame]36 SDValue LowerSTORE(SDValue Op, SelectionDAG &DAG) const;
Matt Arsenaultad14ce82014-07-19 18:44:39 +0000[diff] [blame]37 SDValue LowerTrig(SDValue Op, SelectionDAG &DAG) const;
Tom Stellardf8794352012-12-19 22:10:31 +0000[diff] [blame]38 SDValue LowerBRCOND(SDValue Op, SelectionDAG &DAG) const;
Tom Stellard75aadc22012-12-11 21:25:42 +0000[diff] [blame]39
Christian Konigf82901a2013-02-26 17:52:23 +0000[diff] [blame]40 bool foldImm(SDValue &Operand, int32_t &Immediate,
41 bool &ScalarSlotUsed) const;
Tom Stellard4c0ffcc2013-08-06 23:08:18 +0000[diff] [blame]42 const TargetRegisterClass *getRegClassForNode(SelectionDAG &DAG,
43 const SDValue &Op) const;
Tom Stellardb35efba2013-05-20 15:02:01 +0000[diff] [blame]44 bool fitsRegClass(SelectionDAG &DAG, const SDValue &Op,
45 unsigned RegClass) const;
Matt Arsenault758659232013-05-18 00:21:46 +0000[diff] [blame]46 void ensureSRegLimit(SelectionDAG &DAG, SDValue &Operand,
Christian Konigf82901a2013-02-26 17:52:23 +0000[diff] [blame]47 unsigned RegClass, bool &ScalarSlotUsed) const;
48
Christian Konig8e06e2a2013-04-10 08:39:08 +0000[diff] [blame]49 SDNode *foldOperands(MachineSDNode *N, SelectionDAG &DAG) const;
50 void adjustWritemask(MachineSDNode *&N, SelectionDAG &DAG) const;
Tom Stellard0518ff82013-06-03 17:39:58 +0000[diff] [blame]51 MachineSDNode *AdjustRegClass(MachineSDNode *N, SelectionDAG &DAG) const;
Christian Konig8e06e2a2013-04-10 08:39:08 +0000[diff] [blame]52
Matt Arsenault364a6742014-06-11 17:50:44 +0000[diff] [blame]53 static SDValue performUCharToFloatCombine(SDNode *N,
54 DAGCombinerInfo &DCI);
55
Tom Stellard75aadc22012-12-11 21:25:42 +0000[diff] [blame]56public:
57 SITargetLowering(TargetMachine &tm);
Craig Topper5656db42014-04-29 07:57:24 +0000[diff] [blame]58 bool allowsUnalignedMemoryAccesses(EVT VT, unsigned AS,
59 bool *IsFast) const override;
Chandler Carruth9d010ff2014-07-03 00:23:43 +0000[diff] [blame]60
61 TargetLoweringBase::LegalizeTypeAction
62 getPreferredVectorAction(EVT VT) const override;
Christian Konig2c8f6d52013-03-07 09:03:52 +0000[diff] [blame]63
Craig Topper5656db42014-04-29 07:57:24 +0000[diff] [blame]64 bool shouldConvertConstantLoadToIntImm(const APInt &Imm,
65 Type *Ty) const override;
Matt Arsenaultd7bdcc42014-03-31 19:54:27 +0000[diff] [blame]66
Christian Konig2c8f6d52013-03-07 09:03:52 +0000[diff] [blame]67 SDValue LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv,
68 bool isVarArg,
69 const SmallVectorImpl<ISD::InputArg> &Ins,
Andrew Trickef9de2a2013-05-25 02:42:55 +0000[diff] [blame]70 SDLoc DL, SelectionDAG &DAG,
Craig Topper5656db42014-04-29 07:57:24 +0000[diff] [blame]71 SmallVectorImpl<SDValue> &InVals) const override;
Christian Konig2c8f6d52013-03-07 09:03:52 +0000[diff] [blame]72
Craig Topper5656db42014-04-29 07:57:24 +0000[diff] [blame]73 MachineBasicBlock * EmitInstrWithCustomInserter(MachineInstr * MI,
74 MachineBasicBlock * BB) const override;
75 EVT getSetCCResultType(LLVMContext &Context, EVT VT) const override;
76 MVT getScalarShiftAmountTy(EVT VT) const override;
77 bool isFMAFasterThanFMulAndFAdd(EVT VT) const override;
78 SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
79 SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
80 SDNode *PostISelFolding(MachineSDNode *N, SelectionDAG &DAG) const override;
81 void AdjustInstrPostInstrSelection(MachineInstr *MI,
82 SDNode *Node) const override;
Christian Konigf82901a2013-02-26 17:52:23 +0000[diff] [blame]83
84 int32_t analyzeImmediate(const SDNode *N) const;
Tom Stellard94593ee2013-06-03 17:40:18 +0000[diff] [blame]85 SDValue CreateLiveInRegister(SelectionDAG &DAG, const TargetRegisterClass *RC,
Craig Topper5656db42014-04-29 07:57:24 +0000[diff] [blame]86 unsigned Reg, EVT VT) const override;
Tom Stellard75aadc22012-12-11 21:25:42 +0000[diff] [blame]87};
88
89} // End namespace llvm
90
91#endif //SIISELLOWERING_H