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gerrit-public.fairphone.software / toolchain / llvm-project / 08c391c15618b052864dd32e0acfda78d4ab1a6f / . / llvm / lib / Target / ARM64 / Utils / ARM64BaseInfo.h
blob: 2dc0a34c1f6ce0bf53243ee74941cea43fa52704 [file] [log] [blame]
Tim Northover00ed9962014-03-29 10:18:08 +0000[diff] [blame]1//===-- ARM64BaseInfo.h - Top level definitions for ARM64 -------*- C++ -*-===//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file contains small standalone helper functions and enum definitions for
11// the ARM64 target useful for the compiler back-end and the MC libraries.
12// As such, it deliberately does not include references to LLVM core
13// code gen types, passes, etc..
14//
15//===----------------------------------------------------------------------===//
16
17#ifndef ARM64BASEINFO_H
18#define ARM64BASEINFO_H
19
Bradley Smith2ba17a42014-04-09 14:42:27 +0000[diff] [blame]20// FIXME: Is it easiest to fix this layering violation by moving the .inc
21// #includes from ARM64MCTargetDesc.h to here?
22#include "MCTargetDesc/ARM64MCTargetDesc.h" // For ARM64::X0 and friends.
Bradley Smithceeb04d2014-04-09 14:42:16 +0000[diff] [blame]23#include "llvm/ADT/STLExtras.h"
24#include "llvm/ADT/StringSwitch.h"
Tim Northover00ed9962014-03-29 10:18:08 +0000[diff] [blame]25#include "llvm/Support/ErrorHandling.h"
26
27namespace llvm {
28
29inline static unsigned getWRegFromXReg(unsigned Reg) {
30 switch (Reg) {
31 case ARM64::X0: return ARM64::W0;
32 case ARM64::X1: return ARM64::W1;
33 case ARM64::X2: return ARM64::W2;
34 case ARM64::X3: return ARM64::W3;
35 case ARM64::X4: return ARM64::W4;
36 case ARM64::X5: return ARM64::W5;
37 case ARM64::X6: return ARM64::W6;
38 case ARM64::X7: return ARM64::W7;
39 case ARM64::X8: return ARM64::W8;
40 case ARM64::X9: return ARM64::W9;
41 case ARM64::X10: return ARM64::W10;
42 case ARM64::X11: return ARM64::W11;
43 case ARM64::X12: return ARM64::W12;
44 case ARM64::X13: return ARM64::W13;
45 case ARM64::X14: return ARM64::W14;
46 case ARM64::X15: return ARM64::W15;
47 case ARM64::X16: return ARM64::W16;
48 case ARM64::X17: return ARM64::W17;
49 case ARM64::X18: return ARM64::W18;
50 case ARM64::X19: return ARM64::W19;
51 case ARM64::X20: return ARM64::W20;
52 case ARM64::X21: return ARM64::W21;
53 case ARM64::X22: return ARM64::W22;
54 case ARM64::X23: return ARM64::W23;
55 case ARM64::X24: return ARM64::W24;
56 case ARM64::X25: return ARM64::W25;
57 case ARM64::X26: return ARM64::W26;
58 case ARM64::X27: return ARM64::W27;
59 case ARM64::X28: return ARM64::W28;
60 case ARM64::FP: return ARM64::W29;
61 case ARM64::LR: return ARM64::W30;
62 case ARM64::SP: return ARM64::WSP;
63 case ARM64::XZR: return ARM64::WZR;
64 }
65 // For anything else, return it unchanged.
66 return Reg;
67}
68
69inline static unsigned getXRegFromWReg(unsigned Reg) {
70 switch (Reg) {
71 case ARM64::W0: return ARM64::X0;
72 case ARM64::W1: return ARM64::X1;
73 case ARM64::W2: return ARM64::X2;
74 case ARM64::W3: return ARM64::X3;
75 case ARM64::W4: return ARM64::X4;
76 case ARM64::W5: return ARM64::X5;
77 case ARM64::W6: return ARM64::X6;
78 case ARM64::W7: return ARM64::X7;
79 case ARM64::W8: return ARM64::X8;
80 case ARM64::W9: return ARM64::X9;
81 case ARM64::W10: return ARM64::X10;
82 case ARM64::W11: return ARM64::X11;
83 case ARM64::W12: return ARM64::X12;
84 case ARM64::W13: return ARM64::X13;
85 case ARM64::W14: return ARM64::X14;
86 case ARM64::W15: return ARM64::X15;
87 case ARM64::W16: return ARM64::X16;
88 case ARM64::W17: return ARM64::X17;
89 case ARM64::W18: return ARM64::X18;
90 case ARM64::W19: return ARM64::X19;
91 case ARM64::W20: return ARM64::X20;
92 case ARM64::W21: return ARM64::X21;
93 case ARM64::W22: return ARM64::X22;
94 case ARM64::W23: return ARM64::X23;
95 case ARM64::W24: return ARM64::X24;
96 case ARM64::W25: return ARM64::X25;
97 case ARM64::W26: return ARM64::X26;
98 case ARM64::W27: return ARM64::X27;
99 case ARM64::W28: return ARM64::X28;
100 case ARM64::W29: return ARM64::FP;
101 case ARM64::W30: return ARM64::LR;
102 case ARM64::WSP: return ARM64::SP;
103 case ARM64::WZR: return ARM64::XZR;
104 }
105 // For anything else, return it unchanged.
106 return Reg;
107}
108
109static inline unsigned getBRegFromDReg(unsigned Reg) {
110 switch (Reg) {
111 case ARM64::D0: return ARM64::B0;
112 case ARM64::D1: return ARM64::B1;
113 case ARM64::D2: return ARM64::B2;
114 case ARM64::D3: return ARM64::B3;
115 case ARM64::D4: return ARM64::B4;
116 case ARM64::D5: return ARM64::B5;
117 case ARM64::D6: return ARM64::B6;
118 case ARM64::D7: return ARM64::B7;
119 case ARM64::D8: return ARM64::B8;
120 case ARM64::D9: return ARM64::B9;
121 case ARM64::D10: return ARM64::B10;
122 case ARM64::D11: return ARM64::B11;
123 case ARM64::D12: return ARM64::B12;
124 case ARM64::D13: return ARM64::B13;
125 case ARM64::D14: return ARM64::B14;
126 case ARM64::D15: return ARM64::B15;
127 case ARM64::D16: return ARM64::B16;
128 case ARM64::D17: return ARM64::B17;
129 case ARM64::D18: return ARM64::B18;
130 case ARM64::D19: return ARM64::B19;
131 case ARM64::D20: return ARM64::B20;
132 case ARM64::D21: return ARM64::B21;
133 case ARM64::D22: return ARM64::B22;
134 case ARM64::D23: return ARM64::B23;
135 case ARM64::D24: return ARM64::B24;
136 case ARM64::D25: return ARM64::B25;
137 case ARM64::D26: return ARM64::B26;
138 case ARM64::D27: return ARM64::B27;
139 case ARM64::D28: return ARM64::B28;
140 case ARM64::D29: return ARM64::B29;
141 case ARM64::D30: return ARM64::B30;
142 case ARM64::D31: return ARM64::B31;
143 }
144 // For anything else, return it unchanged.
145 return Reg;
146}
147
148
149static inline unsigned getDRegFromBReg(unsigned Reg) {
150 switch (Reg) {
151 case ARM64::B0: return ARM64::D0;
152 case ARM64::B1: return ARM64::D1;
153 case ARM64::B2: return ARM64::D2;
154 case ARM64::B3: return ARM64::D3;
155 case ARM64::B4: return ARM64::D4;
156 case ARM64::B5: return ARM64::D5;
157 case ARM64::B6: return ARM64::D6;
158 case ARM64::B7: return ARM64::D7;
159 case ARM64::B8: return ARM64::D8;
160 case ARM64::B9: return ARM64::D9;
161 case ARM64::B10: return ARM64::D10;
162 case ARM64::B11: return ARM64::D11;
163 case ARM64::B12: return ARM64::D12;
164 case ARM64::B13: return ARM64::D13;
165 case ARM64::B14: return ARM64::D14;
166 case ARM64::B15: return ARM64::D15;
167 case ARM64::B16: return ARM64::D16;
168 case ARM64::B17: return ARM64::D17;
169 case ARM64::B18: return ARM64::D18;
170 case ARM64::B19: return ARM64::D19;
171 case ARM64::B20: return ARM64::D20;
172 case ARM64::B21: return ARM64::D21;
173 case ARM64::B22: return ARM64::D22;
174 case ARM64::B23: return ARM64::D23;
175 case ARM64::B24: return ARM64::D24;
176 case ARM64::B25: return ARM64::D25;
177 case ARM64::B26: return ARM64::D26;
178 case ARM64::B27: return ARM64::D27;
179 case ARM64::B28: return ARM64::D28;
180 case ARM64::B29: return ARM64::D29;
181 case ARM64::B30: return ARM64::D30;
182 case ARM64::B31: return ARM64::D31;
183 }
184 // For anything else, return it unchanged.
185 return Reg;
186}
187
188namespace ARM64CC {
189
190// The CondCodes constants map directly to the 4-bit encoding of the condition
191// field for predicated instructions.
192enum CondCode { // Meaning (integer) Meaning (floating-point)
193 EQ = 0x0, // Equal Equal
194 NE = 0x1, // Not equal Not equal, or unordered
195 CS = 0x2, // Carry set >, ==, or unordered
196 CC = 0x3, // Carry clear Less than
197 MI = 0x4, // Minus, negative Less than
198 PL = 0x5, // Plus, positive or zero >, ==, or unordered
199 VS = 0x6, // Overflow Unordered
200 VC = 0x7, // No overflow Not unordered
201 HI = 0x8, // Unsigned higher Greater than, or unordered
202 LS = 0x9, // Unsigned lower or same Less than or equal
203 GE = 0xa, // Greater than or equal Greater than or equal
204 LT = 0xb, // Less than Less than, or unordered
205 GT = 0xc, // Greater than Greater than
206 LE = 0xd, // Less than or equal <, ==, or unordered
Bradley Smith527bf862014-04-09 14:42:07 +0000[diff] [blame]207 AL = 0xe, // Always (unconditional) Always (unconditional)
208 NV = 0xf, // Always (unconditional) Always (unconditional)
209 // Note the NV exists purely to disassemble 0b1111. Execution is "always".
210 Invalid
Tim Northover00ed9962014-03-29 10:18:08 +0000[diff] [blame]211};
212
213inline static const char *getCondCodeName(CondCode Code) {
Tim Northover00ed9962014-03-29 10:18:08 +0000[diff] [blame]214 switch (Code) {
Bradley Smith527bf862014-04-09 14:42:07 +0000[diff] [blame]215 default: llvm_unreachable("Unknown condition code");
Tim Northover00ed9962014-03-29 10:18:08 +0000[diff] [blame]216 case EQ: return "eq";
217 case NE: return "ne";
218 case CS: return "cs";
219 case CC: return "cc";
220 case MI: return "mi";
221 case PL: return "pl";
222 case VS: return "vs";
223 case VC: return "vc";
224 case HI: return "hi";
225 case LS: return "ls";
226 case GE: return "ge";
227 case LT: return "lt";
228 case GT: return "gt";
229 case LE: return "le";
230 case AL: return "al";
Bradley Smith527bf862014-04-09 14:42:07 +0000[diff] [blame]231 case NV: return "nv";
Tim Northover00ed9962014-03-29 10:18:08 +0000[diff] [blame]232 }
Tim Northover00ed9962014-03-29 10:18:08 +0000[diff] [blame]233}
234
235inline static CondCode getInvertedCondCode(CondCode Code) {
236 switch (Code) {
237 default: llvm_unreachable("Unknown condition code");
238 case EQ: return NE;
239 case NE: return EQ;
240 case CS: return CC;
241 case CC: return CS;
242 case MI: return PL;
243 case PL: return MI;
244 case VS: return VC;
245 case VC: return VS;
246 case HI: return LS;
247 case LS: return HI;
248 case GE: return LT;
249 case LT: return GE;
250 case GT: return LE;
251 case LE: return GT;
252 }
253}
254
255/// Given a condition code, return NZCV flags that would satisfy that condition.
256/// The flag bits are in the format expected by the ccmp instructions.
257/// Note that many different flag settings can satisfy a given condition code,
258/// this function just returns one of them.
259inline static unsigned getNZCVToSatisfyCondCode(CondCode Code) {
260 // NZCV flags encoded as expected by ccmp instructions, ARMv8 ISA 5.5.7.
261 enum { N = 8, Z = 4, C = 2, V = 1 };
262 switch (Code) {
263 default: llvm_unreachable("Unknown condition code");
264 case EQ: return Z; // Z == 1
265 case NE: return 0; // Z == 0
266 case CS: return C; // C == 1
267 case CC: return 0; // C == 0
268 case MI: return N; // N == 1
269 case PL: return 0; // N == 0
270 case VS: return V; // V == 1
271 case VC: return 0; // V == 0
272 case HI: return C; // C == 1 && Z == 0
273 case LS: return 0; // C == 0 || Z == 1
274 case GE: return 0; // N == V
275 case LT: return N; // N != V
276 case GT: return 0; // Z == 0 && N == V
277 case LE: return Z; // Z == 1 || N != V
278 }
279}
280} // end namespace ARM64CC
281
282namespace ARM64SYS {
283enum BarrierOption {
284 InvalidBarrier = 0xff,
285 OSHLD = 0x1,
286 OSHST = 0x2,
287 OSH = 0x3,
288 NSHLD = 0x5,
289 NSHST = 0x6,
290 NSH = 0x7,
291 ISHLD = 0x9,
292 ISHST = 0xa,
293 ISH = 0xb,
294 LD = 0xd,
295 ST = 0xe,
296 SY = 0xf
297};
298
299inline static const char *getBarrierOptName(BarrierOption Opt) {
300 switch (Opt) {
301 default: return NULL;
302 case 0x1: return "oshld";
303 case 0x2: return "oshst";
304 case 0x3: return "osh";
305 case 0x5: return "nshld";
306 case 0x6: return "nshst";
307 case 0x7: return "nsh";
308 case 0x9: return "ishld";
309 case 0xa: return "ishst";
310 case 0xb: return "ish";
311 case 0xd: return "ld";
312 case 0xe: return "st";
313 case 0xf: return "sy";
314 }
315}
316
317#define A64_SYSREG_ENC(op0,CRn,op2,CRm,op1) ((op0) << 14 | (op1) << 11 | \
318 (CRn) << 7 | (CRm) << 3 | (op2))
319enum SystemRegister {
320 InvalidSystemReg = 0,
321 // Table in section 3.10.3
322 SPSR_EL1 = 0xc200,
323 SPSR_svc = SPSR_EL1,
324 ELR_EL1 = 0xc201,
325 SP_EL0 = 0xc208,
326 SPSel = 0xc210,
327 CurrentEL = 0xc212,
328 DAIF = 0xda11,
329 NZCV = 0xda10,
330 FPCR = 0xda20,
331 FPSR = 0xda21,
332 DSPSR = 0xda28,
333 DLR = 0xda29,
334 SPSR_EL2 = 0xe200,
335 SPSR_hyp = SPSR_EL2,
336 ELR_EL2 = 0xe201,
337 SP_EL1 = 0xe208,
338 SPSR_irq = 0xe218,
339 SPSR_abt = 0xe219,
340 SPSR_und = 0xe21a,
341 SPSR_fiq = 0xe21b,
342 SPSR_EL3 = 0xf200,
343 ELR_EL3 = 0xf201,
344 SP_EL2 = 0xf208,
345
346
347 // Table in section 3.10.8
348 MIDR_EL1 = 0xc000,
349 CTR_EL0 = 0xd801,
350 MPIDR_EL1 = 0xc005,
351 ECOIDR_EL1 = 0xc006,
352 DCZID_EL0 = 0xd807,
353 MVFR0_EL1 = 0xc018,
354 MVFR1_EL1 = 0xc019,
355 ID_AA64PFR0_EL1 = 0xc020,
356 ID_AA64PFR1_EL1 = 0xc021,
357 ID_AA64DFR0_EL1 = 0xc028,
358 ID_AA64DFR1_EL1 = 0xc029,
359 ID_AA64ISAR0_EL1 = 0xc030,
360 ID_AA64ISAR1_EL1 = 0xc031,
361 ID_AA64MMFR0_EL1 = 0xc038,
362 ID_AA64MMFR1_EL1 = 0xc039,
363 CCSIDR_EL1 = 0xc800,
364 CLIDR_EL1 = 0xc801,
365 AIDR_EL1 = 0xc807,
366 CSSELR_EL1 = 0xd000,
367 VPIDR_EL2 = 0xe000,
368 VMPIDR_EL2 = 0xe005,
369 SCTLR_EL1 = 0xc080,
370 SCTLR_EL2 = 0xe080,
371 SCTLR_EL3 = 0xf080,
372 ACTLR_EL1 = 0xc081,
373 ACTLR_EL2 = 0xe081,
374 ACTLR_EL3 = 0xf081,
375 CPACR_EL1 = 0xc082,
376 CPTR_EL2 = 0xe08a,
377 CPTR_EL3 = 0xf08a,
378 SCR_EL3 = 0xf088,
379 HCR_EL2 = 0xe088,
380 MDCR_EL2 = 0xe089,
381 MDCR_EL3 = 0xf099,
382 HSTR_EL2 = 0xe08b,
383 HACR_EL2 = 0xe08f,
384 TTBR0_EL1 = 0xc100,
385 TTBR1_EL1 = 0xc101,
386 TTBR0_EL2 = 0xe100,
387 TTBR0_EL3 = 0xf100,
388 VTTBR_EL2 = 0xe108,
389 TCR_EL1 = 0xc102,
390 TCR_EL2 = 0xe102,
391 TCR_EL3 = 0xf102,
392 VTCR_EL2 = 0xe10a,
393 ADFSR_EL1 = 0xc288,
394 AIFSR_EL1 = 0xc289,
395 ADFSR_EL2 = 0xe288,
396 AIFSR_EL2 = 0xe289,
397 ADFSR_EL3 = 0xf288,
398 AIFSR_EL3 = 0xf289,
399 ESR_EL1 = 0xc290,
400 ESR_EL2 = 0xe290,
401 ESR_EL3 = 0xf290,
402 FAR_EL1 = 0xc300,
403 FAR_EL2 = 0xe300,
404 FAR_EL3 = 0xf300,
405 HPFAR_EL2 = 0xe304,
406 PAR_EL1 = 0xc3a0,
407 MAIR_EL1 = 0xc510,
408 MAIR_EL2 = 0xe510,
409 MAIR_EL3 = 0xf510,
410 AMAIR_EL1 = 0xc518,
411 AMAIR_EL2 = 0xe518,
412 AMAIR_EL3 = 0xf518,
413 VBAR_EL1 = 0xc600,
414 VBAR_EL2 = 0xe600,
415 VBAR_EL3 = 0xf600,
416 RVBAR_EL1 = 0xc601,
417 RVBAR_EL2 = 0xe601,
418 RVBAR_EL3 = 0xf601,
419 ISR_EL1 = 0xc608,
420 CONTEXTIDR_EL1 = 0xc681,
421 TPIDR_EL0 = 0xde82,
422 TPIDRRO_EL0 = 0xde83,
423 TPIDR_EL1 = 0xc684,
424 TPIDR_EL2 = 0xe682,
425 TPIDR_EL3 = 0xf682,
426 TEECR32_EL1 = 0x9000,
427 CNTFRQ_EL0 = 0xdf00,
428 CNTPCT_EL0 = 0xdf01,
429 CNTVCT_EL0 = 0xdf02,
430 CNTVOFF_EL2 = 0xe703,
431 CNTKCTL_EL1 = 0xc708,
432 CNTHCTL_EL2 = 0xe708,
433 CNTP_TVAL_EL0 = 0xdf10,
434 CNTP_CTL_EL0 = 0xdf11,
435 CNTP_CVAL_EL0 = 0xdf12,
436 CNTV_TVAL_EL0 = 0xdf18,
437 CNTV_CTL_EL0 = 0xdf19,
438 CNTV_CVAL_EL0 = 0xdf1a,
439 CNTHP_TVAL_EL2 = 0xe710,
440 CNTHP_CTL_EL2 = 0xe711,
441 CNTHP_CVAL_EL2 = 0xe712,
442 CNTPS_TVAL_EL1 = 0xff10,
443 CNTPS_CTL_EL1 = 0xff11,
444 CNTPS_CVAL_EL1= 0xff12,
445
446 PMEVCNTR0_EL0 = 0xdf40,
447 PMEVCNTR1_EL0 = 0xdf41,
448 PMEVCNTR2_EL0 = 0xdf42,
449 PMEVCNTR3_EL0 = 0xdf43,
450 PMEVCNTR4_EL0 = 0xdf44,
451 PMEVCNTR5_EL0 = 0xdf45,
452 PMEVCNTR6_EL0 = 0xdf46,
453 PMEVCNTR7_EL0 = 0xdf47,
454 PMEVCNTR8_EL0 = 0xdf48,
455 PMEVCNTR9_EL0 = 0xdf49,
456 PMEVCNTR10_EL0 = 0xdf4a,
457 PMEVCNTR11_EL0 = 0xdf4b,
458 PMEVCNTR12_EL0 = 0xdf4c,
459 PMEVCNTR13_EL0 = 0xdf4d,
460 PMEVCNTR14_EL0 = 0xdf4e,
461 PMEVCNTR15_EL0 = 0xdf4f,
462 PMEVCNTR16_EL0 = 0xdf50,
463 PMEVCNTR17_EL0 = 0xdf51,
464 PMEVCNTR18_EL0 = 0xdf52,
465 PMEVCNTR19_EL0 = 0xdf53,
466 PMEVCNTR20_EL0 = 0xdf54,
467 PMEVCNTR21_EL0 = 0xdf55,
468 PMEVCNTR22_EL0 = 0xdf56,
469 PMEVCNTR23_EL0 = 0xdf57,
470 PMEVCNTR24_EL0 = 0xdf58,
471 PMEVCNTR25_EL0 = 0xdf59,
472 PMEVCNTR26_EL0 = 0xdf5a,
473 PMEVCNTR27_EL0 = 0xdf5b,
474 PMEVCNTR28_EL0 = 0xdf5c,
475 PMEVCNTR29_EL0 = 0xdf5d,
476 PMEVCNTR30_EL0 = 0xdf5e,
477
478 PMEVTYPER0_EL0 = 0xdf60,
479 PMEVTYPER1_EL0 = 0xdf61,
480 PMEVTYPER2_EL0 = 0xdf62,
481 PMEVTYPER3_EL0 = 0xdf63,
482 PMEVTYPER4_EL0 = 0xdf64,
483 PMEVTYPER5_EL0 = 0xdf65,
484 PMEVTYPER6_EL0 = 0xdf66,
485 PMEVTYPER7_EL0 = 0xdf67,
486 PMEVTYPER8_EL0 = 0xdf68,
487 PMEVTYPER9_EL0 = 0xdf69,
488 PMEVTYPER10_EL0 = 0xdf6a,
489 PMEVTYPER11_EL0 = 0xdf6b,
490 PMEVTYPER12_EL0 = 0xdf6c,
491 PMEVTYPER13_EL0 = 0xdf6d,
492 PMEVTYPER14_EL0 = 0xdf6e,
493 PMEVTYPER15_EL0 = 0xdf6f,
494 PMEVTYPER16_EL0 = 0xdf70,
495 PMEVTYPER17_EL0 = 0xdf71,
496 PMEVTYPER18_EL0 = 0xdf72,
497 PMEVTYPER19_EL0 = 0xdf73,
498 PMEVTYPER20_EL0 = 0xdf74,
499 PMEVTYPER21_EL0 = 0xdf75,
500 PMEVTYPER22_EL0 = 0xdf76,
501 PMEVTYPER23_EL0 = 0xdf77,
502 PMEVTYPER24_EL0 = 0xdf78,
503 PMEVTYPER25_EL0 = 0xdf79,
504 PMEVTYPER26_EL0 = 0xdf7a,
505 PMEVTYPER27_EL0 = 0xdf7b,
506 PMEVTYPER28_EL0 = 0xdf7c,
507 PMEVTYPER29_EL0 = 0xdf7d,
508 PMEVTYPER30_EL0 = 0xdf7e,
509
510 PMCCFILTR_EL0 = 0xdf7f,
511
512 RMR_EL3 = 0xf602,
513 RMR_EL2 = 0xd602,
514 RMR_EL1 = 0xce02,
515
516 // Debug Architecture 5.3, Table 17.
517 MDCCSR_EL0 = A64_SYSREG_ENC(2, 0, 0, 1, 3),
518 MDCCINT_EL1 = A64_SYSREG_ENC(2, 0, 0, 2, 0),
519 DBGDTR_EL0 = A64_SYSREG_ENC(2, 0, 0, 4, 3),
520 DBGDTRRX_EL0 = A64_SYSREG_ENC(2, 0, 0, 5, 3),
521 DBGDTRTX_EL0 = DBGDTRRX_EL0,
522 DBGVCR32_EL2 = A64_SYSREG_ENC(2, 0, 0, 7, 4),
523 OSDTRRX_EL1 = A64_SYSREG_ENC(2, 0, 2, 0, 0),
524 MDSCR_EL1 = A64_SYSREG_ENC(2, 0, 2, 2, 0),
525 OSDTRTX_EL1 = A64_SYSREG_ENC(2, 0, 2, 3, 0),
526 OSECCR_EL11 = A64_SYSREG_ENC(2, 0, 2, 6, 0),
527
528 DBGBVR0_EL1 = A64_SYSREG_ENC(2, 0, 4, 0, 0),
529 DBGBVR1_EL1 = A64_SYSREG_ENC(2, 0, 4, 1, 0),
530 DBGBVR2_EL1 = A64_SYSREG_ENC(2, 0, 4, 2, 0),
531 DBGBVR3_EL1 = A64_SYSREG_ENC(2, 0, 4, 3, 0),
532 DBGBVR4_EL1 = A64_SYSREG_ENC(2, 0, 4, 4, 0),
533 DBGBVR5_EL1 = A64_SYSREG_ENC(2, 0, 4, 5, 0),
534 DBGBVR6_EL1 = A64_SYSREG_ENC(2, 0, 4, 6, 0),
535 DBGBVR7_EL1 = A64_SYSREG_ENC(2, 0, 4, 7, 0),
536 DBGBVR8_EL1 = A64_SYSREG_ENC(2, 0, 4, 8, 0),
537 DBGBVR9_EL1 = A64_SYSREG_ENC(2, 0, 4, 9, 0),
538 DBGBVR10_EL1 = A64_SYSREG_ENC(2, 0, 4, 10, 0),
539 DBGBVR11_EL1 = A64_SYSREG_ENC(2, 0, 4, 11, 0),
540 DBGBVR12_EL1 = A64_SYSREG_ENC(2, 0, 4, 12, 0),
541 DBGBVR13_EL1 = A64_SYSREG_ENC(2, 0, 4, 13, 0),
542 DBGBVR14_EL1 = A64_SYSREG_ENC(2, 0, 4, 14, 0),
543 DBGBVR15_EL1 = A64_SYSREG_ENC(2, 0, 4, 15, 0),
544
545 DBGBCR0_EL1 = A64_SYSREG_ENC(2, 0, 5, 0, 0),
546 DBGBCR1_EL1 = A64_SYSREG_ENC(2, 0, 5, 1, 0),
547 DBGBCR2_EL1 = A64_SYSREG_ENC(2, 0, 5, 2, 0),
548 DBGBCR3_EL1 = A64_SYSREG_ENC(2, 0, 5, 3, 0),
549 DBGBCR4_EL1 = A64_SYSREG_ENC(2, 0, 5, 4, 0),
550 DBGBCR5_EL1 = A64_SYSREG_ENC(2, 0, 5, 5, 0),
551 DBGBCR6_EL1 = A64_SYSREG_ENC(2, 0, 5, 6, 0),
552 DBGBCR7_EL1 = A64_SYSREG_ENC(2, 0, 5, 7, 0),
553 DBGBCR8_EL1 = A64_SYSREG_ENC(2, 0, 5, 8, 0),
554 DBGBCR9_EL1 = A64_SYSREG_ENC(2, 0, 5, 9, 0),
555 DBGBCR10_EL1 = A64_SYSREG_ENC(2, 0, 5, 10, 0),
556 DBGBCR11_EL1 = A64_SYSREG_ENC(2, 0, 5, 11, 0),
557 DBGBCR12_EL1 = A64_SYSREG_ENC(2, 0, 5, 12, 0),
558 DBGBCR13_EL1 = A64_SYSREG_ENC(2, 0, 5, 13, 0),
559 DBGBCR14_EL1 = A64_SYSREG_ENC(2, 0, 5, 14, 0),
560 DBGBCR15_EL1 = A64_SYSREG_ENC(2, 0, 5, 15, 0),
561
562 DBGWVR0_EL1 = A64_SYSREG_ENC(2, 0, 6, 0, 0),
563 DBGWVR1_EL1 = A64_SYSREG_ENC(2, 0, 6, 1, 0),
564 DBGWVR2_EL1 = A64_SYSREG_ENC(2, 0, 6, 2, 0),
565 DBGWVR3_EL1 = A64_SYSREG_ENC(2, 0, 6, 3, 0),
566 DBGWVR4_EL1 = A64_SYSREG_ENC(2, 0, 6, 4, 0),
567 DBGWVR5_EL1 = A64_SYSREG_ENC(2, 0, 6, 5, 0),
568 DBGWVR6_EL1 = A64_SYSREG_ENC(2, 0, 6, 6, 0),
569 DBGWVR7_EL1 = A64_SYSREG_ENC(2, 0, 6, 7, 0),
570 DBGWVR8_EL1 = A64_SYSREG_ENC(2, 0, 6, 8, 0),
571 DBGWVR9_EL1 = A64_SYSREG_ENC(2, 0, 6, 9, 0),
572 DBGWVR10_EL1 = A64_SYSREG_ENC(2, 0, 6, 10, 0),
573 DBGWVR11_EL1 = A64_SYSREG_ENC(2, 0, 6, 11, 0),
574 DBGWVR12_EL1 = A64_SYSREG_ENC(2, 0, 6, 12, 0),
575 DBGWVR13_EL1 = A64_SYSREG_ENC(2, 0, 6, 13, 0),
576 DBGWVR14_EL1 = A64_SYSREG_ENC(2, 0, 6, 14, 0),
577 DBGWVR15_EL1 = A64_SYSREG_ENC(2, 0, 6, 15, 0),
578
579 DBGWCR0_EL1 = A64_SYSREG_ENC(2, 0, 7, 0, 0),
580 DBGWCR1_EL1 = A64_SYSREG_ENC(2, 0, 7, 1, 0),
581 DBGWCR2_EL1 = A64_SYSREG_ENC(2, 0, 7, 2, 0),
582 DBGWCR3_EL1 = A64_SYSREG_ENC(2, 0, 7, 3, 0),
583 DBGWCR4_EL1 = A64_SYSREG_ENC(2, 0, 7, 4, 0),
584 DBGWCR5_EL1 = A64_SYSREG_ENC(2, 0, 7, 5, 0),
585 DBGWCR6_EL1 = A64_SYSREG_ENC(2, 0, 7, 6, 0),
586 DBGWCR7_EL1 = A64_SYSREG_ENC(2, 0, 7, 7, 0),
587 DBGWCR8_EL1 = A64_SYSREG_ENC(2, 0, 7, 8, 0),
588 DBGWCR9_EL1 = A64_SYSREG_ENC(2, 0, 7, 9, 0),
589 DBGWCR10_EL1 = A64_SYSREG_ENC(2, 0, 7, 10, 0),
590 DBGWCR11_EL1 = A64_SYSREG_ENC(2, 0, 7, 11, 0),
591 DBGWCR12_EL1 = A64_SYSREG_ENC(2, 0, 7, 12, 0),
592 DBGWCR13_EL1 = A64_SYSREG_ENC(2, 0, 7, 13, 0),
593 DBGWCR14_EL1 = A64_SYSREG_ENC(2, 0, 7, 14, 0),
594 DBGWCR15_EL1 = A64_SYSREG_ENC(2, 0, 7, 15, 0),
595
596 MDRAR_EL1 = A64_SYSREG_ENC(2, 1, 0, 0, 0),
597 OSLAR_EL1 = A64_SYSREG_ENC(2, 1, 4, 0, 0),
598 OSLSR_EL1 = A64_SYSREG_ENC(2, 1, 4, 1, 0),
599 OSDLR_EL1 = A64_SYSREG_ENC(2, 1, 4, 3, 0),
600 DBGPRCR_EL1 = A64_SYSREG_ENC(2, 1, 4, 4, 0),
601
602 DBGCLAIMSET_EL1 = A64_SYSREG_ENC(2, 7, 6, 8, 0),
603 DBGCLAIMCLR_EL1 = A64_SYSREG_ENC(2, 7, 6, 9, 0),
604 DBGAUTHSTATUS_EL1 = A64_SYSREG_ENC(2, 7, 6, 14, 0),
605
606 DBGDEVID2 = A64_SYSREG_ENC(2, 7, 7, 0, 0),
607 DBGDEVID1 = A64_SYSREG_ENC(2, 7, 7, 1, 0),
608 DBGDEVID0 = A64_SYSREG_ENC(2, 7, 7, 2, 0),
609
610 // The following registers are defined to allow access from AArch64 to
611 // registers which are only used in the AArch32 architecture.
612 DACR32_EL2 = 0xe180,
613 IFSR32_EL2 = 0xe281,
614 TEEHBR32_EL1 = 0x9080,
615 SDER32_EL3 = 0xf089,
616 FPEXC32_EL2 = 0xe298,
617
618 // Cyclone specific system registers
619 CPM_IOACC_CTL_EL3 = 0xff90,
620
621 // Architectural system registers
622 ID_PFR0_EL1 = 0xc008,
623 ID_PFR1_EL1 = 0xc009,
624 ID_DFR0_EL1 = 0xc00a,
625 ID_AFR0_EL1 = 0xc00b,
626 ID_ISAR0_EL1 = 0xc010,
627 ID_ISAR1_EL1 = 0xc011,
628 ID_ISAR2_EL1 = 0xc012,
629 ID_ISAR3_EL1 = 0xc013,
630 ID_ISAR4_EL1 = 0xc014,
631 ID_ISAR5_EL1 = 0xc015,
632 AFSR1_EL1 = 0xc289, // note same as old AIFSR_EL1
633 AFSR0_EL1 = 0xc288, // note same as old ADFSR_EL1
634 REVIDR_EL1 = 0xc006 // note same as old ECOIDR_EL1
635
636};
637#undef A64_SYSREG_ENC
638
639static inline const char *getSystemRegisterName(SystemRegister Reg) {
640 switch(Reg) {
641 default: return NULL; // Caller is responsible for handling invalid value.
642 case SPSR_EL1: return "SPSR_EL1";
643 case ELR_EL1: return "ELR_EL1";
644 case SP_EL0: return "SP_EL0";
645 case SPSel: return "SPSel";
646 case DAIF: return "DAIF";
647 case CurrentEL: return "CurrentEL";
648 case NZCV: return "NZCV";
649 case FPCR: return "FPCR";
650 case FPSR: return "FPSR";
651 case DSPSR: return "DSPSR";
652 case DLR: return "DLR";
653 case SPSR_EL2: return "SPSR_EL2";
654 case ELR_EL2: return "ELR_EL2";
655 case SP_EL1: return "SP_EL1";
656 case SPSR_irq: return "SPSR_irq";
657 case SPSR_abt: return "SPSR_abt";
658 case SPSR_und: return "SPSR_und";
659 case SPSR_fiq: return "SPSR_fiq";
660 case SPSR_EL3: return "SPSR_EL3";
661 case ELR_EL3: return "ELR_EL3";
662 case SP_EL2: return "SP_EL2";
663 case MIDR_EL1: return "MIDR_EL1";
664 case CTR_EL0: return "CTR_EL0";
665 case MPIDR_EL1: return "MPIDR_EL1";
666 case DCZID_EL0: return "DCZID_EL0";
667 case MVFR0_EL1: return "MVFR0_EL1";
668 case MVFR1_EL1: return "MVFR1_EL1";
669 case ID_AA64PFR0_EL1: return "ID_AA64PFR0_EL1";
670 case ID_AA64PFR1_EL1: return "ID_AA64PFR1_EL1";
671 case ID_AA64DFR0_EL1: return "ID_AA64DFR0_EL1";
672 case ID_AA64DFR1_EL1: return "ID_AA64DFR1_EL1";
673 case ID_AA64ISAR0_EL1: return "ID_AA64ISAR0_EL1";
674 case ID_AA64ISAR1_EL1: return "ID_AA64ISAR1_EL1";
675 case ID_AA64MMFR0_EL1: return "ID_AA64MMFR0_EL1";
676 case ID_AA64MMFR1_EL1: return "ID_AA64MMFR1_EL1";
677 case CCSIDR_EL1: return "CCSIDR_EL1";
678 case CLIDR_EL1: return "CLIDR_EL1";
679 case AIDR_EL1: return "AIDR_EL1";
680 case CSSELR_EL1: return "CSSELR_EL1";
681 case VPIDR_EL2: return "VPIDR_EL2";
682 case VMPIDR_EL2: return "VMPIDR_EL2";
683 case SCTLR_EL1: return "SCTLR_EL1";
684 case SCTLR_EL2: return "SCTLR_EL2";
685 case SCTLR_EL3: return "SCTLR_EL3";
686 case ACTLR_EL1: return "ACTLR_EL1";
687 case ACTLR_EL2: return "ACTLR_EL2";
688 case ACTLR_EL3: return "ACTLR_EL3";
689 case CPACR_EL1: return "CPACR_EL1";
690 case CPTR_EL2: return "CPTR_EL2";
691 case CPTR_EL3: return "CPTR_EL3";
692 case SCR_EL3: return "SCR_EL3";
693 case HCR_EL2: return "HCR_EL2";
694 case MDCR_EL2: return "MDCR_EL2";
695 case MDCR_EL3: return "MDCR_EL3";
696 case HSTR_EL2: return "HSTR_EL2";
697 case HACR_EL2: return "HACR_EL2";
698 case TTBR0_EL1: return "TTBR0_EL1";
699 case TTBR1_EL1: return "TTBR1_EL1";
700 case TTBR0_EL2: return "TTBR0_EL2";
701 case TTBR0_EL3: return "TTBR0_EL3";
702 case VTTBR_EL2: return "VTTBR_EL2";
703 case TCR_EL1: return "TCR_EL1";
704 case TCR_EL2: return "TCR_EL2";
705 case TCR_EL3: return "TCR_EL3";
706 case VTCR_EL2: return "VTCR_EL2";
707 case ADFSR_EL2: return "ADFSR_EL2";
708 case AIFSR_EL2: return "AIFSR_EL2";
709 case ADFSR_EL3: return "ADFSR_EL3";
710 case AIFSR_EL3: return "AIFSR_EL3";
711 case ESR_EL1: return "ESR_EL1";
712 case ESR_EL2: return "ESR_EL2";
713 case ESR_EL3: return "ESR_EL3";
714 case FAR_EL1: return "FAR_EL1";
715 case FAR_EL2: return "FAR_EL2";
716 case FAR_EL3: return "FAR_EL3";
717 case HPFAR_EL2: return "HPFAR_EL2";
718 case PAR_EL1: return "PAR_EL1";
719 case MAIR_EL1: return "MAIR_EL1";
720 case MAIR_EL2: return "MAIR_EL2";
721 case MAIR_EL3: return "MAIR_EL3";
722 case AMAIR_EL1: return "AMAIR_EL1";
723 case AMAIR_EL2: return "AMAIR_EL2";
724 case AMAIR_EL3: return "AMAIR_EL3";
725 case VBAR_EL1: return "VBAR_EL1";
726 case VBAR_EL2: return "VBAR_EL2";
727 case VBAR_EL3: return "VBAR_EL3";
728 case RVBAR_EL1: return "RVBAR_EL1";
729 case RVBAR_EL2: return "RVBAR_EL2";
730 case RVBAR_EL3: return "RVBAR_EL3";
731 case ISR_EL1: return "ISR_EL1";
732 case CONTEXTIDR_EL1: return "CONTEXTIDR_EL1";
733 case TPIDR_EL0: return "TPIDR_EL0";
734 case TPIDRRO_EL0: return "TPIDRRO_EL0";
735 case TPIDR_EL1: return "TPIDR_EL1";
736 case TPIDR_EL2: return "TPIDR_EL2";
737 case TPIDR_EL3: return "TPIDR_EL3";
738 case TEECR32_EL1: return "TEECR32_EL1";
739 case CNTFRQ_EL0: return "CNTFRQ_EL0";
740 case CNTPCT_EL0: return "CNTPCT_EL0";
741 case CNTVCT_EL0: return "CNTVCT_EL0";
742 case CNTVOFF_EL2: return "CNTVOFF_EL2";
743 case CNTKCTL_EL1: return "CNTKCTL_EL1";
744 case CNTHCTL_EL2: return "CNTHCTL_EL2";
745 case CNTP_TVAL_EL0: return "CNTP_TVAL_EL0";
746 case CNTP_CTL_EL0: return "CNTP_CTL_EL0";
747 case CNTP_CVAL_EL0: return "CNTP_CVAL_EL0";
748 case CNTV_TVAL_EL0: return "CNTV_TVAL_EL0";
749 case CNTV_CTL_EL0: return "CNTV_CTL_EL0";
750 case CNTV_CVAL_EL0: return "CNTV_CVAL_EL0";
751 case CNTHP_TVAL_EL2: return "CNTHP_TVAL_EL2";
752 case CNTHP_CTL_EL2: return "CNTHP_CTL_EL2";
753 case CNTHP_CVAL_EL2: return "CNTHP_CVAL_EL2";
754 case CNTPS_TVAL_EL1: return "CNTPS_TVAL_EL1";
755 case CNTPS_CTL_EL1: return "CNTPS_CTL_EL1";
756 case CNTPS_CVAL_EL1: return "CNTPS_CVAL_EL1";
757 case DACR32_EL2: return "DACR32_EL2";
758 case IFSR32_EL2: return "IFSR32_EL2";
759 case TEEHBR32_EL1: return "TEEHBR32_EL1";
760 case SDER32_EL3: return "SDER32_EL3";
761 case FPEXC32_EL2: return "FPEXC32_EL2";
762 case PMEVCNTR0_EL0: return "PMEVCNTR0_EL0";
763 case PMEVCNTR1_EL0: return "PMEVCNTR1_EL0";
764 case PMEVCNTR2_EL0: return "PMEVCNTR2_EL0";
765 case PMEVCNTR3_EL0: return "PMEVCNTR3_EL0";
766 case PMEVCNTR4_EL0: return "PMEVCNTR4_EL0";
767 case PMEVCNTR5_EL0: return "PMEVCNTR5_EL0";
768 case PMEVCNTR6_EL0: return "PMEVCNTR6_EL0";
769 case PMEVCNTR7_EL0: return "PMEVCNTR7_EL0";
770 case PMEVCNTR8_EL0: return "PMEVCNTR8_EL0";
771 case PMEVCNTR9_EL0: return "PMEVCNTR9_EL0";
772 case PMEVCNTR10_EL0: return "PMEVCNTR10_EL0";
773 case PMEVCNTR11_EL0: return "PMEVCNTR11_EL0";
774 case PMEVCNTR12_EL0: return "PMEVCNTR12_EL0";
775 case PMEVCNTR13_EL0: return "PMEVCNTR13_EL0";
776 case PMEVCNTR14_EL0: return "PMEVCNTR14_EL0";
777 case PMEVCNTR15_EL0: return "PMEVCNTR15_EL0";
778 case PMEVCNTR16_EL0: return "PMEVCNTR16_EL0";
779 case PMEVCNTR17_EL0: return "PMEVCNTR17_EL0";
780 case PMEVCNTR18_EL0: return "PMEVCNTR18_EL0";
781 case PMEVCNTR19_EL0: return "PMEVCNTR19_EL0";
782 case PMEVCNTR20_EL0: return "PMEVCNTR20_EL0";
783 case PMEVCNTR21_EL0: return "PMEVCNTR21_EL0";
784 case PMEVCNTR22_EL0: return "PMEVCNTR22_EL0";
785 case PMEVCNTR23_EL0: return "PMEVCNTR23_EL0";
786 case PMEVCNTR24_EL0: return "PMEVCNTR24_EL0";
787 case PMEVCNTR25_EL0: return "PMEVCNTR25_EL0";
788 case PMEVCNTR26_EL0: return "PMEVCNTR26_EL0";
789 case PMEVCNTR27_EL0: return "PMEVCNTR27_EL0";
790 case PMEVCNTR28_EL0: return "PMEVCNTR28_EL0";
791 case PMEVCNTR29_EL0: return "PMEVCNTR29_EL0";
792 case PMEVCNTR30_EL0: return "PMEVCNTR30_EL0";
793 case PMEVTYPER0_EL0: return "PMEVTYPER0_EL0";
794 case PMEVTYPER1_EL0: return "PMEVTYPER1_EL0";
795 case PMEVTYPER2_EL0: return "PMEVTYPER2_EL0";
796 case PMEVTYPER3_EL0: return "PMEVTYPER3_EL0";
797 case PMEVTYPER4_EL0: return "PMEVTYPER4_EL0";
798 case PMEVTYPER5_EL0: return "PMEVTYPER5_EL0";
799 case PMEVTYPER6_EL0: return "PMEVTYPER6_EL0";
800 case PMEVTYPER7_EL0: return "PMEVTYPER7_EL0";
801 case PMEVTYPER8_EL0: return "PMEVTYPER8_EL0";
802 case PMEVTYPER9_EL0: return "PMEVTYPER9_EL0";
803 case PMEVTYPER10_EL0: return "PMEVTYPER10_EL0";
804 case PMEVTYPER11_EL0: return "PMEVTYPER11_EL0";
805 case PMEVTYPER12_EL0: return "PMEVTYPER12_EL0";
806 case PMEVTYPER13_EL0: return "PMEVTYPER13_EL0";
807 case PMEVTYPER14_EL0: return "PMEVTYPER14_EL0";
808 case PMEVTYPER15_EL0: return "PMEVTYPER15_EL0";
809 case PMEVTYPER16_EL0: return "PMEVTYPER16_EL0";
810 case PMEVTYPER17_EL0: return "PMEVTYPER17_EL0";
811 case PMEVTYPER18_EL0: return "PMEVTYPER18_EL0";
812 case PMEVTYPER19_EL0: return "PMEVTYPER19_EL0";
813 case PMEVTYPER20_EL0: return "PMEVTYPER20_EL0";
814 case PMEVTYPER21_EL0: return "PMEVTYPER21_EL0";
815 case PMEVTYPER22_EL0: return "PMEVTYPER22_EL0";
816 case PMEVTYPER23_EL0: return "PMEVTYPER23_EL0";
817 case PMEVTYPER24_EL0: return "PMEVTYPER24_EL0";
818 case PMEVTYPER25_EL0: return "PMEVTYPER25_EL0";
819 case PMEVTYPER26_EL0: return "PMEVTYPER26_EL0";
820 case PMEVTYPER27_EL0: return "PMEVTYPER27_EL0";
821 case PMEVTYPER28_EL0: return "PMEVTYPER28_EL0";
822 case PMEVTYPER29_EL0: return "PMEVTYPER29_EL0";
823 case PMEVTYPER30_EL0: return "PMEVTYPER30_EL0";
824 case PMCCFILTR_EL0: return "PMCCFILTR_EL0";
825 case RMR_EL3: return "RMR_EL3";
826 case RMR_EL2: return "RMR_EL2";
827 case RMR_EL1: return "RMR_EL1";
828 case CPM_IOACC_CTL_EL3: return "CPM_IOACC_CTL_EL3";
829 case MDCCSR_EL0: return "MDCCSR_EL0";
830 case MDCCINT_EL1: return "MDCCINT_EL1";
831 case DBGDTR_EL0: return "DBGDTR_EL0";
832 case DBGDTRRX_EL0: return "DBGDTRRX_EL0";
833 case DBGVCR32_EL2: return "DBGVCR32_EL2";
834 case OSDTRRX_EL1: return "OSDTRRX_EL1";
835 case MDSCR_EL1: return "MDSCR_EL1";
836 case OSDTRTX_EL1: return "OSDTRTX_EL1";
837 case OSECCR_EL11: return "OSECCR_EL11";
838 case DBGBVR0_EL1: return "DBGBVR0_EL1";
839 case DBGBVR1_EL1: return "DBGBVR1_EL1";
840 case DBGBVR2_EL1: return "DBGBVR2_EL1";
841 case DBGBVR3_EL1: return "DBGBVR3_EL1";
842 case DBGBVR4_EL1: return "DBGBVR4_EL1";
843 case DBGBVR5_EL1: return "DBGBVR5_EL1";
844 case DBGBVR6_EL1: return "DBGBVR6_EL1";
845 case DBGBVR7_EL1: return "DBGBVR7_EL1";
846 case DBGBVR8_EL1: return "DBGBVR8_EL1";
847 case DBGBVR9_EL1: return "DBGBVR9_EL1";
848 case DBGBVR10_EL1: return "DBGBVR10_EL1";
849 case DBGBVR11_EL1: return "DBGBVR11_EL1";
850 case DBGBVR12_EL1: return "DBGBVR12_EL1";
851 case DBGBVR13_EL1: return "DBGBVR13_EL1";
852 case DBGBVR14_EL1: return "DBGBVR14_EL1";
853 case DBGBVR15_EL1: return "DBGBVR15_EL1";
854 case DBGBCR0_EL1: return "DBGBCR0_EL1";
855 case DBGBCR1_EL1: return "DBGBCR1_EL1";
856 case DBGBCR2_EL1: return "DBGBCR2_EL1";
857 case DBGBCR3_EL1: return "DBGBCR3_EL1";
858 case DBGBCR4_EL1: return "DBGBCR4_EL1";
859 case DBGBCR5_EL1: return "DBGBCR5_EL1";
860 case DBGBCR6_EL1: return "DBGBCR6_EL1";
861 case DBGBCR7_EL1: return "DBGBCR7_EL1";
862 case DBGBCR8_EL1: return "DBGBCR8_EL1";
863 case DBGBCR9_EL1: return "DBGBCR9_EL1";
864 case DBGBCR10_EL1: return "DBGBCR10_EL1";
865 case DBGBCR11_EL1: return "DBGBCR11_EL1";
866 case DBGBCR12_EL1: return "DBGBCR12_EL1";
867 case DBGBCR13_EL1: return "DBGBCR13_EL1";
868 case DBGBCR14_EL1: return "DBGBCR14_EL1";
869 case DBGBCR15_EL1: return "DBGBCR15_EL1";
870 case DBGWVR0_EL1: return "DBGWVR0_EL1";
871 case DBGWVR1_EL1: return "DBGWVR1_EL1";
872 case DBGWVR2_EL1: return "DBGWVR2_EL1";
873 case DBGWVR3_EL1: return "DBGWVR3_EL1";
874 case DBGWVR4_EL1: return "DBGWVR4_EL1";
875 case DBGWVR5_EL1: return "DBGWVR5_EL1";
876 case DBGWVR6_EL1: return "DBGWVR6_EL1";
877 case DBGWVR7_EL1: return "DBGWVR7_EL1";
878 case DBGWVR8_EL1: return "DBGWVR8_EL1";
879 case DBGWVR9_EL1: return "DBGWVR9_EL1";
880 case DBGWVR10_EL1: return "DBGWVR10_EL1";
881 case DBGWVR11_EL1: return "DBGWVR11_EL1";
882 case DBGWVR12_EL1: return "DBGWVR12_EL1";
883 case DBGWVR13_EL1: return "DBGWVR13_EL1";
884 case DBGWVR14_EL1: return "DBGWVR14_EL1";
885 case DBGWVR15_EL1: return "DBGWVR15_EL1";
886 case DBGWCR0_EL1: return "DBGWCR0_EL1";
887 case DBGWCR1_EL1: return "DBGWCR1_EL1";
888 case DBGWCR2_EL1: return "DBGWCR2_EL1";
889 case DBGWCR3_EL1: return "DBGWCR3_EL1";
890 case DBGWCR4_EL1: return "DBGWCR4_EL1";
891 case DBGWCR5_EL1: return "DBGWCR5_EL1";
892 case DBGWCR6_EL1: return "DBGWCR6_EL1";
893 case DBGWCR7_EL1: return "DBGWCR7_EL1";
894 case DBGWCR8_EL1: return "DBGWCR8_EL1";
895 case DBGWCR9_EL1: return "DBGWCR9_EL1";
896 case DBGWCR10_EL1: return "DBGWCR10_EL1";
897 case DBGWCR11_EL1: return "DBGWCR11_EL1";
898 case DBGWCR12_EL1: return "DBGWCR12_EL1";
899 case DBGWCR13_EL1: return "DBGWCR13_EL1";
900 case DBGWCR14_EL1: return "DBGWCR14_EL1";
901 case DBGWCR15_EL1: return "DBGWCR15_EL1";
902 case MDRAR_EL1: return "MDRAR_EL1";
903 case OSLAR_EL1: return "OSLAR_EL1";
904 case OSLSR_EL1: return "OSLSR_EL1";
905 case OSDLR_EL1: return "OSDLR_EL1";
906 case DBGPRCR_EL1: return "DBGPRCR_EL1";
907 case DBGCLAIMSET_EL1: return "DBGCLAIMSET_EL1";
908 case DBGCLAIMCLR_EL1: return "DBGCLAIMCLR_EL1";
909 case DBGAUTHSTATUS_EL1: return "DBGAUTHSTATUS_EL1";
910 case DBGDEVID2: return "DBGDEVID2";
911 case DBGDEVID1: return "DBGDEVID1";
912 case DBGDEVID0: return "DBGDEVID0";
913 case ID_PFR0_EL1: return "ID_PFR0_EL1";
914 case ID_PFR1_EL1: return "ID_PFR1_EL1";
915 case ID_DFR0_EL1: return "ID_DFR0_EL1";
916 case ID_AFR0_EL1: return "ID_AFR0_EL1";
917 case ID_ISAR0_EL1: return "ID_ISAR0_EL1";
918 case ID_ISAR1_EL1: return "ID_ISAR1_EL1";
919 case ID_ISAR2_EL1: return "ID_ISAR2_EL1";
920 case ID_ISAR3_EL1: return "ID_ISAR3_EL1";
921 case ID_ISAR4_EL1: return "ID_ISAR4_EL1";
922 case ID_ISAR5_EL1: return "ID_ISAR5_EL1";
923 case AFSR1_EL1: return "AFSR1_EL1";
924 case AFSR0_EL1: return "AFSR0_EL1";
925 case REVIDR_EL1: return "REVIDR_EL1";
926 }
927}
928
929enum CPSRField {
930 InvalidCPSRField = 0xff,
931 cpsr_SPSel = 0x5,
932 cpsr_DAIFSet = 0x1e,
933 cpsr_DAIFClr = 0x1f
934};
935
936static inline const char *getCPSRFieldName(CPSRField Val) {
937 switch(Val) {
938 default: assert(0 && "Invalid system register value!");
939 case cpsr_SPSel: return "SPSel";
940 case cpsr_DAIFSet: return "DAIFSet";
941 case cpsr_DAIFClr: return "DAIFClr";
942 }
943}
944
945} // end namespace ARM64SYS
946
Bradley Smithceeb04d2014-04-09 14:42:16 +0000[diff] [blame]947/// Instances of this class can perform bidirectional mapping from random
948/// identifier strings to operand encodings. For example "MSR" takes a named
949/// system-register which must be encoded somehow and decoded for printing. This
950/// central location means that the information for those transformations is not
951/// duplicated and remains in sync.
952///
953/// FIXME: currently the algorithm is a completely unoptimised linear
954/// search. Obviously this could be improved, but we would probably want to work
955/// out just how often these instructions are emitted before working on it. It
956/// might even be optimal to just reorder the tables for the common instructions
957/// rather than changing the algorithm.
958struct ARM64NamedImmMapper {
959 struct Mapping {
960 const char *Name;
961 uint32_t Value;
962 };
963
964 template<int N>
965 ARM64NamedImmMapper(const Mapping (&Pairs)[N], uint32_t TooBigImm)
966 : Pairs(&Pairs[0]), NumPairs(N), TooBigImm(TooBigImm) {}
967
968 StringRef toString(uint32_t Value, bool &Valid) const;
969 uint32_t fromString(StringRef Name, bool &Valid) const;
970
971 /// Many of the instructions allow an alternative assembly form consisting of
972 /// a simple immediate. Currently the only valid forms are ranges [0, N) where
973 /// N being 0 indicates no immediate syntax-form is allowed.
974 bool validImm(uint32_t Value) const;
975protected:
976 const Mapping *Pairs;
977 size_t NumPairs;
978 uint32_t TooBigImm;
979};
980
981namespace ARM64AT {
982 enum ATValues {
983 Invalid = -1, // Op0 Op1 CRn CRm Op2
984 S1E1R = 0x43c0, // 01 000 0111 1000 000
985 S1E2R = 0x63c0, // 01 100 0111 1000 000
986 S1E3R = 0x73c0, // 01 110 0111 1000 000
987 S1E1W = 0x43c1, // 01 000 0111 1000 001
988 S1E2W = 0x63c1, // 01 100 0111 1000 001
989 S1E3W = 0x73c1, // 01 110 0111 1000 001
990 S1E0R = 0x43c2, // 01 000 0111 1000 010
991 S1E0W = 0x43c3, // 01 000 0111 1000 011
992 S12E1R = 0x63c4, // 01 100 0111 1000 100
993 S12E1W = 0x63c5, // 01 100 0111 1000 101
994 S12E0R = 0x63c6, // 01 100 0111 1000 110
995 S12E0W = 0x63c7 // 01 100 0111 1000 111
996 };
997
998 struct ATMapper : ARM64NamedImmMapper {
999 const static Mapping ATPairs[];
1000
1001 ATMapper();
1002 };
1003
1004}
1005namespace ARM64DB {
1006 enum DBValues {
1007 Invalid = -1,
1008 OSHLD = 0x1,
1009 OSHST = 0x2,
1010 OSH = 0x3,
1011 NSHLD = 0x5,
1012 NSHST = 0x6,
1013 NSH = 0x7,
1014 ISHLD = 0x9,
1015 ISHST = 0xa,
1016 ISH = 0xb,
1017 LD = 0xd,
1018 ST = 0xe,
1019 SY = 0xf
1020 };
1021
1022 struct DBarrierMapper : ARM64NamedImmMapper {
1023 const static Mapping DBarrierPairs[];
1024
1025 DBarrierMapper();
1026 };
1027}
1028
1029namespace ARM64DC {
1030 enum DCValues {
1031 Invalid = -1, // Op1 CRn CRm Op2
1032 ZVA = 0x5ba1, // 01 011 0111 0100 001
1033 IVAC = 0x43b1, // 01 000 0111 0110 001
1034 ISW = 0x43b2, // 01 000 0111 0110 010
1035 CVAC = 0x5bd1, // 01 011 0111 1010 001
1036 CSW = 0x43d2, // 01 000 0111 1010 010
1037 CVAU = 0x5bd9, // 01 011 0111 1011 001
1038 CIVAC = 0x5bf1, // 01 011 0111 1110 001
1039 CISW = 0x43f2 // 01 000 0111 1110 010
1040 };
1041
1042 struct DCMapper : ARM64NamedImmMapper {
1043 const static Mapping DCPairs[];
1044
1045 DCMapper();
1046 };
1047
1048}
1049
1050namespace ARM64IC {
1051 enum ICValues {
1052 Invalid = -1, // Op1 CRn CRm Op2
1053 IALLUIS = 0x0388, // 000 0111 0001 000
1054 IALLU = 0x03a8, // 000 0111 0101 000
1055 IVAU = 0x1ba9 // 011 0111 0101 001
1056 };
1057
1058
1059 struct ICMapper : ARM64NamedImmMapper {
1060 const static Mapping ICPairs[];
1061
1062 ICMapper();
1063 };
1064
1065 static inline bool NeedsRegister(ICValues Val) {
1066 return Val == IVAU;
1067 }
1068}
1069
1070namespace ARM64ISB {
1071 enum ISBValues {
1072 Invalid = -1,
1073 SY = 0xf
1074 };
1075 struct ISBMapper : ARM64NamedImmMapper {
1076 const static Mapping ISBPairs[];
1077
1078 ISBMapper();
1079 };
1080}
1081
1082namespace ARM64PRFM {
1083 enum PRFMValues {
1084 Invalid = -1,
1085 PLDL1KEEP = 0x00,
1086 PLDL1STRM = 0x01,
1087 PLDL2KEEP = 0x02,
1088 PLDL2STRM = 0x03,
1089 PLDL3KEEP = 0x04,
1090 PLDL3STRM = 0x05,
1091 PLIL1KEEP = 0x08,
1092 PLIL1STRM = 0x09,
1093 PLIL2KEEP = 0x0a,
1094 PLIL2STRM = 0x0b,
1095 PLIL3KEEP = 0x0c,
1096 PLIL3STRM = 0x0d,
1097 PSTL1KEEP = 0x10,
1098 PSTL1STRM = 0x11,
1099 PSTL2KEEP = 0x12,
1100 PSTL2STRM = 0x13,
1101 PSTL3KEEP = 0x14,
1102 PSTL3STRM = 0x15
1103 };
1104
1105 struct PRFMMapper : ARM64NamedImmMapper {
1106 const static Mapping PRFMPairs[];
1107
1108 PRFMMapper();
1109 };
1110}
1111
1112namespace ARM64PState {
1113 enum PStateValues {
1114 Invalid = -1,
1115 SPSel = 0x05,
1116 DAIFSet = 0x1e,
1117 DAIFClr = 0x1f
1118 };
1119
1120 struct PStateMapper : ARM64NamedImmMapper {
1121 const static Mapping PStatePairs[];
1122
1123 PStateMapper();
1124 };
1125
1126}
1127
1128namespace ARM64SE {
1129 enum ShiftExtSpecifiers {
1130 Invalid = -1,
1131 LSL,
1132 MSL,
1133 LSR,
1134 ASR,
1135 ROR,
1136
1137 UXTB,
1138 UXTH,
1139 UXTW,
1140 UXTX,
1141
1142 SXTB,
1143 SXTH,
1144 SXTW,
1145 SXTX
1146 };
1147}
1148
1149namespace ARM64Layout {
1150 enum VectorLayout {
1151 Invalid = -1,
1152 VL_8B,
1153 VL_4H,
1154 VL_2S,
1155 VL_1D,
1156
1157 VL_16B,
1158 VL_8H,
1159 VL_4S,
1160 VL_2D,
1161
1162 // Bare layout for the 128-bit vector
1163 // (only show ".b", ".h", ".s", ".d" without vector number)
1164 VL_B,
1165 VL_H,
1166 VL_S,
1167 VL_D
1168 };
1169}
1170
1171inline static const char *
1172ARM64VectorLayoutToString(ARM64Layout::VectorLayout Layout) {
1173 switch (Layout) {
1174 case ARM64Layout::VL_8B: return ".8b";
1175 case ARM64Layout::VL_4H: return ".4h";
1176 case ARM64Layout::VL_2S: return ".2s";
1177 case ARM64Layout::VL_1D: return ".1d";
1178 case ARM64Layout::VL_16B: return ".16b";
1179 case ARM64Layout::VL_8H: return ".8h";
1180 case ARM64Layout::VL_4S: return ".4s";
1181 case ARM64Layout::VL_2D: return ".2d";
1182 case ARM64Layout::VL_B: return ".b";
1183 case ARM64Layout::VL_H: return ".h";
1184 case ARM64Layout::VL_S: return ".s";
1185 case ARM64Layout::VL_D: return ".d";
1186 default: llvm_unreachable("Unknown Vector Layout");
1187 }
1188}
1189
1190inline static ARM64Layout::VectorLayout
1191ARM64StringToVectorLayout(StringRef LayoutStr) {
1192 return StringSwitch<ARM64Layout::VectorLayout>(LayoutStr)
1193 .Case(".8b", ARM64Layout::VL_8B)
1194 .Case(".4h", ARM64Layout::VL_4H)
1195 .Case(".2s", ARM64Layout::VL_2S)
1196 .Case(".1d", ARM64Layout::VL_1D)
1197 .Case(".16b", ARM64Layout::VL_16B)
1198 .Case(".8h", ARM64Layout::VL_8H)
1199 .Case(".4s", ARM64Layout::VL_4S)
1200 .Case(".2d", ARM64Layout::VL_2D)
1201 .Case(".b", ARM64Layout::VL_B)
1202 .Case(".h", ARM64Layout::VL_H)
1203 .Case(".s", ARM64Layout::VL_S)
1204 .Case(".d", ARM64Layout::VL_D)
1205 .Default(ARM64Layout::Invalid);
1206}
1207
1208namespace ARM64SysReg {
1209 enum SysRegROValues {
1210 MDCCSR_EL0 = 0x9808, // 10 011 0000 0001 000
1211 DBGDTRRX_EL0 = 0x9828, // 10 011 0000 0101 000
1212 MDRAR_EL1 = 0x8080, // 10 000 0001 0000 000
1213 OSLSR_EL1 = 0x808c, // 10 000 0001 0001 100
1214 DBGAUTHSTATUS_EL1 = 0x83f6, // 10 000 0111 1110 110
1215 PMCEID0_EL0 = 0xdce6, // 11 011 1001 1100 110
1216 PMCEID1_EL0 = 0xdce7, // 11 011 1001 1100 111
1217 MIDR_EL1 = 0xc000, // 11 000 0000 0000 000
1218 CCSIDR_EL1 = 0xc800, // 11 001 0000 0000 000
1219 CLIDR_EL1 = 0xc801, // 11 001 0000 0000 001
1220 CTR_EL0 = 0xd801, // 11 011 0000 0000 001
1221 MPIDR_EL1 = 0xc005, // 11 000 0000 0000 101
1222 REVIDR_EL1 = 0xc006, // 11 000 0000 0000 110
1223 AIDR_EL1 = 0xc807, // 11 001 0000 0000 111
1224 DCZID_EL0 = 0xd807, // 11 011 0000 0000 111
1225 ID_PFR0_EL1 = 0xc008, // 11 000 0000 0001 000
1226 ID_PFR1_EL1 = 0xc009, // 11 000 0000 0001 001
1227 ID_DFR0_EL1 = 0xc00a, // 11 000 0000 0001 010
1228 ID_AFR0_EL1 = 0xc00b, // 11 000 0000 0001 011
1229 ID_MMFR0_EL1 = 0xc00c, // 11 000 0000 0001 100
1230 ID_MMFR1_EL1 = 0xc00d, // 11 000 0000 0001 101
1231 ID_MMFR2_EL1 = 0xc00e, // 11 000 0000 0001 110
1232 ID_MMFR3_EL1 = 0xc00f, // 11 000 0000 0001 111
1233 ID_ISAR0_EL1 = 0xc010, // 11 000 0000 0010 000
1234 ID_ISAR1_EL1 = 0xc011, // 11 000 0000 0010 001
1235 ID_ISAR2_EL1 = 0xc012, // 11 000 0000 0010 010
1236 ID_ISAR3_EL1 = 0xc013, // 11 000 0000 0010 011
1237 ID_ISAR4_EL1 = 0xc014, // 11 000 0000 0010 100
1238 ID_ISAR5_EL1 = 0xc015, // 11 000 0000 0010 101
1239 ID_AARM64PFR0_EL1 = 0xc020, // 11 000 0000 0100 000
1240 ID_AARM64PFR1_EL1 = 0xc021, // 11 000 0000 0100 001
1241 ID_AARM64DFR0_EL1 = 0xc028, // 11 000 0000 0101 000
1242 ID_AARM64DFR1_EL1 = 0xc029, // 11 000 0000 0101 001
1243 ID_AARM64AFR0_EL1 = 0xc02c, // 11 000 0000 0101 100
1244 ID_AARM64AFR1_EL1 = 0xc02d, // 11 000 0000 0101 101
1245 ID_AARM64ISAR0_EL1 = 0xc030, // 11 000 0000 0110 000
1246 ID_AARM64ISAR1_EL1 = 0xc031, // 11 000 0000 0110 001
1247 ID_AARM64MMFR0_EL1 = 0xc038, // 11 000 0000 0111 000
1248 ID_AARM64MMFR1_EL1 = 0xc039, // 11 000 0000 0111 001
1249 MVFR0_EL1 = 0xc018, // 11 000 0000 0011 000
1250 MVFR1_EL1 = 0xc019, // 11 000 0000 0011 001
1251 MVFR2_EL1 = 0xc01a, // 11 000 0000 0011 010
1252 RVBAR_EL1 = 0xc601, // 11 000 1100 0000 001
1253 RVBAR_EL2 = 0xe601, // 11 100 1100 0000 001
1254 RVBAR_EL3 = 0xf601, // 11 110 1100 0000 001
1255 ISR_EL1 = 0xc608, // 11 000 1100 0001 000
1256 CNTPCT_EL0 = 0xdf01, // 11 011 1110 0000 001
1257 CNTVCT_EL0 = 0xdf02, // 11 011 1110 0000 010
1258
1259 // Trace registers
1260 TRCSTATR = 0x8818, // 10 001 0000 0011 000
1261 TRCIDR8 = 0x8806, // 10 001 0000 0000 110
1262 TRCIDR9 = 0x880e, // 10 001 0000 0001 110
1263 TRCIDR10 = 0x8816, // 10 001 0000 0010 110
1264 TRCIDR11 = 0x881e, // 10 001 0000 0011 110
1265 TRCIDR12 = 0x8826, // 10 001 0000 0100 110
1266 TRCIDR13 = 0x882e, // 10 001 0000 0101 110
1267 TRCIDR0 = 0x8847, // 10 001 0000 1000 111
1268 TRCIDR1 = 0x884f, // 10 001 0000 1001 111
1269 TRCIDR2 = 0x8857, // 10 001 0000 1010 111
1270 TRCIDR3 = 0x885f, // 10 001 0000 1011 111
1271 TRCIDR4 = 0x8867, // 10 001 0000 1100 111
1272 TRCIDR5 = 0x886f, // 10 001 0000 1101 111
1273 TRCIDR6 = 0x8877, // 10 001 0000 1110 111
1274 TRCIDR7 = 0x887f, // 10 001 0000 1111 111
1275 TRCOSLSR = 0x888c, // 10 001 0001 0001 100
1276 TRCPDSR = 0x88ac, // 10 001 0001 0101 100
1277 TRCDEVAFF0 = 0x8bd6, // 10 001 0111 1010 110
1278 TRCDEVAFF1 = 0x8bde, // 10 001 0111 1011 110
1279 TRCLSR = 0x8bee, // 10 001 0111 1101 110
1280 TRCAUTHSTATUS = 0x8bf6, // 10 001 0111 1110 110
1281 TRCDEVARCH = 0x8bfe, // 10 001 0111 1111 110
1282 TRCDEVID = 0x8b97, // 10 001 0111 0010 111
1283 TRCDEVTYPE = 0x8b9f, // 10 001 0111 0011 111
1284 TRCPIDR4 = 0x8ba7, // 10 001 0111 0100 111
1285 TRCPIDR5 = 0x8baf, // 10 001 0111 0101 111
1286 TRCPIDR6 = 0x8bb7, // 10 001 0111 0110 111
1287 TRCPIDR7 = 0x8bbf, // 10 001 0111 0111 111
1288 TRCPIDR0 = 0x8bc7, // 10 001 0111 1000 111
1289 TRCPIDR1 = 0x8bcf, // 10 001 0111 1001 111
1290 TRCPIDR2 = 0x8bd7, // 10 001 0111 1010 111
1291 TRCPIDR3 = 0x8bdf, // 10 001 0111 1011 111
1292 TRCCIDR0 = 0x8be7, // 10 001 0111 1100 111
1293 TRCCIDR1 = 0x8bef, // 10 001 0111 1101 111
1294 TRCCIDR2 = 0x8bf7, // 10 001 0111 1110 111
1295 TRCCIDR3 = 0x8bff, // 10 001 0111 1111 111
1296
1297 // GICv3 registers
1298 ICC_IAR1_EL1 = 0xc660, // 11 000 1100 1100 000
1299 ICC_IAR0_EL1 = 0xc640, // 11 000 1100 1000 000
1300 ICC_HPPIR1_EL1 = 0xc662, // 11 000 1100 1100 010
1301 ICC_HPPIR0_EL1 = 0xc642, // 11 000 1100 1000 010
1302 ICC_RPR_EL1 = 0xc65b, // 11 000 1100 1011 011
1303 ICH_VTR_EL2 = 0xe659, // 11 100 1100 1011 001
1304 ICH_EISR_EL2 = 0xe65b, // 11 100 1100 1011 011
1305 ICH_ELSR_EL2 = 0xe65d // 11 100 1100 1011 101
1306 };
1307
1308 enum SysRegWOValues {
1309 DBGDTRTX_EL0 = 0x9828, // 10 011 0000 0101 000
1310 OSLAR_EL1 = 0x8084, // 10 000 0001 0000 100
1311 PMSWINC_EL0 = 0xdce4, // 11 011 1001 1100 100
1312
1313 // Trace Registers
1314 TRCOSLAR = 0x8884, // 10 001 0001 0000 100
1315 TRCLAR = 0x8be6, // 10 001 0111 1100 110
1316
1317 // GICv3 registers
1318 ICC_EOIR1_EL1 = 0xc661, // 11 000 1100 1100 001
1319 ICC_EOIR0_EL1 = 0xc641, // 11 000 1100 1000 001
1320 ICC_DIR_EL1 = 0xc659, // 11 000 1100 1011 001
1321 ICC_SGI1R_EL1 = 0xc65d, // 11 000 1100 1011 101
1322 ICC_ASGI1R_EL1 = 0xc65e, // 11 000 1100 1011 110
1323 ICC_SGI0R_EL1 = 0xc65f // 11 000 1100 1011 111
1324 };
1325
1326 enum SysRegValues {
1327 Invalid = -1, // Op0 Op1 CRn CRm Op2
1328 OSDTRRX_EL1 = 0x8002, // 10 000 0000 0000 010
1329 OSDTRTX_EL1 = 0x801a, // 10 000 0000 0011 010
1330 TEECR32_EL1 = 0x9000, // 10 010 0000 0000 000
1331 MDCCINT_EL1 = 0x8010, // 10 000 0000 0010 000
1332 MDSCR_EL1 = 0x8012, // 10 000 0000 0010 010
1333 DBGDTR_EL0 = 0x9820, // 10 011 0000 0100 000
1334 OSECCR_EL1 = 0x8032, // 10 000 0000 0110 010
1335 DBGVCR32_EL2 = 0xa038, // 10 100 0000 0111 000
1336 DBGBVR0_EL1 = 0x8004, // 10 000 0000 0000 100
1337 DBGBVR1_EL1 = 0x800c, // 10 000 0000 0001 100
1338 DBGBVR2_EL1 = 0x8014, // 10 000 0000 0010 100
1339 DBGBVR3_EL1 = 0x801c, // 10 000 0000 0011 100
1340 DBGBVR4_EL1 = 0x8024, // 10 000 0000 0100 100
1341 DBGBVR5_EL1 = 0x802c, // 10 000 0000 0101 100
1342 DBGBVR6_EL1 = 0x8034, // 10 000 0000 0110 100
1343 DBGBVR7_EL1 = 0x803c, // 10 000 0000 0111 100
1344 DBGBVR8_EL1 = 0x8044, // 10 000 0000 1000 100
1345 DBGBVR9_EL1 = 0x804c, // 10 000 0000 1001 100
1346 DBGBVR10_EL1 = 0x8054, // 10 000 0000 1010 100
1347 DBGBVR11_EL1 = 0x805c, // 10 000 0000 1011 100
1348 DBGBVR12_EL1 = 0x8064, // 10 000 0000 1100 100
1349 DBGBVR13_EL1 = 0x806c, // 10 000 0000 1101 100
1350 DBGBVR14_EL1 = 0x8074, // 10 000 0000 1110 100
1351 DBGBVR15_EL1 = 0x807c, // 10 000 0000 1111 100
1352 DBGBCR0_EL1 = 0x8005, // 10 000 0000 0000 101
1353 DBGBCR1_EL1 = 0x800d, // 10 000 0000 0001 101
1354 DBGBCR2_EL1 = 0x8015, // 10 000 0000 0010 101
1355 DBGBCR3_EL1 = 0x801d, // 10 000 0000 0011 101
1356 DBGBCR4_EL1 = 0x8025, // 10 000 0000 0100 101
1357 DBGBCR5_EL1 = 0x802d, // 10 000 0000 0101 101
1358 DBGBCR6_EL1 = 0x8035, // 10 000 0000 0110 101
1359 DBGBCR7_EL1 = 0x803d, // 10 000 0000 0111 101
1360 DBGBCR8_EL1 = 0x8045, // 10 000 0000 1000 101
1361 DBGBCR9_EL1 = 0x804d, // 10 000 0000 1001 101
1362 DBGBCR10_EL1 = 0x8055, // 10 000 0000 1010 101
1363 DBGBCR11_EL1 = 0x805d, // 10 000 0000 1011 101
1364 DBGBCR12_EL1 = 0x8065, // 10 000 0000 1100 101
1365 DBGBCR13_EL1 = 0x806d, // 10 000 0000 1101 101
1366 DBGBCR14_EL1 = 0x8075, // 10 000 0000 1110 101
1367 DBGBCR15_EL1 = 0x807d, // 10 000 0000 1111 101
1368 DBGWVR0_EL1 = 0x8006, // 10 000 0000 0000 110
1369 DBGWVR1_EL1 = 0x800e, // 10 000 0000 0001 110
1370 DBGWVR2_EL1 = 0x8016, // 10 000 0000 0010 110
1371 DBGWVR3_EL1 = 0x801e, // 10 000 0000 0011 110
1372 DBGWVR4_EL1 = 0x8026, // 10 000 0000 0100 110
1373 DBGWVR5_EL1 = 0x802e, // 10 000 0000 0101 110
1374 DBGWVR6_EL1 = 0x8036, // 10 000 0000 0110 110
1375 DBGWVR7_EL1 = 0x803e, // 10 000 0000 0111 110
1376 DBGWVR8_EL1 = 0x8046, // 10 000 0000 1000 110
1377 DBGWVR9_EL1 = 0x804e, // 10 000 0000 1001 110
1378 DBGWVR10_EL1 = 0x8056, // 10 000 0000 1010 110
1379 DBGWVR11_EL1 = 0x805e, // 10 000 0000 1011 110
1380 DBGWVR12_EL1 = 0x8066, // 10 000 0000 1100 110
1381 DBGWVR13_EL1 = 0x806e, // 10 000 0000 1101 110
1382 DBGWVR14_EL1 = 0x8076, // 10 000 0000 1110 110
1383 DBGWVR15_EL1 = 0x807e, // 10 000 0000 1111 110
1384 DBGWCR0_EL1 = 0x8007, // 10 000 0000 0000 111
1385 DBGWCR1_EL1 = 0x800f, // 10 000 0000 0001 111
1386 DBGWCR2_EL1 = 0x8017, // 10 000 0000 0010 111
1387 DBGWCR3_EL1 = 0x801f, // 10 000 0000 0011 111
1388 DBGWCR4_EL1 = 0x8027, // 10 000 0000 0100 111
1389 DBGWCR5_EL1 = 0x802f, // 10 000 0000 0101 111
1390 DBGWCR6_EL1 = 0x8037, // 10 000 0000 0110 111
1391 DBGWCR7_EL1 = 0x803f, // 10 000 0000 0111 111
1392 DBGWCR8_EL1 = 0x8047, // 10 000 0000 1000 111
1393 DBGWCR9_EL1 = 0x804f, // 10 000 0000 1001 111
1394 DBGWCR10_EL1 = 0x8057, // 10 000 0000 1010 111
1395 DBGWCR11_EL1 = 0x805f, // 10 000 0000 1011 111
1396 DBGWCR12_EL1 = 0x8067, // 10 000 0000 1100 111
1397 DBGWCR13_EL1 = 0x806f, // 10 000 0000 1101 111
1398 DBGWCR14_EL1 = 0x8077, // 10 000 0000 1110 111
1399 DBGWCR15_EL1 = 0x807f, // 10 000 0000 1111 111
1400 TEEHBR32_EL1 = 0x9080, // 10 010 0001 0000 000
1401 OSDLR_EL1 = 0x809c, // 10 000 0001 0011 100
1402 DBGPRCR_EL1 = 0x80a4, // 10 000 0001 0100 100
1403 DBGCLAIMSET_EL1 = 0x83c6, // 10 000 0111 1000 110
1404 DBGCLAIMCLR_EL1 = 0x83ce, // 10 000 0111 1001 110
1405 CSSELR_EL1 = 0xd000, // 11 010 0000 0000 000
1406 VPIDR_EL2 = 0xe000, // 11 100 0000 0000 000
1407 VMPIDR_EL2 = 0xe005, // 11 100 0000 0000 101
1408 CPACR_EL1 = 0xc082, // 11 000 0001 0000 010
1409 SCTLR_EL1 = 0xc080, // 11 000 0001 0000 000
1410 SCTLR_EL2 = 0xe080, // 11 100 0001 0000 000
1411 SCTLR_EL3 = 0xf080, // 11 110 0001 0000 000
1412 ACTLR_EL1 = 0xc081, // 11 000 0001 0000 001
1413 ACTLR_EL2 = 0xe081, // 11 100 0001 0000 001
1414 ACTLR_EL3 = 0xf081, // 11 110 0001 0000 001
1415 HCR_EL2 = 0xe088, // 11 100 0001 0001 000
1416 SCR_EL3 = 0xf088, // 11 110 0001 0001 000
1417 MDCR_EL2 = 0xe089, // 11 100 0001 0001 001
1418 SDER32_EL3 = 0xf089, // 11 110 0001 0001 001
1419 CPTR_EL2 = 0xe08a, // 11 100 0001 0001 010
1420 CPTR_EL3 = 0xf08a, // 11 110 0001 0001 010
1421 HSTR_EL2 = 0xe08b, // 11 100 0001 0001 011
1422 HACR_EL2 = 0xe08f, // 11 100 0001 0001 111
1423 MDCR_EL3 = 0xf099, // 11 110 0001 0011 001
1424 TTBR0_EL1 = 0xc100, // 11 000 0010 0000 000
1425 TTBR0_EL2 = 0xe100, // 11 100 0010 0000 000
1426 TTBR0_EL3 = 0xf100, // 11 110 0010 0000 000
1427 TTBR1_EL1 = 0xc101, // 11 000 0010 0000 001
1428 TCR_EL1 = 0xc102, // 11 000 0010 0000 010
1429 TCR_EL2 = 0xe102, // 11 100 0010 0000 010
1430 TCR_EL3 = 0xf102, // 11 110 0010 0000 010
1431 VTTBR_EL2 = 0xe108, // 11 100 0010 0001 000
1432 VTCR_EL2 = 0xe10a, // 11 100 0010 0001 010
1433 DACR32_EL2 = 0xe180, // 11 100 0011 0000 000
1434 SPSR_EL1 = 0xc200, // 11 000 0100 0000 000
1435 SPSR_EL2 = 0xe200, // 11 100 0100 0000 000
1436 SPSR_EL3 = 0xf200, // 11 110 0100 0000 000
1437 ELR_EL1 = 0xc201, // 11 000 0100 0000 001
1438 ELR_EL2 = 0xe201, // 11 100 0100 0000 001
1439 ELR_EL3 = 0xf201, // 11 110 0100 0000 001
1440 SP_EL0 = 0xc208, // 11 000 0100 0001 000
1441 SP_EL1 = 0xe208, // 11 100 0100 0001 000
1442 SP_EL2 = 0xf208, // 11 110 0100 0001 000
1443 SPSel = 0xc210, // 11 000 0100 0010 000
1444 NZCV = 0xda10, // 11 011 0100 0010 000
1445 DAIF = 0xda11, // 11 011 0100 0010 001
1446 CurrentEL = 0xc212, // 11 000 0100 0010 010
1447 SPSR_irq = 0xe218, // 11 100 0100 0011 000
1448 SPSR_abt = 0xe219, // 11 100 0100 0011 001
1449 SPSR_und = 0xe21a, // 11 100 0100 0011 010
1450 SPSR_fiq = 0xe21b, // 11 100 0100 0011 011
1451 FPCR = 0xda20, // 11 011 0100 0100 000
1452 FPSR = 0xda21, // 11 011 0100 0100 001
1453 DSPSR_EL0 = 0xda28, // 11 011 0100 0101 000
1454 DLR_EL0 = 0xda29, // 11 011 0100 0101 001
1455 IFSR32_EL2 = 0xe281, // 11 100 0101 0000 001
1456 AFSR0_EL1 = 0xc288, // 11 000 0101 0001 000
1457 AFSR0_EL2 = 0xe288, // 11 100 0101 0001 000
1458 AFSR0_EL3 = 0xf288, // 11 110 0101 0001 000
1459 AFSR1_EL1 = 0xc289, // 11 000 0101 0001 001
1460 AFSR1_EL2 = 0xe289, // 11 100 0101 0001 001
1461 AFSR1_EL3 = 0xf289, // 11 110 0101 0001 001
1462 ESR_EL1 = 0xc290, // 11 000 0101 0010 000
1463 ESR_EL2 = 0xe290, // 11 100 0101 0010 000
1464 ESR_EL3 = 0xf290, // 11 110 0101 0010 000
1465 FPEXC32_EL2 = 0xe298, // 11 100 0101 0011 000
1466 FAR_EL1 = 0xc300, // 11 000 0110 0000 000
1467 FAR_EL2 = 0xe300, // 11 100 0110 0000 000
1468 FAR_EL3 = 0xf300, // 11 110 0110 0000 000
1469 HPFAR_EL2 = 0xe304, // 11 100 0110 0000 100
1470 PAR_EL1 = 0xc3a0, // 11 000 0111 0100 000
1471 PMCR_EL0 = 0xdce0, // 11 011 1001 1100 000
1472 PMCNTENSET_EL0 = 0xdce1, // 11 011 1001 1100 001
1473 PMCNTENCLR_EL0 = 0xdce2, // 11 011 1001 1100 010
1474 PMOVSCLR_EL0 = 0xdce3, // 11 011 1001 1100 011
1475 PMSELR_EL0 = 0xdce5, // 11 011 1001 1100 101
1476 PMCCNTR_EL0 = 0xdce8, // 11 011 1001 1101 000
1477 PMXEVTYPER_EL0 = 0xdce9, // 11 011 1001 1101 001
1478 PMXEVCNTR_EL0 = 0xdcea, // 11 011 1001 1101 010
1479 PMUSERENR_EL0 = 0xdcf0, // 11 011 1001 1110 000
1480 PMINTENSET_EL1 = 0xc4f1, // 11 000 1001 1110 001
1481 PMINTENCLR_EL1 = 0xc4f2, // 11 000 1001 1110 010
1482 PMOVSSET_EL0 = 0xdcf3, // 11 011 1001 1110 011
1483 MAIR_EL1 = 0xc510, // 11 000 1010 0010 000
1484 MAIR_EL2 = 0xe510, // 11 100 1010 0010 000
1485 MAIR_EL3 = 0xf510, // 11 110 1010 0010 000
1486 AMAIR_EL1 = 0xc518, // 11 000 1010 0011 000
1487 AMAIR_EL2 = 0xe518, // 11 100 1010 0011 000
1488 AMAIR_EL3 = 0xf518, // 11 110 1010 0011 000
1489 VBAR_EL1 = 0xc600, // 11 000 1100 0000 000
1490 VBAR_EL2 = 0xe600, // 11 100 1100 0000 000
1491 VBAR_EL3 = 0xf600, // 11 110 1100 0000 000
1492 RMR_EL1 = 0xc602, // 11 000 1100 0000 010
1493 RMR_EL2 = 0xe602, // 11 100 1100 0000 010
1494 RMR_EL3 = 0xf602, // 11 110 1100 0000 010
1495 CONTEXTIDR_EL1 = 0xc681, // 11 000 1101 0000 001
1496 TPIDR_EL0 = 0xde82, // 11 011 1101 0000 010
1497 TPIDR_EL2 = 0xe682, // 11 100 1101 0000 010
1498 TPIDR_EL3 = 0xf682, // 11 110 1101 0000 010
1499 TPIDRRO_EL0 = 0xde83, // 11 011 1101 0000 011
1500 TPIDR_EL1 = 0xc684, // 11 000 1101 0000 100
1501 CNTFRQ_EL0 = 0xdf00, // 11 011 1110 0000 000
1502 CNTVOFF_EL2 = 0xe703, // 11 100 1110 0000 011
1503 CNTKCTL_EL1 = 0xc708, // 11 000 1110 0001 000
1504 CNTHCTL_EL2 = 0xe708, // 11 100 1110 0001 000
1505 CNTP_TVAL_EL0 = 0xdf10, // 11 011 1110 0010 000
1506 CNTHP_TVAL_EL2 = 0xe710, // 11 100 1110 0010 000
1507 CNTPS_TVAL_EL1 = 0xff10, // 11 111 1110 0010 000
1508 CNTP_CTL_EL0 = 0xdf11, // 11 011 1110 0010 001
1509 CNTHP_CTL_EL2 = 0xe711, // 11 100 1110 0010 001
1510 CNTPS_CTL_EL1 = 0xff11, // 11 111 1110 0010 001
1511 CNTP_CVAL_EL0 = 0xdf12, // 11 011 1110 0010 010
1512 CNTHP_CVAL_EL2 = 0xe712, // 11 100 1110 0010 010
1513 CNTPS_CVAL_EL1 = 0xff12, // 11 111 1110 0010 010
1514 CNTV_TVAL_EL0 = 0xdf18, // 11 011 1110 0011 000
1515 CNTV_CTL_EL0 = 0xdf19, // 11 011 1110 0011 001
1516 CNTV_CVAL_EL0 = 0xdf1a, // 11 011 1110 0011 010
1517 PMEVCNTR0_EL0 = 0xdf40, // 11 011 1110 1000 000
1518 PMEVCNTR1_EL0 = 0xdf41, // 11 011 1110 1000 001
1519 PMEVCNTR2_EL0 = 0xdf42, // 11 011 1110 1000 010
1520 PMEVCNTR3_EL0 = 0xdf43, // 11 011 1110 1000 011
1521 PMEVCNTR4_EL0 = 0xdf44, // 11 011 1110 1000 100
1522 PMEVCNTR5_EL0 = 0xdf45, // 11 011 1110 1000 101
1523 PMEVCNTR6_EL0 = 0xdf46, // 11 011 1110 1000 110
1524 PMEVCNTR7_EL0 = 0xdf47, // 11 011 1110 1000 111
1525 PMEVCNTR8_EL0 = 0xdf48, // 11 011 1110 1001 000
1526 PMEVCNTR9_EL0 = 0xdf49, // 11 011 1110 1001 001
1527 PMEVCNTR10_EL0 = 0xdf4a, // 11 011 1110 1001 010
1528 PMEVCNTR11_EL0 = 0xdf4b, // 11 011 1110 1001 011
1529 PMEVCNTR12_EL0 = 0xdf4c, // 11 011 1110 1001 100
1530 PMEVCNTR13_EL0 = 0xdf4d, // 11 011 1110 1001 101
1531 PMEVCNTR14_EL0 = 0xdf4e, // 11 011 1110 1001 110
1532 PMEVCNTR15_EL0 = 0xdf4f, // 11 011 1110 1001 111
1533 PMEVCNTR16_EL0 = 0xdf50, // 11 011 1110 1010 000
1534 PMEVCNTR17_EL0 = 0xdf51, // 11 011 1110 1010 001
1535 PMEVCNTR18_EL0 = 0xdf52, // 11 011 1110 1010 010
1536 PMEVCNTR19_EL0 = 0xdf53, // 11 011 1110 1010 011
1537 PMEVCNTR20_EL0 = 0xdf54, // 11 011 1110 1010 100
1538 PMEVCNTR21_EL0 = 0xdf55, // 11 011 1110 1010 101
1539 PMEVCNTR22_EL0 = 0xdf56, // 11 011 1110 1010 110
1540 PMEVCNTR23_EL0 = 0xdf57, // 11 011 1110 1010 111
1541 PMEVCNTR24_EL0 = 0xdf58, // 11 011 1110 1011 000
1542 PMEVCNTR25_EL0 = 0xdf59, // 11 011 1110 1011 001
1543 PMEVCNTR26_EL0 = 0xdf5a, // 11 011 1110 1011 010
1544 PMEVCNTR27_EL0 = 0xdf5b, // 11 011 1110 1011 011
1545 PMEVCNTR28_EL0 = 0xdf5c, // 11 011 1110 1011 100
1546 PMEVCNTR29_EL0 = 0xdf5d, // 11 011 1110 1011 101
1547 PMEVCNTR30_EL0 = 0xdf5e, // 11 011 1110 1011 110
1548 PMCCFILTR_EL0 = 0xdf7f, // 11 011 1110 1111 111
1549 PMEVTYPER0_EL0 = 0xdf60, // 11 011 1110 1100 000
1550 PMEVTYPER1_EL0 = 0xdf61, // 11 011 1110 1100 001
1551 PMEVTYPER2_EL0 = 0xdf62, // 11 011 1110 1100 010
1552 PMEVTYPER3_EL0 = 0xdf63, // 11 011 1110 1100 011
1553 PMEVTYPER4_EL0 = 0xdf64, // 11 011 1110 1100 100
1554 PMEVTYPER5_EL0 = 0xdf65, // 11 011 1110 1100 101
1555 PMEVTYPER6_EL0 = 0xdf66, // 11 011 1110 1100 110
1556 PMEVTYPER7_EL0 = 0xdf67, // 11 011 1110 1100 111
1557 PMEVTYPER8_EL0 = 0xdf68, // 11 011 1110 1101 000
1558 PMEVTYPER9_EL0 = 0xdf69, // 11 011 1110 1101 001
1559 PMEVTYPER10_EL0 = 0xdf6a, // 11 011 1110 1101 010
1560 PMEVTYPER11_EL0 = 0xdf6b, // 11 011 1110 1101 011
1561 PMEVTYPER12_EL0 = 0xdf6c, // 11 011 1110 1101 100
1562 PMEVTYPER13_EL0 = 0xdf6d, // 11 011 1110 1101 101
1563 PMEVTYPER14_EL0 = 0xdf6e, // 11 011 1110 1101 110
1564 PMEVTYPER15_EL0 = 0xdf6f, // 11 011 1110 1101 111
1565 PMEVTYPER16_EL0 = 0xdf70, // 11 011 1110 1110 000
1566 PMEVTYPER17_EL0 = 0xdf71, // 11 011 1110 1110 001
1567 PMEVTYPER18_EL0 = 0xdf72, // 11 011 1110 1110 010
1568 PMEVTYPER19_EL0 = 0xdf73, // 11 011 1110 1110 011
1569 PMEVTYPER20_EL0 = 0xdf74, // 11 011 1110 1110 100
1570 PMEVTYPER21_EL0 = 0xdf75, // 11 011 1110 1110 101
1571 PMEVTYPER22_EL0 = 0xdf76, // 11 011 1110 1110 110
1572 PMEVTYPER23_EL0 = 0xdf77, // 11 011 1110 1110 111
1573 PMEVTYPER24_EL0 = 0xdf78, // 11 011 1110 1111 000
1574 PMEVTYPER25_EL0 = 0xdf79, // 11 011 1110 1111 001
1575 PMEVTYPER26_EL0 = 0xdf7a, // 11 011 1110 1111 010
1576 PMEVTYPER27_EL0 = 0xdf7b, // 11 011 1110 1111 011
1577 PMEVTYPER28_EL0 = 0xdf7c, // 11 011 1110 1111 100
1578 PMEVTYPER29_EL0 = 0xdf7d, // 11 011 1110 1111 101
1579 PMEVTYPER30_EL0 = 0xdf7e, // 11 011 1110 1111 110
1580
1581 // Trace registers
1582 TRCPRGCTLR = 0x8808, // 10 001 0000 0001 000
1583 TRCPROCSELR = 0x8810, // 10 001 0000 0010 000
1584 TRCCONFIGR = 0x8820, // 10 001 0000 0100 000
1585 TRCAUXCTLR = 0x8830, // 10 001 0000 0110 000
1586 TRCEVENTCTL0R = 0x8840, // 10 001 0000 1000 000
1587 TRCEVENTCTL1R = 0x8848, // 10 001 0000 1001 000
1588 TRCSTALLCTLR = 0x8858, // 10 001 0000 1011 000
1589 TRCTSCTLR = 0x8860, // 10 001 0000 1100 000
1590 TRCSYNCPR = 0x8868, // 10 001 0000 1101 000
1591 TRCCCCTLR = 0x8870, // 10 001 0000 1110 000
1592 TRCBBCTLR = 0x8878, // 10 001 0000 1111 000
1593 TRCTRACEIDR = 0x8801, // 10 001 0000 0000 001
1594 TRCQCTLR = 0x8809, // 10 001 0000 0001 001
1595 TRCVICTLR = 0x8802, // 10 001 0000 0000 010
1596 TRCVIIECTLR = 0x880a, // 10 001 0000 0001 010
1597 TRCVISSCTLR = 0x8812, // 10 001 0000 0010 010
1598 TRCVIPCSSCTLR = 0x881a, // 10 001 0000 0011 010
1599 TRCVDCTLR = 0x8842, // 10 001 0000 1000 010
1600 TRCVDSACCTLR = 0x884a, // 10 001 0000 1001 010
1601 TRCVDARCCTLR = 0x8852, // 10 001 0000 1010 010
1602 TRCSEQEVR0 = 0x8804, // 10 001 0000 0000 100
1603 TRCSEQEVR1 = 0x880c, // 10 001 0000 0001 100
1604 TRCSEQEVR2 = 0x8814, // 10 001 0000 0010 100
1605 TRCSEQRSTEVR = 0x8834, // 10 001 0000 0110 100
1606 TRCSEQSTR = 0x883c, // 10 001 0000 0111 100
1607 TRCEXTINSELR = 0x8844, // 10 001 0000 1000 100
1608 TRCCNTRLDVR0 = 0x8805, // 10 001 0000 0000 101
1609 TRCCNTRLDVR1 = 0x880d, // 10 001 0000 0001 101
1610 TRCCNTRLDVR2 = 0x8815, // 10 001 0000 0010 101
1611 TRCCNTRLDVR3 = 0x881d, // 10 001 0000 0011 101
1612 TRCCNTCTLR0 = 0x8825, // 10 001 0000 0100 101
1613 TRCCNTCTLR1 = 0x882d, // 10 001 0000 0101 101
1614 TRCCNTCTLR2 = 0x8835, // 10 001 0000 0110 101
1615 TRCCNTCTLR3 = 0x883d, // 10 001 0000 0111 101
1616 TRCCNTVR0 = 0x8845, // 10 001 0000 1000 101
1617 TRCCNTVR1 = 0x884d, // 10 001 0000 1001 101
1618 TRCCNTVR2 = 0x8855, // 10 001 0000 1010 101
1619 TRCCNTVR3 = 0x885d, // 10 001 0000 1011 101
1620 TRCIMSPEC0 = 0x8807, // 10 001 0000 0000 111
1621 TRCIMSPEC1 = 0x880f, // 10 001 0000 0001 111
1622 TRCIMSPEC2 = 0x8817, // 10 001 0000 0010 111
1623 TRCIMSPEC3 = 0x881f, // 10 001 0000 0011 111
1624 TRCIMSPEC4 = 0x8827, // 10 001 0000 0100 111
1625 TRCIMSPEC5 = 0x882f, // 10 001 0000 0101 111
1626 TRCIMSPEC6 = 0x8837, // 10 001 0000 0110 111
1627 TRCIMSPEC7 = 0x883f, // 10 001 0000 0111 111
1628 TRCRSCTLR2 = 0x8890, // 10 001 0001 0010 000
1629 TRCRSCTLR3 = 0x8898, // 10 001 0001 0011 000
1630 TRCRSCTLR4 = 0x88a0, // 10 001 0001 0100 000
1631 TRCRSCTLR5 = 0x88a8, // 10 001 0001 0101 000
1632 TRCRSCTLR6 = 0x88b0, // 10 001 0001 0110 000
1633 TRCRSCTLR7 = 0x88b8, // 10 001 0001 0111 000
1634 TRCRSCTLR8 = 0x88c0, // 10 001 0001 1000 000
1635 TRCRSCTLR9 = 0x88c8, // 10 001 0001 1001 000
1636 TRCRSCTLR10 = 0x88d0, // 10 001 0001 1010 000
1637 TRCRSCTLR11 = 0x88d8, // 10 001 0001 1011 000
1638 TRCRSCTLR12 = 0x88e0, // 10 001 0001 1100 000
1639 TRCRSCTLR13 = 0x88e8, // 10 001 0001 1101 000
1640 TRCRSCTLR14 = 0x88f0, // 10 001 0001 1110 000
1641 TRCRSCTLR15 = 0x88f8, // 10 001 0001 1111 000
1642 TRCRSCTLR16 = 0x8881, // 10 001 0001 0000 001
1643 TRCRSCTLR17 = 0x8889, // 10 001 0001 0001 001
1644 TRCRSCTLR18 = 0x8891, // 10 001 0001 0010 001
1645 TRCRSCTLR19 = 0x8899, // 10 001 0001 0011 001
1646 TRCRSCTLR20 = 0x88a1, // 10 001 0001 0100 001
1647 TRCRSCTLR21 = 0x88a9, // 10 001 0001 0101 001
1648 TRCRSCTLR22 = 0x88b1, // 10 001 0001 0110 001
1649 TRCRSCTLR23 = 0x88b9, // 10 001 0001 0111 001
1650 TRCRSCTLR24 = 0x88c1, // 10 001 0001 1000 001
1651 TRCRSCTLR25 = 0x88c9, // 10 001 0001 1001 001
1652 TRCRSCTLR26 = 0x88d1, // 10 001 0001 1010 001
1653 TRCRSCTLR27 = 0x88d9, // 10 001 0001 1011 001
1654 TRCRSCTLR28 = 0x88e1, // 10 001 0001 1100 001
1655 TRCRSCTLR29 = 0x88e9, // 10 001 0001 1101 001
1656 TRCRSCTLR30 = 0x88f1, // 10 001 0001 1110 001
1657 TRCRSCTLR31 = 0x88f9, // 10 001 0001 1111 001
1658 TRCSSCCR0 = 0x8882, // 10 001 0001 0000 010
1659 TRCSSCCR1 = 0x888a, // 10 001 0001 0001 010
1660 TRCSSCCR2 = 0x8892, // 10 001 0001 0010 010
1661 TRCSSCCR3 = 0x889a, // 10 001 0001 0011 010
1662 TRCSSCCR4 = 0x88a2, // 10 001 0001 0100 010
1663 TRCSSCCR5 = 0x88aa, // 10 001 0001 0101 010
1664 TRCSSCCR6 = 0x88b2, // 10 001 0001 0110 010
1665 TRCSSCCR7 = 0x88ba, // 10 001 0001 0111 010
1666 TRCSSCSR0 = 0x88c2, // 10 001 0001 1000 010
1667 TRCSSCSR1 = 0x88ca, // 10 001 0001 1001 010
1668 TRCSSCSR2 = 0x88d2, // 10 001 0001 1010 010
1669 TRCSSCSR3 = 0x88da, // 10 001 0001 1011 010
1670 TRCSSCSR4 = 0x88e2, // 10 001 0001 1100 010
1671 TRCSSCSR5 = 0x88ea, // 10 001 0001 1101 010
1672 TRCSSCSR6 = 0x88f2, // 10 001 0001 1110 010
1673 TRCSSCSR7 = 0x88fa, // 10 001 0001 1111 010
1674 TRCSSPCICR0 = 0x8883, // 10 001 0001 0000 011
1675 TRCSSPCICR1 = 0x888b, // 10 001 0001 0001 011
1676 TRCSSPCICR2 = 0x8893, // 10 001 0001 0010 011
1677 TRCSSPCICR3 = 0x889b, // 10 001 0001 0011 011
1678 TRCSSPCICR4 = 0x88a3, // 10 001 0001 0100 011
1679 TRCSSPCICR5 = 0x88ab, // 10 001 0001 0101 011
1680 TRCSSPCICR6 = 0x88b3, // 10 001 0001 0110 011
1681 TRCSSPCICR7 = 0x88bb, // 10 001 0001 0111 011
1682 TRCPDCR = 0x88a4, // 10 001 0001 0100 100
1683 TRCACVR0 = 0x8900, // 10 001 0010 0000 000
1684 TRCACVR1 = 0x8910, // 10 001 0010 0010 000
1685 TRCACVR2 = 0x8920, // 10 001 0010 0100 000
1686 TRCACVR3 = 0x8930, // 10 001 0010 0110 000
1687 TRCACVR4 = 0x8940, // 10 001 0010 1000 000
1688 TRCACVR5 = 0x8950, // 10 001 0010 1010 000
1689 TRCACVR6 = 0x8960, // 10 001 0010 1100 000
1690 TRCACVR7 = 0x8970, // 10 001 0010 1110 000
1691 TRCACVR8 = 0x8901, // 10 001 0010 0000 001
1692 TRCACVR9 = 0x8911, // 10 001 0010 0010 001
1693 TRCACVR10 = 0x8921, // 10 001 0010 0100 001
1694 TRCACVR11 = 0x8931, // 10 001 0010 0110 001
1695 TRCACVR12 = 0x8941, // 10 001 0010 1000 001
1696 TRCACVR13 = 0x8951, // 10 001 0010 1010 001
1697 TRCACVR14 = 0x8961, // 10 001 0010 1100 001
1698 TRCACVR15 = 0x8971, // 10 001 0010 1110 001
1699 TRCACATR0 = 0x8902, // 10 001 0010 0000 010
1700 TRCACATR1 = 0x8912, // 10 001 0010 0010 010
1701 TRCACATR2 = 0x8922, // 10 001 0010 0100 010
1702 TRCACATR3 = 0x8932, // 10 001 0010 0110 010
1703 TRCACATR4 = 0x8942, // 10 001 0010 1000 010
1704 TRCACATR5 = 0x8952, // 10 001 0010 1010 010
1705 TRCACATR6 = 0x8962, // 10 001 0010 1100 010
1706 TRCACATR7 = 0x8972, // 10 001 0010 1110 010
1707 TRCACATR8 = 0x8903, // 10 001 0010 0000 011
1708 TRCACATR9 = 0x8913, // 10 001 0010 0010 011
1709 TRCACATR10 = 0x8923, // 10 001 0010 0100 011
1710 TRCACATR11 = 0x8933, // 10 001 0010 0110 011
1711 TRCACATR12 = 0x8943, // 10 001 0010 1000 011
1712 TRCACATR13 = 0x8953, // 10 001 0010 1010 011
1713 TRCACATR14 = 0x8963, // 10 001 0010 1100 011
1714 TRCACATR15 = 0x8973, // 10 001 0010 1110 011
1715 TRCDVCVR0 = 0x8904, // 10 001 0010 0000 100
1716 TRCDVCVR1 = 0x8924, // 10 001 0010 0100 100
1717 TRCDVCVR2 = 0x8944, // 10 001 0010 1000 100
1718 TRCDVCVR3 = 0x8964, // 10 001 0010 1100 100
1719 TRCDVCVR4 = 0x8905, // 10 001 0010 0000 101
1720 TRCDVCVR5 = 0x8925, // 10 001 0010 0100 101
1721 TRCDVCVR6 = 0x8945, // 10 001 0010 1000 101
1722 TRCDVCVR7 = 0x8965, // 10 001 0010 1100 101
1723 TRCDVCMR0 = 0x8906, // 10 001 0010 0000 110
1724 TRCDVCMR1 = 0x8926, // 10 001 0010 0100 110
1725 TRCDVCMR2 = 0x8946, // 10 001 0010 1000 110
1726 TRCDVCMR3 = 0x8966, // 10 001 0010 1100 110
1727 TRCDVCMR4 = 0x8907, // 10 001 0010 0000 111
1728 TRCDVCMR5 = 0x8927, // 10 001 0010 0100 111
1729 TRCDVCMR6 = 0x8947, // 10 001 0010 1000 111
1730 TRCDVCMR7 = 0x8967, // 10 001 0010 1100 111
1731 TRCCIDCVR0 = 0x8980, // 10 001 0011 0000 000
1732 TRCCIDCVR1 = 0x8990, // 10 001 0011 0010 000
1733 TRCCIDCVR2 = 0x89a0, // 10 001 0011 0100 000
1734 TRCCIDCVR3 = 0x89b0, // 10 001 0011 0110 000
1735 TRCCIDCVR4 = 0x89c0, // 10 001 0011 1000 000
1736 TRCCIDCVR5 = 0x89d0, // 10 001 0011 1010 000
1737 TRCCIDCVR6 = 0x89e0, // 10 001 0011 1100 000
1738 TRCCIDCVR7 = 0x89f0, // 10 001 0011 1110 000
1739 TRCVMIDCVR0 = 0x8981, // 10 001 0011 0000 001
1740 TRCVMIDCVR1 = 0x8991, // 10 001 0011 0010 001
1741 TRCVMIDCVR2 = 0x89a1, // 10 001 0011 0100 001
1742 TRCVMIDCVR3 = 0x89b1, // 10 001 0011 0110 001
1743 TRCVMIDCVR4 = 0x89c1, // 10 001 0011 1000 001
1744 TRCVMIDCVR5 = 0x89d1, // 10 001 0011 1010 001
1745 TRCVMIDCVR6 = 0x89e1, // 10 001 0011 1100 001
1746 TRCVMIDCVR7 = 0x89f1, // 10 001 0011 1110 001
1747 TRCCIDCCTLR0 = 0x8982, // 10 001 0011 0000 010
1748 TRCCIDCCTLR1 = 0x898a, // 10 001 0011 0001 010
1749 TRCVMIDCCTLR0 = 0x8992, // 10 001 0011 0010 010
1750 TRCVMIDCCTLR1 = 0x899a, // 10 001 0011 0011 010
1751 TRCITCTRL = 0x8b84, // 10 001 0111 0000 100
1752 TRCCLAIMSET = 0x8bc6, // 10 001 0111 1000 110
1753 TRCCLAIMCLR = 0x8bce, // 10 001 0111 1001 110
1754
1755 // GICv3 registers
1756 ICC_BPR1_EL1 = 0xc663, // 11 000 1100 1100 011
1757 ICC_BPR0_EL1 = 0xc643, // 11 000 1100 1000 011
1758 ICC_PMR_EL1 = 0xc230, // 11 000 0100 0110 000
1759 ICC_CTLR_EL1 = 0xc664, // 11 000 1100 1100 100
1760 ICC_CTLR_EL3 = 0xf664, // 11 110 1100 1100 100
1761 ICC_SRE_EL1 = 0xc665, // 11 000 1100 1100 101
1762 ICC_SRE_EL2 = 0xe64d, // 11 100 1100 1001 101
1763 ICC_SRE_EL3 = 0xf665, // 11 110 1100 1100 101
1764 ICC_IGRPEN0_EL1 = 0xc666, // 11 000 1100 1100 110
1765 ICC_IGRPEN1_EL1 = 0xc667, // 11 000 1100 1100 111
1766 ICC_IGRPEN1_EL3 = 0xf667, // 11 110 1100 1100 111
1767 ICC_SEIEN_EL1 = 0xc668, // 11 000 1100 1101 000
1768 ICC_AP0R0_EL1 = 0xc644, // 11 000 1100 1000 100
1769 ICC_AP0R1_EL1 = 0xc645, // 11 000 1100 1000 101
1770 ICC_AP0R2_EL1 = 0xc646, // 11 000 1100 1000 110
1771 ICC_AP0R3_EL1 = 0xc647, // 11 000 1100 1000 111
1772 ICC_AP1R0_EL1 = 0xc648, // 11 000 1100 1001 000
1773 ICC_AP1R1_EL1 = 0xc649, // 11 000 1100 1001 001
1774 ICC_AP1R2_EL1 = 0xc64a, // 11 000 1100 1001 010
1775 ICC_AP1R3_EL1 = 0xc64b, // 11 000 1100 1001 011
1776 ICH_AP0R0_EL2 = 0xe640, // 11 100 1100 1000 000
1777 ICH_AP0R1_EL2 = 0xe641, // 11 100 1100 1000 001
1778 ICH_AP0R2_EL2 = 0xe642, // 11 100 1100 1000 010
1779 ICH_AP0R3_EL2 = 0xe643, // 11 100 1100 1000 011
1780 ICH_AP1R0_EL2 = 0xe648, // 11 100 1100 1001 000
1781 ICH_AP1R1_EL2 = 0xe649, // 11 100 1100 1001 001
1782 ICH_AP1R2_EL2 = 0xe64a, // 11 100 1100 1001 010
1783 ICH_AP1R3_EL2 = 0xe64b, // 11 100 1100 1001 011
1784 ICH_HCR_EL2 = 0xe658, // 11 100 1100 1011 000
1785 ICH_MISR_EL2 = 0xe65a, // 11 100 1100 1011 010
1786 ICH_VMCR_EL2 = 0xe65f, // 11 100 1100 1011 111
1787 ICH_VSEIR_EL2 = 0xe64c, // 11 100 1100 1001 100
1788 ICH_LR0_EL2 = 0xe660, // 11 100 1100 1100 000
1789 ICH_LR1_EL2 = 0xe661, // 11 100 1100 1100 001
1790 ICH_LR2_EL2 = 0xe662, // 11 100 1100 1100 010
1791 ICH_LR3_EL2 = 0xe663, // 11 100 1100 1100 011
1792 ICH_LR4_EL2 = 0xe664, // 11 100 1100 1100 100
1793 ICH_LR5_EL2 = 0xe665, // 11 100 1100 1100 101
1794 ICH_LR6_EL2 = 0xe666, // 11 100 1100 1100 110
1795 ICH_LR7_EL2 = 0xe667, // 11 100 1100 1100 111
1796 ICH_LR8_EL2 = 0xe668, // 11 100 1100 1101 000
1797 ICH_LR9_EL2 = 0xe669, // 11 100 1100 1101 001
1798 ICH_LR10_EL2 = 0xe66a, // 11 100 1100 1101 010
1799 ICH_LR11_EL2 = 0xe66b, // 11 100 1100 1101 011
1800 ICH_LR12_EL2 = 0xe66c, // 11 100 1100 1101 100
1801 ICH_LR13_EL2 = 0xe66d, // 11 100 1100 1101 101
1802 ICH_LR14_EL2 = 0xe66e, // 11 100 1100 1101 110
Bradley Smith08c391c2014-04-09 14:42:36 +0000[diff] [blame^]1803 ICH_LR15_EL2 = 0xe66f, // 11 100 1100 1101 111
1804
1805 // Cyclone specific system registers
1806 CPM_IOACC_CTL_EL3 = 0xff90
Bradley Smithceeb04d2014-04-09 14:42:16 +0000[diff] [blame]1807 };
1808
1809 // Note that these do not inherit from ARM64NamedImmMapper. This class is
1810 // sufficiently different in its behaviour that I don't believe it's worth
1811 // burdening the common ARM64NamedImmMapper with abstractions only needed in
1812 // this one case.
1813 struct SysRegMapper {
1814 static const ARM64NamedImmMapper::Mapping SysRegPairs[];
1815
1816 const ARM64NamedImmMapper::Mapping *InstPairs;
1817 size_t NumInstPairs;
1818
1819 SysRegMapper() {}
1820 uint32_t fromString(StringRef Name, bool &Valid) const;
1821 std::string toString(uint32_t Bits, bool &Valid) const;
1822 };
1823
1824 struct MSRMapper : SysRegMapper {
1825 static const ARM64NamedImmMapper::Mapping MSRPairs[];
1826 MSRMapper();
1827 };
1828
1829 struct MRSMapper : SysRegMapper {
1830 static const ARM64NamedImmMapper::Mapping MRSPairs[];
1831 MRSMapper();
1832 };
1833
1834 uint32_t ParseGenericRegister(StringRef Name, bool &Valid);
1835}
1836
1837namespace ARM64TLBI {
1838 enum TLBIValues {
1839 Invalid = -1, // Op0 Op1 CRn CRm Op2
1840 IPAS2E1IS = 0x6401, // 01 100 1000 0000 001
1841 IPAS2LE1IS = 0x6405, // 01 100 1000 0000 101
1842 VMALLE1IS = 0x4418, // 01 000 1000 0011 000
1843 ALLE2IS = 0x6418, // 01 100 1000 0011 000
1844 ALLE3IS = 0x7418, // 01 110 1000 0011 000
1845 VAE1IS = 0x4419, // 01 000 1000 0011 001
1846 VAE2IS = 0x6419, // 01 100 1000 0011 001
1847 VAE3IS = 0x7419, // 01 110 1000 0011 001
1848 ASIDE1IS = 0x441a, // 01 000 1000 0011 010
1849 VAAE1IS = 0x441b, // 01 000 1000 0011 011
1850 ALLE1IS = 0x641c, // 01 100 1000 0011 100
1851 VALE1IS = 0x441d, // 01 000 1000 0011 101
1852 VALE2IS = 0x641d, // 01 100 1000 0011 101
1853 VALE3IS = 0x741d, // 01 110 1000 0011 101
1854 VMALLS12E1IS = 0x641e, // 01 100 1000 0011 110
1855 VAALE1IS = 0x441f, // 01 000 1000 0011 111
1856 IPAS2E1 = 0x6421, // 01 100 1000 0100 001
1857 IPAS2LE1 = 0x6425, // 01 100 1000 0100 101
1858 VMALLE1 = 0x4438, // 01 000 1000 0111 000
1859 ALLE2 = 0x6438, // 01 100 1000 0111 000
1860 ALLE3 = 0x7438, // 01 110 1000 0111 000
1861 VAE1 = 0x4439, // 01 000 1000 0111 001
1862 VAE2 = 0x6439, // 01 100 1000 0111 001
1863 VAE3 = 0x7439, // 01 110 1000 0111 001
1864 ASIDE1 = 0x443a, // 01 000 1000 0111 010
1865 VAAE1 = 0x443b, // 01 000 1000 0111 011
1866 ALLE1 = 0x643c, // 01 100 1000 0111 100
1867 VALE1 = 0x443d, // 01 000 1000 0111 101
1868 VALE2 = 0x643d, // 01 100 1000 0111 101
1869 VALE3 = 0x743d, // 01 110 1000 0111 101
1870 VMALLS12E1 = 0x643e, // 01 100 1000 0111 110
1871 VAALE1 = 0x443f // 01 000 1000 0111 111
1872 };
1873
1874 struct TLBIMapper : ARM64NamedImmMapper {
1875 const static Mapping TLBIPairs[];
1876
1877 TLBIMapper();
1878 };
1879
1880 static inline bool NeedsRegister(TLBIValues Val) {
1881 switch (Val) {
1882 case VMALLE1IS:
1883 case ALLE2IS:
1884 case ALLE3IS:
1885 case ALLE1IS:
1886 case VMALLS12E1IS:
1887 case VMALLE1:
1888 case ALLE2:
1889 case ALLE3:
1890 case ALLE1:
1891 case VMALLS12E1:
1892 return false;
1893 default:
1894 return true;
1895 }
1896 }
1897}
1898
Tim Northover00ed9962014-03-29 10:18:08 +0000[diff] [blame]1899namespace ARM64II {
1900 /// Target Operand Flag enum.
1901 enum TOF {
1902 //===------------------------------------------------------------------===//
1903 // ARM64 Specific MachineOperand flags.
1904
1905 MO_NO_FLAG,
1906
1907 MO_FRAGMENT = 0x7,
1908
1909 /// MO_PAGE - A symbol operand with this flag represents the pc-relative
1910 /// offset of the 4K page containing the symbol. This is used with the
1911 /// ADRP instruction.
1912 MO_PAGE = 1,
1913
1914 /// MO_PAGEOFF - A symbol operand with this flag represents the offset of
1915 /// that symbol within a 4K page. This offset is added to the page address
1916 /// to produce the complete address.
1917 MO_PAGEOFF = 2,
1918
1919 /// MO_G3 - A symbol operand with this flag (granule 3) represents the high
1920 /// 16-bits of a 64-bit address, used in a MOVZ or MOVK instruction
1921 MO_G3 = 3,
1922
1923 /// MO_G2 - A symbol operand with this flag (granule 2) represents the bits
1924 /// 32-47 of a 64-bit address, used in a MOVZ or MOVK instruction
1925 MO_G2 = 4,
1926
1927 /// MO_G1 - A symbol operand with this flag (granule 1) represents the bits
1928 /// 16-31 of a 64-bit address, used in a MOVZ or MOVK instruction
1929 MO_G1 = 5,
1930
1931 /// MO_G0 - A symbol operand with this flag (granule 0) represents the bits
1932 /// 0-15 of a 64-bit address, used in a MOVZ or MOVK instruction
1933 MO_G0 = 6,
1934
1935 /// MO_GOT - This flag indicates that a symbol operand represents the
1936 /// address of the GOT entry for the symbol, rather than the address of
1937 /// the symbol itself.
1938 MO_GOT = 8,
1939
1940 /// MO_NC - Indicates whether the linker is expected to check the symbol
1941 /// reference for overflow. For example in an ADRP/ADD pair of relocations
1942 /// the ADRP usually does check, but not the ADD.
1943 MO_NC = 0x10,
1944
1945 /// MO_TLS - Indicates that the operand being accessed is some kind of
1946 /// thread-local symbol. On Darwin, only one type of thread-local access
1947 /// exists (pre linker-relaxation), but on ELF the TLSModel used for the
1948 /// referee will affect interpretation.
1949 MO_TLS = 0x20
1950 };
1951} // end namespace ARM64II
1952
1953} // end namespace llvm
1954
1955#endif