Blame - llvm/lib/Target/AMDGPU/Processors.td - toolchain/llvm-project

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Tom Stellard	c2516c6	2013-05-03 17:21:14 +0000	[diff] [blame]	1	//===-- Processors.td - R600 Processor definitions ------------------------===//
Tom Stellard	75aadc2	2012-12-11 21:25:42 +0000	[diff] [blame]	2	//
				3	// The LLVM Compiler Infrastructure
				4	//
				5	// This file is distributed under the University of Illinois Open Source
				6	// License. See LICENSE.TXT for details.
				7	//
				8	//===----------------------------------------------------------------------===//
Tom Stellard	75aadc2	2012-12-11 21:25:42 +0000	[diff] [blame]	9
				10	class Proc<string Name, ProcessorItineraries itin, list<SubtargetFeature> Features>
				11	: Processor<Name, itin, Features>;
Tom Stellard	d7e146e	2013-12-11 17:51:51 +0000	[diff] [blame]	12
				13	//===----------------------------------------------------------------------===//
				14	// R600
				15	//===----------------------------------------------------------------------===//
Vincent Lejeune	076c0b2	2013-04-30 00:14:17 +0000	[diff] [blame]	16	def : Proc<"r600", R600_VLIW5_Itin,
Matt Arsenault	8e00194	2016-06-02 18:37:16 +0000	[diff] [blame]	17	[FeatureR600, FeatureVertexCache, FeatureWavefrontSize64]>;
Tom Stellard	8c347b0	2014-01-22 21:55:40 +0000	[diff] [blame]	18
				19	def : Proc<"r630", R600_VLIW5_Itin,
				20	[FeatureR600, FeatureVertexCache, FeatureWavefrontSize32]>;
Tom Stellard	d7e146e	2013-12-11 17:51:51 +0000	[diff] [blame]	21
Vincent Lejeune	076c0b2	2013-04-30 00:14:17 +0000	[diff] [blame]	22	def : Proc<"rs880", R600_VLIW5_Itin,
Tom Stellard	8c347b0	2014-01-22 21:55:40 +0000	[diff] [blame]	23	[FeatureR600, FeatureWavefrontSize16]>;
Tom Stellard	d7e146e	2013-12-11 17:51:51 +0000	[diff] [blame]	24
Vincent Lejeune	076c0b2	2013-04-30 00:14:17 +0000	[diff] [blame]	25	def : Proc<"rv670", R600_VLIW5_Itin,
Tom Stellard	8c347b0	2014-01-22 21:55:40 +0000	[diff] [blame]	26	[FeatureR600, FeatureFP64, FeatureVertexCache, FeatureWavefrontSize64]>;
Tom Stellard	d7e146e	2013-12-11 17:51:51 +0000	[diff] [blame]	27
				28	//===----------------------------------------------------------------------===//
				29	// R700
				30	//===----------------------------------------------------------------------===//
				31
Vincent Lejeune	076c0b2	2013-04-30 00:14:17 +0000	[diff] [blame]	32	def : Proc<"rv710", R600_VLIW5_Itin,
Tom Stellard	8c347b0	2014-01-22 21:55:40 +0000	[diff] [blame]	33	[FeatureR700, FeatureVertexCache, FeatureWavefrontSize32]>;
Tom Stellard	d7e146e	2013-12-11 17:51:51 +0000	[diff] [blame]	34
Vincent Lejeune	076c0b2	2013-04-30 00:14:17 +0000	[diff] [blame]	35	def : Proc<"rv730", R600_VLIW5_Itin,
Tom Stellard	8c347b0	2014-01-22 21:55:40 +0000	[diff] [blame]	36	[FeatureR700, FeatureVertexCache, FeatureWavefrontSize32]>;
Tom Stellard	d7e146e	2013-12-11 17:51:51 +0000	[diff] [blame]	37
Vincent Lejeune	076c0b2	2013-04-30 00:14:17 +0000	[diff] [blame]	38	def : Proc<"rv770", R600_VLIW5_Itin,
Tom Stellard	8c347b0	2014-01-22 21:55:40 +0000	[diff] [blame]	39	[FeatureR700, FeatureFP64, FeatureVertexCache, FeatureWavefrontSize64]>;
Tom Stellard	d7e146e	2013-12-11 17:51:51 +0000	[diff] [blame]	40
				41	//===----------------------------------------------------------------------===//
				42	// Evergreen
				43	//===----------------------------------------------------------------------===//
				44
Vincent Lejeune	076c0b2	2013-04-30 00:14:17 +0000	[diff] [blame]	45	def : Proc<"cedar", R600_VLIW5_Itin,
Tom Stellard	348273d	2014-01-23 16:18:02 +0000	[diff] [blame]	46	[FeatureEvergreen, FeatureVertexCache, FeatureWavefrontSize32,
				47	FeatureCFALUBug]>;
Tom Stellard	d7e146e	2013-12-11 17:51:51 +0000	[diff] [blame]	48
Vincent Lejeune	076c0b2	2013-04-30 00:14:17 +0000	[diff] [blame]	49	def : Proc<"redwood", R600_VLIW5_Itin,
Tom Stellard	348273d	2014-01-23 16:18:02 +0000	[diff] [blame]	50	[FeatureEvergreen, FeatureVertexCache, FeatureWavefrontSize64,
				51	FeatureCFALUBug]>;
Tom Stellard	d7e146e	2013-12-11 17:51:51 +0000	[diff] [blame]	52
Vincent Lejeune	076c0b2	2013-04-30 00:14:17 +0000	[diff] [blame]	53	def : Proc<"sumo", R600_VLIW5_Itin,
Tom Stellard	348273d	2014-01-23 16:18:02 +0000	[diff] [blame]	54	[FeatureEvergreen, FeatureWavefrontSize64, FeatureCFALUBug]>;
Tom Stellard	d7e146e	2013-12-11 17:51:51 +0000	[diff] [blame]	55
Vincent Lejeune	076c0b2	2013-04-30 00:14:17 +0000	[diff] [blame]	56	def : Proc<"juniper", R600_VLIW5_Itin,
Tom Stellard	8c347b0	2014-01-22 21:55:40 +0000	[diff] [blame]	57	[FeatureEvergreen, FeatureVertexCache, FeatureWavefrontSize64]>;
Tom Stellard	d7e146e	2013-12-11 17:51:51 +0000	[diff] [blame]	58
Vincent Lejeune	076c0b2	2013-04-30 00:14:17 +0000	[diff] [blame]	59	def : Proc<"cypress", R600_VLIW5_Itin,
Tom Stellard	8c347b0	2014-01-22 21:55:40 +0000	[diff] [blame]	60	[FeatureEvergreen, FeatureFP64, FeatureVertexCache,
				61	FeatureWavefrontSize64]>;
Tom Stellard	d7e146e	2013-12-11 17:51:51 +0000	[diff] [blame]	62
				63	//===----------------------------------------------------------------------===//
				64	// Northern Islands
				65	//===----------------------------------------------------------------------===//
				66
Vincent Lejeune	076c0b2	2013-04-30 00:14:17 +0000	[diff] [blame]	67	def : Proc<"barts", R600_VLIW5_Itin,
Tom Stellard	348273d	2014-01-23 16:18:02 +0000	[diff] [blame]	68	[FeatureNorthernIslands, FeatureVertexCache, FeatureCFALUBug]>;
Tom Stellard	d7e146e	2013-12-11 17:51:51 +0000	[diff] [blame]	69
Vincent Lejeune	076c0b2	2013-04-30 00:14:17 +0000	[diff] [blame]	70	def : Proc<"turks", R600_VLIW5_Itin,
Tom Stellard	348273d	2014-01-23 16:18:02 +0000	[diff] [blame]	71	[FeatureNorthernIslands, FeatureVertexCache, FeatureCFALUBug]>;
Tom Stellard	d7e146e	2013-12-11 17:51:51 +0000	[diff] [blame]	72
Vincent Lejeune	076c0b2	2013-04-30 00:14:17 +0000	[diff] [blame]	73	def : Proc<"caicos", R600_VLIW5_Itin,
Tom Stellard	348273d	2014-01-23 16:18:02 +0000	[diff] [blame]	74	[FeatureNorthernIslands, FeatureCFALUBug]>;
Tom Stellard	d7e146e	2013-12-11 17:51:51 +0000	[diff] [blame]	75
Vincent Lejeune	076c0b2	2013-04-30 00:14:17 +0000	[diff] [blame]	76	def : Proc<"cayman", R600_VLIW4_Itin,
Tom Stellard	a6c6e1b	2013-06-07 20:37:48 +0000	[diff] [blame]	77	[FeatureNorthernIslands, FeatureFP64, FeatureCaymanISA]>;
Tom Stellard	3498e4f	2013-06-07 20:28:55 +0000	[diff] [blame]	78
Tom Stellard	d7e146e	2013-12-11 17:51:51 +0000	[diff] [blame]	79	//===----------------------------------------------------------------------===//
				80	// Southern Islands
				81	//===----------------------------------------------------------------------===//
				82
Matt Arsenault	8bcf2f2	2017-06-26 03:01:36 +0000	[diff] [blame]	83	def : ProcessorModel<"gfx600", SIFullSpeedModel,
Wei Ding	7c3e511	2017-06-10 03:53:19 +0000	[diff] [blame]	84	[FeatureISAVersion6_0_0]>;
				85
				86	def : ProcessorModel<"SI", SIFullSpeedModel,
				87	[FeatureISAVersion6_0_0]
Matt Arsenault	b035a57	2015-01-29 19:34:25 +0000	[diff] [blame]	88	>;
Tom Stellard	d7e146e	2013-12-11 17:51:51 +0000	[diff] [blame]	89
Wei Ding	7c3e511	2017-06-10 03:53:19 +0000	[diff] [blame]	90	def : ProcessorModel<"tahiti", SIFullSpeedModel,
				91	[FeatureISAVersion6_0_0]
Matt Arsenault	b035a57	2015-01-29 19:34:25 +0000	[diff] [blame]	92	>;
Tom Stellard	d7e146e	2013-12-11 17:51:51 +0000	[diff] [blame]	93
Wei Ding	7c3e511	2017-06-10 03:53:19 +0000	[diff] [blame]	94	def : ProcessorModel<"gfx601", SIQuarterSpeedModel,
				95	[FeatureISAVersion6_0_1]
				96	>;
Tom Stellard	d7e146e	2013-12-11 17:51:51 +0000	[diff] [blame]	97
Matt Arsenault	8bcf2f2	2017-06-26 03:01:36 +0000	[diff] [blame]	98	def : ProcessorModel<"pitcairn", SIQuarterSpeedModel,
Wei Ding	7c3e511	2017-06-10 03:53:19 +0000	[diff] [blame]	99	[FeatureISAVersion6_0_1]>;
Tom Stellard	d7e146e	2013-12-11 17:51:51 +0000	[diff] [blame]	100
Wei Ding	7c3e511	2017-06-10 03:53:19 +0000	[diff] [blame]	101	def : ProcessorModel<"verde", SIQuarterSpeedModel,
				102	[FeatureISAVersion6_0_1]>;
Tom Stellard	d7e146e	2013-12-11 17:51:51 +0000	[diff] [blame]	103
Wei Ding	7c3e511	2017-06-10 03:53:19 +0000	[diff] [blame]	104	def : ProcessorModel<"oland", SIQuarterSpeedModel,
				105	[FeatureISAVersion6_0_1]>;
				106
				107	def : ProcessorModel<"hainan", SIQuarterSpeedModel, [FeatureISAVersion6_0_1]>;
Tom Stellard	d7e146e	2013-12-11 17:51:51 +0000	[diff] [blame]	108
				109	//===----------------------------------------------------------------------===//
				110	// Sea Islands
				111	//===----------------------------------------------------------------------===//
				112
Wei Ding	7c3e511	2017-06-10 03:53:19 +0000	[diff] [blame]	113	def : ProcessorModel<"gfx700", SIQuarterSpeedModel,
				114	[FeatureISAVersion7_0_0]
				115	>;
				116
Tom Stellard	ec87f84	2015-05-25 16:15:54 +0000	[diff] [blame]	117	def : ProcessorModel<"bonaire", SIQuarterSpeedModel,
Yaxun Liu	94add85	2016-10-26 16:37:56 +0000	[diff] [blame]	118	[FeatureISAVersion7_0_0]
Matt Arsenault	b035a57	2015-01-29 19:34:25 +0000	[diff] [blame]	119	>;
Tom Stellard	10b1502	2014-05-02 15:41:49 +0000	[diff] [blame]	120
Tom Stellard	ec87f84	2015-05-25 16:15:54 +0000	[diff] [blame]	121	def : ProcessorModel<"kaveri", SIQuarterSpeedModel,
Yaxun Liu	94add85	2016-10-26 16:37:56 +0000	[diff] [blame]	122	[FeatureISAVersion7_0_0]
Tom Stellard	ec87f84	2015-05-25 16:15:54 +0000	[diff] [blame]	123	>;
				124
Yaxun Liu	94add85	2016-10-26 16:37:56 +0000	[diff] [blame]	125	def : ProcessorModel<"gfx701", SIFullSpeedModel,
				126	[FeatureISAVersion7_0_1]
				127	>;
				128
Wei Ding	7c3e511	2017-06-10 03:53:19 +0000	[diff] [blame]	129	def : ProcessorModel<"hawaii", SIFullSpeedModel,
				130	[FeatureISAVersion7_0_1]
				131	>;
				132
Yaxun Liu	94add85	2016-10-26 16:37:56 +0000	[diff] [blame]	133	def : ProcessorModel<"gfx702", SIQuarterSpeedModel,
				134	[FeatureISAVersion7_0_2]
				135	>;
Marek Olsak	5df00d6	2014-12-07 12:18:57 +0000	[diff] [blame]	136
Wei Ding	7c3e511	2017-06-10 03:53:19 +0000	[diff] [blame]	137	def : ProcessorModel<"gfx703", SIQuarterSpeedModel,
				138	[FeatureISAVersion7_0_3]
				139	>;
				140
				141	def : ProcessorModel<"kabini", SIQuarterSpeedModel,
				142	[FeatureISAVersion7_0_3]
				143	>;
				144
				145	def : ProcessorModel<"mullins", SIQuarterSpeedModel,
				146	[FeatureISAVersion7_0_3]>;
				147
Tom Stellard	ae38f30	2015-01-14 01:13:19 +0000	[diff] [blame]	148	//===----------------------------------------------------------------------===//
				149	// Volcanic Islands
				150	//===----------------------------------------------------------------------===//
Marek Olsak	5df00d6	2014-12-07 12:18:57 +0000	[diff] [blame]	151
Marek Olsak	4d00dd2	2015-03-09 15:48:09 +0000	[diff] [blame]	152	def : ProcessorModel<"tonga", SIQuarterSpeedModel,
Yaxun Liu	94add85	2016-10-26 16:37:56 +0000	[diff] [blame]	153	[FeatureISAVersion8_0_2]
Marek Olsak	4d00dd2	2015-03-09 15:48:09 +0000	[diff] [blame]	154	>;
Marek Olsak	5df00d6	2014-12-07 12:18:57 +0000	[diff] [blame]	155
Marek Olsak	4d00dd2	2015-03-09 15:48:09 +0000	[diff] [blame]	156	def : ProcessorModel<"iceland", SIQuarterSpeedModel,
Yaxun Liu	94add85	2016-10-26 16:37:56 +0000	[diff] [blame]	157	[FeatureISAVersion8_0_0]
Marek Olsak	4d00dd2	2015-03-09 15:48:09 +0000	[diff] [blame]	158	>;
Tom Stellard	ae38f30	2015-01-14 01:13:19 +0000	[diff] [blame]	159
Tom Stellard	347ac79	2015-06-26 21:15:07 +0000	[diff] [blame]	160	def : ProcessorModel<"carrizo", SIQuarterSpeedModel,
Yaxun Liu	94add85	2016-10-26 16:37:56 +0000	[diff] [blame]	161	[FeatureISAVersion8_0_1]
Tom Stellard	347ac79	2015-06-26 21:15:07 +0000	[diff] [blame]	162	>;
Tom Stellard	d488605	2015-08-06 19:43:02 +0000	[diff] [blame]	163
Yaxun Liu	94add85	2016-10-26 16:37:56 +0000	[diff] [blame]	164	def : ProcessorModel<"fiji", SIQuarterSpeedModel,
				165	[FeatureISAVersion8_0_3]
Tom Stellard	d488605	2015-08-06 19:43:02 +0000	[diff] [blame]	166	>;
Tom Stellard	afd6e2f	2015-11-13 17:06:32 +0000	[diff] [blame]	167
Yaxun Liu	94add85	2016-10-26 16:37:56 +0000	[diff] [blame]	168	def : ProcessorModel<"stoney", SIQuarterSpeedModel,
				169	[FeatureISAVersion8_1_0]
Tom Stellard	afd6e2f	2015-11-13 17:06:32 +0000	[diff] [blame]	170	>;
Tom Stellard	9babad2	2016-03-24 15:31:05 +0000	[diff] [blame]	171
				172	def : ProcessorModel<"polaris10", SIQuarterSpeedModel,
Yaxun Liu	94add85	2016-10-26 16:37:56 +0000	[diff] [blame]	173	[FeatureISAVersion8_0_3]
Tom Stellard	9babad2	2016-03-24 15:31:05 +0000	[diff] [blame]	174	>;
				175
				176	def : ProcessorModel<"polaris11", SIQuarterSpeedModel,
Yaxun Liu	94add85	2016-10-26 16:37:56 +0000	[diff] [blame]	177	[FeatureISAVersion8_0_3]
Tom Stellard	9babad2	2016-03-24 15:31:05 +0000	[diff] [blame]	178	>;
Yaxun Liu	94add85	2016-10-26 16:37:56 +0000	[diff] [blame]	179
				180	def : ProcessorModel<"gfx800", SIQuarterSpeedModel,
				181	[FeatureISAVersion8_0_0]
				182	>;
				183
				184	def : ProcessorModel<"gfx801", SIQuarterSpeedModel,
				185	[FeatureISAVersion8_0_1]
				186	>;
				187
				188	def : ProcessorModel<"gfx802", SIQuarterSpeedModel,
				189	[FeatureISAVersion8_0_2]
				190	>;
				191
				192	def : ProcessorModel<"gfx803", SIQuarterSpeedModel,
				193	[FeatureISAVersion8_0_3]
				194	>;
				195
				196	def : ProcessorModel<"gfx804", SIQuarterSpeedModel,
				197	[FeatureISAVersion8_0_4]
				198	>;
				199
				200	def : ProcessorModel<"gfx810", SIQuarterSpeedModel,
				201	[FeatureISAVersion8_1_0]
				202	>;
				203
Wei Ding	7c3e511	2017-06-10 03:53:19 +0000	[diff] [blame]	204	//===----------------------------------------------------------------------===//
				205	// GFX9
				206	//===----------------------------------------------------------------------===//
				207
				208	def : ProcessorModel<"gfx900", SIQuarterSpeedModel,
				209	[FeatureISAVersion9_0_0]
Matt Arsenault	e823d92	2017-02-18 18:29:53 +0000	[diff] [blame]	210	>;
				211
Wei Ding	7c3e511	2017-06-10 03:53:19 +0000	[diff] [blame]	212	def : ProcessorModel<"gfx901", SIQuarterSpeedModel,
				213	[FeatureISAVersion9_0_1]
Matt Arsenault	e823d92	2017-02-18 18:29:53 +0000	[diff] [blame]	214	>;
Wei Ding	7c3e511	2017-06-10 03:53:19 +0000	[diff] [blame]	215
				216	def : ProcessorModel<"gfx902", SIQuarterSpeedModel,
				217	[FeatureISAVersion9_0_2]
				218	>;
				219
				220	def : ProcessorModel<"gfx903", SIQuarterSpeedModel,
				221	[FeatureISAVersion9_0_3]
				222	>;
				223