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gerrit-public.fairphone.software / toolchain / llvm-project / bb36fe8dbabfe92e8b78bba58bc462f590145a88 / . / llvm / lib / Target / Mips / MipsSEISelLowering.cpp
blob: 26e0f9a94368a6c04150a05a80194124e45559e8 [file] [log] [blame]
Akira Hatanaka44ebe002013-03-14 19:09:52 +0000[diff] [blame]1//===-- MipsSEISelLowering.cpp - MipsSE DAG Lowering Interface --*- C++ -*-===//
Akira Hatanaka96ca1822013-03-13 00:54:29 +0000[diff] [blame]2//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// Subclass of MipsTargetLowering specialized for mips32/64.
11//
12//===----------------------------------------------------------------------===//
13#include "MipsSEISelLowering.h"
Eric Christopher79cc1e32014-09-02 22:28:02 +0000[diff] [blame]14#include "MipsMachineFunction.h"
Akira Hatanaka96ca1822013-03-13 00:54:29 +0000[diff] [blame]15#include "MipsRegisterInfo.h"
16#include "MipsTargetMachine.h"
17#include "llvm/CodeGen/MachineInstrBuilder.h"
18#include "llvm/CodeGen/MachineRegisterInfo.h"
Akira Hatanakaa6bbde52013-04-13 02:13:30 +0000[diff] [blame]19#include "llvm/IR/Intrinsics.h"
Akira Hatanaka96ca1822013-03-13 00:54:29 +0000[diff] [blame]20#include "llvm/Support/CommandLine.h"
Daniel Sanders62aeab82013-10-30 13:31:27 +0000[diff] [blame]21#include "llvm/Support/Debug.h"
Hans Wennborg3e9b1c12013-10-30 16:10:10 +0000[diff] [blame]22#include "llvm/Support/raw_ostream.h"
Akira Hatanaka96ca1822013-03-13 00:54:29 +0000[diff] [blame]23#include "llvm/Target/TargetInstrInfo.h"
24
25using namespace llvm;
26
Chandler Carruth84e68b22014-04-22 02:41:26 +0000[diff] [blame]27#define DEBUG_TYPE "mips-isel"
28
Akira Hatanaka96ca1822013-03-13 00:54:29 +0000[diff] [blame]29static cl::opt<bool>
Simon Dardis57f4ae42016-08-04 09:17:07 +0000[diff] [blame]30UseMipsTailCalls("mips-tail-calls", cl::Hidden,
Simon Dardisd2ed8ab2016-09-27 13:15:54 +0000[diff] [blame]31 cl::desc("MIPS: permit tail calls."), cl::init(false));
Akira Hatanaka96ca1822013-03-13 00:54:29 +0000[diff] [blame]32
Akira Hatanaka63791212013-09-07 00:52:30 +0000[diff] [blame]33static cl::opt<bool> NoDPLoadStore("mno-ldc1-sdc1", cl::init(false),
34 cl::desc("Expand double precision loads and "
35 "stores to their single precision "
36 "counterparts"));
37
Eric Christopherb1526602014-09-19 23:30:42 +0000[diff] [blame]38MipsSETargetLowering::MipsSETargetLowering(const MipsTargetMachine &TM,
Eric Christopher8924d272014-07-18 23:25:04 +0000[diff] [blame]39 const MipsSubtarget &STI)
40 : MipsTargetLowering(TM, STI) {
Akira Hatanaka96ca1822013-03-13 00:54:29 +0000[diff] [blame]41 // Set up the register classes
Akira Hatanaka13e6ccf2013-08-06 23:08:38 +0000[diff] [blame]42 addRegisterClass(MVT::i32, &Mips::GPR32RegClass);
Akira Hatanaka96ca1822013-03-13 00:54:29 +0000[diff] [blame]43
Eric Christopher1c29a652014-07-18 22:55:25 +0000[diff] [blame]44 if (Subtarget.isGP64bit())
Akira Hatanaka13e6ccf2013-08-06 23:08:38 +0000[diff] [blame]45 addRegisterClass(MVT::i64, &Mips::GPR64RegClass);
Akira Hatanaka96ca1822013-03-13 00:54:29 +0000[diff] [blame]46
Eric Christopher1c29a652014-07-18 22:55:25 +0000[diff] [blame]47 if (Subtarget.hasDSP() || Subtarget.hasMSA()) {
Daniel Sanders36c671e2013-09-27 09:44:59 +0000[diff] [blame]48 // Expand all truncating stores and extending loads.
Ahmed Bougacha67dd2d22015-01-07 21:27:10 +0000[diff] [blame]49 for (MVT VT0 : MVT::vector_valuetypes()) {
Ahmed Bougacha2b6917b2015-01-08 00:51:32 +0000[diff] [blame]50 for (MVT VT1 : MVT::vector_valuetypes()) {
Ahmed Bougacha67dd2d22015-01-07 21:27:10 +0000[diff] [blame]51 setTruncStoreAction(VT0, VT1, Expand);
Ahmed Bougacha2b6917b2015-01-08 00:51:32 +0000[diff] [blame]52 setLoadExtAction(ISD::SEXTLOAD, VT0, VT1, Expand);
53 setLoadExtAction(ISD::ZEXTLOAD, VT0, VT1, Expand);
54 setLoadExtAction(ISD::EXTLOAD, VT0, VT1, Expand);
55 }
Daniel Sanders36c671e2013-09-27 09:44:59 +0000[diff] [blame]56 }
57 }
58
Eric Christopher1c29a652014-07-18 22:55:25 +0000[diff] [blame]59 if (Subtarget.hasDSP()) {
Akira Hatanaka96ca1822013-03-13 00:54:29 +0000[diff] [blame]60 MVT::SimpleValueType VecTys[2] = {MVT::v2i16, MVT::v4i8};
61
62 for (unsigned i = 0; i < array_lengthof(VecTys); ++i) {
Akira Hatanaka654655f2013-08-14 00:53:38 +0000[diff] [blame]63 addRegisterClass(VecTys[i], &Mips::DSPRRegClass);
Akira Hatanaka96ca1822013-03-13 00:54:29 +0000[diff] [blame]64
65 // Expand all builtin opcodes.
66 for (unsigned Opc = 0; Opc < ISD::BUILTIN_OP_END; ++Opc)
67 setOperationAction(Opc, VecTys[i], Expand);
68
Akira Hatanaka2f088222013-04-13 00:55:41 +0000[diff] [blame]69 setOperationAction(ISD::ADD, VecTys[i], Legal);
70 setOperationAction(ISD::SUB, VecTys[i], Legal);
Akira Hatanaka96ca1822013-03-13 00:54:29 +0000[diff] [blame]71 setOperationAction(ISD::LOAD, VecTys[i], Legal);
72 setOperationAction(ISD::STORE, VecTys[i], Legal);
73 setOperationAction(ISD::BITCAST, VecTys[i], Legal);
74 }
Akira Hatanaka1ebb2a12013-04-19 23:21:32 +0000[diff] [blame]75
76 setTargetDAGCombine(ISD::SHL);
77 setTargetDAGCombine(ISD::SRA);
78 setTargetDAGCombine(ISD::SRL);
Akira Hatanaka68741cc2013-04-30 22:37:26 +0000[diff] [blame]79 setTargetDAGCombine(ISD::SETCC);
80 setTargetDAGCombine(ISD::VSELECT);
Akira Hatanaka96ca1822013-03-13 00:54:29 +0000[diff] [blame]81 }
82
Eric Christopher1c29a652014-07-18 22:55:25 +0000[diff] [blame]83 if (Subtarget.hasDSPR2())
Akira Hatanaka2f088222013-04-13 00:55:41 +0000[diff] [blame]84 setOperationAction(ISD::MUL, MVT::v2i16, Legal);
85
Eric Christopher1c29a652014-07-18 22:55:25 +0000[diff] [blame]86 if (Subtarget.hasMSA()) {
Daniel Sandersc65f58a2013-09-11 10:15:48 +0000[diff] [blame]87 addMSAIntType(MVT::v16i8, &Mips::MSA128BRegClass);
88 addMSAIntType(MVT::v8i16, &Mips::MSA128HRegClass);
89 addMSAIntType(MVT::v4i32, &Mips::MSA128WRegClass);
90 addMSAIntType(MVT::v2i64, &Mips::MSA128DRegClass);
91 addMSAFloatType(MVT::v8f16, &Mips::MSA128HRegClass);
92 addMSAFloatType(MVT::v4f32, &Mips::MSA128WRegClass);
93 addMSAFloatType(MVT::v2f64, &Mips::MSA128DRegClass);
Daniel Sandersf7456c72013-09-23 13:22:24 +0000[diff] [blame]94
Simon Dardis0e2ee3b2016-11-18 16:17:44 +0000[diff] [blame]95 // f16 is a storage-only type, always promote it to f32.
96 addRegisterClass(MVT::f16, &Mips::MSA128HRegClass);
97 setOperationAction(ISD::SETCC, MVT::f16, Promote);
98 setOperationAction(ISD::BR_CC, MVT::f16, Promote);
99 setOperationAction(ISD::SELECT_CC, MVT::f16, Promote);
100 setOperationAction(ISD::SELECT, MVT::f16, Promote);
101 setOperationAction(ISD::FADD, MVT::f16, Promote);
102 setOperationAction(ISD::FSUB, MVT::f16, Promote);
103 setOperationAction(ISD::FMUL, MVT::f16, Promote);
104 setOperationAction(ISD::FDIV, MVT::f16, Promote);
105 setOperationAction(ISD::FREM, MVT::f16, Promote);
106 setOperationAction(ISD::FMA, MVT::f16, Promote);
107 setOperationAction(ISD::FNEG, MVT::f16, Promote);
108 setOperationAction(ISD::FABS, MVT::f16, Promote);
109 setOperationAction(ISD::FCEIL, MVT::f16, Promote);
110 setOperationAction(ISD::FCOPYSIGN, MVT::f16, Promote);
111 setOperationAction(ISD::FCOS, MVT::f16, Promote);
112 setOperationAction(ISD::FP_EXTEND, MVT::f16, Promote);
113 setOperationAction(ISD::FFLOOR, MVT::f16, Promote);
114 setOperationAction(ISD::FNEARBYINT, MVT::f16, Promote);
115 setOperationAction(ISD::FPOW, MVT::f16, Promote);
116 setOperationAction(ISD::FPOWI, MVT::f16, Promote);
117 setOperationAction(ISD::FRINT, MVT::f16, Promote);
118 setOperationAction(ISD::FSIN, MVT::f16, Promote);
119 setOperationAction(ISD::FSINCOS, MVT::f16, Promote);
120 setOperationAction(ISD::FSQRT, MVT::f16, Promote);
121 setOperationAction(ISD::FEXP, MVT::f16, Promote);
122 setOperationAction(ISD::FEXP2, MVT::f16, Promote);
123 setOperationAction(ISD::FLOG, MVT::f16, Promote);
124 setOperationAction(ISD::FLOG2, MVT::f16, Promote);
125 setOperationAction(ISD::FLOG10, MVT::f16, Promote);
126 setOperationAction(ISD::FROUND, MVT::f16, Promote);
127 setOperationAction(ISD::FTRUNC, MVT::f16, Promote);
128 setOperationAction(ISD::FMINNUM, MVT::f16, Promote);
129 setOperationAction(ISD::FMAXNUM, MVT::f16, Promote);
130 setOperationAction(ISD::FMINNAN, MVT::f16, Promote);
131 setOperationAction(ISD::FMAXNAN, MVT::f16, Promote);
132
Daniel Sandersa4c8f3a2013-09-23 14:03:12 +0000[diff] [blame]133 setTargetDAGCombine(ISD::AND);
Daniel Sanders53fe6c42013-10-30 13:51:01 +0000[diff] [blame]134 setTargetDAGCombine(ISD::OR);
Daniel Sandersa4c8f3a2013-09-23 14:03:12 +0000[diff] [blame]135 setTargetDAGCombine(ISD::SRA);
Daniel Sanderse1d24352013-09-24 12:04:44 +0000[diff] [blame]136 setTargetDAGCombine(ISD::VSELECT);
Daniel Sandersf7456c72013-09-23 13:22:24 +0000[diff] [blame]137 setTargetDAGCombine(ISD::XOR);
Jack Carter3a2c2d42013-08-13 20:54:07 +0000[diff] [blame]138 }
139
Eric Christophere8ae3e32015-05-07 23:10:21 +0000[diff] [blame]140 if (!Subtarget.useSoftFloat()) {
Akira Hatanaka96ca1822013-03-13 00:54:29 +0000[diff] [blame]141 addRegisterClass(MVT::f32, &Mips::FGR32RegClass);
142
143 // When dealing with single precision only, use libcalls
Eric Christopher1c29a652014-07-18 22:55:25 +0000[diff] [blame]144 if (!Subtarget.isSingleFloat()) {
145 if (Subtarget.isFP64bit())
Akira Hatanaka96ca1822013-03-13 00:54:29 +0000[diff] [blame]146 addRegisterClass(MVT::f64, &Mips::FGR64RegClass);
147 else
148 addRegisterClass(MVT::f64, &Mips::AFGR64RegClass);
149 }
150 }
151
Akira Hatanakabe8612f2013-03-30 01:36:35 +0000[diff] [blame]152 setOperationAction(ISD::SMUL_LOHI, MVT::i32, Custom);
153 setOperationAction(ISD::UMUL_LOHI, MVT::i32, Custom);
154 setOperationAction(ISD::MULHS, MVT::i32, Custom);
155 setOperationAction(ISD::MULHU, MVT::i32, Custom);
156
Eric Christopher1c29a652014-07-18 22:55:25 +0000[diff] [blame]157 if (Subtarget.hasCnMips())
Kai Nacke93fe5e82014-03-20 11:51:58 +0000[diff] [blame]158 setOperationAction(ISD::MUL, MVT::i64, Legal);
Eric Christopher1c29a652014-07-18 22:55:25 +0000[diff] [blame]159 else if (Subtarget.isGP64bit())
Kai Nacke93fe5e82014-03-20 11:51:58 +0000[diff] [blame]160 setOperationAction(ISD::MUL, MVT::i64, Custom);
161
Eric Christopher1c29a652014-07-18 22:55:25 +0000[diff] [blame]162 if (Subtarget.isGP64bit()) {
Vasileios Kalintirisef96a8e2015-01-26 12:33:22 +0000[diff] [blame]163 setOperationAction(ISD::SMUL_LOHI, MVT::i64, Custom);
164 setOperationAction(ISD::UMUL_LOHI, MVT::i64, Custom);
Akira Hatanaka4f1130e2013-04-11 19:29:26 +0000[diff] [blame]165 setOperationAction(ISD::MULHS, MVT::i64, Custom);
166 setOperationAction(ISD::MULHU, MVT::i64, Custom);
Jan Vesely54468a5a2014-10-17 14:45:28 +0000[diff] [blame]167 setOperationAction(ISD::SDIVREM, MVT::i64, Custom);
168 setOperationAction(ISD::UDIVREM, MVT::i64, Custom);
Akira Hatanaka4f1130e2013-04-11 19:29:26 +0000[diff] [blame]169 }
Akira Hatanakabe8612f2013-03-30 01:36:35 +0000[diff] [blame]170
Akira Hatanakaa6bbde52013-04-13 02:13:30 +0000[diff] [blame]171 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::i64, Custom);
172 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::i64, Custom);
173
Akira Hatanakabe8612f2013-03-30 01:36:35 +0000[diff] [blame]174 setOperationAction(ISD::SDIVREM, MVT::i32, Custom);
175 setOperationAction(ISD::UDIVREM, MVT::i32, Custom);
Akira Hatanaka96ca1822013-03-13 00:54:29 +0000[diff] [blame]176 setOperationAction(ISD::ATOMIC_FENCE, MVT::Other, Custom);
177 setOperationAction(ISD::LOAD, MVT::i32, Custom);
178 setOperationAction(ISD::STORE, MVT::i32, Custom);
179
Akira Hatanaka9efcd762013-03-30 01:42:24 +0000[diff] [blame]180 setTargetDAGCombine(ISD::ADDE);
181 setTargetDAGCombine(ISD::SUBE);
Akira Hatanaka5832fc62013-06-26 18:48:17 +0000[diff] [blame]182 setTargetDAGCombine(ISD::MUL);
Akira Hatanaka9efcd762013-03-30 01:42:24 +0000[diff] [blame]183
Daniel Sandersce09d072013-08-28 12:14:50 +0000[diff] [blame]184 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
Daniel Sanderse6ed5b72013-08-28 12:04:29 +0000[diff] [blame]185 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::Other, Custom);
186 setOperationAction(ISD::INTRINSIC_VOID, MVT::Other, Custom);
187
Akira Hatanaka63791212013-09-07 00:52:30 +0000[diff] [blame]188 if (NoDPLoadStore) {
189 setOperationAction(ISD::LOAD, MVT::f64, Custom);
190 setOperationAction(ISD::STORE, MVT::f64, Custom);
191 }
192
Eric Christopher1c29a652014-07-18 22:55:25 +0000[diff] [blame]193 if (Subtarget.hasMips32r6()) {
Daniel Sanders308181e2014-06-12 10:44:10 +0000[diff] [blame]194 // MIPS32r6 replaces the accumulator-based multiplies with a three register
195 // instruction
Daniel Sanders826f8b32014-06-12 10:54:16 +0000[diff] [blame]196 setOperationAction(ISD::SMUL_LOHI, MVT::i32, Expand);
197 setOperationAction(ISD::UMUL_LOHI, MVT::i32, Expand);
Daniel Sanders308181e2014-06-12 10:44:10 +0000[diff] [blame]198 setOperationAction(ISD::MUL, MVT::i32, Legal);
199 setOperationAction(ISD::MULHS, MVT::i32, Legal);
200 setOperationAction(ISD::MULHU, MVT::i32, Legal);
201
202 // MIPS32r6 replaces the accumulator-based division/remainder with separate
203 // three register division and remainder instructions.
204 setOperationAction(ISD::SDIVREM, MVT::i32, Expand);
205 setOperationAction(ISD::UDIVREM, MVT::i32, Expand);
206 setOperationAction(ISD::SDIV, MVT::i32, Legal);
207 setOperationAction(ISD::UDIV, MVT::i32, Legal);
208 setOperationAction(ISD::SREM, MVT::i32, Legal);
209 setOperationAction(ISD::UREM, MVT::i32, Legal);
Daniel Sanders0fa60412014-06-12 13:39:06 +0000[diff] [blame]210
211 // MIPS32r6 replaces conditional moves with an equivalent that removes the
212 // need for three GPR read ports.
213 setOperationAction(ISD::SETCC, MVT::i32, Legal);
214 setOperationAction(ISD::SELECT, MVT::i32, Legal);
215 setOperationAction(ISD::SELECT_CC, MVT::i32, Expand);
216
217 setOperationAction(ISD::SETCC, MVT::f32, Legal);
218 setOperationAction(ISD::SELECT, MVT::f32, Legal);
219 setOperationAction(ISD::SELECT_CC, MVT::f32, Expand);
220
Eric Christopher1c29a652014-07-18 22:55:25 +0000[diff] [blame]221 assert(Subtarget.isFP64bit() && "FR=1 is required for MIPS32r6");
Daniel Sanders0fa60412014-06-12 13:39:06 +0000[diff] [blame]222 setOperationAction(ISD::SETCC, MVT::f64, Legal);
223 setOperationAction(ISD::SELECT, MVT::f64, Legal);
224 setOperationAction(ISD::SELECT_CC, MVT::f64, Expand);
225
Daniel Sanders3d3ea532014-06-12 15:00:17 +0000[diff] [blame]226 setOperationAction(ISD::BRCOND, MVT::Other, Legal);
227
Daniel Sanders0fa60412014-06-12 13:39:06 +0000[diff] [blame]228 // Floating point > and >= are supported via < and <=
229 setCondCodeAction(ISD::SETOGE, MVT::f32, Expand);
230 setCondCodeAction(ISD::SETOGT, MVT::f32, Expand);
231 setCondCodeAction(ISD::SETUGE, MVT::f32, Expand);
232 setCondCodeAction(ISD::SETUGT, MVT::f32, Expand);
233
234 setCondCodeAction(ISD::SETOGE, MVT::f64, Expand);
235 setCondCodeAction(ISD::SETOGT, MVT::f64, Expand);
236 setCondCodeAction(ISD::SETUGE, MVT::f64, Expand);
237 setCondCodeAction(ISD::SETUGT, MVT::f64, Expand);
Daniel Sanders308181e2014-06-12 10:44:10 +0000[diff] [blame]238 }
239
Eric Christopher1c29a652014-07-18 22:55:25 +0000[diff] [blame]240 if (Subtarget.hasMips64r6()) {
Daniel Sanders308181e2014-06-12 10:44:10 +0000[diff] [blame]241 // MIPS64r6 replaces the accumulator-based multiplies with a three register
242 // instruction
Vasileios Kalintirisef96a8e2015-01-26 12:33:22 +0000[diff] [blame]243 setOperationAction(ISD::SMUL_LOHI, MVT::i64, Expand);
244 setOperationAction(ISD::UMUL_LOHI, MVT::i64, Expand);
Daniel Sanders308181e2014-06-12 10:44:10 +0000[diff] [blame]245 setOperationAction(ISD::MUL, MVT::i64, Legal);
246 setOperationAction(ISD::MULHS, MVT::i64, Legal);
247 setOperationAction(ISD::MULHU, MVT::i64, Legal);
248
249 // MIPS32r6 replaces the accumulator-based division/remainder with separate
250 // three register division and remainder instructions.
251 setOperationAction(ISD::SDIVREM, MVT::i64, Expand);
252 setOperationAction(ISD::UDIVREM, MVT::i64, Expand);
253 setOperationAction(ISD::SDIV, MVT::i64, Legal);
254 setOperationAction(ISD::UDIV, MVT::i64, Legal);
255 setOperationAction(ISD::SREM, MVT::i64, Legal);
256 setOperationAction(ISD::UREM, MVT::i64, Legal);
Daniel Sanders0fa60412014-06-12 13:39:06 +0000[diff] [blame]257
258 // MIPS64r6 replaces conditional moves with an equivalent that removes the
259 // need for three GPR read ports.
260 setOperationAction(ISD::SETCC, MVT::i64, Legal);
261 setOperationAction(ISD::SELECT, MVT::i64, Legal);
262 setOperationAction(ISD::SELECT_CC, MVT::i64, Expand);
Daniel Sanders308181e2014-06-12 10:44:10 +0000[diff] [blame]263 }
264
Eric Christopher23a3a7c2015-02-26 00:00:24 +0000[diff] [blame]265 computeRegisterProperties(Subtarget.getRegisterInfo());
Akira Hatanaka96ca1822013-03-13 00:54:29 +0000[diff] [blame]266}
267
268const MipsTargetLowering *
Eric Christopherb1526602014-09-19 23:30:42 +0000[diff] [blame]269llvm::createMipsSETargetLowering(const MipsTargetMachine &TM,
Eric Christopher8924d272014-07-18 23:25:04 +0000[diff] [blame]270 const MipsSubtarget &STI) {
271 return new MipsSETargetLowering(TM, STI);
Akira Hatanaka96ca1822013-03-13 00:54:29 +0000[diff] [blame]272}
273
Eric Christopherbf33a3c2014-07-02 23:18:40 +0000[diff] [blame]274const TargetRegisterClass *
275MipsSETargetLowering::getRepRegClassFor(MVT VT) const {
276 if (VT == MVT::Untyped)
Eric Christopher1c29a652014-07-18 22:55:25 +0000[diff] [blame]277 return Subtarget.hasDSP() ? &Mips::ACC64DSPRegClass : &Mips::ACC64RegClass;
Eric Christopherbf33a3c2014-07-02 23:18:40 +0000[diff] [blame]278
279 return TargetLowering::getRepRegClassFor(VT);
280}
281
Daniel Sanders7a289d02013-09-23 12:02:46 +0000[diff] [blame]282// Enable MSA support for the given integer type and Register class.
Daniel Sanders3c9a0ad2013-08-23 10:10:13 +0000[diff] [blame]283void MipsSETargetLowering::
Daniel Sandersc65f58a2013-09-11 10:15:48 +0000[diff] [blame]284addMSAIntType(MVT::SimpleValueType Ty, const TargetRegisterClass *RC) {
285 addRegisterClass(Ty, RC);
286
287 // Expand all builtin opcodes.
288 for (unsigned Opc = 0; Opc < ISD::BUILTIN_OP_END; ++Opc)
289 setOperationAction(Opc, Ty, Expand);
290
291 setOperationAction(ISD::BITCAST, Ty, Legal);
292 setOperationAction(ISD::LOAD, Ty, Legal);
293 setOperationAction(ISD::STORE, Ty, Legal);
Daniel Sandersa4c8f3a2013-09-23 14:03:12 +0000[diff] [blame]294 setOperationAction(ISD::EXTRACT_VECTOR_ELT, Ty, Custom);
295 setOperationAction(ISD::INSERT_VECTOR_ELT, Ty, Legal);
Daniel Sanders7a289d02013-09-23 12:02:46 +0000[diff] [blame]296 setOperationAction(ISD::BUILD_VECTOR, Ty, Custom);
Daniel Sandersc65f58a2013-09-11 10:15:48 +0000[diff] [blame]297
Daniel Sandersfa5ab1c2013-09-11 10:28:16 +0000[diff] [blame]298 setOperationAction(ISD::ADD, Ty, Legal);
Daniel Sanders8ca81e42013-09-23 12:57:42 +0000[diff] [blame]299 setOperationAction(ISD::AND, Ty, Legal);
Daniel Sandersfbcb5822013-09-11 11:58:30 +0000[diff] [blame]300 setOperationAction(ISD::CTLZ, Ty, Legal);
Daniel Sanders766cb692013-09-23 13:40:21 +0000[diff] [blame]301 setOperationAction(ISD::CTPOP, Ty, Legal);
Daniel Sandersfbcb5822013-09-11 11:58:30 +0000[diff] [blame]302 setOperationAction(ISD::MUL, Ty, Legal);
Daniel Sanders8ca81e42013-09-23 12:57:42 +0000[diff] [blame]303 setOperationAction(ISD::OR, Ty, Legal);
Daniel Sanders607952b2013-09-11 10:38:58 +0000[diff] [blame]304 setOperationAction(ISD::SDIV, Ty, Legal);
Daniel Sanders0210dd42013-10-01 10:22:35 +0000[diff] [blame]305 setOperationAction(ISD::SREM, Ty, Legal);
Daniel Sandersfbcb5822013-09-11 11:58:30 +0000[diff] [blame]306 setOperationAction(ISD::SHL, Ty, Legal);
307 setOperationAction(ISD::SRA, Ty, Legal);
308 setOperationAction(ISD::SRL, Ty, Legal);
309 setOperationAction(ISD::SUB, Ty, Legal);
Daniel Sanders607952b2013-09-11 10:38:58 +0000[diff] [blame]310 setOperationAction(ISD::UDIV, Ty, Legal);
Daniel Sanders0210dd42013-10-01 10:22:35 +0000[diff] [blame]311 setOperationAction(ISD::UREM, Ty, Legal);
Daniel Sanderse5087042013-09-24 14:02:15 +0000[diff] [blame]312 setOperationAction(ISD::VECTOR_SHUFFLE, Ty, Custom);
Daniel Sanderse1d24352013-09-24 12:04:44 +0000[diff] [blame]313 setOperationAction(ISD::VSELECT, Ty, Legal);
Daniel Sanders8ca81e42013-09-23 12:57:42 +0000[diff] [blame]314 setOperationAction(ISD::XOR, Ty, Legal);
Daniel Sandersfd538dc2013-09-24 10:46:19 +0000[diff] [blame]315
Daniel Sanders015972b2013-10-11 10:00:06 +0000[diff] [blame]316 if (Ty == MVT::v4i32 || Ty == MVT::v2i64) {
317 setOperationAction(ISD::FP_TO_SINT, Ty, Legal);
318 setOperationAction(ISD::FP_TO_UINT, Ty, Legal);
319 setOperationAction(ISD::SINT_TO_FP, Ty, Legal);
320 setOperationAction(ISD::UINT_TO_FP, Ty, Legal);
321 }
322
Daniel Sandersfd538dc2013-09-24 10:46:19 +0000[diff] [blame]323 setOperationAction(ISD::SETCC, Ty, Legal);
324 setCondCodeAction(ISD::SETNE, Ty, Expand);
325 setCondCodeAction(ISD::SETGE, Ty, Expand);
326 setCondCodeAction(ISD::SETGT, Ty, Expand);
327 setCondCodeAction(ISD::SETUGE, Ty, Expand);
328 setCondCodeAction(ISD::SETUGT, Ty, Expand);
Daniel Sandersc65f58a2013-09-11 10:15:48 +0000[diff] [blame]329}
330
Daniel Sanders7a289d02013-09-23 12:02:46 +0000[diff] [blame]331// Enable MSA support for the given floating-point type and Register class.
Daniel Sandersc65f58a2013-09-11 10:15:48 +0000[diff] [blame]332void MipsSETargetLowering::
333addMSAFloatType(MVT::SimpleValueType Ty, const TargetRegisterClass *RC) {
Daniel Sanders3c9a0ad2013-08-23 10:10:13 +0000[diff] [blame]334 addRegisterClass(Ty, RC);
Jack Carterbabdcc82013-08-15 12:24:57 +0000[diff] [blame]335
336 // Expand all builtin opcodes.
337 for (unsigned Opc = 0; Opc < ISD::BUILTIN_OP_END; ++Opc)
338 setOperationAction(Opc, Ty, Expand);
339
340 setOperationAction(ISD::LOAD, Ty, Legal);
341 setOperationAction(ISD::STORE, Ty, Legal);
342 setOperationAction(ISD::BITCAST, Ty, Legal);
Daniel Sandersa4c8f3a2013-09-23 14:03:12 +0000[diff] [blame]343 setOperationAction(ISD::EXTRACT_VECTOR_ELT, Ty, Legal);
Daniel Sandersa5150702013-09-27 12:31:32 +0000[diff] [blame]344 setOperationAction(ISD::INSERT_VECTOR_ELT, Ty, Legal);
Daniel Sanders1dfddc72013-10-15 13:14:41 +0000[diff] [blame]345 setOperationAction(ISD::BUILD_VECTOR, Ty, Custom);
Daniel Sandersf5bd9372013-09-11 10:51:30 +0000[diff] [blame]346
347 if (Ty != MVT::v8f16) {
Daniel Sanders4f3ff1b2013-09-24 13:02:08 +0000[diff] [blame]348 setOperationAction(ISD::FABS, Ty, Legal);
Daniel Sandersf5bd9372013-09-11 10:51:30 +0000[diff] [blame]349 setOperationAction(ISD::FADD, Ty, Legal);
350 setOperationAction(ISD::FDIV, Ty, Legal);
Daniel Sandersa9521602013-10-23 10:36:52 +0000[diff] [blame]351 setOperationAction(ISD::FEXP2, Ty, Legal);
Daniel Sandersf5bd9372013-09-11 10:51:30 +0000[diff] [blame]352 setOperationAction(ISD::FLOG2, Ty, Legal);
Daniel Sandersd7103f32013-10-11 10:14:25 +0000[diff] [blame]353 setOperationAction(ISD::FMA, Ty, Legal);
Daniel Sandersf5bd9372013-09-11 10:51:30 +0000[diff] [blame]354 setOperationAction(ISD::FMUL, Ty, Legal);
355 setOperationAction(ISD::FRINT, Ty, Legal);
356 setOperationAction(ISD::FSQRT, Ty, Legal);
357 setOperationAction(ISD::FSUB, Ty, Legal);
Daniel Sanderse1d24352013-09-24 12:04:44 +0000[diff] [blame]358 setOperationAction(ISD::VSELECT, Ty, Legal);
Daniel Sandersfd538dc2013-09-24 10:46:19 +0000[diff] [blame]359
360 setOperationAction(ISD::SETCC, Ty, Legal);
361 setCondCodeAction(ISD::SETOGE, Ty, Expand);
362 setCondCodeAction(ISD::SETOGT, Ty, Expand);
363 setCondCodeAction(ISD::SETUGE, Ty, Expand);
364 setCondCodeAction(ISD::SETUGT, Ty, Expand);
365 setCondCodeAction(ISD::SETGE, Ty, Expand);
366 setCondCodeAction(ISD::SETGT, Ty, Expand);
Daniel Sandersf5bd9372013-09-11 10:51:30 +0000[diff] [blame]367 }
Jack Carterbabdcc82013-08-15 12:24:57 +0000[diff] [blame]368}
Akira Hatanaka96ca1822013-03-13 00:54:29 +0000[diff] [blame]369
370bool
Matt Arsenault6f2a5262014-07-27 17:46:40 +0000[diff] [blame]371MipsSETargetLowering::allowsMisalignedMemoryAccesses(EVT VT,
372 unsigned,
373 unsigned,
374 bool *Fast) const {
Akira Hatanaka96ca1822013-03-13 00:54:29 +0000[diff] [blame]375 MVT::SimpleValueType SVT = VT.getSimpleVT().SimpleTy;
376
Eric Christopher1c29a652014-07-18 22:55:25 +0000[diff] [blame]377 if (Subtarget.systemSupportsUnalignedAccess()) {
Daniel Sandersac272632014-05-23 13:18:02 +0000[diff] [blame]378 // MIPS32r6/MIPS64r6 is required to support unaligned access. It's
379 // implementation defined whether this is handled by hardware, software, or
380 // a hybrid of the two but it's expected that most implementations will
381 // handle the majority of cases in hardware.
382 if (Fast)
383 *Fast = true;
384 return true;
385 }
386
Akira Hatanaka96ca1822013-03-13 00:54:29 +0000[diff] [blame]387 switch (SVT) {
388 case MVT::i64:
389 case MVT::i32:
390 if (Fast)
391 *Fast = true;
392 return true;
393 default:
394 return false;
395 }
396}
397
Akira Hatanakabe8612f2013-03-30 01:36:35 +0000[diff] [blame]398SDValue MipsSETargetLowering::LowerOperation(SDValue Op,
399 SelectionDAG &DAG) const {
400 switch(Op.getOpcode()) {
Akira Hatanaka63791212013-09-07 00:52:30 +0000[diff] [blame]401 case ISD::LOAD: return lowerLOAD(Op, DAG);
402 case ISD::STORE: return lowerSTORE(Op, DAG);
Akira Hatanakabe8612f2013-03-30 01:36:35 +0000[diff] [blame]403 case ISD::SMUL_LOHI: return lowerMulDiv(Op, MipsISD::Mult, true, true, DAG);
404 case ISD::UMUL_LOHI: return lowerMulDiv(Op, MipsISD::Multu, true, true, DAG);
405 case ISD::MULHS: return lowerMulDiv(Op, MipsISD::Mult, false, true, DAG);
406 case ISD::MULHU: return lowerMulDiv(Op, MipsISD::Multu, false, true, DAG);
407 case ISD::MUL: return lowerMulDiv(Op, MipsISD::Mult, true, false, DAG);
408 case ISD::SDIVREM: return lowerMulDiv(Op, MipsISD::DivRem, true, true, DAG);
Akira Hatanakad8fb0322013-04-22 20:13:37 +0000[diff] [blame]409 case ISD::UDIVREM: return lowerMulDiv(Op, MipsISD::DivRemU, true, true,
410 DAG);
Akira Hatanakaa6bbde52013-04-13 02:13:30 +0000[diff] [blame]411 case ISD::INTRINSIC_WO_CHAIN: return lowerINTRINSIC_WO_CHAIN(Op, DAG);
412 case ISD::INTRINSIC_W_CHAIN: return lowerINTRINSIC_W_CHAIN(Op, DAG);
Daniel Sanderse6ed5b72013-08-28 12:04:29 +0000[diff] [blame]413 case ISD::INTRINSIC_VOID: return lowerINTRINSIC_VOID(Op, DAG);
Daniel Sandersa4c8f3a2013-09-23 14:03:12 +0000[diff] [blame]414 case ISD::EXTRACT_VECTOR_ELT: return lowerEXTRACT_VECTOR_ELT(Op, DAG);
Daniel Sanders7a289d02013-09-23 12:02:46 +0000[diff] [blame]415 case ISD::BUILD_VECTOR: return lowerBUILD_VECTOR(Op, DAG);
Daniel Sanderse5087042013-09-24 14:02:15 +0000[diff] [blame]416 case ISD::VECTOR_SHUFFLE: return lowerVECTOR_SHUFFLE(Op, DAG);
Akira Hatanakabe8612f2013-03-30 01:36:35 +0000[diff] [blame]417 }
418
419 return MipsTargetLowering::LowerOperation(Op, DAG);
420}
421
Akira Hatanaka9efcd762013-03-30 01:42:24 +0000[diff] [blame]422// selectMADD -
423// Transforms a subgraph in CurDAG if the following pattern is found:
424// (addc multLo, Lo0), (adde multHi, Hi0),
425// where,
426// multHi/Lo: product of multiplication
427// Lo0: initial value of Lo register
428// Hi0: initial value of Hi register
429// Return true if pattern matching was successful.
430static bool selectMADD(SDNode *ADDENode, SelectionDAG *CurDAG) {
431 // ADDENode's second operand must be a flag output of an ADDC node in order
432 // for the matching to be successful.
433 SDNode *ADDCNode = ADDENode->getOperand(2).getNode();
434
435 if (ADDCNode->getOpcode() != ISD::ADDC)
436 return false;
437
438 SDValue MultHi = ADDENode->getOperand(0);
439 SDValue MultLo = ADDCNode->getOperand(0);
440 SDNode *MultNode = MultHi.getNode();
441 unsigned MultOpc = MultHi.getOpcode();
442
443 // MultHi and MultLo must be generated by the same node,
444 if (MultLo.getNode() != MultNode)
445 return false;
446
447 // and it must be a multiplication.
448 if (MultOpc != ISD::SMUL_LOHI && MultOpc != ISD::UMUL_LOHI)
449 return false;
450
451 // MultLo amd MultHi must be the first and second output of MultNode
452 // respectively.
453 if (MultHi.getResNo() != 1 || MultLo.getResNo() != 0)
454 return false;
455
456 // Transform this to a MADD only if ADDENode and ADDCNode are the only users
457 // of the values of MultNode, in which case MultNode will be removed in later
458 // phases.
459 // If there exist users other than ADDENode or ADDCNode, this function returns
460 // here, which will result in MultNode being mapped to a single MULT
461 // instruction node rather than a pair of MULT and MADD instructions being
462 // produced.
463 if (!MultHi.hasOneUse() || !MultLo.hasOneUse())
464 return false;
465
Andrew Trickef9de2a2013-05-25 02:42:55 +0000[diff] [blame]466 SDLoc DL(ADDENode);
Akira Hatanaka9efcd762013-03-30 01:42:24 +0000[diff] [blame]467
468 // Initialize accumulator.
Akira Hatanakad98c99f2013-10-15 01:12:50 +0000[diff] [blame]469 SDValue ACCIn = CurDAG->getNode(MipsISD::MTLOHI, DL, MVT::Untyped,
Akira Hatanaka9efcd762013-03-30 01:42:24 +0000[diff] [blame]470 ADDCNode->getOperand(1),
471 ADDENode->getOperand(1));
472
473 // create MipsMAdd(u) node
474 MultOpc = MultOpc == ISD::UMUL_LOHI ? MipsISD::MAddu : MipsISD::MAdd;
475
476 SDValue MAdd = CurDAG->getNode(MultOpc, DL, MVT::Untyped,
477 MultNode->getOperand(0),// Factor 0
478 MultNode->getOperand(1),// Factor 1
479 ACCIn);
480
481 // replace uses of adde and addc here
482 if (!SDValue(ADDCNode, 0).use_empty()) {
Akira Hatanakad98c99f2013-10-15 01:12:50 +0000[diff] [blame]483 SDValue LoOut = CurDAG->getNode(MipsISD::MFLO, DL, MVT::i32, MAdd);
Akira Hatanaka9efcd762013-03-30 01:42:24 +0000[diff] [blame]484 CurDAG->ReplaceAllUsesOfValueWith(SDValue(ADDCNode, 0), LoOut);
485 }
486 if (!SDValue(ADDENode, 0).use_empty()) {
Akira Hatanakad98c99f2013-10-15 01:12:50 +0000[diff] [blame]487 SDValue HiOut = CurDAG->getNode(MipsISD::MFHI, DL, MVT::i32, MAdd);
Akira Hatanaka9efcd762013-03-30 01:42:24 +0000[diff] [blame]488 CurDAG->ReplaceAllUsesOfValueWith(SDValue(ADDENode, 0), HiOut);
489 }
490
491 return true;
492}
493
494// selectMSUB -
495// Transforms a subgraph in CurDAG if the following pattern is found:
496// (addc Lo0, multLo), (sube Hi0, multHi),
497// where,
498// multHi/Lo: product of multiplication
499// Lo0: initial value of Lo register
500// Hi0: initial value of Hi register
501// Return true if pattern matching was successful.
502static bool selectMSUB(SDNode *SUBENode, SelectionDAG *CurDAG) {
503 // SUBENode's second operand must be a flag output of an SUBC node in order
504 // for the matching to be successful.
505 SDNode *SUBCNode = SUBENode->getOperand(2).getNode();
506
507 if (SUBCNode->getOpcode() != ISD::SUBC)
508 return false;
509
510 SDValue MultHi = SUBENode->getOperand(1);
511 SDValue MultLo = SUBCNode->getOperand(1);
512 SDNode *MultNode = MultHi.getNode();
513 unsigned MultOpc = MultHi.getOpcode();
514
515 // MultHi and MultLo must be generated by the same node,
516 if (MultLo.getNode() != MultNode)
517 return false;
518
519 // and it must be a multiplication.
520 if (MultOpc != ISD::SMUL_LOHI && MultOpc != ISD::UMUL_LOHI)
521 return false;
522
523 // MultLo amd MultHi must be the first and second output of MultNode
524 // respectively.
525 if (MultHi.getResNo() != 1 || MultLo.getResNo() != 0)
526 return false;
527
528 // Transform this to a MSUB only if SUBENode and SUBCNode are the only users
529 // of the values of MultNode, in which case MultNode will be removed in later
530 // phases.
531 // If there exist users other than SUBENode or SUBCNode, this function returns
532 // here, which will result in MultNode being mapped to a single MULT
533 // instruction node rather than a pair of MULT and MSUB instructions being
534 // produced.
535 if (!MultHi.hasOneUse() || !MultLo.hasOneUse())
536 return false;
537
Andrew Trickef9de2a2013-05-25 02:42:55 +0000[diff] [blame]538 SDLoc DL(SUBENode);
Akira Hatanaka9efcd762013-03-30 01:42:24 +0000[diff] [blame]539
540 // Initialize accumulator.
Akira Hatanakad98c99f2013-10-15 01:12:50 +0000[diff] [blame]541 SDValue ACCIn = CurDAG->getNode(MipsISD::MTLOHI, DL, MVT::Untyped,
Akira Hatanaka9efcd762013-03-30 01:42:24 +0000[diff] [blame]542 SUBCNode->getOperand(0),
543 SUBENode->getOperand(0));
544
545 // create MipsSub(u) node
546 MultOpc = MultOpc == ISD::UMUL_LOHI ? MipsISD::MSubu : MipsISD::MSub;
547
548 SDValue MSub = CurDAG->getNode(MultOpc, DL, MVT::Glue,
549 MultNode->getOperand(0),// Factor 0
550 MultNode->getOperand(1),// Factor 1
551 ACCIn);
552
553 // replace uses of sube and subc here
554 if (!SDValue(SUBCNode, 0).use_empty()) {
Akira Hatanakad98c99f2013-10-15 01:12:50 +0000[diff] [blame]555 SDValue LoOut = CurDAG->getNode(MipsISD::MFLO, DL, MVT::i32, MSub);
Akira Hatanaka9efcd762013-03-30 01:42:24 +0000[diff] [blame]556 CurDAG->ReplaceAllUsesOfValueWith(SDValue(SUBCNode, 0), LoOut);
557 }
558 if (!SDValue(SUBENode, 0).use_empty()) {
Akira Hatanakad98c99f2013-10-15 01:12:50 +0000[diff] [blame]559 SDValue HiOut = CurDAG->getNode(MipsISD::MFHI, DL, MVT::i32, MSub);
Akira Hatanaka9efcd762013-03-30 01:42:24 +0000[diff] [blame]560 CurDAG->ReplaceAllUsesOfValueWith(SDValue(SUBENode, 0), HiOut);
561 }
562
563 return true;
564}
565
566static SDValue performADDECombine(SDNode *N, SelectionDAG &DAG,
567 TargetLowering::DAGCombinerInfo &DCI,
Eric Christopher1c29a652014-07-18 22:55:25 +0000[diff] [blame]568 const MipsSubtarget &Subtarget) {
Akira Hatanaka9efcd762013-03-30 01:42:24 +0000[diff] [blame]569 if (DCI.isBeforeLegalize())
570 return SDValue();
571
Eric Christopher1c29a652014-07-18 22:55:25 +0000[diff] [blame]572 if (Subtarget.hasMips32() && !Subtarget.hasMips32r6() &&
Daniel Sanders826f8b32014-06-12 10:54:16 +0000[diff] [blame]573 N->getValueType(0) == MVT::i32 && selectMADD(N, &DAG))
Akira Hatanaka9efcd762013-03-30 01:42:24 +0000[diff] [blame]574 return SDValue(N, 0);
575
576 return SDValue();
577}
578
Daniel Sandersa4c8f3a2013-09-23 14:03:12 +0000[diff] [blame]579// Fold zero extensions into MipsISD::VEXTRACT_[SZ]EXT_ELT
580//
581// Performs the following transformations:
582// - Changes MipsISD::VEXTRACT_[SZ]EXT_ELT to zero extension if its
583// sign/zero-extension is completely overwritten by the new one performed by
584// the ISD::AND.
585// - Removes redundant zero extensions performed by an ISD::AND.
586static SDValue performANDCombine(SDNode *N, SelectionDAG &DAG,
587 TargetLowering::DAGCombinerInfo &DCI,
Eric Christopher1c29a652014-07-18 22:55:25 +0000[diff] [blame]588 const MipsSubtarget &Subtarget) {
589 if (!Subtarget.hasMSA())
Daniel Sandersa4c8f3a2013-09-23 14:03:12 +0000[diff] [blame]590 return SDValue();
591
592 SDValue Op0 = N->getOperand(0);
593 SDValue Op1 = N->getOperand(1);
594 unsigned Op0Opcode = Op0->getOpcode();
595
596 // (and (MipsVExtract[SZ]Ext $a, $b, $c), imm:$d)
597 // where $d + 1 == 2^n and n == 32
598 // or $d + 1 == 2^n and n <= 32 and ZExt
599 // -> (MipsVExtractZExt $a, $b, $c)
600 if (Op0Opcode == MipsISD::VEXTRACT_SEXT_ELT ||
601 Op0Opcode == MipsISD::VEXTRACT_ZEXT_ELT) {
602 ConstantSDNode *Mask = dyn_cast<ConstantSDNode>(Op1);
603
604 if (!Mask)
605 return SDValue();
606
607 int32_t Log2IfPositive = (Mask->getAPIntValue() + 1).exactLogBase2();
608
609 if (Log2IfPositive <= 0)
610 return SDValue(); // Mask+1 is not a power of 2
611
612 SDValue Op0Op2 = Op0->getOperand(2);
613 EVT ExtendTy = cast<VTSDNode>(Op0Op2)->getVT();
614 unsigned ExtendTySize = ExtendTy.getSizeInBits();
615 unsigned Log2 = Log2IfPositive;
616
617 if ((Op0Opcode == MipsISD::VEXTRACT_ZEXT_ELT && Log2 >= ExtendTySize) ||
618 Log2 == ExtendTySize) {
619 SDValue Ops[] = { Op0->getOperand(0), Op0->getOperand(1), Op0Op2 };
Chandler Carruth356665a2014-08-01 22:09:43 +0000[diff] [blame]620 return DAG.getNode(MipsISD::VEXTRACT_ZEXT_ELT, SDLoc(Op0),
621 Op0->getVTList(),
622 makeArrayRef(Ops, Op0->getNumOperands()));
Daniel Sandersa4c8f3a2013-09-23 14:03:12 +0000[diff] [blame]623 }
624 }
625
626 return SDValue();
627}
628
Daniel Sanders53fe6c42013-10-30 13:51:01 +0000[diff] [blame]629// Determine if the specified node is a constant vector splat.
630//
631// Returns true and sets Imm if:
632// * N is a ISD::BUILD_VECTOR representing a constant splat
633//
634// This function is quite similar to MipsSEDAGToDAGISel::selectVSplat. The
635// differences are that it assumes the MSA has already been checked and the
636// arbitrary requirement for a maximum of 32-bit integers isn't applied (and
637// must not be in order for binsri.d to be selectable).
638static bool isVSplat(SDValue N, APInt &Imm, bool IsLittleEndian) {
639 BuildVectorSDNode *Node = dyn_cast<BuildVectorSDNode>(N.getNode());
640
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]641 if (!Node)
Daniel Sanders53fe6c42013-10-30 13:51:01 +0000[diff] [blame]642 return false;
643
644 APInt SplatValue, SplatUndef;
645 unsigned SplatBitSize;
646 bool HasAnyUndefs;
647
648 if (!Node->isConstantSplat(SplatValue, SplatUndef, SplatBitSize, HasAnyUndefs,
649 8, !IsLittleEndian))
650 return false;
651
652 Imm = SplatValue;
653
654 return true;
655}
656
Daniel Sandersab94b532013-10-30 15:20:38 +0000[diff] [blame]657// Test whether the given node is an all-ones build_vector.
658static bool isVectorAllOnes(SDValue N) {
659 // Look through bitcasts. Endianness doesn't matter because we are looking
660 // for an all-ones value.
661 if (N->getOpcode() == ISD::BITCAST)
662 N = N->getOperand(0);
663
664 BuildVectorSDNode *BVN = dyn_cast<BuildVectorSDNode>(N);
665
666 if (!BVN)
667 return false;
668
669 APInt SplatValue, SplatUndef;
670 unsigned SplatBitSize;
671 bool HasAnyUndefs;
672
673 // Endianness doesn't matter in this context because we are looking for
674 // an all-ones value.
675 if (BVN->isConstantSplat(SplatValue, SplatUndef, SplatBitSize, HasAnyUndefs))
676 return SplatValue.isAllOnesValue();
677
678 return false;
679}
680
681// Test whether N is the bitwise inverse of OfNode.
682static bool isBitwiseInverse(SDValue N, SDValue OfNode) {
683 if (N->getOpcode() != ISD::XOR)
684 return false;
685
686 if (isVectorAllOnes(N->getOperand(0)))
687 return N->getOperand(1) == OfNode;
688
689 if (isVectorAllOnes(N->getOperand(1)))
690 return N->getOperand(0) == OfNode;
691
692 return false;
693}
694
Daniel Sanders53fe6c42013-10-30 13:51:01 +0000[diff] [blame]695// Perform combines where ISD::OR is the root node.
696//
697// Performs the following transformations:
698// - (or (and $a, $mask), (and $b, $inv_mask)) => (vselect $mask, $a, $b)
699// where $inv_mask is the bitwise inverse of $mask and the 'or' has a 128-bit
700// vector type.
701static SDValue performORCombine(SDNode *N, SelectionDAG &DAG,
702 TargetLowering::DAGCombinerInfo &DCI,
Eric Christopher1c29a652014-07-18 22:55:25 +0000[diff] [blame]703 const MipsSubtarget &Subtarget) {
704 if (!Subtarget.hasMSA())
Daniel Sanders53fe6c42013-10-30 13:51:01 +0000[diff] [blame]705 return SDValue();
706
707 EVT Ty = N->getValueType(0);
708
709 if (!Ty.is128BitVector())
710 return SDValue();
711
712 SDValue Op0 = N->getOperand(0);
713 SDValue Op1 = N->getOperand(1);
714
715 if (Op0->getOpcode() == ISD::AND && Op1->getOpcode() == ISD::AND) {
716 SDValue Op0Op0 = Op0->getOperand(0);
717 SDValue Op0Op1 = Op0->getOperand(1);
718 SDValue Op1Op0 = Op1->getOperand(0);
719 SDValue Op1Op1 = Op1->getOperand(1);
Eric Christopher1c29a652014-07-18 22:55:25 +0000[diff] [blame]720 bool IsLittleEndian = !Subtarget.isLittle();
Daniel Sanders53fe6c42013-10-30 13:51:01 +0000[diff] [blame]721
722 SDValue IfSet, IfClr, Cond;
Daniel Sandersab94b532013-10-30 15:20:38 +0000[diff] [blame]723 bool IsConstantMask = false;
Daniel Sanders53fe6c42013-10-30 13:51:01 +0000[diff] [blame]724 APInt Mask, InvMask;
725
726 // If Op0Op0 is an appropriate mask, try to find it's inverse in either
727 // Op1Op0, or Op1Op1. Keep track of the Cond, IfSet, and IfClr nodes, while
728 // looking.
729 // IfClr will be set if we find a valid match.
730 if (isVSplat(Op0Op0, Mask, IsLittleEndian)) {
731 Cond = Op0Op0;
732 IfSet = Op0Op1;
733
Daniel Sandersc8c50fb2013-11-21 16:11:31 +0000[diff] [blame]734 if (isVSplat(Op1Op0, InvMask, IsLittleEndian) &&
735 Mask.getBitWidth() == InvMask.getBitWidth() && Mask == ~InvMask)
Daniel Sanders53fe6c42013-10-30 13:51:01 +0000[diff] [blame]736 IfClr = Op1Op1;
Daniel Sandersc8c50fb2013-11-21 16:11:31 +0000[diff] [blame]737 else if (isVSplat(Op1Op1, InvMask, IsLittleEndian) &&
738 Mask.getBitWidth() == InvMask.getBitWidth() && Mask == ~InvMask)
Daniel Sanders53fe6c42013-10-30 13:51:01 +0000[diff] [blame]739 IfClr = Op1Op0;
Daniel Sandersab94b532013-10-30 15:20:38 +0000[diff] [blame]740
741 IsConstantMask = true;
Daniel Sanders53fe6c42013-10-30 13:51:01 +0000[diff] [blame]742 }
743
744 // If IfClr is not yet set, and Op0Op1 is an appropriate mask, try the same
745 // thing again using this mask.
746 // IfClr will be set if we find a valid match.
747 if (!IfClr.getNode() && isVSplat(Op0Op1, Mask, IsLittleEndian)) {
748 Cond = Op0Op1;
749 IfSet = Op0Op0;
750
Daniel Sandersc8c50fb2013-11-21 16:11:31 +0000[diff] [blame]751 if (isVSplat(Op1Op0, InvMask, IsLittleEndian) &&
752 Mask.getBitWidth() == InvMask.getBitWidth() && Mask == ~InvMask)
Daniel Sanders53fe6c42013-10-30 13:51:01 +0000[diff] [blame]753 IfClr = Op1Op1;
Daniel Sandersc8c50fb2013-11-21 16:11:31 +0000[diff] [blame]754 else if (isVSplat(Op1Op1, InvMask, IsLittleEndian) &&
755 Mask.getBitWidth() == InvMask.getBitWidth() && Mask == ~InvMask)
Daniel Sanders53fe6c42013-10-30 13:51:01 +0000[diff] [blame]756 IfClr = Op1Op0;
Daniel Sandersab94b532013-10-30 15:20:38 +0000[diff] [blame]757
758 IsConstantMask = true;
759 }
760
761 // If IfClr is not yet set, try looking for a non-constant match.
762 // IfClr will be set if we find a valid match amongst the eight
763 // possibilities.
764 if (!IfClr.getNode()) {
765 if (isBitwiseInverse(Op0Op0, Op1Op0)) {
766 Cond = Op1Op0;
767 IfSet = Op1Op1;
768 IfClr = Op0Op1;
769 } else if (isBitwiseInverse(Op0Op1, Op1Op0)) {
770 Cond = Op1Op0;
771 IfSet = Op1Op1;
772 IfClr = Op0Op0;
773 } else if (isBitwiseInverse(Op0Op0, Op1Op1)) {
774 Cond = Op1Op1;
775 IfSet = Op1Op0;
776 IfClr = Op0Op1;
777 } else if (isBitwiseInverse(Op0Op1, Op1Op1)) {
778 Cond = Op1Op1;
779 IfSet = Op1Op0;
780 IfClr = Op0Op0;
781 } else if (isBitwiseInverse(Op1Op0, Op0Op0)) {
782 Cond = Op0Op0;
783 IfSet = Op0Op1;
784 IfClr = Op1Op1;
785 } else if (isBitwiseInverse(Op1Op1, Op0Op0)) {
786 Cond = Op0Op0;
787 IfSet = Op0Op1;
788 IfClr = Op1Op0;
789 } else if (isBitwiseInverse(Op1Op0, Op0Op1)) {
790 Cond = Op0Op1;
791 IfSet = Op0Op0;
792 IfClr = Op1Op1;
793 } else if (isBitwiseInverse(Op1Op1, Op0Op1)) {
794 Cond = Op0Op1;
795 IfSet = Op0Op0;
796 IfClr = Op1Op0;
797 }
Daniel Sanders53fe6c42013-10-30 13:51:01 +0000[diff] [blame]798 }
799
800 // At this point, IfClr will be set if we have a valid match.
801 if (!IfClr.getNode())
802 return SDValue();
803
804 assert(Cond.getNode() && IfSet.getNode());
805
806 // Fold degenerate cases.
Daniel Sandersab94b532013-10-30 15:20:38 +0000[diff] [blame]807 if (IsConstantMask) {
808 if (Mask.isAllOnesValue())
809 return IfSet;
810 else if (Mask == 0)
811 return IfClr;
812 }
Daniel Sanders53fe6c42013-10-30 13:51:01 +0000[diff] [blame]813
814 // Transform the DAG into an equivalent VSELECT.
Daniel Sandersdf2215452014-03-12 11:54:00 +0000[diff] [blame]815 return DAG.getNode(ISD::VSELECT, SDLoc(N), Ty, Cond, IfSet, IfClr);
Daniel Sanders53fe6c42013-10-30 13:51:01 +0000[diff] [blame]816 }
817
818 return SDValue();
819}
820
Akira Hatanaka9efcd762013-03-30 01:42:24 +0000[diff] [blame]821static SDValue performSUBECombine(SDNode *N, SelectionDAG &DAG,
822 TargetLowering::DAGCombinerInfo &DCI,
Eric Christopher1c29a652014-07-18 22:55:25 +0000[diff] [blame]823 const MipsSubtarget &Subtarget) {
Akira Hatanaka9efcd762013-03-30 01:42:24 +0000[diff] [blame]824 if (DCI.isBeforeLegalize())
825 return SDValue();
826
Eric Christopher1c29a652014-07-18 22:55:25 +0000[diff] [blame]827 if (Subtarget.hasMips32() && N->getValueType(0) == MVT::i32 &&
Akira Hatanaka9efcd762013-03-30 01:42:24 +0000[diff] [blame]828 selectMSUB(N, &DAG))
829 return SDValue(N, 0);
830
831 return SDValue();
832}
833
Benjamin Kramerbdc49562016-06-12 15:39:02 +0000[diff] [blame]834static SDValue genConstMult(SDValue X, uint64_t C, const SDLoc &DL, EVT VT,
Akira Hatanaka5832fc62013-06-26 18:48:17 +0000[diff] [blame]835 EVT ShiftTy, SelectionDAG &DAG) {
836 // Clear the upper (64 - VT.sizeInBits) bits.
837 C &= ((uint64_t)-1) >> (64 - VT.getSizeInBits());
838
839 // Return 0.
840 if (C == 0)
Sergey Dmitrouk842a51b2015-04-28 14:05:47 +0000[diff] [blame]841 return DAG.getConstant(0, DL, VT);
Akira Hatanaka5832fc62013-06-26 18:48:17 +0000[diff] [blame]842
843 // Return x.
844 if (C == 1)
845 return X;
846
847 // If c is power of 2, return (shl x, log2(c)).
848 if (isPowerOf2_64(C))
849 return DAG.getNode(ISD::SHL, DL, VT, X,
Sergey Dmitrouk842a51b2015-04-28 14:05:47 +0000[diff] [blame]850 DAG.getConstant(Log2_64(C), DL, ShiftTy));
Akira Hatanaka5832fc62013-06-26 18:48:17 +0000[diff] [blame]851
852 unsigned Log2Ceil = Log2_64_Ceil(C);
853 uint64_t Floor = 1LL << Log2_64(C);
854 uint64_t Ceil = Log2Ceil == 64 ? 0LL : 1LL << Log2Ceil;
855
856 // If |c - floor_c| <= |c - ceil_c|,
857 // where floor_c = pow(2, floor(log2(c))) and ceil_c = pow(2, ceil(log2(c))),
858 // return (add constMult(x, floor_c), constMult(x, c - floor_c)).
859 if (C - Floor <= Ceil - C) {
860 SDValue Op0 = genConstMult(X, Floor, DL, VT, ShiftTy, DAG);
861 SDValue Op1 = genConstMult(X, C - Floor, DL, VT, ShiftTy, DAG);
862 return DAG.getNode(ISD::ADD, DL, VT, Op0, Op1);
863 }
864
865 // If |c - floor_c| > |c - ceil_c|,
866 // return (sub constMult(x, ceil_c), constMult(x, ceil_c - c)).
867 SDValue Op0 = genConstMult(X, Ceil, DL, VT, ShiftTy, DAG);
868 SDValue Op1 = genConstMult(X, Ceil - C, DL, VT, ShiftTy, DAG);
869 return DAG.getNode(ISD::SUB, DL, VT, Op0, Op1);
870}
871
872static SDValue performMULCombine(SDNode *N, SelectionDAG &DAG,
873 const TargetLowering::DAGCombinerInfo &DCI,
874 const MipsSETargetLowering *TL) {
875 EVT VT = N->getValueType(0);
876
877 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1)))
878 if (!VT.isVector())
Mehdi Amini9639d652015-07-09 02:09:20 +0000[diff] [blame]879 return genConstMult(N->getOperand(0), C->getZExtValue(), SDLoc(N), VT,
Mehdi Aminieaabc512015-07-09 15:12:23 +0000[diff] [blame]880 TL->getScalarShiftAmountTy(DAG.getDataLayout(), VT),
881 DAG);
Akira Hatanaka5832fc62013-06-26 18:48:17 +0000[diff] [blame]882
883 return SDValue(N, 0);
884}
885
Akira Hatanaka1ebb2a12013-04-19 23:21:32 +0000[diff] [blame]886static SDValue performDSPShiftCombine(unsigned Opc, SDNode *N, EVT Ty,
887 SelectionDAG &DAG,
Eric Christopher1c29a652014-07-18 22:55:25 +0000[diff] [blame]888 const MipsSubtarget &Subtarget) {
Akira Hatanaka1ebb2a12013-04-19 23:21:32 +0000[diff] [blame]889 // See if this is a vector splat immediate node.
890 APInt SplatValue, SplatUndef;
891 unsigned SplatBitSize;
892 bool HasAnyUndefs;
Sanjay Patel1ed771f2016-09-14 16:37:15 +0000[diff] [blame]893 unsigned EltSize = Ty.getScalarSizeInBits();
Akira Hatanaka1ebb2a12013-04-19 23:21:32 +0000[diff] [blame]894 BuildVectorSDNode *BV = dyn_cast<BuildVectorSDNode>(N->getOperand(1));
895
Eric Christopher1c29a652014-07-18 22:55:25 +0000[diff] [blame]896 if (!Subtarget.hasDSP())
Daniel Sanders6e664bc2013-11-21 11:40:14 +0000[diff] [blame]897 return SDValue();
898
Akira Hatanaka0d6964c2013-04-22 19:58:23 +0000[diff] [blame]899 if (!BV ||
Akira Hatanakad8fb0322013-04-22 20:13:37 +0000[diff] [blame]900 !BV->isConstantSplat(SplatValue, SplatUndef, SplatBitSize, HasAnyUndefs,
Eric Christopher1c29a652014-07-18 22:55:25 +0000[diff] [blame]901 EltSize, !Subtarget.isLittle()) ||
Akira Hatanaka0d6964c2013-04-22 19:58:23 +0000[diff] [blame]902 (SplatBitSize != EltSize) ||
Akira Hatanakae9d0b312013-04-23 18:09:42 +0000[diff] [blame]903 (SplatValue.getZExtValue() >= EltSize))
Akira Hatanaka1ebb2a12013-04-19 23:21:32 +0000[diff] [blame]904 return SDValue();
905
Sergey Dmitrouk842a51b2015-04-28 14:05:47 +0000[diff] [blame]906 SDLoc DL(N);
907 return DAG.getNode(Opc, DL, Ty, N->getOperand(0),
908 DAG.getConstant(SplatValue.getZExtValue(), DL, MVT::i32));
Akira Hatanaka1ebb2a12013-04-19 23:21:32 +0000[diff] [blame]909}
910
911static SDValue performSHLCombine(SDNode *N, SelectionDAG &DAG,
912 TargetLowering::DAGCombinerInfo &DCI,
Eric Christopher1c29a652014-07-18 22:55:25 +0000[diff] [blame]913 const MipsSubtarget &Subtarget) {
Akira Hatanaka1ebb2a12013-04-19 23:21:32 +0000[diff] [blame]914 EVT Ty = N->getValueType(0);
915
916 if ((Ty != MVT::v2i16) && (Ty != MVT::v4i8))
917 return SDValue();
918
919 return performDSPShiftCombine(MipsISD::SHLL_DSP, N, Ty, DAG, Subtarget);
920}
921
Daniel Sandersa4c8f3a2013-09-23 14:03:12 +0000[diff] [blame]922// Fold sign-extensions into MipsISD::VEXTRACT_[SZ]EXT_ELT for MSA and fold
923// constant splats into MipsISD::SHRA_DSP for DSPr2.
924//
925// Performs the following transformations:
926// - Changes MipsISD::VEXTRACT_[SZ]EXT_ELT to sign extension if its
927// sign/zero-extension is completely overwritten by the new one performed by
928// the ISD::SRA and ISD::SHL nodes.
929// - Removes redundant sign extensions performed by an ISD::SRA and ISD::SHL
930// sequence.
931//
932// See performDSPShiftCombine for more information about the transformation
933// used for DSPr2.
Akira Hatanaka1ebb2a12013-04-19 23:21:32 +0000[diff] [blame]934static SDValue performSRACombine(SDNode *N, SelectionDAG &DAG,
935 TargetLowering::DAGCombinerInfo &DCI,
Eric Christopher1c29a652014-07-18 22:55:25 +0000[diff] [blame]936 const MipsSubtarget &Subtarget) {
Akira Hatanaka1ebb2a12013-04-19 23:21:32 +0000[diff] [blame]937 EVT Ty = N->getValueType(0);
938
Eric Christopher1c29a652014-07-18 22:55:25 +0000[diff] [blame]939 if (Subtarget.hasMSA()) {
Daniel Sandersa4c8f3a2013-09-23 14:03:12 +0000[diff] [blame]940 SDValue Op0 = N->getOperand(0);
941 SDValue Op1 = N->getOperand(1);
942
943 // (sra (shl (MipsVExtract[SZ]Ext $a, $b, $c), imm:$d), imm:$d)
944 // where $d + sizeof($c) == 32
945 // or $d + sizeof($c) <= 32 and SExt
946 // -> (MipsVExtractSExt $a, $b, $c)
947 if (Op0->getOpcode() == ISD::SHL && Op1 == Op0->getOperand(1)) {
948 SDValue Op0Op0 = Op0->getOperand(0);
949 ConstantSDNode *ShAmount = dyn_cast<ConstantSDNode>(Op1);
950
951 if (!ShAmount)
952 return SDValue();
953
Daniel Sandersf4f1a872013-09-27 09:25:29 +0000[diff] [blame]954 if (Op0Op0->getOpcode() != MipsISD::VEXTRACT_SEXT_ELT &&
955 Op0Op0->getOpcode() != MipsISD::VEXTRACT_ZEXT_ELT)
956 return SDValue();
957
Daniel Sandersa4c8f3a2013-09-23 14:03:12 +0000[diff] [blame]958 EVT ExtendTy = cast<VTSDNode>(Op0Op0->getOperand(2))->getVT();
959 unsigned TotalBits = ShAmount->getZExtValue() + ExtendTy.getSizeInBits();
960
961 if (TotalBits == 32 ||
962 (Op0Op0->getOpcode() == MipsISD::VEXTRACT_SEXT_ELT &&
963 TotalBits <= 32)) {
964 SDValue Ops[] = { Op0Op0->getOperand(0), Op0Op0->getOperand(1),
965 Op0Op0->getOperand(2) };
Chandler Carruth356665a2014-08-01 22:09:43 +0000[diff] [blame]966 return DAG.getNode(MipsISD::VEXTRACT_SEXT_ELT, SDLoc(Op0Op0),
967 Op0Op0->getVTList(),
968 makeArrayRef(Ops, Op0Op0->getNumOperands()));
Daniel Sandersa4c8f3a2013-09-23 14:03:12 +0000[diff] [blame]969 }
970 }
971 }
972
Eric Christopher1c29a652014-07-18 22:55:25 +0000[diff] [blame]973 if ((Ty != MVT::v2i16) && ((Ty != MVT::v4i8) || !Subtarget.hasDSPR2()))
Akira Hatanaka1ebb2a12013-04-19 23:21:32 +0000[diff] [blame]974 return SDValue();
975
976 return performDSPShiftCombine(MipsISD::SHRA_DSP, N, Ty, DAG, Subtarget);
977}
978
979
980static SDValue performSRLCombine(SDNode *N, SelectionDAG &DAG,
981 TargetLowering::DAGCombinerInfo &DCI,
Eric Christopher1c29a652014-07-18 22:55:25 +0000[diff] [blame]982 const MipsSubtarget &Subtarget) {
Akira Hatanaka1ebb2a12013-04-19 23:21:32 +0000[diff] [blame]983 EVT Ty = N->getValueType(0);
984
Eric Christopher1c29a652014-07-18 22:55:25 +0000[diff] [blame]985 if (((Ty != MVT::v2i16) || !Subtarget.hasDSPR2()) && (Ty != MVT::v4i8))
Akira Hatanaka1ebb2a12013-04-19 23:21:32 +0000[diff] [blame]986 return SDValue();
987
988 return performDSPShiftCombine(MipsISD::SHRL_DSP, N, Ty, DAG, Subtarget);
989}
990
Akira Hatanaka68741cc2013-04-30 22:37:26 +0000[diff] [blame]991static bool isLegalDSPCondCode(EVT Ty, ISD::CondCode CC) {
992 bool IsV216 = (Ty == MVT::v2i16);
993
994 switch (CC) {
995 case ISD::SETEQ:
996 case ISD::SETNE: return true;
997 case ISD::SETLT:
998 case ISD::SETLE:
999 case ISD::SETGT:
1000 case ISD::SETGE: return IsV216;
1001 case ISD::SETULT:
1002 case ISD::SETULE:
1003 case ISD::SETUGT:
1004 case ISD::SETUGE: return !IsV216;
1005 default: return false;
1006 }
1007}
1008
1009static SDValue performSETCCCombine(SDNode *N, SelectionDAG &DAG) {
1010 EVT Ty = N->getValueType(0);
1011
1012 if ((Ty != MVT::v2i16) && (Ty != MVT::v4i8))
1013 return SDValue();
1014
1015 if (!isLegalDSPCondCode(Ty, cast<CondCodeSDNode>(N->getOperand(2))->get()))
1016 return SDValue();
1017
Andrew Trickef9de2a2013-05-25 02:42:55 +0000[diff] [blame]1018 return DAG.getNode(MipsISD::SETCC_DSP, SDLoc(N), Ty, N->getOperand(0),
Akira Hatanaka68741cc2013-04-30 22:37:26 +0000[diff] [blame]1019 N->getOperand(1), N->getOperand(2));
1020}
1021
1022static SDValue performVSELECTCombine(SDNode *N, SelectionDAG &DAG) {
1023 EVT Ty = N->getValueType(0);
1024
Daniel Sanders3ce56622013-09-24 12:18:31 +0000[diff] [blame]1025 if (Ty.is128BitVector() && Ty.isInteger()) {
1026 // Try the following combines:
1027 // (vselect (setcc $a, $b, SETLT), $b, $a)) -> (vsmax $a, $b)
1028 // (vselect (setcc $a, $b, SETLE), $b, $a)) -> (vsmax $a, $b)
1029 // (vselect (setcc $a, $b, SETLT), $a, $b)) -> (vsmin $a, $b)
1030 // (vselect (setcc $a, $b, SETLE), $a, $b)) -> (vsmin $a, $b)
1031 // (vselect (setcc $a, $b, SETULT), $b, $a)) -> (vumax $a, $b)
1032 // (vselect (setcc $a, $b, SETULE), $b, $a)) -> (vumax $a, $b)
1033 // (vselect (setcc $a, $b, SETULT), $a, $b)) -> (vumin $a, $b)
1034 // (vselect (setcc $a, $b, SETULE), $a, $b)) -> (vumin $a, $b)
1035 // SETGT/SETGE/SETUGT/SETUGE variants of these will show up initially but
1036 // will be expanded to equivalent SETLT/SETLE/SETULT/SETULE versions by the
1037 // legalizer.
1038 SDValue Op0 = N->getOperand(0);
Akira Hatanaka68741cc2013-04-30 22:37:26 +0000[diff] [blame]1039
Daniel Sanders3ce56622013-09-24 12:18:31 +0000[diff] [blame]1040 if (Op0->getOpcode() != ISD::SETCC)
1041 return SDValue();
Akira Hatanaka68741cc2013-04-30 22:37:26 +0000[diff] [blame]1042
Daniel Sanders3ce56622013-09-24 12:18:31 +0000[diff] [blame]1043 ISD::CondCode CondCode = cast<CondCodeSDNode>(Op0->getOperand(2))->get();
1044 bool Signed;
Akira Hatanaka68741cc2013-04-30 22:37:26 +0000[diff] [blame]1045
Daniel Sanders3ce56622013-09-24 12:18:31 +0000[diff] [blame]1046 if (CondCode == ISD::SETLT || CondCode == ISD::SETLE)
1047 Signed = true;
1048 else if (CondCode == ISD::SETULT || CondCode == ISD::SETULE)
1049 Signed = false;
1050 else
1051 return SDValue();
1052
1053 SDValue Op1 = N->getOperand(1);
1054 SDValue Op2 = N->getOperand(2);
1055 SDValue Op0Op0 = Op0->getOperand(0);
1056 SDValue Op0Op1 = Op0->getOperand(1);
1057
1058 if (Op1 == Op0Op0 && Op2 == Op0Op1)
1059 return DAG.getNode(Signed ? MipsISD::VSMIN : MipsISD::VUMIN, SDLoc(N),
1060 Ty, Op1, Op2);
1061 else if (Op1 == Op0Op1 && Op2 == Op0Op0)
1062 return DAG.getNode(Signed ? MipsISD::VSMAX : MipsISD::VUMAX, SDLoc(N),
1063 Ty, Op1, Op2);
1064 } else if ((Ty == MVT::v2i16) || (Ty == MVT::v4i8)) {
1065 SDValue SetCC = N->getOperand(0);
1066
1067 if (SetCC.getOpcode() != MipsISD::SETCC_DSP)
1068 return SDValue();
1069
1070 return DAG.getNode(MipsISD::SELECT_CC_DSP, SDLoc(N), Ty,
1071 SetCC.getOperand(0), SetCC.getOperand(1),
1072 N->getOperand(1), N->getOperand(2), SetCC.getOperand(2));
1073 }
1074
1075 return SDValue();
Akira Hatanaka68741cc2013-04-30 22:37:26 +0000[diff] [blame]1076}
1077
Daniel Sandersf7456c72013-09-23 13:22:24 +0000[diff] [blame]1078static SDValue performXORCombine(SDNode *N, SelectionDAG &DAG,
Eric Christopher1c29a652014-07-18 22:55:25 +0000[diff] [blame]1079 const MipsSubtarget &Subtarget) {
Daniel Sandersf7456c72013-09-23 13:22:24 +0000[diff] [blame]1080 EVT Ty = N->getValueType(0);
1081
Eric Christopher1c29a652014-07-18 22:55:25 +0000[diff] [blame]1082 if (Subtarget.hasMSA() && Ty.is128BitVector() && Ty.isInteger()) {
Daniel Sandersf7456c72013-09-23 13:22:24 +0000[diff] [blame]1083 // Try the following combines:
1084 // (xor (or $a, $b), (build_vector allones))
1085 // (xor (or $a, $b), (bitcast (build_vector allones)))
1086 SDValue Op0 = N->getOperand(0);
1087 SDValue Op1 = N->getOperand(1);
1088 SDValue NotOp;
Daniel Sandersf7456c72013-09-23 13:22:24 +0000[diff] [blame]1089
1090 if (ISD::isBuildVectorAllOnes(Op0.getNode()))
1091 NotOp = Op1;
1092 else if (ISD::isBuildVectorAllOnes(Op1.getNode()))
1093 NotOp = Op0;
Daniel Sandersf7456c72013-09-23 13:22:24 +0000[diff] [blame]1094 else
1095 return SDValue();
1096
1097 if (NotOp->getOpcode() == ISD::OR)
1098 return DAG.getNode(MipsISD::VNOR, SDLoc(N), Ty, NotOp->getOperand(0),
1099 NotOp->getOperand(1));
1100 }
1101
1102 return SDValue();
1103}
1104
Akira Hatanaka9efcd762013-03-30 01:42:24 +0000[diff] [blame]1105SDValue
1106MipsSETargetLowering::PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const {
1107 SelectionDAG &DAG = DCI.DAG;
Akira Hatanaka68741cc2013-04-30 22:37:26 +0000[diff] [blame]1108 SDValue Val;
Akira Hatanaka9efcd762013-03-30 01:42:24 +0000[diff] [blame]1109
1110 switch (N->getOpcode()) {
1111 case ISD::ADDE:
1112 return performADDECombine(N, DAG, DCI, Subtarget);
Daniel Sandersa4c8f3a2013-09-23 14:03:12 +0000[diff] [blame]1113 case ISD::AND:
1114 Val = performANDCombine(N, DAG, DCI, Subtarget);
1115 break;
Daniel Sanders53fe6c42013-10-30 13:51:01 +0000[diff] [blame]1116 case ISD::OR:
1117 Val = performORCombine(N, DAG, DCI, Subtarget);
1118 break;
Akira Hatanaka9efcd762013-03-30 01:42:24 +0000[diff] [blame]1119 case ISD::SUBE:
1120 return performSUBECombine(N, DAG, DCI, Subtarget);
Akira Hatanaka5832fc62013-06-26 18:48:17 +0000[diff] [blame]1121 case ISD::MUL:
1122 return performMULCombine(N, DAG, DCI, this);
Akira Hatanaka1ebb2a12013-04-19 23:21:32 +0000[diff] [blame]1123 case ISD::SHL:
1124 return performSHLCombine(N, DAG, DCI, Subtarget);
1125 case ISD::SRA:
1126 return performSRACombine(N, DAG, DCI, Subtarget);
1127 case ISD::SRL:
1128 return performSRLCombine(N, DAG, DCI, Subtarget);
Akira Hatanaka68741cc2013-04-30 22:37:26 +0000[diff] [blame]1129 case ISD::VSELECT:
1130 return performVSELECTCombine(N, DAG);
Daniel Sandersf7456c72013-09-23 13:22:24 +0000[diff] [blame]1131 case ISD::XOR:
1132 Val = performXORCombine(N, DAG, Subtarget);
1133 break;
1134 case ISD::SETCC:
Akira Hatanaka68741cc2013-04-30 22:37:26 +0000[diff] [blame]1135 Val = performSETCCCombine(N, DAG);
1136 break;
Akira Hatanaka9efcd762013-03-30 01:42:24 +0000[diff] [blame]1137 }
Akira Hatanaka68741cc2013-04-30 22:37:26 +0000[diff] [blame]1138
Daniel Sanders62aeab82013-10-30 13:31:27 +0000[diff] [blame]1139 if (Val.getNode()) {
1140 DEBUG(dbgs() << "\nMipsSE DAG Combine:\n";
1141 N->printrWithDepth(dbgs(), &DAG);
1142 dbgs() << "\n=> \n";
1143 Val.getNode()->printrWithDepth(dbgs(), &DAG);
1144 dbgs() << "\n");
Akira Hatanaka68741cc2013-04-30 22:37:26 +0000[diff] [blame]1145 return Val;
Daniel Sanders62aeab82013-10-30 13:31:27 +0000[diff] [blame]1146 }
Akira Hatanaka68741cc2013-04-30 22:37:26 +0000[diff] [blame]1147
1148 return MipsTargetLowering::PerformDAGCombine(N, DCI);
Akira Hatanaka9efcd762013-03-30 01:42:24 +0000[diff] [blame]1149}
1150
Akira Hatanaka96ca1822013-03-13 00:54:29 +0000[diff] [blame]1151MachineBasicBlock *
Duncan P. N. Exon Smithe4f5e4f2016-06-30 22:52:52 +0000[diff] [blame]1152MipsSETargetLowering::EmitInstrWithCustomInserter(MachineInstr &MI,
Akira Hatanaka96ca1822013-03-13 00:54:29 +0000[diff] [blame]1153 MachineBasicBlock *BB) const {
Duncan P. N. Exon Smithe4f5e4f2016-06-30 22:52:52 +0000[diff] [blame]1154 switch (MI.getOpcode()) {
Akira Hatanaka96ca1822013-03-13 00:54:29 +0000[diff] [blame]1155 default:
1156 return MipsTargetLowering::EmitInstrWithCustomInserter(MI, BB);
1157 case Mips::BPOSGE32_PSEUDO:
1158 return emitBPOSGE32(MI, BB);
Daniel Sandersce09d072013-08-28 12:14:50 +0000[diff] [blame]1159 case Mips::SNZ_B_PSEUDO:
1160 return emitMSACBranchPseudo(MI, BB, Mips::BNZ_B);
1161 case Mips::SNZ_H_PSEUDO:
1162 return emitMSACBranchPseudo(MI, BB, Mips::BNZ_H);
1163 case Mips::SNZ_W_PSEUDO:
1164 return emitMSACBranchPseudo(MI, BB, Mips::BNZ_W);
1165 case Mips::SNZ_D_PSEUDO:
1166 return emitMSACBranchPseudo(MI, BB, Mips::BNZ_D);
1167 case Mips::SNZ_V_PSEUDO:
1168 return emitMSACBranchPseudo(MI, BB, Mips::BNZ_V);
1169 case Mips::SZ_B_PSEUDO:
1170 return emitMSACBranchPseudo(MI, BB, Mips::BZ_B);
1171 case Mips::SZ_H_PSEUDO:
1172 return emitMSACBranchPseudo(MI, BB, Mips::BZ_H);
1173 case Mips::SZ_W_PSEUDO:
1174 return emitMSACBranchPseudo(MI, BB, Mips::BZ_W);
1175 case Mips::SZ_D_PSEUDO:
1176 return emitMSACBranchPseudo(MI, BB, Mips::BZ_D);
1177 case Mips::SZ_V_PSEUDO:
1178 return emitMSACBranchPseudo(MI, BB, Mips::BZ_V);
Daniel Sanders39bb8ba2013-09-27 12:17:32 +0000[diff] [blame]1179 case Mips::COPY_FW_PSEUDO:
1180 return emitCOPY_FW(MI, BB);
1181 case Mips::COPY_FD_PSEUDO:
1182 return emitCOPY_FD(MI, BB);
Daniel Sandersa5150702013-09-27 12:31:32 +0000[diff] [blame]1183 case Mips::INSERT_FW_PSEUDO:
1184 return emitINSERT_FW(MI, BB);
1185 case Mips::INSERT_FD_PSEUDO:
1186 return emitINSERT_FD(MI, BB);
Daniel Sanderse296a0f2014-04-30 12:09:32 +0000[diff] [blame]1187 case Mips::INSERT_B_VIDX_PSEUDO:
Daniel Sanderseda60d22015-05-05 10:32:24 +0000[diff] [blame]1188 case Mips::INSERT_B_VIDX64_PSEUDO:
Daniel Sanderse296a0f2014-04-30 12:09:32 +0000[diff] [blame]1189 return emitINSERT_DF_VIDX(MI, BB, 1, false);
1190 case Mips::INSERT_H_VIDX_PSEUDO:
Daniel Sanderseda60d22015-05-05 10:32:24 +0000[diff] [blame]1191 case Mips::INSERT_H_VIDX64_PSEUDO:
Daniel Sanderse296a0f2014-04-30 12:09:32 +0000[diff] [blame]1192 return emitINSERT_DF_VIDX(MI, BB, 2, false);
1193 case Mips::INSERT_W_VIDX_PSEUDO:
Daniel Sanderseda60d22015-05-05 10:32:24 +0000[diff] [blame]1194 case Mips::INSERT_W_VIDX64_PSEUDO:
Daniel Sanderse296a0f2014-04-30 12:09:32 +0000[diff] [blame]1195 return emitINSERT_DF_VIDX(MI, BB, 4, false);
1196 case Mips::INSERT_D_VIDX_PSEUDO:
Daniel Sanderseda60d22015-05-05 10:32:24 +0000[diff] [blame]1197 case Mips::INSERT_D_VIDX64_PSEUDO:
Daniel Sanderse296a0f2014-04-30 12:09:32 +0000[diff] [blame]1198 return emitINSERT_DF_VIDX(MI, BB, 8, false);
1199 case Mips::INSERT_FW_VIDX_PSEUDO:
Daniel Sanderseda60d22015-05-05 10:32:24 +0000[diff] [blame]1200 case Mips::INSERT_FW_VIDX64_PSEUDO:
Daniel Sanderse296a0f2014-04-30 12:09:32 +0000[diff] [blame]1201 return emitINSERT_DF_VIDX(MI, BB, 4, true);
1202 case Mips::INSERT_FD_VIDX_PSEUDO:
Daniel Sanderseda60d22015-05-05 10:32:24 +0000[diff] [blame]1203 case Mips::INSERT_FD_VIDX64_PSEUDO:
Daniel Sanderse296a0f2014-04-30 12:09:32 +0000[diff] [blame]1204 return emitINSERT_DF_VIDX(MI, BB, 8, true);
Daniel Sanders1dfddc72013-10-15 13:14:41 +0000[diff] [blame]1205 case Mips::FILL_FW_PSEUDO:
1206 return emitFILL_FW(MI, BB);
1207 case Mips::FILL_FD_PSEUDO:
1208 return emitFILL_FD(MI, BB);
Daniel Sandersa9521602013-10-23 10:36:52 +0000[diff] [blame]1209 case Mips::FEXP2_W_1_PSEUDO:
1210 return emitFEXP2_W_1(MI, BB);
1211 case Mips::FEXP2_D_1_PSEUDO:
1212 return emitFEXP2_D_1(MI, BB);
Simon Dardis0e2ee3b2016-11-18 16:17:44 +0000[diff] [blame]1213 case Mips::ST_F16:
1214 return emitST_F16_PSEUDO(MI, BB);
1215 case Mips::LD_F16:
1216 return emitLD_F16_PSEUDO(MI, BB);
1217 case Mips::MSA_FP_EXTEND_W_PSEUDO:
1218 return emitFPEXTEND_PSEUDO(MI, BB, false);
1219 case Mips::MSA_FP_ROUND_W_PSEUDO:
1220 return emitFPROUND_PSEUDO(MI, BB, false);
1221 case Mips::MSA_FP_EXTEND_D_PSEUDO:
1222 return emitFPEXTEND_PSEUDO(MI, BB, true);
1223 case Mips::MSA_FP_ROUND_D_PSEUDO:
1224 return emitFPROUND_PSEUDO(MI, BB, true);
Akira Hatanaka96ca1822013-03-13 00:54:29 +0000[diff] [blame]1225 }
1226}
1227
Daniel Sanders23e98772014-11-02 16:09:29 +0000[diff] [blame]1228bool MipsSETargetLowering::isEligibleForTailCallOptimization(
1229 const CCState &CCInfo, unsigned NextStackOffset,
1230 const MipsFunctionInfo &FI) const {
Simon Dardis57f4ae42016-08-04 09:17:07 +0000[diff] [blame]1231 if (!UseMipsTailCalls)
Akira Hatanaka96ca1822013-03-13 00:54:29 +0000[diff] [blame]1232 return false;
1233
Vasileios Kalintiris43dff0c2015-10-26 12:38:43 +0000[diff] [blame]1234 // Exception has to be cleared with eret.
1235 if (FI.isISR())
1236 return false;
1237
Akira Hatanaka96ca1822013-03-13 00:54:29 +0000[diff] [blame]1238 // Return false if either the callee or caller has a byval argument.
Daniel Sanders23e98772014-11-02 16:09:29 +0000[diff] [blame]1239 if (CCInfo.getInRegsParamsCount() > 0 || FI.hasByvalArg())
Akira Hatanaka96ca1822013-03-13 00:54:29 +0000[diff] [blame]1240 return false;
1241
1242 // Return true if the callee's argument area is no larger than the
1243 // caller's.
1244 return NextStackOffset <= FI.getIncomingArgSize();
1245}
1246
1247void MipsSETargetLowering::
1248getOpndList(SmallVectorImpl<SDValue> &Ops,
1249 std::deque< std::pair<unsigned, SDValue> > &RegsToPass,
1250 bool IsPICCall, bool GlobalOrExternal, bool InternalLinkage,
Sasa Stankovic7072a792014-10-01 08:22:21 +0000[diff] [blame]1251 bool IsCallReloc, CallLoweringInfo &CLI, SDValue Callee,
1252 SDValue Chain) const {
Akira Hatanaka168d4e52013-11-27 23:38:42 +0000[diff] [blame]1253 Ops.push_back(Callee);
Akira Hatanaka96ca1822013-03-13 00:54:29 +0000[diff] [blame]1254 MipsTargetLowering::getOpndList(Ops, RegsToPass, IsPICCall, GlobalOrExternal,
Sasa Stankovic7072a792014-10-01 08:22:21 +0000[diff] [blame]1255 InternalLinkage, IsCallReloc, CLI, Callee,
1256 Chain);
Akira Hatanaka96ca1822013-03-13 00:54:29 +0000[diff] [blame]1257}
1258
Akira Hatanaka63791212013-09-07 00:52:30 +0000[diff] [blame]1259SDValue MipsSETargetLowering::lowerLOAD(SDValue Op, SelectionDAG &DAG) const {
1260 LoadSDNode &Nd = *cast<LoadSDNode>(Op);
1261
1262 if (Nd.getMemoryVT() != MVT::f64 || !NoDPLoadStore)
1263 return MipsTargetLowering::lowerLOAD(Op, DAG);
1264
1265 // Replace a double precision load with two i32 loads and a buildpair64.
1266 SDLoc DL(Op);
1267 SDValue Ptr = Nd.getBasePtr(), Chain = Nd.getChain();
1268 EVT PtrVT = Ptr.getValueType();
1269
1270 // i32 load from lower address.
Justin Lebar9c375812016-07-15 18:27:10 +0000[diff] [blame]1271 SDValue Lo = DAG.getLoad(MVT::i32, DL, Chain, Ptr, MachinePointerInfo(),
1272 Nd.getAlignment(), Nd.getMemOperand()->getFlags());
Akira Hatanaka63791212013-09-07 00:52:30 +0000[diff] [blame]1273
1274 // i32 load from higher address.
Sergey Dmitrouk842a51b2015-04-28 14:05:47 +0000[diff] [blame]1275 Ptr = DAG.getNode(ISD::ADD, DL, PtrVT, Ptr, DAG.getConstant(4, DL, PtrVT));
Justin Lebar9c375812016-07-15 18:27:10 +0000[diff] [blame]1276 SDValue Hi = DAG.getLoad(
1277 MVT::i32, DL, Lo.getValue(1), Ptr, MachinePointerInfo(),
1278 std::min(Nd.getAlignment(), 4U), Nd.getMemOperand()->getFlags());
Akira Hatanaka63791212013-09-07 00:52:30 +0000[diff] [blame]1279
Eric Christopher1c29a652014-07-18 22:55:25 +0000[diff] [blame]1280 if (!Subtarget.isLittle())
Akira Hatanaka63791212013-09-07 00:52:30 +0000[diff] [blame]1281 std::swap(Lo, Hi);
1282
1283 SDValue BP = DAG.getNode(MipsISD::BuildPairF64, DL, MVT::f64, Lo, Hi);
1284 SDValue Ops[2] = {BP, Hi.getValue(1)};
Craig Topper64941d92014-04-27 19:20:57 +0000[diff] [blame]1285 return DAG.getMergeValues(Ops, DL);
Akira Hatanaka63791212013-09-07 00:52:30 +0000[diff] [blame]1286}
1287
1288SDValue MipsSETargetLowering::lowerSTORE(SDValue Op, SelectionDAG &DAG) const {
1289 StoreSDNode &Nd = *cast<StoreSDNode>(Op);
1290
1291 if (Nd.getMemoryVT() != MVT::f64 || !NoDPLoadStore)
1292 return MipsTargetLowering::lowerSTORE(Op, DAG);
1293
1294 // Replace a double precision store with two extractelement64s and i32 stores.
1295 SDLoc DL(Op);
1296 SDValue Val = Nd.getValue(), Ptr = Nd.getBasePtr(), Chain = Nd.getChain();
1297 EVT PtrVT = Ptr.getValueType();
1298 SDValue Lo = DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32,
Sergey Dmitrouk842a51b2015-04-28 14:05:47 +0000[diff] [blame]1299 Val, DAG.getConstant(0, DL, MVT::i32));
Akira Hatanaka63791212013-09-07 00:52:30 +0000[diff] [blame]1300 SDValue Hi = DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32,
Sergey Dmitrouk842a51b2015-04-28 14:05:47 +0000[diff] [blame]1301 Val, DAG.getConstant(1, DL, MVT::i32));
Akira Hatanaka63791212013-09-07 00:52:30 +0000[diff] [blame]1302
Eric Christopher1c29a652014-07-18 22:55:25 +0000[diff] [blame]1303 if (!Subtarget.isLittle())
Akira Hatanaka63791212013-09-07 00:52:30 +0000[diff] [blame]1304 std::swap(Lo, Hi);
1305
1306 // i32 store to lower address.
Justin Lebar9c375812016-07-15 18:27:10 +0000[diff] [blame]1307 Chain =
1308 DAG.getStore(Chain, DL, Lo, Ptr, MachinePointerInfo(), Nd.getAlignment(),
1309 Nd.getMemOperand()->getFlags(), Nd.getAAInfo());
Akira Hatanaka63791212013-09-07 00:52:30 +0000[diff] [blame]1310
1311 // i32 store to higher address.
Sergey Dmitrouk842a51b2015-04-28 14:05:47 +0000[diff] [blame]1312 Ptr = DAG.getNode(ISD::ADD, DL, PtrVT, Ptr, DAG.getConstant(4, DL, PtrVT));
Akira Hatanaka63791212013-09-07 00:52:30 +0000[diff] [blame]1313 return DAG.getStore(Chain, DL, Hi, Ptr, MachinePointerInfo(),
Justin Lebar9c375812016-07-15 18:27:10 +0000[diff] [blame]1314 std::min(Nd.getAlignment(), 4U),
1315 Nd.getMemOperand()->getFlags(), Nd.getAAInfo());
Akira Hatanaka63791212013-09-07 00:52:30 +0000[diff] [blame]1316}
1317
Akira Hatanakabe8612f2013-03-30 01:36:35 +0000[diff] [blame]1318SDValue MipsSETargetLowering::lowerMulDiv(SDValue Op, unsigned NewOpc,
1319 bool HasLo, bool HasHi,
1320 SelectionDAG &DAG) const {
Daniel Sanders308181e2014-06-12 10:44:10 +0000[diff] [blame]1321 // MIPS32r6/MIPS64r6 removed accumulator based multiplies.
Eric Christopher1c29a652014-07-18 22:55:25 +0000[diff] [blame]1322 assert(!Subtarget.hasMips32r6());
Daniel Sanders308181e2014-06-12 10:44:10 +0000[diff] [blame]1323
Akira Hatanakabe8612f2013-03-30 01:36:35 +0000[diff] [blame]1324 EVT Ty = Op.getOperand(0).getValueType();
Andrew Trickef9de2a2013-05-25 02:42:55 +0000[diff] [blame]1325 SDLoc DL(Op);
Akira Hatanakabe8612f2013-03-30 01:36:35 +0000[diff] [blame]1326 SDValue Mult = DAG.getNode(NewOpc, DL, MVT::Untyped,
1327 Op.getOperand(0), Op.getOperand(1));
1328 SDValue Lo, Hi;
1329
1330 if (HasLo)
Akira Hatanakad98c99f2013-10-15 01:12:50 +0000[diff] [blame]1331 Lo = DAG.getNode(MipsISD::MFLO, DL, Ty, Mult);
Akira Hatanakabe8612f2013-03-30 01:36:35 +0000[diff] [blame]1332 if (HasHi)
Akira Hatanakad98c99f2013-10-15 01:12:50 +0000[diff] [blame]1333 Hi = DAG.getNode(MipsISD::MFHI, DL, Ty, Mult);
Akira Hatanakabe8612f2013-03-30 01:36:35 +0000[diff] [blame]1334
1335 if (!HasLo || !HasHi)
1336 return HasLo ? Lo : Hi;
1337
1338 SDValue Vals[] = { Lo, Hi };
Craig Topper64941d92014-04-27 19:20:57 +0000[diff] [blame]1339 return DAG.getMergeValues(Vals, DL);
Akira Hatanakabe8612f2013-03-30 01:36:35 +0000[diff] [blame]1340}
1341
Benjamin Kramerbdc49562016-06-12 15:39:02 +0000[diff] [blame]1342static SDValue initAccumulator(SDValue In, const SDLoc &DL, SelectionDAG &DAG) {
Akira Hatanakaa6bbde52013-04-13 02:13:30 +0000[diff] [blame]1343 SDValue InLo = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, In,
Sergey Dmitrouk842a51b2015-04-28 14:05:47 +0000[diff] [blame]1344 DAG.getConstant(0, DL, MVT::i32));
Akira Hatanakaa6bbde52013-04-13 02:13:30 +0000[diff] [blame]1345 SDValue InHi = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, In,
Sergey Dmitrouk842a51b2015-04-28 14:05:47 +0000[diff] [blame]1346 DAG.getConstant(1, DL, MVT::i32));
Akira Hatanakad98c99f2013-10-15 01:12:50 +0000[diff] [blame]1347 return DAG.getNode(MipsISD::MTLOHI, DL, MVT::Untyped, InLo, InHi);
Akira Hatanakaa6bbde52013-04-13 02:13:30 +0000[diff] [blame]1348}
1349
Benjamin Kramerbdc49562016-06-12 15:39:02 +0000[diff] [blame]1350static SDValue extractLOHI(SDValue Op, const SDLoc &DL, SelectionDAG &DAG) {
Akira Hatanakad98c99f2013-10-15 01:12:50 +0000[diff] [blame]1351 SDValue Lo = DAG.getNode(MipsISD::MFLO, DL, MVT::i32, Op);
1352 SDValue Hi = DAG.getNode(MipsISD::MFHI, DL, MVT::i32, Op);
Akira Hatanakaa6bbde52013-04-13 02:13:30 +0000[diff] [blame]1353 return DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Lo, Hi);
1354}
1355
1356// This function expands mips intrinsic nodes which have 64-bit input operands
1357// or output values.
1358//
1359// out64 = intrinsic-node in64
1360// =>
1361// lo = copy (extract-element (in64, 0))
1362// hi = copy (extract-element (in64, 1))
1363// mips-specific-node
1364// v0 = copy lo
1365// v1 = copy hi
1366// out64 = merge-values (v0, v1)
1367//
1368static SDValue lowerDSPIntr(SDValue Op, SelectionDAG &DAG, unsigned Opc) {
Andrew Trickef9de2a2013-05-25 02:42:55 +0000[diff] [blame]1369 SDLoc DL(Op);
Akira Hatanakaa6bbde52013-04-13 02:13:30 +0000[diff] [blame]1370 bool HasChainIn = Op->getOperand(0).getValueType() == MVT::Other;
1371 SmallVector<SDValue, 3> Ops;
1372 unsigned OpNo = 0;
1373
1374 // See if Op has a chain input.
1375 if (HasChainIn)
1376 Ops.push_back(Op->getOperand(OpNo++));
1377
1378 // The next operand is the intrinsic opcode.
1379 assert(Op->getOperand(OpNo).getOpcode() == ISD::TargetConstant);
1380
1381 // See if the next operand has type i64.
1382 SDValue Opnd = Op->getOperand(++OpNo), In64;
1383
1384 if (Opnd.getValueType() == MVT::i64)
1385 In64 = initAccumulator(Opnd, DL, DAG);
1386 else
1387 Ops.push_back(Opnd);
1388
1389 // Push the remaining operands.
1390 for (++OpNo ; OpNo < Op->getNumOperands(); ++OpNo)
1391 Ops.push_back(Op->getOperand(OpNo));
1392
1393 // Add In64 to the end of the list.
1394 if (In64.getNode())
1395 Ops.push_back(In64);
1396
1397 // Scan output.
1398 SmallVector<EVT, 2> ResTys;
1399
1400 for (SDNode::value_iterator I = Op->value_begin(), E = Op->value_end();
1401 I != E; ++I)
1402 ResTys.push_back((*I == MVT::i64) ? MVT::Untyped : *I);
1403
1404 // Create node.
Craig Topper48d114b2014-04-26 18:35:24 +0000[diff] [blame]1405 SDValue Val = DAG.getNode(Opc, DL, ResTys, Ops);
Akira Hatanakaa6bbde52013-04-13 02:13:30 +0000[diff] [blame]1406 SDValue Out = (ResTys[0] == MVT::Untyped) ? extractLOHI(Val, DL, DAG) : Val;
1407
1408 if (!HasChainIn)
1409 return Out;
1410
1411 assert(Val->getValueType(1) == MVT::Other);
1412 SDValue Vals[] = { Out, SDValue(Val.getNode(), 1) };
Craig Topper64941d92014-04-27 19:20:57 +0000[diff] [blame]1413 return DAG.getMergeValues(Vals, DL);
Akira Hatanakaa6bbde52013-04-13 02:13:30 +0000[diff] [blame]1414}
1415
Daniel Sandersa4c8f3a2013-09-23 14:03:12 +0000[diff] [blame]1416// Lower an MSA copy intrinsic into the specified SelectionDAG node
1417static SDValue lowerMSACopyIntr(SDValue Op, SelectionDAG &DAG, unsigned Opc) {
1418 SDLoc DL(Op);
1419 SDValue Vec = Op->getOperand(1);
1420 SDValue Idx = Op->getOperand(2);
1421 EVT ResTy = Op->getValueType(0);
1422 EVT EltTy = Vec->getValueType(0).getVectorElementType();
1423
1424 SDValue Result = DAG.getNode(Opc, DL, ResTy, Vec, Idx,
1425 DAG.getValueType(EltTy));
1426
1427 return Result;
1428}
1429
Daniel Sanders50b80412013-11-15 12:56:49 +0000[diff] [blame]1430static SDValue lowerMSASplatZExt(SDValue Op, unsigned OpNr, SelectionDAG &DAG) {
1431 EVT ResVecTy = Op->getValueType(0);
1432 EVT ViaVecTy = ResVecTy;
1433 SDLoc DL(Op);
Daniel Sanders86d0c8d2013-09-23 14:29:55 +0000[diff] [blame]1434
Daniel Sanders50b80412013-11-15 12:56:49 +0000[diff] [blame]1435 // When ResVecTy == MVT::v2i64, LaneA is the upper 32 bits of the lane and
1436 // LaneB is the lower 32-bits. Otherwise LaneA and LaneB are alternating
1437 // lanes.
1438 SDValue LaneA;
1439 SDValue LaneB = Op->getOperand(2);
1440
1441 if (ResVecTy == MVT::v2i64) {
Sergey Dmitrouk842a51b2015-04-28 14:05:47 +0000[diff] [blame]1442 LaneA = DAG.getConstant(0, DL, MVT::i32);
Daniel Sandersf49dd822013-09-24 13:33:07 +0000[diff] [blame]1443 ViaVecTy = MVT::v4i32;
Daniel Sanders50b80412013-11-15 12:56:49 +0000[diff] [blame]1444 } else
1445 LaneA = LaneB;
Daniel Sanders86d0c8d2013-09-23 14:29:55 +0000[diff] [blame]1446
Daniel Sanders50b80412013-11-15 12:56:49 +0000[diff] [blame]1447 SDValue Ops[16] = { LaneA, LaneB, LaneA, LaneB, LaneA, LaneB, LaneA, LaneB,
1448 LaneA, LaneB, LaneA, LaneB, LaneA, LaneB, LaneA, LaneB };
Daniel Sandersf49dd822013-09-24 13:33:07 +0000[diff] [blame]1449
Ahmed Bougacha128f8732016-04-26 21:15:30 +0000[diff] [blame]1450 SDValue Result = DAG.getBuildVector(
1451 ViaVecTy, DL, makeArrayRef(Ops, ViaVecTy.getVectorNumElements()));
Daniel Sanders50b80412013-11-15 12:56:49 +0000[diff] [blame]1452
1453 if (ViaVecTy != ResVecTy)
1454 Result = DAG.getNode(ISD::BITCAST, DL, ResVecTy, Result);
Daniel Sandersf49dd822013-09-24 13:33:07 +0000[diff] [blame]1455
1456 return Result;
1457}
1458
Daniel Sanders50b80412013-11-15 12:56:49 +0000[diff] [blame]1459static SDValue lowerMSASplatImm(SDValue Op, unsigned ImmOp, SelectionDAG &DAG) {
Sergey Dmitrouk842a51b2015-04-28 14:05:47 +0000[diff] [blame]1460 return DAG.getConstant(Op->getConstantOperandVal(ImmOp), SDLoc(Op),
1461 Op->getValueType(0));
Daniel Sanders50b80412013-11-15 12:56:49 +0000[diff] [blame]1462}
1463
1464static SDValue getBuildVectorSplat(EVT VecTy, SDValue SplatValue,
1465 bool BigEndian, SelectionDAG &DAG) {
1466 EVT ViaVecTy = VecTy;
1467 SDValue SplatValueA = SplatValue;
1468 SDValue SplatValueB = SplatValue;
1469 SDLoc DL(SplatValue);
1470
1471 if (VecTy == MVT::v2i64) {
1472 // v2i64 BUILD_VECTOR must be performed via v4i32 so split into i32's.
1473 ViaVecTy = MVT::v4i32;
1474
1475 SplatValueA = DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, SplatValue);
1476 SplatValueB = DAG.getNode(ISD::SRL, DL, MVT::i64, SplatValue,
Sergey Dmitrouk842a51b2015-04-28 14:05:47 +0000[diff] [blame]1477 DAG.getConstant(32, DL, MVT::i32));
Daniel Sanders50b80412013-11-15 12:56:49 +0000[diff] [blame]1478 SplatValueB = DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, SplatValueB);
1479 }
1480
1481 // We currently hold the parts in little endian order. Swap them if
1482 // necessary.
1483 if (BigEndian)
1484 std::swap(SplatValueA, SplatValueB);
1485
1486 SDValue Ops[16] = { SplatValueA, SplatValueB, SplatValueA, SplatValueB,
1487 SplatValueA, SplatValueB, SplatValueA, SplatValueB,
1488 SplatValueA, SplatValueB, SplatValueA, SplatValueB,
1489 SplatValueA, SplatValueB, SplatValueA, SplatValueB };
1490
Ahmed Bougacha128f8732016-04-26 21:15:30 +0000[diff] [blame]1491 SDValue Result = DAG.getBuildVector(
1492 ViaVecTy, DL, makeArrayRef(Ops, ViaVecTy.getVectorNumElements()));
Daniel Sanders50b80412013-11-15 12:56:49 +0000[diff] [blame]1493
1494 if (VecTy != ViaVecTy)
1495 Result = DAG.getNode(ISD::BITCAST, DL, VecTy, Result);
1496
1497 return Result;
Daniel Sandersf5bd9372013-09-11 10:51:30 +0000[diff] [blame]1498}
1499
Daniel Sandersa5bc99f2013-11-12 10:31:49 +0000[diff] [blame]1500static SDValue lowerMSABinaryBitImmIntr(SDValue Op, SelectionDAG &DAG,
1501 unsigned Opc, SDValue Imm,
1502 bool BigEndian) {
1503 EVT VecTy = Op->getValueType(0);
1504 SDValue Exp2Imm;
1505 SDLoc DL(Op);
1506
Daniel Sanders50b80412013-11-15 12:56:49 +0000[diff] [blame]1507 // The DAG Combiner can't constant fold bitcasted vectors yet so we must do it
1508 // here for now.
Daniel Sandersa5bc99f2013-11-12 10:31:49 +0000[diff] [blame]1509 if (VecTy == MVT::v2i64) {
1510 if (ConstantSDNode *CImm = dyn_cast<ConstantSDNode>(Imm)) {
1511 APInt BitImm = APInt(64, 1) << CImm->getAPIntValue();
1512
Sergey Dmitrouk842a51b2015-04-28 14:05:47 +0000[diff] [blame]1513 SDValue BitImmHiOp = DAG.getConstant(BitImm.lshr(32).trunc(32), DL,
1514 MVT::i32);
1515 SDValue BitImmLoOp = DAG.getConstant(BitImm.trunc(32), DL, MVT::i32);
Daniel Sanders50b80412013-11-15 12:56:49 +0000[diff] [blame]1516
1517 if (BigEndian)
1518 std::swap(BitImmLoOp, BitImmHiOp);
1519
Ahmed Bougacha128f8732016-04-26 21:15:30 +0000[diff] [blame]1520 Exp2Imm = DAG.getNode(
1521 ISD::BITCAST, DL, MVT::v2i64,
1522 DAG.getBuildVector(MVT::v4i32, DL,
1523 {BitImmLoOp, BitImmHiOp, BitImmLoOp, BitImmHiOp}));
Daniel Sandersa5bc99f2013-11-12 10:31:49 +0000[diff] [blame]1524 }
1525 }
1526
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]1527 if (!Exp2Imm.getNode()) {
Daniel Sandersa5bc99f2013-11-12 10:31:49 +0000[diff] [blame]1528 // We couldnt constant fold, do a vector shift instead
Daniel Sanders50b80412013-11-15 12:56:49 +0000[diff] [blame]1529
1530 // Extend i32 to i64 if necessary. Sign or zero extend doesn't matter since
1531 // only values 0-63 are valid.
1532 if (VecTy == MVT::v2i64)
1533 Imm = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i64, Imm);
1534
1535 Exp2Imm = getBuildVectorSplat(VecTy, Imm, BigEndian, DAG);
1536
Sergey Dmitrouk842a51b2015-04-28 14:05:47 +0000[diff] [blame]1537 Exp2Imm = DAG.getNode(ISD::SHL, DL, VecTy, DAG.getConstant(1, DL, VecTy),
1538 Exp2Imm);
Daniel Sandersa5bc99f2013-11-12 10:31:49 +0000[diff] [blame]1539 }
1540
1541 return DAG.getNode(Opc, DL, VecTy, Op->getOperand(1), Exp2Imm);
1542}
1543
Daniel Sanders3f6eb542013-11-12 10:45:18 +0000[diff] [blame]1544static SDValue lowerMSABitClear(SDValue Op, SelectionDAG &DAG) {
1545 EVT ResTy = Op->getValueType(0);
Daniel Sanders3f6eb542013-11-12 10:45:18 +0000[diff] [blame]1546 SDLoc DL(Op);
Sergey Dmitrouk842a51b2015-04-28 14:05:47 +0000[diff] [blame]1547 SDValue One = DAG.getConstant(1, DL, ResTy);
Daniel Sanders3f6eb542013-11-12 10:45:18 +0000[diff] [blame]1548 SDValue Bit = DAG.getNode(ISD::SHL, DL, ResTy, One, Op->getOperand(2));
1549
Daniel Sanders71ce0ca2013-11-15 16:02:04 +0000[diff] [blame]1550 return DAG.getNode(ISD::AND, DL, ResTy, Op->getOperand(1),
1551 DAG.getNOT(DL, Bit, ResTy));
Daniel Sanders3f6eb542013-11-12 10:45:18 +0000[diff] [blame]1552}
1553
1554static SDValue lowerMSABitClearImm(SDValue Op, SelectionDAG &DAG) {
1555 SDLoc DL(Op);
1556 EVT ResTy = Op->getValueType(0);
Sanjay Patel1ed771f2016-09-14 16:37:15 +0000[diff] [blame]1557 APInt BitImm = APInt(ResTy.getScalarSizeInBits(), 1)
Daniel Sanders50b80412013-11-15 12:56:49 +0000[diff] [blame]1558 << cast<ConstantSDNode>(Op->getOperand(2))->getAPIntValue();
Sergey Dmitrouk842a51b2015-04-28 14:05:47 +0000[diff] [blame]1559 SDValue BitMask = DAG.getConstant(~BitImm, DL, ResTy);
Daniel Sanders3f6eb542013-11-12 10:45:18 +0000[diff] [blame]1560
1561 return DAG.getNode(ISD::AND, DL, ResTy, Op->getOperand(1), BitMask);
1562}
1563
Akira Hatanakaa6bbde52013-04-13 02:13:30 +0000[diff] [blame]1564SDValue MipsSETargetLowering::lowerINTRINSIC_WO_CHAIN(SDValue Op,
1565 SelectionDAG &DAG) const {
Daniel Sanders84e7caf2013-09-27 10:25:41 +0000[diff] [blame]1566 SDLoc DL(Op);
1567
Akira Hatanakaa6bbde52013-04-13 02:13:30 +0000[diff] [blame]1568 switch (cast<ConstantSDNode>(Op->getOperand(0))->getZExtValue()) {
1569 default:
1570 return SDValue();
1571 case Intrinsic::mips_shilo:
1572 return lowerDSPIntr(Op, DAG, MipsISD::SHILO);
1573 case Intrinsic::mips_dpau_h_qbl:
1574 return lowerDSPIntr(Op, DAG, MipsISD::DPAU_H_QBL);
1575 case Intrinsic::mips_dpau_h_qbr:
1576 return lowerDSPIntr(Op, DAG, MipsISD::DPAU_H_QBR);
1577 case Intrinsic::mips_dpsu_h_qbl:
1578 return lowerDSPIntr(Op, DAG, MipsISD::DPSU_H_QBL);
1579 case Intrinsic::mips_dpsu_h_qbr:
1580 return lowerDSPIntr(Op, DAG, MipsISD::DPSU_H_QBR);
1581 case Intrinsic::mips_dpa_w_ph:
1582 return lowerDSPIntr(Op, DAG, MipsISD::DPA_W_PH);
1583 case Intrinsic::mips_dps_w_ph:
1584 return lowerDSPIntr(Op, DAG, MipsISD::DPS_W_PH);
1585 case Intrinsic::mips_dpax_w_ph:
1586 return lowerDSPIntr(Op, DAG, MipsISD::DPAX_W_PH);
1587 case Intrinsic::mips_dpsx_w_ph:
1588 return lowerDSPIntr(Op, DAG, MipsISD::DPSX_W_PH);
1589 case Intrinsic::mips_mulsa_w_ph:
1590 return lowerDSPIntr(Op, DAG, MipsISD::MULSA_W_PH);
1591 case Intrinsic::mips_mult:
1592 return lowerDSPIntr(Op, DAG, MipsISD::Mult);
1593 case Intrinsic::mips_multu:
1594 return lowerDSPIntr(Op, DAG, MipsISD::Multu);
1595 case Intrinsic::mips_madd:
1596 return lowerDSPIntr(Op, DAG, MipsISD::MAdd);
1597 case Intrinsic::mips_maddu:
1598 return lowerDSPIntr(Op, DAG, MipsISD::MAddu);
1599 case Intrinsic::mips_msub:
1600 return lowerDSPIntr(Op, DAG, MipsISD::MSub);
1601 case Intrinsic::mips_msubu:
1602 return lowerDSPIntr(Op, DAG, MipsISD::MSubu);
Daniel Sandersfa5ab1c2013-09-11 10:28:16 +0000[diff] [blame]1603 case Intrinsic::mips_addv_b:
1604 case Intrinsic::mips_addv_h:
1605 case Intrinsic::mips_addv_w:
1606 case Intrinsic::mips_addv_d:
Daniel Sanders84e7caf2013-09-27 10:25:41 +0000[diff] [blame]1607 return DAG.getNode(ISD::ADD, DL, Op->getValueType(0), Op->getOperand(1),
1608 Op->getOperand(2));
Daniel Sanders86d0c8d2013-09-23 14:29:55 +0000[diff] [blame]1609 case Intrinsic::mips_addvi_b:
1610 case Intrinsic::mips_addvi_h:
1611 case Intrinsic::mips_addvi_w:
1612 case Intrinsic::mips_addvi_d:
Daniel Sanders84e7caf2013-09-27 10:25:41 +0000[diff] [blame]1613 return DAG.getNode(ISD::ADD, DL, Op->getValueType(0), Op->getOperand(1),
1614 lowerMSASplatImm(Op, 2, DAG));
Daniel Sanders8ca81e42013-09-23 12:57:42 +0000[diff] [blame]1615 case Intrinsic::mips_and_v:
Daniel Sanders84e7caf2013-09-27 10:25:41 +0000[diff] [blame]1616 return DAG.getNode(ISD::AND, DL, Op->getValueType(0), Op->getOperand(1),
1617 Op->getOperand(2));
Daniel Sandersbfc39ce2013-09-24 12:32:47 +0000[diff] [blame]1618 case Intrinsic::mips_andi_b:
Daniel Sanders84e7caf2013-09-27 10:25:41 +0000[diff] [blame]1619 return DAG.getNode(ISD::AND, DL, Op->getValueType(0), Op->getOperand(1),
1620 lowerMSASplatImm(Op, 2, DAG));
Daniel Sanders3f6eb542013-11-12 10:45:18 +0000[diff] [blame]1621 case Intrinsic::mips_bclr_b:
1622 case Intrinsic::mips_bclr_h:
1623 case Intrinsic::mips_bclr_w:
1624 case Intrinsic::mips_bclr_d:
1625 return lowerMSABitClear(Op, DAG);
1626 case Intrinsic::mips_bclri_b:
1627 case Intrinsic::mips_bclri_h:
1628 case Intrinsic::mips_bclri_w:
1629 case Intrinsic::mips_bclri_d:
1630 return lowerMSABitClearImm(Op, DAG);
Daniel Sandersd74b1302013-10-30 14:45:14 +0000[diff] [blame]1631 case Intrinsic::mips_binsli_b:
1632 case Intrinsic::mips_binsli_h:
1633 case Intrinsic::mips_binsli_w:
1634 case Intrinsic::mips_binsli_d: {
Daniel Sandersdf2215452014-03-12 11:54:00 +0000[diff] [blame]1635 // binsli_x(IfClear, IfSet, nbits) -> (vselect LBitsMask, IfSet, IfClear)
Daniel Sandersd74b1302013-10-30 14:45:14 +0000[diff] [blame]1636 EVT VecTy = Op->getValueType(0);
1637 EVT EltTy = VecTy.getVectorElementType();
1638 APInt Mask = APInt::getHighBitsSet(EltTy.getSizeInBits(),
1639 Op->getConstantOperandVal(3));
1640 return DAG.getNode(ISD::VSELECT, DL, VecTy,
Sergey Dmitrouk842a51b2015-04-28 14:05:47 +0000[diff] [blame]1641 DAG.getConstant(Mask, DL, VecTy, true),
1642 Op->getOperand(2), Op->getOperand(1));
Daniel Sandersd74b1302013-10-30 14:45:14 +0000[diff] [blame]1643 }
1644 case Intrinsic::mips_binsri_b:
1645 case Intrinsic::mips_binsri_h:
1646 case Intrinsic::mips_binsri_w:
1647 case Intrinsic::mips_binsri_d: {
Daniel Sandersdf2215452014-03-12 11:54:00 +0000[diff] [blame]1648 // binsri_x(IfClear, IfSet, nbits) -> (vselect RBitsMask, IfSet, IfClear)
Daniel Sandersd74b1302013-10-30 14:45:14 +0000[diff] [blame]1649 EVT VecTy = Op->getValueType(0);
1650 EVT EltTy = VecTy.getVectorElementType();
1651 APInt Mask = APInt::getLowBitsSet(EltTy.getSizeInBits(),
1652 Op->getConstantOperandVal(3));
1653 return DAG.getNode(ISD::VSELECT, DL, VecTy,
Sergey Dmitrouk842a51b2015-04-28 14:05:47 +0000[diff] [blame]1654 DAG.getConstant(Mask, DL, VecTy, true),
1655 Op->getOperand(2), Op->getOperand(1));
Daniel Sandersd74b1302013-10-30 14:45:14 +0000[diff] [blame]1656 }
Daniel Sandersab94b532013-10-30 15:20:38 +0000[diff] [blame]1657 case Intrinsic::mips_bmnz_v:
1658 return DAG.getNode(ISD::VSELECT, DL, Op->getValueType(0), Op->getOperand(3),
1659 Op->getOperand(2), Op->getOperand(1));
1660 case Intrinsic::mips_bmnzi_b:
1661 return DAG.getNode(ISD::VSELECT, DL, Op->getValueType(0),
1662 lowerMSASplatImm(Op, 3, DAG), Op->getOperand(2),
1663 Op->getOperand(1));
1664 case Intrinsic::mips_bmz_v:
1665 return DAG.getNode(ISD::VSELECT, DL, Op->getValueType(0), Op->getOperand(3),
1666 Op->getOperand(1), Op->getOperand(2));
1667 case Intrinsic::mips_bmzi_b:
1668 return DAG.getNode(ISD::VSELECT, DL, Op->getValueType(0),
1669 lowerMSASplatImm(Op, 3, DAG), Op->getOperand(1),
1670 Op->getOperand(2));
Daniel Sandersa5bc99f2013-11-12 10:31:49 +0000[diff] [blame]1671 case Intrinsic::mips_bneg_b:
1672 case Intrinsic::mips_bneg_h:
1673 case Intrinsic::mips_bneg_w:
1674 case Intrinsic::mips_bneg_d: {
1675 EVT VecTy = Op->getValueType(0);
Sergey Dmitrouk842a51b2015-04-28 14:05:47 +0000[diff] [blame]1676 SDValue One = DAG.getConstant(1, DL, VecTy);
Daniel Sandersa5bc99f2013-11-12 10:31:49 +0000[diff] [blame]1677
1678 return DAG.getNode(ISD::XOR, DL, VecTy, Op->getOperand(1),
1679 DAG.getNode(ISD::SHL, DL, VecTy, One,
1680 Op->getOperand(2)));
1681 }
1682 case Intrinsic::mips_bnegi_b:
1683 case Intrinsic::mips_bnegi_h:
1684 case Intrinsic::mips_bnegi_w:
1685 case Intrinsic::mips_bnegi_d:
1686 return lowerMSABinaryBitImmIntr(Op, DAG, ISD::XOR, Op->getOperand(2),
Eric Christopher1c29a652014-07-18 22:55:25 +0000[diff] [blame]1687 !Subtarget.isLittle());
Daniel Sandersce09d072013-08-28 12:14:50 +0000[diff] [blame]1688 case Intrinsic::mips_bnz_b:
1689 case Intrinsic::mips_bnz_h:
1690 case Intrinsic::mips_bnz_w:
1691 case Intrinsic::mips_bnz_d:
Daniel Sanders84e7caf2013-09-27 10:25:41 +0000[diff] [blame]1692 return DAG.getNode(MipsISD::VALL_NONZERO, DL, Op->getValueType(0),
1693 Op->getOperand(1));
Daniel Sandersce09d072013-08-28 12:14:50 +0000[diff] [blame]1694 case Intrinsic::mips_bnz_v:
Daniel Sanders84e7caf2013-09-27 10:25:41 +0000[diff] [blame]1695 return DAG.getNode(MipsISD::VANY_NONZERO, DL, Op->getValueType(0),
1696 Op->getOperand(1));
Daniel Sanderse1d24352013-09-24 12:04:44 +0000[diff] [blame]1697 case Intrinsic::mips_bsel_v:
Daniel Sandersdf2215452014-03-12 11:54:00 +0000[diff] [blame]1698 // bsel_v(Mask, IfClear, IfSet) -> (vselect Mask, IfSet, IfClear)
Daniel Sanders84e7caf2013-09-27 10:25:41 +0000[diff] [blame]1699 return DAG.getNode(ISD::VSELECT, DL, Op->getValueType(0),
Daniel Sandersdf2215452014-03-12 11:54:00 +0000[diff] [blame]1700 Op->getOperand(1), Op->getOperand(3),
1701 Op->getOperand(2));
Daniel Sanderse1d24352013-09-24 12:04:44 +0000[diff] [blame]1702 case Intrinsic::mips_bseli_b:
Daniel Sandersdf2215452014-03-12 11:54:00 +0000[diff] [blame]1703 // bseli_v(Mask, IfClear, IfSet) -> (vselect Mask, IfSet, IfClear)
Daniel Sanders84e7caf2013-09-27 10:25:41 +0000[diff] [blame]1704 return DAG.getNode(ISD::VSELECT, DL, Op->getValueType(0),
Daniel Sandersdf2215452014-03-12 11:54:00 +0000[diff] [blame]1705 Op->getOperand(1), lowerMSASplatImm(Op, 3, DAG),
1706 Op->getOperand(2));
Daniel Sandersa5bc99f2013-11-12 10:31:49 +0000[diff] [blame]1707 case Intrinsic::mips_bset_b:
1708 case Intrinsic::mips_bset_h:
1709 case Intrinsic::mips_bset_w:
1710 case Intrinsic::mips_bset_d: {
1711 EVT VecTy = Op->getValueType(0);
Sergey Dmitrouk842a51b2015-04-28 14:05:47 +0000[diff] [blame]1712 SDValue One = DAG.getConstant(1, DL, VecTy);
Daniel Sandersa5bc99f2013-11-12 10:31:49 +0000[diff] [blame]1713
1714 return DAG.getNode(ISD::OR, DL, VecTy, Op->getOperand(1),
1715 DAG.getNode(ISD::SHL, DL, VecTy, One,
1716 Op->getOperand(2)));
1717 }
1718 case Intrinsic::mips_bseti_b:
1719 case Intrinsic::mips_bseti_h:
1720 case Intrinsic::mips_bseti_w:
1721 case Intrinsic::mips_bseti_d:
1722 return lowerMSABinaryBitImmIntr(Op, DAG, ISD::OR, Op->getOperand(2),
Eric Christopher1c29a652014-07-18 22:55:25 +0000[diff] [blame]1723 !Subtarget.isLittle());
Daniel Sandersce09d072013-08-28 12:14:50 +0000[diff] [blame]1724 case Intrinsic::mips_bz_b:
1725 case Intrinsic::mips_bz_h:
1726 case Intrinsic::mips_bz_w:
1727 case Intrinsic::mips_bz_d:
Daniel Sanders84e7caf2013-09-27 10:25:41 +0000[diff] [blame]1728 return DAG.getNode(MipsISD::VALL_ZERO, DL, Op->getValueType(0),
1729 Op->getOperand(1));
Daniel Sandersce09d072013-08-28 12:14:50 +0000[diff] [blame]1730 case Intrinsic::mips_bz_v:
Daniel Sanders84e7caf2013-09-27 10:25:41 +0000[diff] [blame]1731 return DAG.getNode(MipsISD::VANY_ZERO, DL, Op->getValueType(0),
1732 Op->getOperand(1));
Daniel Sandersfd538dc2013-09-24 10:46:19 +0000[diff] [blame]1733 case Intrinsic::mips_ceq_b:
1734 case Intrinsic::mips_ceq_h:
1735 case Intrinsic::mips_ceq_w:
1736 case Intrinsic::mips_ceq_d:
Daniel Sanders84e7caf2013-09-27 10:25:41 +0000[diff] [blame]1737 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
Daniel Sandersfd538dc2013-09-24 10:46:19 +0000[diff] [blame]1738 Op->getOperand(2), ISD::SETEQ);
1739 case Intrinsic::mips_ceqi_b:
1740 case Intrinsic::mips_ceqi_h:
1741 case Intrinsic::mips_ceqi_w:
1742 case Intrinsic::mips_ceqi_d:
Daniel Sanders84e7caf2013-09-27 10:25:41 +0000[diff] [blame]1743 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
Daniel Sandersfd538dc2013-09-24 10:46:19 +0000[diff] [blame]1744 lowerMSASplatImm(Op, 2, DAG), ISD::SETEQ);
1745 case Intrinsic::mips_cle_s_b:
1746 case Intrinsic::mips_cle_s_h:
1747 case Intrinsic::mips_cle_s_w:
1748 case Intrinsic::mips_cle_s_d:
Daniel Sanders84e7caf2013-09-27 10:25:41 +0000[diff] [blame]1749 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
Daniel Sandersfd538dc2013-09-24 10:46:19 +0000[diff] [blame]1750 Op->getOperand(2), ISD::SETLE);
1751 case Intrinsic::mips_clei_s_b:
1752 case Intrinsic::mips_clei_s_h:
1753 case Intrinsic::mips_clei_s_w:
1754 case Intrinsic::mips_clei_s_d:
Daniel Sanders84e7caf2013-09-27 10:25:41 +0000[diff] [blame]1755 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
Daniel Sandersfd538dc2013-09-24 10:46:19 +0000[diff] [blame]1756 lowerMSASplatImm(Op, 2, DAG), ISD::SETLE);
1757 case Intrinsic::mips_cle_u_b:
1758 case Intrinsic::mips_cle_u_h:
1759 case Intrinsic::mips_cle_u_w:
1760 case Intrinsic::mips_cle_u_d:
Daniel Sanders84e7caf2013-09-27 10:25:41 +0000[diff] [blame]1761 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
Daniel Sandersfd538dc2013-09-24 10:46:19 +0000[diff] [blame]1762 Op->getOperand(2), ISD::SETULE);
1763 case Intrinsic::mips_clei_u_b:
1764 case Intrinsic::mips_clei_u_h:
1765 case Intrinsic::mips_clei_u_w:
1766 case Intrinsic::mips_clei_u_d:
Daniel Sanders84e7caf2013-09-27 10:25:41 +0000[diff] [blame]1767 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
Daniel Sandersfd538dc2013-09-24 10:46:19 +0000[diff] [blame]1768 lowerMSASplatImm(Op, 2, DAG), ISD::SETULE);
1769 case Intrinsic::mips_clt_s_b:
1770 case Intrinsic::mips_clt_s_h:
1771 case Intrinsic::mips_clt_s_w:
1772 case Intrinsic::mips_clt_s_d:
Daniel Sanders84e7caf2013-09-27 10:25:41 +0000[diff] [blame]1773 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
Daniel Sandersfd538dc2013-09-24 10:46:19 +0000[diff] [blame]1774 Op->getOperand(2), ISD::SETLT);
1775 case Intrinsic::mips_clti_s_b:
1776 case Intrinsic::mips_clti_s_h:
1777 case Intrinsic::mips_clti_s_w:
1778 case Intrinsic::mips_clti_s_d:
Daniel Sanders84e7caf2013-09-27 10:25:41 +0000[diff] [blame]1779 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
Daniel Sandersfd538dc2013-09-24 10:46:19 +0000[diff] [blame]1780 lowerMSASplatImm(Op, 2, DAG), ISD::SETLT);
1781 case Intrinsic::mips_clt_u_b:
1782 case Intrinsic::mips_clt_u_h:
1783 case Intrinsic::mips_clt_u_w:
1784 case Intrinsic::mips_clt_u_d:
Daniel Sanders84e7caf2013-09-27 10:25:41 +0000[diff] [blame]1785 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
Daniel Sandersfd538dc2013-09-24 10:46:19 +0000[diff] [blame]1786 Op->getOperand(2), ISD::SETULT);
1787 case Intrinsic::mips_clti_u_b:
1788 case Intrinsic::mips_clti_u_h:
1789 case Intrinsic::mips_clti_u_w:
1790 case Intrinsic::mips_clti_u_d:
Daniel Sanders84e7caf2013-09-27 10:25:41 +0000[diff] [blame]1791 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
Daniel Sandersfd538dc2013-09-24 10:46:19 +0000[diff] [blame]1792 lowerMSASplatImm(Op, 2, DAG), ISD::SETULT);
Daniel Sandersa4c8f3a2013-09-23 14:03:12 +0000[diff] [blame]1793 case Intrinsic::mips_copy_s_b:
1794 case Intrinsic::mips_copy_s_h:
1795 case Intrinsic::mips_copy_s_w:
1796 return lowerMSACopyIntr(Op, DAG, MipsISD::VEXTRACT_SEXT_ELT);
Daniel Sanders7f3d9462013-09-27 13:04:21 +0000[diff] [blame]1797 case Intrinsic::mips_copy_s_d:
Eric Christopher1c29a652014-07-18 22:55:25 +0000[diff] [blame]1798 if (Subtarget.hasMips64())
Matheus Almeida74070322014-01-29 14:05:28 +0000[diff] [blame]1799 // Lower directly into VEXTRACT_SEXT_ELT since i64 is legal on Mips64.
1800 return lowerMSACopyIntr(Op, DAG, MipsISD::VEXTRACT_SEXT_ELT);
1801 else {
1802 // Lower into the generic EXTRACT_VECTOR_ELT node and let the type
1803 // legalizer and EXTRACT_VECTOR_ELT lowering sort it out.
1804 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SDLoc(Op),
1805 Op->getValueType(0), Op->getOperand(1),
1806 Op->getOperand(2));
1807 }
Daniel Sandersa4c8f3a2013-09-23 14:03:12 +0000[diff] [blame]1808 case Intrinsic::mips_copy_u_b:
1809 case Intrinsic::mips_copy_u_h:
1810 case Intrinsic::mips_copy_u_w:
1811 return lowerMSACopyIntr(Op, DAG, MipsISD::VEXTRACT_ZEXT_ELT);
Daniel Sanders7f3d9462013-09-27 13:04:21 +0000[diff] [blame]1812 case Intrinsic::mips_copy_u_d:
Eric Christopher1c29a652014-07-18 22:55:25 +0000[diff] [blame]1813 if (Subtarget.hasMips64())
Matheus Almeida74070322014-01-29 14:05:28 +0000[diff] [blame]1814 // Lower directly into VEXTRACT_ZEXT_ELT since i64 is legal on Mips64.
1815 return lowerMSACopyIntr(Op, DAG, MipsISD::VEXTRACT_ZEXT_ELT);
1816 else {
1817 // Lower into the generic EXTRACT_VECTOR_ELT node and let the type
1818 // legalizer and EXTRACT_VECTOR_ELT lowering sort it out.
1819 // Note: When i64 is illegal, this results in copy_s.w instructions
1820 // instead of copy_u.w instructions. This makes no difference to the
1821 // behaviour since i64 is only illegal when the register file is 32-bit.
1822 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SDLoc(Op),
1823 Op->getValueType(0), Op->getOperand(1),
1824 Op->getOperand(2));
1825 }
Daniel Sanders607952b2013-09-11 10:38:58 +0000[diff] [blame]1826 case Intrinsic::mips_div_s_b:
1827 case Intrinsic::mips_div_s_h:
1828 case Intrinsic::mips_div_s_w:
1829 case Intrinsic::mips_div_s_d:
Daniel Sanders84e7caf2013-09-27 10:25:41 +0000[diff] [blame]1830 return DAG.getNode(ISD::SDIV, DL, Op->getValueType(0), Op->getOperand(1),
1831 Op->getOperand(2));
Daniel Sanders607952b2013-09-11 10:38:58 +0000[diff] [blame]1832 case Intrinsic::mips_div_u_b:
1833 case Intrinsic::mips_div_u_h:
1834 case Intrinsic::mips_div_u_w:
1835 case Intrinsic::mips_div_u_d:
Daniel Sanders84e7caf2013-09-27 10:25:41 +0000[diff] [blame]1836 return DAG.getNode(ISD::UDIV, DL, Op->getValueType(0), Op->getOperand(1),
1837 Op->getOperand(2));
Daniel Sandersf5bd9372013-09-11 10:51:30 +0000[diff] [blame]1838 case Intrinsic::mips_fadd_w:
Sanjay Patela2607012015-09-16 16:31:21 +0000[diff] [blame]1839 case Intrinsic::mips_fadd_d: {
1840 // TODO: If intrinsics have fast-math-flags, propagate them.
Daniel Sanders84e7caf2013-09-27 10:25:41 +0000[diff] [blame]1841 return DAG.getNode(ISD::FADD, DL, Op->getValueType(0), Op->getOperand(1),
1842 Op->getOperand(2));
Sanjay Patela2607012015-09-16 16:31:21 +0000[diff] [blame]1843 }
Daniel Sandersfd538dc2013-09-24 10:46:19 +0000[diff] [blame]1844 // Don't lower mips_fcaf_[wd] since LLVM folds SETFALSE condcodes away
1845 case Intrinsic::mips_fceq_w:
1846 case Intrinsic::mips_fceq_d:
Daniel Sanders84e7caf2013-09-27 10:25:41 +0000[diff] [blame]1847 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
Daniel Sandersfd538dc2013-09-24 10:46:19 +0000[diff] [blame]1848 Op->getOperand(2), ISD::SETOEQ);
1849 case Intrinsic::mips_fcle_w:
1850 case Intrinsic::mips_fcle_d:
Daniel Sanders84e7caf2013-09-27 10:25:41 +0000[diff] [blame]1851 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
Daniel Sandersfd538dc2013-09-24 10:46:19 +0000[diff] [blame]1852 Op->getOperand(2), ISD::SETOLE);
1853 case Intrinsic::mips_fclt_w:
1854 case Intrinsic::mips_fclt_d:
Daniel Sanders84e7caf2013-09-27 10:25:41 +0000[diff] [blame]1855 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
Daniel Sandersfd538dc2013-09-24 10:46:19 +0000[diff] [blame]1856 Op->getOperand(2), ISD::SETOLT);
1857 case Intrinsic::mips_fcne_w:
1858 case Intrinsic::mips_fcne_d:
Daniel Sanders84e7caf2013-09-27 10:25:41 +0000[diff] [blame]1859 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
Daniel Sandersfd538dc2013-09-24 10:46:19 +0000[diff] [blame]1860 Op->getOperand(2), ISD::SETONE);
1861 case Intrinsic::mips_fcor_w:
1862 case Intrinsic::mips_fcor_d:
Daniel Sanders84e7caf2013-09-27 10:25:41 +0000[diff] [blame]1863 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
Daniel Sandersfd538dc2013-09-24 10:46:19 +0000[diff] [blame]1864 Op->getOperand(2), ISD::SETO);
1865 case Intrinsic::mips_fcueq_w:
1866 case Intrinsic::mips_fcueq_d:
Daniel Sanders84e7caf2013-09-27 10:25:41 +0000[diff] [blame]1867 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
Daniel Sandersfd538dc2013-09-24 10:46:19 +0000[diff] [blame]1868 Op->getOperand(2), ISD::SETUEQ);
1869 case Intrinsic::mips_fcule_w:
1870 case Intrinsic::mips_fcule_d:
Daniel Sanders84e7caf2013-09-27 10:25:41 +0000[diff] [blame]1871 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
Daniel Sandersfd538dc2013-09-24 10:46:19 +0000[diff] [blame]1872 Op->getOperand(2), ISD::SETULE);
1873 case Intrinsic::mips_fcult_w:
1874 case Intrinsic::mips_fcult_d:
Daniel Sanders84e7caf2013-09-27 10:25:41 +0000[diff] [blame]1875 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
Daniel Sandersfd538dc2013-09-24 10:46:19 +0000[diff] [blame]1876 Op->getOperand(2), ISD::SETULT);
1877 case Intrinsic::mips_fcun_w:
1878 case Intrinsic::mips_fcun_d:
Daniel Sanders84e7caf2013-09-27 10:25:41 +0000[diff] [blame]1879 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
Daniel Sandersfd538dc2013-09-24 10:46:19 +0000[diff] [blame]1880 Op->getOperand(2), ISD::SETUO);
1881 case Intrinsic::mips_fcune_w:
1882 case Intrinsic::mips_fcune_d:
Daniel Sanders84e7caf2013-09-27 10:25:41 +0000[diff] [blame]1883 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
Daniel Sandersfd538dc2013-09-24 10:46:19 +0000[diff] [blame]1884 Op->getOperand(2), ISD::SETUNE);
Daniel Sandersf5bd9372013-09-11 10:51:30 +0000[diff] [blame]1885 case Intrinsic::mips_fdiv_w:
Sanjay Patela2607012015-09-16 16:31:21 +0000[diff] [blame]1886 case Intrinsic::mips_fdiv_d: {
1887 // TODO: If intrinsics have fast-math-flags, propagate them.
Daniel Sanders84e7caf2013-09-27 10:25:41 +0000[diff] [blame]1888 return DAG.getNode(ISD::FDIV, DL, Op->getValueType(0), Op->getOperand(1),
1889 Op->getOperand(2));
Sanjay Patela2607012015-09-16 16:31:21 +0000[diff] [blame]1890 }
Daniel Sanders015972b2013-10-11 10:00:06 +0000[diff] [blame]1891 case Intrinsic::mips_ffint_u_w:
1892 case Intrinsic::mips_ffint_u_d:
1893 return DAG.getNode(ISD::UINT_TO_FP, DL, Op->getValueType(0),
1894 Op->getOperand(1));
1895 case Intrinsic::mips_ffint_s_w:
1896 case Intrinsic::mips_ffint_s_d:
1897 return DAG.getNode(ISD::SINT_TO_FP, DL, Op->getValueType(0),
1898 Op->getOperand(1));
Daniel Sanders7a289d02013-09-23 12:02:46 +0000[diff] [blame]1899 case Intrinsic::mips_fill_b:
1900 case Intrinsic::mips_fill_h:
Daniel Sandersc72593e2013-09-27 13:20:41 +0000[diff] [blame]1901 case Intrinsic::mips_fill_w:
1902 case Intrinsic::mips_fill_d: {
Daniel Sandersf49dd822013-09-24 13:33:07 +0000[diff] [blame]1903 EVT ResTy = Op->getValueType(0);
Benjamin Kramer6cd780f2015-02-17 15:29:18 +0000[diff] [blame]1904 SmallVector<SDValue, 16> Ops(ResTy.getVectorNumElements(),
1905 Op->getOperand(1));
Daniel Sandersf49dd822013-09-24 13:33:07 +0000[diff] [blame]1906
Daniel Sandersc72593e2013-09-27 13:20:41 +0000[diff] [blame]1907 // If ResTy is v2i64 then the type legalizer will break this node down into
1908 // an equivalent v4i32.
Ahmed Bougacha128f8732016-04-26 21:15:30 +0000[diff] [blame]1909 return DAG.getBuildVector(ResTy, DL, Ops);
Daniel Sandersf49dd822013-09-24 13:33:07 +0000[diff] [blame]1910 }
Daniel Sandersa9521602013-10-23 10:36:52 +0000[diff] [blame]1911 case Intrinsic::mips_fexp2_w:
1912 case Intrinsic::mips_fexp2_d: {
Sanjay Patela2607012015-09-16 16:31:21 +0000[diff] [blame]1913 // TODO: If intrinsics have fast-math-flags, propagate them.
Daniel Sandersa9521602013-10-23 10:36:52 +0000[diff] [blame]1914 EVT ResTy = Op->getValueType(0);
1915 return DAG.getNode(
1916 ISD::FMUL, SDLoc(Op), ResTy, Op->getOperand(1),
1917 DAG.getNode(ISD::FEXP2, SDLoc(Op), ResTy, Op->getOperand(2)));
1918 }
Daniel Sandersf5bd9372013-09-11 10:51:30 +0000[diff] [blame]1919 case Intrinsic::mips_flog2_w:
1920 case Intrinsic::mips_flog2_d:
Daniel Sanders84e7caf2013-09-27 10:25:41 +0000[diff] [blame]1921 return DAG.getNode(ISD::FLOG2, DL, Op->getValueType(0), Op->getOperand(1));
Daniel Sandersd7103f32013-10-11 10:14:25 +0000[diff] [blame]1922 case Intrinsic::mips_fmadd_w:
1923 case Intrinsic::mips_fmadd_d:
1924 return DAG.getNode(ISD::FMA, SDLoc(Op), Op->getValueType(0),
1925 Op->getOperand(1), Op->getOperand(2), Op->getOperand(3));
Daniel Sandersf5bd9372013-09-11 10:51:30 +0000[diff] [blame]1926 case Intrinsic::mips_fmul_w:
Sanjay Patela2607012015-09-16 16:31:21 +0000[diff] [blame]1927 case Intrinsic::mips_fmul_d: {
1928 // TODO: If intrinsics have fast-math-flags, propagate them.
Daniel Sanders84e7caf2013-09-27 10:25:41 +0000[diff] [blame]1929 return DAG.getNode(ISD::FMUL, DL, Op->getValueType(0), Op->getOperand(1),
1930 Op->getOperand(2));
Sanjay Patela2607012015-09-16 16:31:21 +0000[diff] [blame]1931 }
Daniel Sanderse67bd872013-10-11 10:27:32 +0000[diff] [blame]1932 case Intrinsic::mips_fmsub_w:
1933 case Intrinsic::mips_fmsub_d: {
Sanjay Patela2607012015-09-16 16:31:21 +0000[diff] [blame]1934 // TODO: If intrinsics have fast-math-flags, propagate them.
Daniel Sanderse67bd872013-10-11 10:27:32 +0000[diff] [blame]1935 EVT ResTy = Op->getValueType(0);
1936 return DAG.getNode(ISD::FSUB, SDLoc(Op), ResTy, Op->getOperand(1),
1937 DAG.getNode(ISD::FMUL, SDLoc(Op), ResTy,
1938 Op->getOperand(2), Op->getOperand(3)));
1939 }
Daniel Sandersf5bd9372013-09-11 10:51:30 +0000[diff] [blame]1940 case Intrinsic::mips_frint_w:
1941 case Intrinsic::mips_frint_d:
Daniel Sanders84e7caf2013-09-27 10:25:41 +0000[diff] [blame]1942 return DAG.getNode(ISD::FRINT, DL, Op->getValueType(0), Op->getOperand(1));
Daniel Sandersf5bd9372013-09-11 10:51:30 +0000[diff] [blame]1943 case Intrinsic::mips_fsqrt_w:
1944 case Intrinsic::mips_fsqrt_d:
Daniel Sanders84e7caf2013-09-27 10:25:41 +0000[diff] [blame]1945 return DAG.getNode(ISD::FSQRT, DL, Op->getValueType(0), Op->getOperand(1));
Daniel Sandersf5bd9372013-09-11 10:51:30 +0000[diff] [blame]1946 case Intrinsic::mips_fsub_w:
Sanjay Patela2607012015-09-16 16:31:21 +0000[diff] [blame]1947 case Intrinsic::mips_fsub_d: {
1948 // TODO: If intrinsics have fast-math-flags, propagate them.
Daniel Sanders84e7caf2013-09-27 10:25:41 +0000[diff] [blame]1949 return DAG.getNode(ISD::FSUB, DL, Op->getValueType(0), Op->getOperand(1),
1950 Op->getOperand(2));
Sanjay Patela2607012015-09-16 16:31:21 +0000[diff] [blame]1951 }
Daniel Sanders015972b2013-10-11 10:00:06 +0000[diff] [blame]1952 case Intrinsic::mips_ftrunc_u_w:
1953 case Intrinsic::mips_ftrunc_u_d:
1954 return DAG.getNode(ISD::FP_TO_UINT, DL, Op->getValueType(0),
1955 Op->getOperand(1));
1956 case Intrinsic::mips_ftrunc_s_w:
1957 case Intrinsic::mips_ftrunc_s_d:
1958 return DAG.getNode(ISD::FP_TO_SINT, DL, Op->getValueType(0),
1959 Op->getOperand(1));
Daniel Sanders2ed228b2013-09-24 14:36:12 +0000[diff] [blame]1960 case Intrinsic::mips_ilvev_b:
1961 case Intrinsic::mips_ilvev_h:
1962 case Intrinsic::mips_ilvev_w:
1963 case Intrinsic::mips_ilvev_d:
Daniel Sanders84e7caf2013-09-27 10:25:41 +0000[diff] [blame]1964 return DAG.getNode(MipsISD::ILVEV, DL, Op->getValueType(0),
Daniel Sanders2ed228b2013-09-24 14:36:12 +0000[diff] [blame]1965 Op->getOperand(1), Op->getOperand(2));
1966 case Intrinsic::mips_ilvl_b:
1967 case Intrinsic::mips_ilvl_h:
1968 case Intrinsic::mips_ilvl_w:
1969 case Intrinsic::mips_ilvl_d:
Daniel Sanders84e7caf2013-09-27 10:25:41 +0000[diff] [blame]1970 return DAG.getNode(MipsISD::ILVL, DL, Op->getValueType(0),
Daniel Sanders2ed228b2013-09-24 14:36:12 +0000[diff] [blame]1971 Op->getOperand(1), Op->getOperand(2));
1972 case Intrinsic::mips_ilvod_b:
1973 case Intrinsic::mips_ilvod_h:
1974 case Intrinsic::mips_ilvod_w:
1975 case Intrinsic::mips_ilvod_d:
Daniel Sanders84e7caf2013-09-27 10:25:41 +0000[diff] [blame]1976 return DAG.getNode(MipsISD::ILVOD, DL, Op->getValueType(0),
Daniel Sanders2ed228b2013-09-24 14:36:12 +0000[diff] [blame]1977 Op->getOperand(1), Op->getOperand(2));
1978 case Intrinsic::mips_ilvr_b:
1979 case Intrinsic::mips_ilvr_h:
1980 case Intrinsic::mips_ilvr_w:
1981 case Intrinsic::mips_ilvr_d:
Daniel Sanders84e7caf2013-09-27 10:25:41 +0000[diff] [blame]1982 return DAG.getNode(MipsISD::ILVR, DL, Op->getValueType(0),
Daniel Sanders2ed228b2013-09-24 14:36:12 +0000[diff] [blame]1983 Op->getOperand(1), Op->getOperand(2));
Daniel Sandersa4c8f3a2013-09-23 14:03:12 +0000[diff] [blame]1984 case Intrinsic::mips_insert_b:
1985 case Intrinsic::mips_insert_h:
1986 case Intrinsic::mips_insert_w:
Daniel Sanders6098b332013-09-27 13:36:54 +0000[diff] [blame]1987 case Intrinsic::mips_insert_d:
1988 return DAG.getNode(ISD::INSERT_VECTOR_ELT, SDLoc(Op), Op->getValueType(0),
1989 Op->getOperand(1), Op->getOperand(3), Op->getOperand(2));
Daniel Sandersb50ccf82014-04-01 10:35:28 +0000[diff] [blame]1990 case Intrinsic::mips_insve_b:
1991 case Intrinsic::mips_insve_h:
1992 case Intrinsic::mips_insve_w:
1993 case Intrinsic::mips_insve_d:
1994 return DAG.getNode(MipsISD::INSVE, DL, Op->getValueType(0),
1995 Op->getOperand(1), Op->getOperand(2), Op->getOperand(3),
Sergey Dmitrouk842a51b2015-04-28 14:05:47 +0000[diff] [blame]1996 DAG.getConstant(0, DL, MVT::i32));
Daniel Sanders7a289d02013-09-23 12:02:46 +0000[diff] [blame]1997 case Intrinsic::mips_ldi_b:
1998 case Intrinsic::mips_ldi_h:
1999 case Intrinsic::mips_ldi_w:
2000 case Intrinsic::mips_ldi_d:
Daniel Sandersf49dd822013-09-24 13:33:07 +0000[diff] [blame]2001 return lowerMSASplatImm(Op, 1, DAG);
Matheus Almeida4b27eb52014-02-10 12:05:17 +0000[diff] [blame]2002 case Intrinsic::mips_lsa:
2003 case Intrinsic::mips_dlsa: {
Daniel Sandersa4eaf592013-10-17 13:38:20 +0000[diff] [blame]2004 EVT ResTy = Op->getValueType(0);
2005 return DAG.getNode(ISD::ADD, SDLoc(Op), ResTy, Op->getOperand(1),
2006 DAG.getNode(ISD::SHL, SDLoc(Op), ResTy,
2007 Op->getOperand(2), Op->getOperand(3)));
2008 }
Daniel Sanders50e5ed32013-10-11 10:50:42 +0000[diff] [blame]2009 case Intrinsic::mips_maddv_b:
2010 case Intrinsic::mips_maddv_h:
2011 case Intrinsic::mips_maddv_w:
2012 case Intrinsic::mips_maddv_d: {
2013 EVT ResTy = Op->getValueType(0);
2014 return DAG.getNode(ISD::ADD, SDLoc(Op), ResTy, Op->getOperand(1),
2015 DAG.getNode(ISD::MUL, SDLoc(Op), ResTy,
2016 Op->getOperand(2), Op->getOperand(3)));
2017 }
Daniel Sanders3ce56622013-09-24 12:18:31 +0000[diff] [blame]2018 case Intrinsic::mips_max_s_b:
2019 case Intrinsic::mips_max_s_h:
2020 case Intrinsic::mips_max_s_w:
2021 case Intrinsic::mips_max_s_d:
Daniel Sanders84e7caf2013-09-27 10:25:41 +0000[diff] [blame]2022 return DAG.getNode(MipsISD::VSMAX, DL, Op->getValueType(0),
2023 Op->getOperand(1), Op->getOperand(2));
Daniel Sanders3ce56622013-09-24 12:18:31 +0000[diff] [blame]2024 case Intrinsic::mips_max_u_b:
2025 case Intrinsic::mips_max_u_h:
2026 case Intrinsic::mips_max_u_w:
2027 case Intrinsic::mips_max_u_d:
Daniel Sanders84e7caf2013-09-27 10:25:41 +0000[diff] [blame]2028 return DAG.getNode(MipsISD::VUMAX, DL, Op->getValueType(0),
2029 Op->getOperand(1), Op->getOperand(2));
Daniel Sanders3ce56622013-09-24 12:18:31 +0000[diff] [blame]2030 case Intrinsic::mips_maxi_s_b:
2031 case Intrinsic::mips_maxi_s_h:
2032 case Intrinsic::mips_maxi_s_w:
2033 case Intrinsic::mips_maxi_s_d:
Daniel Sanders84e7caf2013-09-27 10:25:41 +0000[diff] [blame]2034 return DAG.getNode(MipsISD::VSMAX, DL, Op->getValueType(0),
2035 Op->getOperand(1), lowerMSASplatImm(Op, 2, DAG));
Daniel Sanders3ce56622013-09-24 12:18:31 +0000[diff] [blame]2036 case Intrinsic::mips_maxi_u_b:
2037 case Intrinsic::mips_maxi_u_h:
2038 case Intrinsic::mips_maxi_u_w:
2039 case Intrinsic::mips_maxi_u_d:
Daniel Sanders84e7caf2013-09-27 10:25:41 +0000[diff] [blame]2040 return DAG.getNode(MipsISD::VUMAX, DL, Op->getValueType(0),
2041 Op->getOperand(1), lowerMSASplatImm(Op, 2, DAG));
Daniel Sanders3ce56622013-09-24 12:18:31 +0000[diff] [blame]2042 case Intrinsic::mips_min_s_b:
2043 case Intrinsic::mips_min_s_h:
2044 case Intrinsic::mips_min_s_w:
2045 case Intrinsic::mips_min_s_d:
Daniel Sanders84e7caf2013-09-27 10:25:41 +0000[diff] [blame]2046 return DAG.getNode(MipsISD::VSMIN, DL, Op->getValueType(0),
2047 Op->getOperand(1), Op->getOperand(2));
Daniel Sanders3ce56622013-09-24 12:18:31 +0000[diff] [blame]2048 case Intrinsic::mips_min_u_b:
2049 case Intrinsic::mips_min_u_h:
2050 case Intrinsic::mips_min_u_w:
2051 case Intrinsic::mips_min_u_d:
Daniel Sanders84e7caf2013-09-27 10:25:41 +0000[diff] [blame]2052 return DAG.getNode(MipsISD::VUMIN, DL, Op->getValueType(0),
2053 Op->getOperand(1), Op->getOperand(2));
Daniel Sanders3ce56622013-09-24 12:18:31 +0000[diff] [blame]2054 case Intrinsic::mips_mini_s_b:
2055 case Intrinsic::mips_mini_s_h:
2056 case Intrinsic::mips_mini_s_w:
2057 case Intrinsic::mips_mini_s_d:
Daniel Sanders84e7caf2013-09-27 10:25:41 +0000[diff] [blame]2058 return DAG.getNode(MipsISD::VSMIN, DL, Op->getValueType(0),
2059 Op->getOperand(1), lowerMSASplatImm(Op, 2, DAG));
Daniel Sanders3ce56622013-09-24 12:18:31 +0000[diff] [blame]2060 case Intrinsic::mips_mini_u_b:
2061 case Intrinsic::mips_mini_u_h:
2062 case Intrinsic::mips_mini_u_w:
2063 case Intrinsic::mips_mini_u_d:
Daniel Sanders84e7caf2013-09-27 10:25:41 +0000[diff] [blame]2064 return DAG.getNode(MipsISD::VUMIN, DL, Op->getValueType(0),
2065 Op->getOperand(1), lowerMSASplatImm(Op, 2, DAG));
Daniel Sanders0210dd42013-10-01 10:22:35 +0000[diff] [blame]2066 case Intrinsic::mips_mod_s_b:
2067 case Intrinsic::mips_mod_s_h:
2068 case Intrinsic::mips_mod_s_w:
2069 case Intrinsic::mips_mod_s_d:
2070 return DAG.getNode(ISD::SREM, DL, Op->getValueType(0), Op->getOperand(1),
2071 Op->getOperand(2));
2072 case Intrinsic::mips_mod_u_b:
2073 case Intrinsic::mips_mod_u_h:
2074 case Intrinsic::mips_mod_u_w:
2075 case Intrinsic::mips_mod_u_d:
2076 return DAG.getNode(ISD::UREM, DL, Op->getValueType(0), Op->getOperand(1),
2077 Op->getOperand(2));
Daniel Sandersfbcb5822013-09-11 11:58:30 +0000[diff] [blame]2078 case Intrinsic::mips_mulv_b:
2079 case Intrinsic::mips_mulv_h:
2080 case Intrinsic::mips_mulv_w:
2081 case Intrinsic::mips_mulv_d:
Daniel Sanders84e7caf2013-09-27 10:25:41 +0000[diff] [blame]2082 return DAG.getNode(ISD::MUL, DL, Op->getValueType(0), Op->getOperand(1),
2083 Op->getOperand(2));
Daniel Sanders50e5ed32013-10-11 10:50:42 +0000[diff] [blame]2084 case Intrinsic::mips_msubv_b:
2085 case Intrinsic::mips_msubv_h:
2086 case Intrinsic::mips_msubv_w:
2087 case Intrinsic::mips_msubv_d: {
2088 EVT ResTy = Op->getValueType(0);
2089 return DAG.getNode(ISD::SUB, SDLoc(Op), ResTy, Op->getOperand(1),
2090 DAG.getNode(ISD::MUL, SDLoc(Op), ResTy,
2091 Op->getOperand(2), Op->getOperand(3)));
2092 }
Daniel Sandersfbcb5822013-09-11 11:58:30 +0000[diff] [blame]2093 case Intrinsic::mips_nlzc_b:
2094 case Intrinsic::mips_nlzc_h:
2095 case Intrinsic::mips_nlzc_w:
2096 case Intrinsic::mips_nlzc_d:
Daniel Sanders84e7caf2013-09-27 10:25:41 +0000[diff] [blame]2097 return DAG.getNode(ISD::CTLZ, DL, Op->getValueType(0), Op->getOperand(1));
Daniel Sandersf7456c72013-09-23 13:22:24 +0000[diff] [blame]2098 case Intrinsic::mips_nor_v: {
Daniel Sanders84e7caf2013-09-27 10:25:41 +0000[diff] [blame]2099 SDValue Res = DAG.getNode(ISD::OR, DL, Op->getValueType(0),
2100 Op->getOperand(1), Op->getOperand(2));
2101 return DAG.getNOT(DL, Res, Res->getValueType(0));
Daniel Sandersf7456c72013-09-23 13:22:24 +0000[diff] [blame]2102 }
Daniel Sandersbfc39ce2013-09-24 12:32:47 +0000[diff] [blame]2103 case Intrinsic::mips_nori_b: {
Daniel Sanders84e7caf2013-09-27 10:25:41 +0000[diff] [blame]2104 SDValue Res = DAG.getNode(ISD::OR, DL, Op->getValueType(0),
2105 Op->getOperand(1),
2106 lowerMSASplatImm(Op, 2, DAG));
2107 return DAG.getNOT(DL, Res, Res->getValueType(0));
Daniel Sandersbfc39ce2013-09-24 12:32:47 +0000[diff] [blame]2108 }
Daniel Sanders8ca81e42013-09-23 12:57:42 +0000[diff] [blame]2109 case Intrinsic::mips_or_v:
Daniel Sanders84e7caf2013-09-27 10:25:41 +0000[diff] [blame]2110 return DAG.getNode(ISD::OR, DL, Op->getValueType(0), Op->getOperand(1),
2111 Op->getOperand(2));
Daniel Sandersbfc39ce2013-09-24 12:32:47 +0000[diff] [blame]2112 case Intrinsic::mips_ori_b:
Daniel Sanders84e7caf2013-09-27 10:25:41 +0000[diff] [blame]2113 return DAG.getNode(ISD::OR, DL, Op->getValueType(0),
2114 Op->getOperand(1), lowerMSASplatImm(Op, 2, DAG));
Daniel Sandersfae5f2a2013-09-24 14:53:25 +0000[diff] [blame]2115 case Intrinsic::mips_pckev_b:
2116 case Intrinsic::mips_pckev_h:
2117 case Intrinsic::mips_pckev_w:
2118 case Intrinsic::mips_pckev_d:
Daniel Sanders84e7caf2013-09-27 10:25:41 +0000[diff] [blame]2119 return DAG.getNode(MipsISD::PCKEV, DL, Op->getValueType(0),
Daniel Sandersfae5f2a2013-09-24 14:53:25 +0000[diff] [blame]2120 Op->getOperand(1), Op->getOperand(2));
2121 case Intrinsic::mips_pckod_b:
2122 case Intrinsic::mips_pckod_h:
2123 case Intrinsic::mips_pckod_w:
2124 case Intrinsic::mips_pckod_d:
Daniel Sanders84e7caf2013-09-27 10:25:41 +0000[diff] [blame]2125 return DAG.getNode(MipsISD::PCKOD, DL, Op->getValueType(0),
Daniel Sandersfae5f2a2013-09-24 14:53:25 +0000[diff] [blame]2126 Op->getOperand(1), Op->getOperand(2));
Daniel Sanders766cb692013-09-23 13:40:21 +0000[diff] [blame]2127 case Intrinsic::mips_pcnt_b:
2128 case Intrinsic::mips_pcnt_h:
2129 case Intrinsic::mips_pcnt_w:
2130 case Intrinsic::mips_pcnt_d:
Daniel Sanders84e7caf2013-09-27 10:25:41 +0000[diff] [blame]2131 return DAG.getNode(ISD::CTPOP, DL, Op->getValueType(0), Op->getOperand(1));
Daniel Sanders26307182013-09-24 14:20:00 +0000[diff] [blame]2132 case Intrinsic::mips_shf_b:
2133 case Intrinsic::mips_shf_h:
2134 case Intrinsic::mips_shf_w:
Daniel Sanders84e7caf2013-09-27 10:25:41 +0000[diff] [blame]2135 return DAG.getNode(MipsISD::SHF, DL, Op->getValueType(0),
Daniel Sanders26307182013-09-24 14:20:00 +0000[diff] [blame]2136 Op->getOperand(2), Op->getOperand(1));
Daniel Sandersfbcb5822013-09-11 11:58:30 +0000[diff] [blame]2137 case Intrinsic::mips_sll_b:
2138 case Intrinsic::mips_sll_h:
2139 case Intrinsic::mips_sll_w:
2140 case Intrinsic::mips_sll_d:
Daniel Sanders84e7caf2013-09-27 10:25:41 +0000[diff] [blame]2141 return DAG.getNode(ISD::SHL, DL, Op->getValueType(0), Op->getOperand(1),
2142 Op->getOperand(2));
Daniel Sanderscba19222013-09-24 10:28:18 +0000[diff] [blame]2143 case Intrinsic::mips_slli_b:
2144 case Intrinsic::mips_slli_h:
2145 case Intrinsic::mips_slli_w:
2146 case Intrinsic::mips_slli_d:
Daniel Sanders84e7caf2013-09-27 10:25:41 +0000[diff] [blame]2147 return DAG.getNode(ISD::SHL, DL, Op->getValueType(0),
2148 Op->getOperand(1), lowerMSASplatImm(Op, 2, DAG));
Daniel Sanderse7ef0c82013-10-30 13:07:44 +0000[diff] [blame]2149 case Intrinsic::mips_splat_b:
2150 case Intrinsic::mips_splat_h:
2151 case Intrinsic::mips_splat_w:
2152 case Intrinsic::mips_splat_d:
2153 // We can't lower via VECTOR_SHUFFLE because it requires constant shuffle
2154 // masks, nor can we lower via BUILD_VECTOR & EXTRACT_VECTOR_ELT because
2155 // EXTRACT_VECTOR_ELT can't extract i64's on MIPS32.
2156 // Instead we lower to MipsISD::VSHF and match from there.
2157 return DAG.getNode(MipsISD::VSHF, DL, Op->getValueType(0),
Daniel Sanders50b80412013-11-15 12:56:49 +0000[diff] [blame]2158 lowerMSASplatZExt(Op, 2, DAG), Op->getOperand(1),
Daniel Sanderse7ef0c82013-10-30 13:07:44 +0000[diff] [blame]2159 Op->getOperand(1));
Daniel Sanders7e51fe12013-09-27 11:48:57 +0000[diff] [blame]2160 case Intrinsic::mips_splati_b:
2161 case Intrinsic::mips_splati_h:
2162 case Intrinsic::mips_splati_w:
2163 case Intrinsic::mips_splati_d:
2164 return DAG.getNode(MipsISD::VSHF, DL, Op->getValueType(0),
2165 lowerMSASplatImm(Op, 2, DAG), Op->getOperand(1),
2166 Op->getOperand(1));
Daniel Sandersfbcb5822013-09-11 11:58:30 +0000[diff] [blame]2167 case Intrinsic::mips_sra_b:
2168 case Intrinsic::mips_sra_h:
2169 case Intrinsic::mips_sra_w:
2170 case Intrinsic::mips_sra_d:
Daniel Sanders84e7caf2013-09-27 10:25:41 +0000[diff] [blame]2171 return DAG.getNode(ISD::SRA, DL, Op->getValueType(0), Op->getOperand(1),
2172 Op->getOperand(2));
Daniel Sanderscba19222013-09-24 10:28:18 +0000[diff] [blame]2173 case Intrinsic::mips_srai_b:
2174 case Intrinsic::mips_srai_h:
2175 case Intrinsic::mips_srai_w:
2176 case Intrinsic::mips_srai_d:
Daniel Sanders84e7caf2013-09-27 10:25:41 +0000[diff] [blame]2177 return DAG.getNode(ISD::SRA, DL, Op->getValueType(0),
2178 Op->getOperand(1), lowerMSASplatImm(Op, 2, DAG));
Daniel Sandersfbcb5822013-09-11 11:58:30 +0000[diff] [blame]2179 case Intrinsic::mips_srl_b:
2180 case Intrinsic::mips_srl_h:
2181 case Intrinsic::mips_srl_w:
2182 case Intrinsic::mips_srl_d:
Daniel Sanders84e7caf2013-09-27 10:25:41 +0000[diff] [blame]2183 return DAG.getNode(ISD::SRL, DL, Op->getValueType(0), Op->getOperand(1),
2184 Op->getOperand(2));
Daniel Sanderscba19222013-09-24 10:28:18 +0000[diff] [blame]2185 case Intrinsic::mips_srli_b:
2186 case Intrinsic::mips_srli_h:
2187 case Intrinsic::mips_srli_w:
2188 case Intrinsic::mips_srli_d:
Daniel Sanders84e7caf2013-09-27 10:25:41 +0000[diff] [blame]2189 return DAG.getNode(ISD::SRL, DL, Op->getValueType(0),
2190 Op->getOperand(1), lowerMSASplatImm(Op, 2, DAG));
Daniel Sandersfbcb5822013-09-11 11:58:30 +0000[diff] [blame]2191 case Intrinsic::mips_subv_b:
2192 case Intrinsic::mips_subv_h:
2193 case Intrinsic::mips_subv_w:
2194 case Intrinsic::mips_subv_d:
Daniel Sanders84e7caf2013-09-27 10:25:41 +0000[diff] [blame]2195 return DAG.getNode(ISD::SUB, DL, Op->getValueType(0), Op->getOperand(1),
2196 Op->getOperand(2));
Daniel Sanders86d0c8d2013-09-23 14:29:55 +0000[diff] [blame]2197 case Intrinsic::mips_subvi_b:
2198 case Intrinsic::mips_subvi_h:
2199 case Intrinsic::mips_subvi_w:
2200 case Intrinsic::mips_subvi_d:
Daniel Sanders84e7caf2013-09-27 10:25:41 +0000[diff] [blame]2201 return DAG.getNode(ISD::SUB, DL, Op->getValueType(0),
2202 Op->getOperand(1), lowerMSASplatImm(Op, 2, DAG));
Daniel Sanderse5087042013-09-24 14:02:15 +0000[diff] [blame]2203 case Intrinsic::mips_vshf_b:
2204 case Intrinsic::mips_vshf_h:
2205 case Intrinsic::mips_vshf_w:
2206 case Intrinsic::mips_vshf_d:
Daniel Sanders84e7caf2013-09-27 10:25:41 +0000[diff] [blame]2207 return DAG.getNode(MipsISD::VSHF, DL, Op->getValueType(0),
Daniel Sanderse5087042013-09-24 14:02:15 +0000[diff] [blame]2208 Op->getOperand(1), Op->getOperand(2), Op->getOperand(3));
Daniel Sanders8ca81e42013-09-23 12:57:42 +0000[diff] [blame]2209 case Intrinsic::mips_xor_v:
Daniel Sanders84e7caf2013-09-27 10:25:41 +0000[diff] [blame]2210 return DAG.getNode(ISD::XOR, DL, Op->getValueType(0), Op->getOperand(1),
2211 Op->getOperand(2));
Daniel Sandersbfc39ce2013-09-24 12:32:47 +0000[diff] [blame]2212 case Intrinsic::mips_xori_b:
Daniel Sanders84e7caf2013-09-27 10:25:41 +0000[diff] [blame]2213 return DAG.getNode(ISD::XOR, DL, Op->getValueType(0),
2214 Op->getOperand(1), lowerMSASplatImm(Op, 2, DAG));
Marcin Koscielnicki7efdca52016-04-27 17:21:49 +0000[diff] [blame]2215 case Intrinsic::thread_pointer: {
2216 EVT PtrVT = getPointerTy(DAG.getDataLayout());
2217 return DAG.getNode(MipsISD::ThreadPointer, DL, PtrVT);
2218 }
Akira Hatanakaa6bbde52013-04-13 02:13:30 +0000[diff] [blame]2219 }
2220}
2221
Daniel Sanderse6ed5b72013-08-28 12:04:29 +0000[diff] [blame]2222static SDValue lowerMSALoadIntr(SDValue Op, SelectionDAG &DAG, unsigned Intr) {
2223 SDLoc DL(Op);
2224 SDValue ChainIn = Op->getOperand(0);
2225 SDValue Address = Op->getOperand(2);
2226 SDValue Offset = Op->getOperand(3);
2227 EVT ResTy = Op->getValueType(0);
2228 EVT PtrTy = Address->getValueType(0);
2229
2230 Address = DAG.getNode(ISD::ADD, DL, PtrTy, Address, Offset);
Justin Lebar9c375812016-07-15 18:27:10 +0000[diff] [blame]2231 return DAG.getLoad(ResTy, DL, ChainIn, Address, MachinePointerInfo(),
2232 /* Alignment = */ 16);
Daniel Sanderse6ed5b72013-08-28 12:04:29 +0000[diff] [blame]2233}
2234
Akira Hatanakaa6bbde52013-04-13 02:13:30 +0000[diff] [blame]2235SDValue MipsSETargetLowering::lowerINTRINSIC_W_CHAIN(SDValue Op,
2236 SelectionDAG &DAG) const {
Daniel Sanderse6ed5b72013-08-28 12:04:29 +0000[diff] [blame]2237 unsigned Intr = cast<ConstantSDNode>(Op->getOperand(1))->getZExtValue();
2238 switch (Intr) {
Akira Hatanakaa6bbde52013-04-13 02:13:30 +0000[diff] [blame]2239 default:
2240 return SDValue();
2241 case Intrinsic::mips_extp:
2242 return lowerDSPIntr(Op, DAG, MipsISD::EXTP);
2243 case Intrinsic::mips_extpdp:
2244 return lowerDSPIntr(Op, DAG, MipsISD::EXTPDP);
2245 case Intrinsic::mips_extr_w:
2246 return lowerDSPIntr(Op, DAG, MipsISD::EXTR_W);
2247 case Intrinsic::mips_extr_r_w:
2248 return lowerDSPIntr(Op, DAG, MipsISD::EXTR_R_W);
2249 case Intrinsic::mips_extr_rs_w:
2250 return lowerDSPIntr(Op, DAG, MipsISD::EXTR_RS_W);
2251 case Intrinsic::mips_extr_s_h:
2252 return lowerDSPIntr(Op, DAG, MipsISD::EXTR_S_H);
2253 case Intrinsic::mips_mthlip:
2254 return lowerDSPIntr(Op, DAG, MipsISD::MTHLIP);
2255 case Intrinsic::mips_mulsaq_s_w_ph:
2256 return lowerDSPIntr(Op, DAG, MipsISD::MULSAQ_S_W_PH);
2257 case Intrinsic::mips_maq_s_w_phl:
2258 return lowerDSPIntr(Op, DAG, MipsISD::MAQ_S_W_PHL);
2259 case Intrinsic::mips_maq_s_w_phr:
2260 return lowerDSPIntr(Op, DAG, MipsISD::MAQ_S_W_PHR);
2261 case Intrinsic::mips_maq_sa_w_phl:
2262 return lowerDSPIntr(Op, DAG, MipsISD::MAQ_SA_W_PHL);
2263 case Intrinsic::mips_maq_sa_w_phr:
2264 return lowerDSPIntr(Op, DAG, MipsISD::MAQ_SA_W_PHR);
2265 case Intrinsic::mips_dpaq_s_w_ph:
2266 return lowerDSPIntr(Op, DAG, MipsISD::DPAQ_S_W_PH);
2267 case Intrinsic::mips_dpsq_s_w_ph:
2268 return lowerDSPIntr(Op, DAG, MipsISD::DPSQ_S_W_PH);
2269 case Intrinsic::mips_dpaq_sa_l_w:
2270 return lowerDSPIntr(Op, DAG, MipsISD::DPAQ_SA_L_W);
2271 case Intrinsic::mips_dpsq_sa_l_w:
2272 return lowerDSPIntr(Op, DAG, MipsISD::DPSQ_SA_L_W);
2273 case Intrinsic::mips_dpaqx_s_w_ph:
2274 return lowerDSPIntr(Op, DAG, MipsISD::DPAQX_S_W_PH);
2275 case Intrinsic::mips_dpaqx_sa_w_ph:
2276 return lowerDSPIntr(Op, DAG, MipsISD::DPAQX_SA_W_PH);
2277 case Intrinsic::mips_dpsqx_s_w_ph:
2278 return lowerDSPIntr(Op, DAG, MipsISD::DPSQX_S_W_PH);
2279 case Intrinsic::mips_dpsqx_sa_w_ph:
2280 return lowerDSPIntr(Op, DAG, MipsISD::DPSQX_SA_W_PH);
Daniel Sanderse6ed5b72013-08-28 12:04:29 +0000[diff] [blame]2281 case Intrinsic::mips_ld_b:
2282 case Intrinsic::mips_ld_h:
2283 case Intrinsic::mips_ld_w:
2284 case Intrinsic::mips_ld_d:
Daniel Sanderse6ed5b72013-08-28 12:04:29 +0000[diff] [blame]2285 return lowerMSALoadIntr(Op, DAG, Intr);
2286 }
2287}
2288
2289static SDValue lowerMSAStoreIntr(SDValue Op, SelectionDAG &DAG, unsigned Intr) {
2290 SDLoc DL(Op);
2291 SDValue ChainIn = Op->getOperand(0);
2292 SDValue Value = Op->getOperand(2);
2293 SDValue Address = Op->getOperand(3);
2294 SDValue Offset = Op->getOperand(4);
2295 EVT PtrTy = Address->getValueType(0);
2296
2297 Address = DAG.getNode(ISD::ADD, DL, PtrTy, Address, Offset);
2298
Justin Lebar9c375812016-07-15 18:27:10 +0000[diff] [blame]2299 return DAG.getStore(ChainIn, DL, Value, Address, MachinePointerInfo(),
2300 /* Alignment = */ 16);
Daniel Sanderse6ed5b72013-08-28 12:04:29 +0000[diff] [blame]2301}
2302
2303SDValue MipsSETargetLowering::lowerINTRINSIC_VOID(SDValue Op,
2304 SelectionDAG &DAG) const {
2305 unsigned Intr = cast<ConstantSDNode>(Op->getOperand(1))->getZExtValue();
2306 switch (Intr) {
2307 default:
2308 return SDValue();
2309 case Intrinsic::mips_st_b:
2310 case Intrinsic::mips_st_h:
2311 case Intrinsic::mips_st_w:
2312 case Intrinsic::mips_st_d:
Daniel Sandersce09d072013-08-28 12:14:50 +0000[diff] [blame]2313 return lowerMSAStoreIntr(Op, DAG, Intr);
Akira Hatanakaa6bbde52013-04-13 02:13:30 +0000[diff] [blame]2314 }
2315}
2316
Daniel Sanders7a289d02013-09-23 12:02:46 +0000[diff] [blame]2317/// \brief Check if the given BuildVectorSDNode is a splat.
2318/// This method currently relies on DAG nodes being reused when equivalent,
2319/// so it's possible for this to return false even when isConstantSplat returns
2320/// true.
2321static bool isSplatVector(const BuildVectorSDNode *N) {
Daniel Sanders7a289d02013-09-23 12:02:46 +0000[diff] [blame]2322 unsigned int nOps = N->getNumOperands();
Daniel Sandersab94b532013-10-30 15:20:38 +0000[diff] [blame]2323 assert(nOps > 1 && "isSplatVector has 0 or 1 sized build vector");
Daniel Sanders7a289d02013-09-23 12:02:46 +0000[diff] [blame]2324
2325 SDValue Operand0 = N->getOperand(0);
2326
2327 for (unsigned int i = 1; i < nOps; ++i) {
2328 if (N->getOperand(i) != Operand0)
2329 return false;
2330 }
2331
2332 return true;
2333}
2334
Daniel Sandersa4c8f3a2013-09-23 14:03:12 +0000[diff] [blame]2335// Lower ISD::EXTRACT_VECTOR_ELT into MipsISD::VEXTRACT_SEXT_ELT.
2336//
2337// The non-value bits resulting from ISD::EXTRACT_VECTOR_ELT are undefined. We
2338// choose to sign-extend but we could have equally chosen zero-extend. The
2339// DAGCombiner will fold any sign/zero extension of the ISD::EXTRACT_VECTOR_ELT
2340// result into this node later (possibly changing it to a zero-extend in the
2341// process).
2342SDValue MipsSETargetLowering::
2343lowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const {
2344 SDLoc DL(Op);
2345 EVT ResTy = Op->getValueType(0);
2346 SDValue Op0 = Op->getOperand(0);
Daniel Sanders39bb8ba2013-09-27 12:17:32 +0000[diff] [blame]2347 EVT VecTy = Op0->getValueType(0);
2348
2349 if (!VecTy.is128BitVector())
2350 return SDValue();
2351
2352 if (ResTy.isInteger()) {
2353 SDValue Op1 = Op->getOperand(1);
2354 EVT EltTy = VecTy.getVectorElementType();
2355 return DAG.getNode(MipsISD::VEXTRACT_SEXT_ELT, DL, ResTy, Op0, Op1,
2356 DAG.getValueType(EltTy));
2357 }
2358
2359 return Op;
Daniel Sandersa4c8f3a2013-09-23 14:03:12 +0000[diff] [blame]2360}
2361
Daniel Sandersf49dd822013-09-24 13:33:07 +0000[diff] [blame]2362static bool isConstantOrUndef(const SDValue Op) {
Sanjay Patel57195842016-03-14 17:28:46 +0000[diff] [blame]2363 if (Op->isUndef())
Daniel Sandersf49dd822013-09-24 13:33:07 +0000[diff] [blame]2364 return true;
Vasileios Kalintiris46963f62015-02-13 19:12:16 +0000[diff] [blame]2365 if (isa<ConstantSDNode>(Op))
Daniel Sandersf49dd822013-09-24 13:33:07 +0000[diff] [blame]2366 return true;
Vasileios Kalintiris46963f62015-02-13 19:12:16 +0000[diff] [blame]2367 if (isa<ConstantFPSDNode>(Op))
Daniel Sandersf49dd822013-09-24 13:33:07 +0000[diff] [blame]2368 return true;
2369 return false;
2370}
2371
2372static bool isConstantOrUndefBUILD_VECTOR(const BuildVectorSDNode *Op) {
2373 for (unsigned i = 0; i < Op->getNumOperands(); ++i)
2374 if (isConstantOrUndef(Op->getOperand(i)))
2375 return true;
2376 return false;
2377}
2378
Daniel Sanders7a289d02013-09-23 12:02:46 +0000[diff] [blame]2379// Lowers ISD::BUILD_VECTOR into appropriate SelectionDAG nodes for the
2380// backend.
2381//
2382// Lowers according to the following rules:
Daniel Sandersf49dd822013-09-24 13:33:07 +0000[diff] [blame]2383// - Constant splats are legal as-is as long as the SplatBitSize is a power of
2384// 2 less than or equal to 64 and the value fits into a signed 10-bit
2385// immediate
2386// - Constant splats are lowered to bitconverted BUILD_VECTORs if SplatBitSize
2387// is a power of 2 less than or equal to 64 and the value does not fit into a
2388// signed 10-bit immediate
2389// - Non-constant splats are legal as-is.
2390// - Non-constant non-splats are lowered to sequences of INSERT_VECTOR_ELT.
2391// - All others are illegal and must be expanded.
Daniel Sanders7a289d02013-09-23 12:02:46 +0000[diff] [blame]2392SDValue MipsSETargetLowering::lowerBUILD_VECTOR(SDValue Op,
2393 SelectionDAG &DAG) const {
2394 BuildVectorSDNode *Node = cast<BuildVectorSDNode>(Op);
2395 EVT ResTy = Op->getValueType(0);
2396 SDLoc DL(Op);
2397 APInt SplatValue, SplatUndef;
2398 unsigned SplatBitSize;
2399 bool HasAnyUndefs;
2400
Eric Christopher1c29a652014-07-18 22:55:25 +0000[diff] [blame]2401 if (!Subtarget.hasMSA() || !ResTy.is128BitVector())
Daniel Sanders7a289d02013-09-23 12:02:46 +0000[diff] [blame]2402 return SDValue();
2403
2404 if (Node->isConstantSplat(SplatValue, SplatUndef, SplatBitSize,
2405 HasAnyUndefs, 8,
Eric Christopher1c29a652014-07-18 22:55:25 +0000[diff] [blame]2406 !Subtarget.isLittle()) && SplatBitSize <= 64) {
Daniel Sandersf49dd822013-09-24 13:33:07 +0000[diff] [blame]2407 // We can only cope with 8, 16, 32, or 64-bit elements
2408 if (SplatBitSize != 8 && SplatBitSize != 16 && SplatBitSize != 32 &&
2409 SplatBitSize != 64)
2410 return SDValue();
2411
2412 // If the value fits into a simm10 then we can use ldi.[bhwd]
Daniel Sandersfd8e4162013-11-22 11:24:50 +0000[diff] [blame]2413 // However, if it isn't an integer type we will have to bitcast from an
Daniel Sandersd40aea82013-11-22 13:22:52 +0000[diff] [blame]2414 // integer type first. Also, if there are any undefs, we must lower them
Daniel Sanders630dbe02013-11-22 13:14:06 +0000[diff] [blame]2415 // to defined values first.
2416 if (ResTy.isInteger() && !HasAnyUndefs && SplatValue.isSignedIntN(10))
Daniel Sandersf49dd822013-09-24 13:33:07 +0000[diff] [blame]2417 return Op;
2418
2419 EVT ViaVecTy;
Daniel Sanders7a289d02013-09-23 12:02:46 +0000[diff] [blame]2420
2421 switch (SplatBitSize) {
2422 default:
2423 return SDValue();
Daniel Sandersf49dd822013-09-24 13:33:07 +0000[diff] [blame]2424 case 8:
2425 ViaVecTy = MVT::v16i8;
Daniel Sanders7a289d02013-09-23 12:02:46 +0000[diff] [blame]2426 break;
2427 case 16:
Daniel Sandersf49dd822013-09-24 13:33:07 +0000[diff] [blame]2428 ViaVecTy = MVT::v8i16;
Daniel Sanders7a289d02013-09-23 12:02:46 +0000[diff] [blame]2429 break;
Daniel Sandersf49dd822013-09-24 13:33:07 +0000[diff] [blame]2430 case 32:
2431 ViaVecTy = MVT::v4i32;
Daniel Sanders7a289d02013-09-23 12:02:46 +0000[diff] [blame]2432 break;
Daniel Sandersf49dd822013-09-24 13:33:07 +0000[diff] [blame]2433 case 64:
2434 // There's no fill.d to fall back on for 64-bit values
2435 return SDValue();
Daniel Sanders7a289d02013-09-23 12:02:46 +0000[diff] [blame]2436 }
2437
Daniel Sanders50b80412013-11-15 12:56:49 +0000[diff] [blame]2438 // SelectionDAG::getConstant will promote SplatValue appropriately.
Sergey Dmitrouk842a51b2015-04-28 14:05:47 +0000[diff] [blame]2439 SDValue Result = DAG.getConstant(SplatValue, DL, ViaVecTy);
Daniel Sandersf49dd822013-09-24 13:33:07 +0000[diff] [blame]2440
Daniel Sanders50b80412013-11-15 12:56:49 +0000[diff] [blame]2441 // Bitcast to the type we originally wanted
Daniel Sandersf49dd822013-09-24 13:33:07 +0000[diff] [blame]2442 if (ViaVecTy != ResTy)
2443 Result = DAG.getNode(ISD::BITCAST, SDLoc(Node), ResTy, Result);
Daniel Sanders7a289d02013-09-23 12:02:46 +0000[diff] [blame]2444
2445 return Result;
Daniel Sandersf49dd822013-09-24 13:33:07 +0000[diff] [blame]2446 } else if (isSplatVector(Node))
2447 return Op;
2448 else if (!isConstantOrUndefBUILD_VECTOR(Node)) {
Daniel Sandersf86622b2013-09-24 13:16:15 +0000[diff] [blame]2449 // Use INSERT_VECTOR_ELT operations rather than expand to stores.
2450 // The resulting code is the same length as the expansion, but it doesn't
2451 // use memory operations
2452 EVT ResTy = Node->getValueType(0);
2453
2454 assert(ResTy.isVector());
2455
2456 unsigned NumElts = ResTy.getVectorNumElements();
2457 SDValue Vector = DAG.getUNDEF(ResTy);
2458 for (unsigned i = 0; i < NumElts; ++i) {
2459 Vector = DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, ResTy, Vector,
2460 Node->getOperand(i),
Sergey Dmitrouk842a51b2015-04-28 14:05:47 +0000[diff] [blame]2461 DAG.getConstant(i, DL, MVT::i32));
Daniel Sandersf86622b2013-09-24 13:16:15 +0000[diff] [blame]2462 }
2463 return Vector;
2464 }
Daniel Sanders7a289d02013-09-23 12:02:46 +0000[diff] [blame]2465
2466 return SDValue();
2467}
2468
Daniel Sanders26307182013-09-24 14:20:00 +0000[diff] [blame]2469// Lower VECTOR_SHUFFLE into SHF (if possible).
2470//
2471// SHF splits the vector into blocks of four elements, then shuffles these
2472// elements according to a <4 x i2> constant (encoded as an integer immediate).
2473//
2474// It is therefore possible to lower into SHF when the mask takes the form:
2475// <a, b, c, d, a+4, b+4, c+4, d+4, a+8, b+8, c+8, d+8, ...>
2476// When undef's appear they are treated as if they were whatever value is
Daniel Sandersc8cd58f2015-05-19 12:24:52 +0000[diff] [blame]2477// necessary in order to fit the above forms.
Daniel Sanders26307182013-09-24 14:20:00 +0000[diff] [blame]2478//
2479// For example:
2480// %2 = shufflevector <8 x i16> %0, <8 x i16> undef,
2481// <8 x i32> <i32 3, i32 2, i32 1, i32 0,
2482// i32 7, i32 6, i32 5, i32 4>
2483// is lowered to:
2484// (SHF_H $w0, $w1, 27)
2485// where the 27 comes from:
2486// 3 + (2 << 2) + (1 << 4) + (0 << 6)
2487static SDValue lowerVECTOR_SHUFFLE_SHF(SDValue Op, EVT ResTy,
2488 SmallVector<int, 16> Indices,
2489 SelectionDAG &DAG) {
2490 int SHFIndices[4] = { -1, -1, -1, -1 };
2491
2492 if (Indices.size() < 4)
2493 return SDValue();
2494
2495 for (unsigned i = 0; i < 4; ++i) {
2496 for (unsigned j = i; j < Indices.size(); j += 4) {
2497 int Idx = Indices[j];
2498
2499 // Convert from vector index to 4-element subvector index
2500 // If an index refers to an element outside of the subvector then give up
2501 if (Idx != -1) {
2502 Idx -= 4 * (j / 4);
2503 if (Idx < 0 || Idx >= 4)
2504 return SDValue();
2505 }
2506
2507 // If the mask has an undef, replace it with the current index.
2508 // Note that it might still be undef if the current index is also undef
2509 if (SHFIndices[i] == -1)
2510 SHFIndices[i] = Idx;
2511
2512 // Check that non-undef values are the same as in the mask. If they
2513 // aren't then give up
2514 if (!(Idx == -1 || Idx == SHFIndices[i]))
2515 return SDValue();
2516 }
2517 }
2518
2519 // Calculate the immediate. Replace any remaining undefs with zero
2520 APInt Imm(32, 0);
2521 for (int i = 3; i >= 0; --i) {
2522 int Idx = SHFIndices[i];
2523
2524 if (Idx == -1)
2525 Idx = 0;
2526
2527 Imm <<= 2;
2528 Imm |= Idx & 0x3;
2529 }
2530
Sergey Dmitrouk842a51b2015-04-28 14:05:47 +0000[diff] [blame]2531 SDLoc DL(Op);
2532 return DAG.getNode(MipsISD::SHF, DL, ResTy,
2533 DAG.getConstant(Imm, DL, MVT::i32), Op->getOperand(0));
Daniel Sanders26307182013-09-24 14:20:00 +0000[diff] [blame]2534}
2535
Daniel Sandersc8cd58f2015-05-19 12:24:52 +0000[diff] [blame]2536/// Determine whether a range fits a regular pattern of values.
2537/// This function accounts for the possibility of jumping over the End iterator.
2538template <typename ValType>
2539static bool
2540fitsRegularPattern(typename SmallVectorImpl<ValType>::const_iterator Begin,
2541 unsigned CheckStride,
2542 typename SmallVectorImpl<ValType>::const_iterator End,
2543 ValType ExpectedIndex, unsigned ExpectedIndexStride) {
2544 auto &I = Begin;
2545
2546 while (I != End) {
2547 if (*I != -1 && *I != ExpectedIndex)
2548 return false;
2549 ExpectedIndex += ExpectedIndexStride;
2550
2551 // Incrementing past End is undefined behaviour so we must increment one
2552 // step at a time and check for End at each step.
2553 for (unsigned n = 0; n < CheckStride && I != End; ++n, ++I)
2554 ; // Empty loop body.
2555 }
2556 return true;
2557}
2558
2559// Determine whether VECTOR_SHUFFLE is a SPLATI.
2560//
2561// It is a SPLATI when the mask is:
2562// <x, x, x, ...>
2563// where x is any valid index.
2564//
2565// When undef's appear in the mask they are treated as if they were whatever
2566// value is necessary in order to fit the above form.
2567static bool isVECTOR_SHUFFLE_SPLATI(SDValue Op, EVT ResTy,
2568 SmallVector<int, 16> Indices,
2569 SelectionDAG &DAG) {
2570 assert((Indices.size() % 2) == 0);
2571
2572 int SplatIndex = -1;
2573 for (const auto &V : Indices) {
2574 if (V != -1) {
2575 SplatIndex = V;
2576 break;
2577 }
2578 }
2579
2580 return fitsRegularPattern<int>(Indices.begin(), 1, Indices.end(), SplatIndex,
2581 0);
2582}
2583
Daniel Sanders2ed228b2013-09-24 14:36:12 +0000[diff] [blame]2584// Lower VECTOR_SHUFFLE into ILVEV (if possible).
2585//
2586// ILVEV interleaves the even elements from each vector.
2587//
Daniel Sandersc8cd58f2015-05-19 12:24:52 +0000[diff] [blame]2588// It is possible to lower into ILVEV when the mask consists of two of the
2589// following forms interleaved:
2590// <0, 2, 4, ...>
2591// <n, n+2, n+4, ...>
Daniel Sanders2ed228b2013-09-24 14:36:12 +0000[diff] [blame]2592// where n is the number of elements in the vector.
Daniel Sandersc8cd58f2015-05-19 12:24:52 +0000[diff] [blame]2593// For example:
2594// <0, 0, 2, 2, 4, 4, ...>
2595// <0, n, 2, n+2, 4, n+4, ...>
Daniel Sanders2ed228b2013-09-24 14:36:12 +0000[diff] [blame]2596//
2597// When undef's appear in the mask they are treated as if they were whatever
Daniel Sandersc8cd58f2015-05-19 12:24:52 +0000[diff] [blame]2598// value is necessary in order to fit the above forms.
Daniel Sanders2ed228b2013-09-24 14:36:12 +0000[diff] [blame]2599static SDValue lowerVECTOR_SHUFFLE_ILVEV(SDValue Op, EVT ResTy,
2600 SmallVector<int, 16> Indices,
2601 SelectionDAG &DAG) {
Daniel Sandersc8cd58f2015-05-19 12:24:52 +0000[diff] [blame]2602 assert((Indices.size() % 2) == 0);
Daniel Sanders2ed228b2013-09-24 14:36:12 +0000[diff] [blame]2603
Daniel Sandersc8cd58f2015-05-19 12:24:52 +0000[diff] [blame]2604 SDValue Wt;
2605 SDValue Ws;
2606 const auto &Begin = Indices.begin();
2607 const auto &End = Indices.end();
Daniel Sanders2ed228b2013-09-24 14:36:12 +0000[diff] [blame]2608
Daniel Sandersc8cd58f2015-05-19 12:24:52 +0000[diff] [blame]2609 // Check even elements are taken from the even elements of one half or the
2610 // other and pick an operand accordingly.
2611 if (fitsRegularPattern<int>(Begin, 2, End, 0, 2))
2612 Wt = Op->getOperand(0);
2613 else if (fitsRegularPattern<int>(Begin, 2, End, Indices.size(), 2))
2614 Wt = Op->getOperand(1);
2615 else
2616 return SDValue();
2617
2618 // Check odd elements are taken from the even elements of one half or the
2619 // other and pick an operand accordingly.
2620 if (fitsRegularPattern<int>(Begin + 1, 2, End, 0, 2))
2621 Ws = Op->getOperand(0);
2622 else if (fitsRegularPattern<int>(Begin + 1, 2, End, Indices.size(), 2))
2623 Ws = Op->getOperand(1);
2624 else
2625 return SDValue();
2626
2627 return DAG.getNode(MipsISD::ILVEV, SDLoc(Op), ResTy, Ws, Wt);
Daniel Sanders2ed228b2013-09-24 14:36:12 +0000[diff] [blame]2628}
2629
2630// Lower VECTOR_SHUFFLE into ILVOD (if possible).
2631//
2632// ILVOD interleaves the odd elements from each vector.
2633//
Daniel Sandersc8cd58f2015-05-19 12:24:52 +0000[diff] [blame]2634// It is possible to lower into ILVOD when the mask consists of two of the
2635// following forms interleaved:
2636// <1, 3, 5, ...>
2637// <n+1, n+3, n+5, ...>
Daniel Sanders2ed228b2013-09-24 14:36:12 +0000[diff] [blame]2638// where n is the number of elements in the vector.
Daniel Sandersc8cd58f2015-05-19 12:24:52 +0000[diff] [blame]2639// For example:
2640// <1, 1, 3, 3, 5, 5, ...>
2641// <1, n+1, 3, n+3, 5, n+5, ...>
Daniel Sanders2ed228b2013-09-24 14:36:12 +0000[diff] [blame]2642//
2643// When undef's appear in the mask they are treated as if they were whatever
Daniel Sandersc8cd58f2015-05-19 12:24:52 +0000[diff] [blame]2644// value is necessary in order to fit the above forms.
Daniel Sanders2ed228b2013-09-24 14:36:12 +0000[diff] [blame]2645static SDValue lowerVECTOR_SHUFFLE_ILVOD(SDValue Op, EVT ResTy,
2646 SmallVector<int, 16> Indices,
2647 SelectionDAG &DAG) {
Daniel Sandersc8cd58f2015-05-19 12:24:52 +0000[diff] [blame]2648 assert((Indices.size() % 2) == 0);
Daniel Sanders2ed228b2013-09-24 14:36:12 +0000[diff] [blame]2649
Daniel Sandersc8cd58f2015-05-19 12:24:52 +0000[diff] [blame]2650 SDValue Wt;
2651 SDValue Ws;
2652 const auto &Begin = Indices.begin();
2653 const auto &End = Indices.end();
Daniel Sanders2ed228b2013-09-24 14:36:12 +0000[diff] [blame]2654
Daniel Sandersc8cd58f2015-05-19 12:24:52 +0000[diff] [blame]2655 // Check even elements are taken from the odd elements of one half or the
2656 // other and pick an operand accordingly.
2657 if (fitsRegularPattern<int>(Begin, 2, End, 1, 2))
2658 Wt = Op->getOperand(0);
2659 else if (fitsRegularPattern<int>(Begin, 2, End, Indices.size() + 1, 2))
2660 Wt = Op->getOperand(1);
2661 else
2662 return SDValue();
Daniel Sanders2ed228b2013-09-24 14:36:12 +0000[diff] [blame]2663
Daniel Sandersc8cd58f2015-05-19 12:24:52 +0000[diff] [blame]2664 // Check odd elements are taken from the odd elements of one half or the
2665 // other and pick an operand accordingly.
2666 if (fitsRegularPattern<int>(Begin + 1, 2, End, 1, 2))
2667 Ws = Op->getOperand(0);
2668 else if (fitsRegularPattern<int>(Begin + 1, 2, End, Indices.size() + 1, 2))
2669 Ws = Op->getOperand(1);
2670 else
2671 return SDValue();
Daniel Sanders2ed228b2013-09-24 14:36:12 +0000[diff] [blame]2672
Daniel Sandersc8cd58f2015-05-19 12:24:52 +0000[diff] [blame]2673 return DAG.getNode(MipsISD::ILVOD, SDLoc(Op), ResTy, Wt, Ws);
Daniel Sanders2ed228b2013-09-24 14:36:12 +0000[diff] [blame]2674}
2675
2676// Lower VECTOR_SHUFFLE into ILVR (if possible).
2677//
Daniel Sandersc8cd58f2015-05-19 12:24:52 +0000[diff] [blame]2678// ILVR interleaves consecutive elements from the right (lowest-indexed) half of
2679// each vector.
Daniel Sanders2ed228b2013-09-24 14:36:12 +0000[diff] [blame]2680//
Daniel Sandersc8cd58f2015-05-19 12:24:52 +0000[diff] [blame]2681// It is possible to lower into ILVR when the mask consists of two of the
2682// following forms interleaved:
2683// <0, 1, 2, ...>
2684// <n, n+1, n+2, ...>
2685// where n is the number of elements in the vector.
2686// For example:
2687// <0, 0, 1, 1, 2, 2, ...>
2688// <0, n, 1, n+1, 2, n+2, ...>
Daniel Sanders2ed228b2013-09-24 14:36:12 +0000[diff] [blame]2689//
2690// When undef's appear in the mask they are treated as if they were whatever
Daniel Sandersc8cd58f2015-05-19 12:24:52 +0000[diff] [blame]2691// value is necessary in order to fit the above forms.
Daniel Sanders2ed228b2013-09-24 14:36:12 +0000[diff] [blame]2692static SDValue lowerVECTOR_SHUFFLE_ILVR(SDValue Op, EVT ResTy,
2693 SmallVector<int, 16> Indices,
2694 SelectionDAG &DAG) {
Daniel Sandersc8cd58f2015-05-19 12:24:52 +0000[diff] [blame]2695 assert((Indices.size() % 2) == 0);
Daniel Sanders2ed228b2013-09-24 14:36:12 +0000[diff] [blame]2696
Daniel Sandersc8cd58f2015-05-19 12:24:52 +0000[diff] [blame]2697 SDValue Wt;
2698 SDValue Ws;
2699 const auto &Begin = Indices.begin();
2700 const auto &End = Indices.end();
Daniel Sanders2ed228b2013-09-24 14:36:12 +0000[diff] [blame]2701
Daniel Sandersc8cd58f2015-05-19 12:24:52 +0000[diff] [blame]2702 // Check even elements are taken from the right (lowest-indexed) elements of
2703 // one half or the other and pick an operand accordingly.
2704 if (fitsRegularPattern<int>(Begin, 2, End, 0, 1))
2705 Wt = Op->getOperand(0);
2706 else if (fitsRegularPattern<int>(Begin, 2, End, Indices.size(), 1))
2707 Wt = Op->getOperand(1);
2708 else
2709 return SDValue();
2710
2711 // Check odd elements are taken from the right (lowest-indexed) elements of
2712 // one half or the other and pick an operand accordingly.
2713 if (fitsRegularPattern<int>(Begin + 1, 2, End, 0, 1))
2714 Ws = Op->getOperand(0);
2715 else if (fitsRegularPattern<int>(Begin + 1, 2, End, Indices.size(), 1))
2716 Ws = Op->getOperand(1);
2717 else
2718 return SDValue();
2719
2720 return DAG.getNode(MipsISD::ILVR, SDLoc(Op), ResTy, Ws, Wt);
2721}
2722
2723// Lower VECTOR_SHUFFLE into ILVL (if possible).
2724//
2725// ILVL interleaves consecutive elements from the left (highest-indexed) half
2726// of each vector.
2727//
2728// It is possible to lower into ILVL when the mask consists of two of the
2729// following forms interleaved:
2730// <x, x+1, x+2, ...>
2731// <n+x, n+x+1, n+x+2, ...>
2732// where n is the number of elements in the vector and x is half n.
2733// For example:
2734// <x, x, x+1, x+1, x+2, x+2, ...>
2735// <x, n+x, x+1, n+x+1, x+2, n+x+2, ...>
2736//
2737// When undef's appear in the mask they are treated as if they were whatever
2738// value is necessary in order to fit the above forms.
2739static SDValue lowerVECTOR_SHUFFLE_ILVL(SDValue Op, EVT ResTy,
2740 SmallVector<int, 16> Indices,
2741 SelectionDAG &DAG) {
2742 assert((Indices.size() % 2) == 0);
2743
2744 unsigned HalfSize = Indices.size() / 2;
2745 SDValue Wt;
2746 SDValue Ws;
2747 const auto &Begin = Indices.begin();
2748 const auto &End = Indices.end();
2749
2750 // Check even elements are taken from the left (highest-indexed) elements of
2751 // one half or the other and pick an operand accordingly.
2752 if (fitsRegularPattern<int>(Begin, 2, End, HalfSize, 1))
2753 Wt = Op->getOperand(0);
2754 else if (fitsRegularPattern<int>(Begin, 2, End, Indices.size() + HalfSize, 1))
2755 Wt = Op->getOperand(1);
2756 else
2757 return SDValue();
2758
2759 // Check odd elements are taken from the left (highest-indexed) elements of
2760 // one half or the other and pick an operand accordingly.
2761 if (fitsRegularPattern<int>(Begin + 1, 2, End, HalfSize, 1))
2762 Ws = Op->getOperand(0);
2763 else if (fitsRegularPattern<int>(Begin + 1, 2, End, Indices.size() + HalfSize,
2764 1))
2765 Ws = Op->getOperand(1);
2766 else
2767 return SDValue();
2768
2769 return DAG.getNode(MipsISD::ILVL, SDLoc(Op), ResTy, Ws, Wt);
Daniel Sanders2ed228b2013-09-24 14:36:12 +0000[diff] [blame]2770}
2771
Daniel Sandersfae5f2a2013-09-24 14:53:25 +0000[diff] [blame]2772// Lower VECTOR_SHUFFLE into PCKEV (if possible).
2773//
2774// PCKEV copies the even elements of each vector into the result vector.
2775//
Daniel Sandersc8cd58f2015-05-19 12:24:52 +0000[diff] [blame]2776// It is possible to lower into PCKEV when the mask consists of two of the
2777// following forms concatenated:
2778// <0, 2, 4, ...>
2779// <n, n+2, n+4, ...>
Daniel Sandersfae5f2a2013-09-24 14:53:25 +0000[diff] [blame]2780// where n is the number of elements in the vector.
Daniel Sandersc8cd58f2015-05-19 12:24:52 +0000[diff] [blame]2781// For example:
2782// <0, 2, 4, ..., 0, 2, 4, ...>
2783// <0, 2, 4, ..., n, n+2, n+4, ...>
Daniel Sandersfae5f2a2013-09-24 14:53:25 +0000[diff] [blame]2784//
2785// When undef's appear in the mask they are treated as if they were whatever
Daniel Sandersc8cd58f2015-05-19 12:24:52 +0000[diff] [blame]2786// value is necessary in order to fit the above forms.
Daniel Sandersfae5f2a2013-09-24 14:53:25 +0000[diff] [blame]2787static SDValue lowerVECTOR_SHUFFLE_PCKEV(SDValue Op, EVT ResTy,
2788 SmallVector<int, 16> Indices,
2789 SelectionDAG &DAG) {
Daniel Sandersc8cd58f2015-05-19 12:24:52 +0000[diff] [blame]2790 assert((Indices.size() % 2) == 0);
Daniel Sandersfae5f2a2013-09-24 14:53:25 +0000[diff] [blame]2791
Daniel Sandersc8cd58f2015-05-19 12:24:52 +0000[diff] [blame]2792 SDValue Wt;
2793 SDValue Ws;
2794 const auto &Begin = Indices.begin();
2795 const auto &Mid = Indices.begin() + Indices.size() / 2;
2796 const auto &End = Indices.end();
Daniel Sandersfae5f2a2013-09-24 14:53:25 +0000[diff] [blame]2797
Daniel Sandersc8cd58f2015-05-19 12:24:52 +0000[diff] [blame]2798 if (fitsRegularPattern<int>(Begin, 1, Mid, 0, 2))
2799 Wt = Op->getOperand(0);
2800 else if (fitsRegularPattern<int>(Begin, 1, Mid, Indices.size(), 2))
2801 Wt = Op->getOperand(1);
2802 else
2803 return SDValue();
2804
2805 if (fitsRegularPattern<int>(Mid, 1, End, 0, 2))
2806 Ws = Op->getOperand(0);
2807 else if (fitsRegularPattern<int>(Mid, 1, End, Indices.size(), 2))
2808 Ws = Op->getOperand(1);
2809 else
2810 return SDValue();
2811
2812 return DAG.getNode(MipsISD::PCKEV, SDLoc(Op), ResTy, Ws, Wt);
Daniel Sandersfae5f2a2013-09-24 14:53:25 +0000[diff] [blame]2813}
2814
2815// Lower VECTOR_SHUFFLE into PCKOD (if possible).
2816//
2817// PCKOD copies the odd elements of each vector into the result vector.
2818//
Daniel Sandersc8cd58f2015-05-19 12:24:52 +0000[diff] [blame]2819// It is possible to lower into PCKOD when the mask consists of two of the
2820// following forms concatenated:
2821// <1, 3, 5, ...>
2822// <n+1, n+3, n+5, ...>
Daniel Sandersfae5f2a2013-09-24 14:53:25 +0000[diff] [blame]2823// where n is the number of elements in the vector.
Daniel Sandersc8cd58f2015-05-19 12:24:52 +0000[diff] [blame]2824// For example:
2825// <1, 3, 5, ..., 1, 3, 5, ...>
2826// <1, 3, 5, ..., n+1, n+3, n+5, ...>
Daniel Sandersfae5f2a2013-09-24 14:53:25 +0000[diff] [blame]2827//
2828// When undef's appear in the mask they are treated as if they were whatever
Daniel Sandersc8cd58f2015-05-19 12:24:52 +0000[diff] [blame]2829// value is necessary in order to fit the above forms.
Daniel Sandersfae5f2a2013-09-24 14:53:25 +0000[diff] [blame]2830static SDValue lowerVECTOR_SHUFFLE_PCKOD(SDValue Op, EVT ResTy,
2831 SmallVector<int, 16> Indices,
2832 SelectionDAG &DAG) {
Daniel Sandersc8cd58f2015-05-19 12:24:52 +0000[diff] [blame]2833 assert((Indices.size() % 2) == 0);
Daniel Sandersfae5f2a2013-09-24 14:53:25 +0000[diff] [blame]2834
Daniel Sandersc8cd58f2015-05-19 12:24:52 +0000[diff] [blame]2835 SDValue Wt;
2836 SDValue Ws;
2837 const auto &Begin = Indices.begin();
2838 const auto &Mid = Indices.begin() + Indices.size() / 2;
2839 const auto &End = Indices.end();
Daniel Sandersfae5f2a2013-09-24 14:53:25 +0000[diff] [blame]2840
Daniel Sandersc8cd58f2015-05-19 12:24:52 +0000[diff] [blame]2841 if (fitsRegularPattern<int>(Begin, 1, Mid, 1, 2))
2842 Wt = Op->getOperand(0);
2843 else if (fitsRegularPattern<int>(Begin, 1, Mid, Indices.size() + 1, 2))
2844 Wt = Op->getOperand(1);
2845 else
2846 return SDValue();
2847
2848 if (fitsRegularPattern<int>(Mid, 1, End, 1, 2))
2849 Ws = Op->getOperand(0);
2850 else if (fitsRegularPattern<int>(Mid, 1, End, Indices.size() + 1, 2))
2851 Ws = Op->getOperand(1);
2852 else
2853 return SDValue();
2854
2855 return DAG.getNode(MipsISD::PCKOD, SDLoc(Op), ResTy, Ws, Wt);
Daniel Sandersfae5f2a2013-09-24 14:53:25 +0000[diff] [blame]2856}
2857
Daniel Sanderse5087042013-09-24 14:02:15 +0000[diff] [blame]2858// Lower VECTOR_SHUFFLE into VSHF.
2859//
2860// This mostly consists of converting the shuffle indices in Indices into a
2861// BUILD_VECTOR and adding it as an operand to the resulting VSHF. There is
2862// also code to eliminate unused operands of the VECTOR_SHUFFLE. For example,
2863// if the type is v8i16 and all the indices are less than 8 then the second
2864// operand is unused and can be replaced with anything. We choose to replace it
2865// with the used operand since this reduces the number of instructions overall.
2866static SDValue lowerVECTOR_SHUFFLE_VSHF(SDValue Op, EVT ResTy,
2867 SmallVector<int, 16> Indices,
2868 SelectionDAG &DAG) {
2869 SmallVector<SDValue, 16> Ops;
2870 SDValue Op0;
2871 SDValue Op1;
2872 EVT MaskVecTy = ResTy.changeVectorElementTypeToInteger();
2873 EVT MaskEltTy = MaskVecTy.getVectorElementType();
2874 bool Using1stVec = false;
2875 bool Using2ndVec = false;
2876 SDLoc DL(Op);
2877 int ResTyNumElts = ResTy.getVectorNumElements();
2878
2879 for (int i = 0; i < ResTyNumElts; ++i) {
2880 // Idx == -1 means UNDEF
2881 int Idx = Indices[i];
2882
2883 if (0 <= Idx && Idx < ResTyNumElts)
2884 Using1stVec = true;
2885 if (ResTyNumElts <= Idx && Idx < ResTyNumElts * 2)
2886 Using2ndVec = true;
2887 }
2888
2889 for (SmallVector<int, 16>::iterator I = Indices.begin(); I != Indices.end();
2890 ++I)
Sergey Dmitrouk842a51b2015-04-28 14:05:47 +0000[diff] [blame]2891 Ops.push_back(DAG.getTargetConstant(*I, DL, MaskEltTy));
Daniel Sanderse5087042013-09-24 14:02:15 +0000[diff] [blame]2892
Ahmed Bougacha128f8732016-04-26 21:15:30 +0000[diff] [blame]2893 SDValue MaskVec = DAG.getBuildVector(MaskVecTy, DL, Ops);
Daniel Sanderse5087042013-09-24 14:02:15 +0000[diff] [blame]2894
2895 if (Using1stVec && Using2ndVec) {
2896 Op0 = Op->getOperand(0);
2897 Op1 = Op->getOperand(1);
2898 } else if (Using1stVec)
2899 Op0 = Op1 = Op->getOperand(0);
2900 else if (Using2ndVec)
2901 Op0 = Op1 = Op->getOperand(1);
2902 else
2903 llvm_unreachable("shuffle vector mask references neither vector operand?");
2904
Daniel Sandersf88a29e2014-03-21 16:56:51 +0000[diff] [blame]2905 // VECTOR_SHUFFLE concatenates the vectors in an vectorwise fashion.
2906 // <0b00, 0b01> + <0b10, 0b11> -> <0b00, 0b01, 0b10, 0b11>
2907 // VSHF concatenates the vectors in a bitwise fashion:
2908 // <0b00, 0b01> + <0b10, 0b11> ->
2909 // 0b0100 + 0b1110 -> 0b01001110
2910 // <0b10, 0b11, 0b00, 0b01>
2911 // We must therefore swap the operands to get the correct result.
2912 return DAG.getNode(MipsISD::VSHF, DL, ResTy, MaskVec, Op1, Op0);
Daniel Sanderse5087042013-09-24 14:02:15 +0000[diff] [blame]2913}
2914
2915// Lower VECTOR_SHUFFLE into one of a number of instructions depending on the
2916// indices in the shuffle.
2917SDValue MipsSETargetLowering::lowerVECTOR_SHUFFLE(SDValue Op,
2918 SelectionDAG &DAG) const {
2919 ShuffleVectorSDNode *Node = cast<ShuffleVectorSDNode>(Op);
2920 EVT ResTy = Op->getValueType(0);
2921
2922 if (!ResTy.is128BitVector())
2923 return SDValue();
2924
2925 int ResTyNumElts = ResTy.getVectorNumElements();
2926 SmallVector<int, 16> Indices;
2927
2928 for (int i = 0; i < ResTyNumElts; ++i)
2929 Indices.push_back(Node->getMaskElt(i));
2930
Daniel Sandersc8cd58f2015-05-19 12:24:52 +0000[diff] [blame]2931 // splati.[bhwd] is preferable to the others but is matched from
2932 // MipsISD::VSHF.
2933 if (isVECTOR_SHUFFLE_SPLATI(Op, ResTy, Indices, DAG))
2934 return lowerVECTOR_SHUFFLE_VSHF(Op, ResTy, Indices, DAG);
Ahmed Bougachaf8dfb472016-02-09 22:54:12 +0000[diff] [blame]2935 SDValue Result;
2936 if ((Result = lowerVECTOR_SHUFFLE_ILVEV(Op, ResTy, Indices, DAG)))
Daniel Sanders2ed228b2013-09-24 14:36:12 +0000[diff] [blame]2937 return Result;
Ahmed Bougachaf8dfb472016-02-09 22:54:12 +0000[diff] [blame]2938 if ((Result = lowerVECTOR_SHUFFLE_ILVOD(Op, ResTy, Indices, DAG)))
Daniel Sanders2ed228b2013-09-24 14:36:12 +0000[diff] [blame]2939 return Result;
Ahmed Bougachaf8dfb472016-02-09 22:54:12 +0000[diff] [blame]2940 if ((Result = lowerVECTOR_SHUFFLE_ILVL(Op, ResTy, Indices, DAG)))
Daniel Sanders2ed228b2013-09-24 14:36:12 +0000[diff] [blame]2941 return Result;
Ahmed Bougachaf8dfb472016-02-09 22:54:12 +0000[diff] [blame]2942 if ((Result = lowerVECTOR_SHUFFLE_ILVR(Op, ResTy, Indices, DAG)))
Daniel Sanders2ed228b2013-09-24 14:36:12 +0000[diff] [blame]2943 return Result;
Ahmed Bougachaf8dfb472016-02-09 22:54:12 +0000[diff] [blame]2944 if ((Result = lowerVECTOR_SHUFFLE_PCKEV(Op, ResTy, Indices, DAG)))
Daniel Sandersfae5f2a2013-09-24 14:53:25 +0000[diff] [blame]2945 return Result;
Ahmed Bougachaf8dfb472016-02-09 22:54:12 +0000[diff] [blame]2946 if ((Result = lowerVECTOR_SHUFFLE_PCKOD(Op, ResTy, Indices, DAG)))
Daniel Sandersfae5f2a2013-09-24 14:53:25 +0000[diff] [blame]2947 return Result;
Ahmed Bougachaf8dfb472016-02-09 22:54:12 +0000[diff] [blame]2948 if ((Result = lowerVECTOR_SHUFFLE_SHF(Op, ResTy, Indices, DAG)))
Daniel Sandersc8cd58f2015-05-19 12:24:52 +0000[diff] [blame]2949 return Result;
Daniel Sanderse5087042013-09-24 14:02:15 +0000[diff] [blame]2950 return lowerVECTOR_SHUFFLE_VSHF(Op, ResTy, Indices, DAG);
2951}
2952
Duncan P. N. Exon Smithe4f5e4f2016-06-30 22:52:52 +0000[diff] [blame]2953MachineBasicBlock *
2954MipsSETargetLowering::emitBPOSGE32(MachineInstr &MI,
2955 MachineBasicBlock *BB) const {
Akira Hatanaka96ca1822013-03-13 00:54:29 +0000[diff] [blame]2956 // $bb:
2957 // bposge32_pseudo $vr0
2958 // =>
2959 // $bb:
2960 // bposge32 $tbb
2961 // $fbb:
2962 // li $vr2, 0
2963 // b $sink
2964 // $tbb:
2965 // li $vr1, 1
2966 // $sink:
2967 // $vr0 = phi($vr2, $fbb, $vr1, $tbb)
2968
2969 MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo();
Eric Christopher96e72c62015-01-29 23:27:36 +0000[diff] [blame]2970 const TargetInstrInfo *TII = Subtarget.getInstrInfo();
Akira Hatanaka13e6ccf2013-08-06 23:08:38 +0000[diff] [blame]2971 const TargetRegisterClass *RC = &Mips::GPR32RegClass;
Duncan P. N. Exon Smithe4f5e4f2016-06-30 22:52:52 +0000[diff] [blame]2972 DebugLoc DL = MI.getDebugLoc();
Akira Hatanaka96ca1822013-03-13 00:54:29 +0000[diff] [blame]2973 const BasicBlock *LLVM_BB = BB->getBasicBlock();
Benjamin Kramerb6d0bd42014-03-02 12:27:27 +0000[diff] [blame]2974 MachineFunction::iterator It = std::next(MachineFunction::iterator(BB));
Akira Hatanaka96ca1822013-03-13 00:54:29 +0000[diff] [blame]2975 MachineFunction *F = BB->getParent();
2976 MachineBasicBlock *FBB = F->CreateMachineBasicBlock(LLVM_BB);
2977 MachineBasicBlock *TBB = F->CreateMachineBasicBlock(LLVM_BB);
2978 MachineBasicBlock *Sink = F->CreateMachineBasicBlock(LLVM_BB);
2979 F->insert(It, FBB);
2980 F->insert(It, TBB);
2981 F->insert(It, Sink);
2982
2983 // Transfer the remainder of BB and its successor edges to Sink.
Benjamin Kramerb6d0bd42014-03-02 12:27:27 +0000[diff] [blame]2984 Sink->splice(Sink->begin(), BB, std::next(MachineBasicBlock::iterator(MI)),
Akira Hatanaka96ca1822013-03-13 00:54:29 +0000[diff] [blame]2985 BB->end());
2986 Sink->transferSuccessorsAndUpdatePHIs(BB);
2987
2988 // Add successors.
2989 BB->addSuccessor(FBB);
2990 BB->addSuccessor(TBB);
2991 FBB->addSuccessor(Sink);
2992 TBB->addSuccessor(Sink);
2993
2994 // Insert the real bposge32 instruction to $BB.
2995 BuildMI(BB, DL, TII->get(Mips::BPOSGE32)).addMBB(TBB);
Hrvoje Varga6f09cdf2016-05-13 11:32:53 +0000[diff] [blame]2996 // Insert the real bposge32c instruction to $BB.
2997 BuildMI(BB, DL, TII->get(Mips::BPOSGE32C_MMR3)).addMBB(TBB);
Akira Hatanaka96ca1822013-03-13 00:54:29 +0000[diff] [blame]2998
2999 // Fill $FBB.
3000 unsigned VR2 = RegInfo.createVirtualRegister(RC);
3001 BuildMI(*FBB, FBB->end(), DL, TII->get(Mips::ADDiu), VR2)
3002 .addReg(Mips::ZERO).addImm(0);
3003 BuildMI(*FBB, FBB->end(), DL, TII->get(Mips::B)).addMBB(Sink);
3004
3005 // Fill $TBB.
3006 unsigned VR1 = RegInfo.createVirtualRegister(RC);
3007 BuildMI(*TBB, TBB->end(), DL, TII->get(Mips::ADDiu), VR1)
3008 .addReg(Mips::ZERO).addImm(1);
3009
3010 // Insert phi function to $Sink.
3011 BuildMI(*Sink, Sink->begin(), DL, TII->get(Mips::PHI),
Duncan P. N. Exon Smithe4f5e4f2016-06-30 22:52:52 +0000[diff] [blame]3012 MI.getOperand(0).getReg())
3013 .addReg(VR2)
3014 .addMBB(FBB)
3015 .addReg(VR1)
3016 .addMBB(TBB);
Akira Hatanaka96ca1822013-03-13 00:54:29 +0000[diff] [blame]3017
Duncan P. N. Exon Smithe4f5e4f2016-06-30 22:52:52 +0000[diff] [blame]3018 MI.eraseFromParent(); // The pseudo instruction is gone now.
Akira Hatanaka96ca1822013-03-13 00:54:29 +0000[diff] [blame]3019 return Sink;
3020}
Daniel Sandersce09d072013-08-28 12:14:50 +0000[diff] [blame]3021
Duncan P. N. Exon Smithe4f5e4f2016-06-30 22:52:52 +0000[diff] [blame]3022MachineBasicBlock *MipsSETargetLowering::emitMSACBranchPseudo(
3023 MachineInstr &MI, MachineBasicBlock *BB, unsigned BranchOp) const {
Daniel Sandersce09d072013-08-28 12:14:50 +0000[diff] [blame]3024 // $bb:
3025 // vany_nonzero $rd, $ws
3026 // =>
3027 // $bb:
3028 // bnz.b $ws, $tbb
3029 // b $fbb
3030 // $fbb:
3031 // li $rd1, 0
3032 // b $sink
3033 // $tbb:
3034 // li $rd2, 1
3035 // $sink:
3036 // $rd = phi($rd1, $fbb, $rd2, $tbb)
3037
3038 MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo();
Eric Christopher96e72c62015-01-29 23:27:36 +0000[diff] [blame]3039 const TargetInstrInfo *TII = Subtarget.getInstrInfo();
Daniel Sandersce09d072013-08-28 12:14:50 +0000[diff] [blame]3040 const TargetRegisterClass *RC = &Mips::GPR32RegClass;
Duncan P. N. Exon Smithe4f5e4f2016-06-30 22:52:52 +0000[diff] [blame]3041 DebugLoc DL = MI.getDebugLoc();
Daniel Sandersce09d072013-08-28 12:14:50 +0000[diff] [blame]3042 const BasicBlock *LLVM_BB = BB->getBasicBlock();
Benjamin Kramerb6d0bd42014-03-02 12:27:27 +0000[diff] [blame]3043 MachineFunction::iterator It = std::next(MachineFunction::iterator(BB));
Daniel Sandersce09d072013-08-28 12:14:50 +0000[diff] [blame]3044 MachineFunction *F = BB->getParent();
3045 MachineBasicBlock *FBB = F->CreateMachineBasicBlock(LLVM_BB);
3046 MachineBasicBlock *TBB = F->CreateMachineBasicBlock(LLVM_BB);
3047 MachineBasicBlock *Sink = F->CreateMachineBasicBlock(LLVM_BB);
3048 F->insert(It, FBB);
3049 F->insert(It, TBB);
3050 F->insert(It, Sink);
3051
3052 // Transfer the remainder of BB and its successor edges to Sink.
Benjamin Kramerb6d0bd42014-03-02 12:27:27 +0000[diff] [blame]3053 Sink->splice(Sink->begin(), BB, std::next(MachineBasicBlock::iterator(MI)),
Daniel Sandersce09d072013-08-28 12:14:50 +0000[diff] [blame]3054 BB->end());
3055 Sink->transferSuccessorsAndUpdatePHIs(BB);
3056
3057 // Add successors.
3058 BB->addSuccessor(FBB);
3059 BB->addSuccessor(TBB);
3060 FBB->addSuccessor(Sink);
3061 TBB->addSuccessor(Sink);
3062
3063 // Insert the real bnz.b instruction to $BB.
3064 BuildMI(BB, DL, TII->get(BranchOp))
Duncan P. N. Exon Smithe4f5e4f2016-06-30 22:52:52 +0000[diff] [blame]3065 .addReg(MI.getOperand(1).getReg())
3066 .addMBB(TBB);
Daniel Sandersce09d072013-08-28 12:14:50 +0000[diff] [blame]3067
3068 // Fill $FBB.
3069 unsigned RD1 = RegInfo.createVirtualRegister(RC);
3070 BuildMI(*FBB, FBB->end(), DL, TII->get(Mips::ADDiu), RD1)
3071 .addReg(Mips::ZERO).addImm(0);
3072 BuildMI(*FBB, FBB->end(), DL, TII->get(Mips::B)).addMBB(Sink);
3073
3074 // Fill $TBB.
3075 unsigned RD2 = RegInfo.createVirtualRegister(RC);
3076 BuildMI(*TBB, TBB->end(), DL, TII->get(Mips::ADDiu), RD2)
3077 .addReg(Mips::ZERO).addImm(1);
3078
3079 // Insert phi function to $Sink.
3080 BuildMI(*Sink, Sink->begin(), DL, TII->get(Mips::PHI),
Duncan P. N. Exon Smithe4f5e4f2016-06-30 22:52:52 +0000[diff] [blame]3081 MI.getOperand(0).getReg())
3082 .addReg(RD1)
3083 .addMBB(FBB)
3084 .addReg(RD2)
3085 .addMBB(TBB);
Daniel Sandersce09d072013-08-28 12:14:50 +0000[diff] [blame]3086
Duncan P. N. Exon Smithe4f5e4f2016-06-30 22:52:52 +0000[diff] [blame]3087 MI.eraseFromParent(); // The pseudo instruction is gone now.
Daniel Sandersce09d072013-08-28 12:14:50 +0000[diff] [blame]3088 return Sink;
3089}
Daniel Sanders39bb8ba2013-09-27 12:17:32 +0000[diff] [blame]3090
3091// Emit the COPY_FW pseudo instruction.
3092//
3093// copy_fw_pseudo $fd, $ws, n
3094// =>
3095// copy_u_w $rt, $ws, $n
3096// mtc1 $rt, $fd
3097//
3098// When n is zero, the equivalent operation can be performed with (potentially)
3099// zero instructions due to register overlaps. This optimization is never valid
3100// for lane 1 because it would require FR=0 mode which isn't supported by MSA.
Duncan P. N. Exon Smithe4f5e4f2016-06-30 22:52:52 +0000[diff] [blame]3101MachineBasicBlock *
3102MipsSETargetLowering::emitCOPY_FW(MachineInstr &MI,
3103 MachineBasicBlock *BB) const {
Eric Christopher96e72c62015-01-29 23:27:36 +0000[diff] [blame]3104 const TargetInstrInfo *TII = Subtarget.getInstrInfo();
Daniel Sanders39bb8ba2013-09-27 12:17:32 +0000[diff] [blame]3105 MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo();
Duncan P. N. Exon Smithe4f5e4f2016-06-30 22:52:52 +0000[diff] [blame]3106 DebugLoc DL = MI.getDebugLoc();
3107 unsigned Fd = MI.getOperand(0).getReg();
3108 unsigned Ws = MI.getOperand(1).getReg();
3109 unsigned Lane = MI.getOperand(2).getImm();
Daniel Sanders39bb8ba2013-09-27 12:17:32 +0000[diff] [blame]3110
Daniel Sandersafe27c72015-02-23 17:22:16 +0000[diff] [blame]3111 if (Lane == 0) {
3112 unsigned Wt = Ws;
3113 if (!Subtarget.useOddSPReg()) {
3114 // We must copy to an even-numbered MSA register so that the
3115 // single-precision sub-register is also guaranteed to be even-numbered.
3116 Wt = RegInfo.createVirtualRegister(&Mips::MSA128WEvensRegClass);
3117
3118 BuildMI(*BB, MI, DL, TII->get(Mips::COPY), Wt).addReg(Ws);
3119 }
3120
3121 BuildMI(*BB, MI, DL, TII->get(Mips::COPY), Fd).addReg(Wt, 0, Mips::sub_lo);
3122 } else {
3123 unsigned Wt = RegInfo.createVirtualRegister(
3124 Subtarget.useOddSPReg() ? &Mips::MSA128WRegClass :
3125 &Mips::MSA128WEvensRegClass);
Daniel Sanders39bb8ba2013-09-27 12:17:32 +0000[diff] [blame]3126
Daniel Sandersd9207702014-03-04 13:54:30 +0000[diff] [blame]3127 BuildMI(*BB, MI, DL, TII->get(Mips::SPLATI_W), Wt).addReg(Ws).addImm(Lane);
Daniel Sanders39bb8ba2013-09-27 12:17:32 +0000[diff] [blame]3128 BuildMI(*BB, MI, DL, TII->get(Mips::COPY), Fd).addReg(Wt, 0, Mips::sub_lo);
3129 }
3130
Duncan P. N. Exon Smithe4f5e4f2016-06-30 22:52:52 +0000[diff] [blame]3131 MI.eraseFromParent(); // The pseudo instruction is gone now.
Daniel Sanders39bb8ba2013-09-27 12:17:32 +0000[diff] [blame]3132 return BB;
3133}
3134
3135// Emit the COPY_FD pseudo instruction.
3136//
3137// copy_fd_pseudo $fd, $ws, n
3138// =>
3139// splati.d $wt, $ws, $n
3140// copy $fd, $wt:sub_64
3141//
3142// When n is zero, the equivalent operation can be performed with (potentially)
3143// zero instructions due to register overlaps. This optimization is always
3144// valid because FR=1 mode which is the only supported mode in MSA.
Duncan P. N. Exon Smithe4f5e4f2016-06-30 22:52:52 +0000[diff] [blame]3145MachineBasicBlock *
3146MipsSETargetLowering::emitCOPY_FD(MachineInstr &MI,
3147 MachineBasicBlock *BB) const {
Eric Christopher1c29a652014-07-18 22:55:25 +0000[diff] [blame]3148 assert(Subtarget.isFP64bit());
Daniel Sanders39bb8ba2013-09-27 12:17:32 +0000[diff] [blame]3149
Eric Christopher96e72c62015-01-29 23:27:36 +0000[diff] [blame]3150 const TargetInstrInfo *TII = Subtarget.getInstrInfo();
Daniel Sanders39bb8ba2013-09-27 12:17:32 +0000[diff] [blame]3151 MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo();
Duncan P. N. Exon Smithe4f5e4f2016-06-30 22:52:52 +0000[diff] [blame]3152 unsigned Fd = MI.getOperand(0).getReg();
3153 unsigned Ws = MI.getOperand(1).getReg();
3154 unsigned Lane = MI.getOperand(2).getImm() * 2;
3155 DebugLoc DL = MI.getDebugLoc();
Daniel Sanders39bb8ba2013-09-27 12:17:32 +0000[diff] [blame]3156
3157 if (Lane == 0)
3158 BuildMI(*BB, MI, DL, TII->get(Mips::COPY), Fd).addReg(Ws, 0, Mips::sub_64);
3159 else {
3160 unsigned Wt = RegInfo.createVirtualRegister(&Mips::MSA128DRegClass);
3161
3162 BuildMI(*BB, MI, DL, TII->get(Mips::SPLATI_D), Wt).addReg(Ws).addImm(1);
3163 BuildMI(*BB, MI, DL, TII->get(Mips::COPY), Fd).addReg(Wt, 0, Mips::sub_64);
3164 }
3165
Duncan P. N. Exon Smithe4f5e4f2016-06-30 22:52:52 +0000[diff] [blame]3166 MI.eraseFromParent(); // The pseudo instruction is gone now.
Daniel Sanders39bb8ba2013-09-27 12:17:32 +0000[diff] [blame]3167 return BB;
3168}
Daniel Sandersa5150702013-09-27 12:31:32 +0000[diff] [blame]3169
3170// Emit the INSERT_FW pseudo instruction.
3171//
3172// insert_fw_pseudo $wd, $wd_in, $n, $fs
3173// =>
3174// subreg_to_reg $wt:sub_lo, $fs
3175// insve_w $wd[$n], $wd_in, $wt[0]
Daniel Sanders1dfddc72013-10-15 13:14:41 +0000[diff] [blame]3176MachineBasicBlock *
Duncan P. N. Exon Smithe4f5e4f2016-06-30 22:52:52 +0000[diff] [blame]3177MipsSETargetLowering::emitINSERT_FW(MachineInstr &MI,
Daniel Sanders1dfddc72013-10-15 13:14:41 +0000[diff] [blame]3178 MachineBasicBlock *BB) const {
Eric Christopher96e72c62015-01-29 23:27:36 +0000[diff] [blame]3179 const TargetInstrInfo *TII = Subtarget.getInstrInfo();
Daniel Sandersa5150702013-09-27 12:31:32 +0000[diff] [blame]3180 MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo();
Duncan P. N. Exon Smithe4f5e4f2016-06-30 22:52:52 +0000[diff] [blame]3181 DebugLoc DL = MI.getDebugLoc();
3182 unsigned Wd = MI.getOperand(0).getReg();
3183 unsigned Wd_in = MI.getOperand(1).getReg();
3184 unsigned Lane = MI.getOperand(2).getImm();
3185 unsigned Fs = MI.getOperand(3).getReg();
Daniel Sandersafe27c72015-02-23 17:22:16 +0000[diff] [blame]3186 unsigned Wt = RegInfo.createVirtualRegister(
3187 Subtarget.useOddSPReg() ? &Mips::MSA128WRegClass :
3188 &Mips::MSA128WEvensRegClass);
Daniel Sandersa5150702013-09-27 12:31:32 +0000[diff] [blame]3189
3190 BuildMI(*BB, MI, DL, TII->get(Mips::SUBREG_TO_REG), Wt)
Daniel Sanders1dfddc72013-10-15 13:14:41 +0000[diff] [blame]3191 .addImm(0)
3192 .addReg(Fs)
3193 .addImm(Mips::sub_lo);
Daniel Sandersa5150702013-09-27 12:31:32 +0000[diff] [blame]3194 BuildMI(*BB, MI, DL, TII->get(Mips::INSVE_W), Wd)
Daniel Sanders1dfddc72013-10-15 13:14:41 +0000[diff] [blame]3195 .addReg(Wd_in)
3196 .addImm(Lane)
Daniel Sandersb50ccf82014-04-01 10:35:28 +0000[diff] [blame]3197 .addReg(Wt)
3198 .addImm(0);
Daniel Sandersa5150702013-09-27 12:31:32 +0000[diff] [blame]3199
Duncan P. N. Exon Smithe4f5e4f2016-06-30 22:52:52 +0000[diff] [blame]3200 MI.eraseFromParent(); // The pseudo instruction is gone now.
Daniel Sandersa5150702013-09-27 12:31:32 +0000[diff] [blame]3201 return BB;
3202}
3203
3204// Emit the INSERT_FD pseudo instruction.
3205//
3206// insert_fd_pseudo $wd, $fs, n
3207// =>
3208// subreg_to_reg $wt:sub_64, $fs
3209// insve_d $wd[$n], $wd_in, $wt[0]
Daniel Sanders1dfddc72013-10-15 13:14:41 +0000[diff] [blame]3210MachineBasicBlock *
Duncan P. N. Exon Smithe4f5e4f2016-06-30 22:52:52 +0000[diff] [blame]3211MipsSETargetLowering::emitINSERT_FD(MachineInstr &MI,
Daniel Sanders1dfddc72013-10-15 13:14:41 +0000[diff] [blame]3212 MachineBasicBlock *BB) const {
Eric Christopher1c29a652014-07-18 22:55:25 +0000[diff] [blame]3213 assert(Subtarget.isFP64bit());
Daniel Sandersa5150702013-09-27 12:31:32 +0000[diff] [blame]3214
Eric Christopher96e72c62015-01-29 23:27:36 +0000[diff] [blame]3215 const TargetInstrInfo *TII = Subtarget.getInstrInfo();
Daniel Sandersa5150702013-09-27 12:31:32 +0000[diff] [blame]3216 MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo();
Duncan P. N. Exon Smithe4f5e4f2016-06-30 22:52:52 +0000[diff] [blame]3217 DebugLoc DL = MI.getDebugLoc();
3218 unsigned Wd = MI.getOperand(0).getReg();
3219 unsigned Wd_in = MI.getOperand(1).getReg();
3220 unsigned Lane = MI.getOperand(2).getImm();
3221 unsigned Fs = MI.getOperand(3).getReg();
Daniel Sandersa5150702013-09-27 12:31:32 +0000[diff] [blame]3222 unsigned Wt = RegInfo.createVirtualRegister(&Mips::MSA128DRegClass);
3223
3224 BuildMI(*BB, MI, DL, TII->get(Mips::SUBREG_TO_REG), Wt)
Daniel Sanders1dfddc72013-10-15 13:14:41 +0000[diff] [blame]3225 .addImm(0)
3226 .addReg(Fs)
3227 .addImm(Mips::sub_64);
Daniel Sandersa5150702013-09-27 12:31:32 +0000[diff] [blame]3228 BuildMI(*BB, MI, DL, TII->get(Mips::INSVE_D), Wd)
Daniel Sanders1dfddc72013-10-15 13:14:41 +0000[diff] [blame]3229 .addReg(Wd_in)
3230 .addImm(Lane)
Daniel Sandersb50ccf82014-04-01 10:35:28 +0000[diff] [blame]3231 .addReg(Wt)
3232 .addImm(0);
Daniel Sanders1dfddc72013-10-15 13:14:41 +0000[diff] [blame]3233
Duncan P. N. Exon Smithe4f5e4f2016-06-30 22:52:52 +0000[diff] [blame]3234 MI.eraseFromParent(); // The pseudo instruction is gone now.
Daniel Sanders1dfddc72013-10-15 13:14:41 +0000[diff] [blame]3235 return BB;
3236}
3237
Daniel Sanderse296a0f2014-04-30 12:09:32 +0000[diff] [blame]3238// Emit the INSERT_([BHWD]|F[WD])_VIDX pseudo instruction.
3239//
3240// For integer:
3241// (INSERT_([BHWD]|F[WD])_PSEUDO $wd, $wd_in, $n, $rs)
3242// =>
3243// (SLL $lanetmp1, $lane, <log2size)
3244// (SLD_B $wdtmp1, $wd_in, $wd_in, $lanetmp1)
3245// (INSERT_[BHWD], $wdtmp2, $wdtmp1, 0, $rs)
3246// (NEG $lanetmp2, $lanetmp1)
3247// (SLD_B $wd, $wdtmp2, $wdtmp2, $lanetmp2)
3248//
3249// For floating point:
3250// (INSERT_([BHWD]|F[WD])_PSEUDO $wd, $wd_in, $n, $fs)
3251// =>
3252// (SUBREG_TO_REG $wt, $fs, <subreg>)
3253// (SLL $lanetmp1, $lane, <log2size)
3254// (SLD_B $wdtmp1, $wd_in, $wd_in, $lanetmp1)
3255// (INSVE_[WD], $wdtmp2, 0, $wdtmp1, 0)
3256// (NEG $lanetmp2, $lanetmp1)
3257// (SLD_B $wd, $wdtmp2, $wdtmp2, $lanetmp2)
Duncan P. N. Exon Smithe4f5e4f2016-06-30 22:52:52 +0000[diff] [blame]3258MachineBasicBlock *MipsSETargetLowering::emitINSERT_DF_VIDX(
3259 MachineInstr &MI, MachineBasicBlock *BB, unsigned EltSizeInBytes,
3260 bool IsFP) const {
Eric Christopher96e72c62015-01-29 23:27:36 +0000[diff] [blame]3261 const TargetInstrInfo *TII = Subtarget.getInstrInfo();
Daniel Sanderse296a0f2014-04-30 12:09:32 +0000[diff] [blame]3262 MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo();
Duncan P. N. Exon Smithe4f5e4f2016-06-30 22:52:52 +0000[diff] [blame]3263 DebugLoc DL = MI.getDebugLoc();
3264 unsigned Wd = MI.getOperand(0).getReg();
3265 unsigned SrcVecReg = MI.getOperand(1).getReg();
3266 unsigned LaneReg = MI.getOperand(2).getReg();
3267 unsigned SrcValReg = MI.getOperand(3).getReg();
Daniel Sanderse296a0f2014-04-30 12:09:32 +0000[diff] [blame]3268
3269 const TargetRegisterClass *VecRC = nullptr;
Daniel Sandersd3bb2082016-06-15 08:43:23 +0000[diff] [blame]3270 // FIXME: This should be true for N32 too.
Eric Christopherbf33a3c2014-07-02 23:18:40 +0000[diff] [blame]3271 const TargetRegisterClass *GPRRC =
Daniel Sanders4160c802015-05-05 08:48:35 +0000[diff] [blame]3272 Subtarget.isABI_N64() ? &Mips::GPR64RegClass : &Mips::GPR32RegClass;
Daniel Sandersd3bb2082016-06-15 08:43:23 +0000[diff] [blame]3273 unsigned SubRegIdx = Subtarget.isABI_N64() ? Mips::sub_32 : 0;
3274 unsigned ShiftOp = Subtarget.isABI_N64() ? Mips::DSLL : Mips::SLL;
Daniel Sanderse296a0f2014-04-30 12:09:32 +0000[diff] [blame]3275 unsigned EltLog2Size;
3276 unsigned InsertOp = 0;
3277 unsigned InsveOp = 0;
3278 switch (EltSizeInBytes) {
3279 default:
3280 llvm_unreachable("Unexpected size");
3281 case 1:
3282 EltLog2Size = 0;
3283 InsertOp = Mips::INSERT_B;
3284 InsveOp = Mips::INSVE_B;
3285 VecRC = &Mips::MSA128BRegClass;
3286 break;
3287 case 2:
3288 EltLog2Size = 1;
3289 InsertOp = Mips::INSERT_H;
3290 InsveOp = Mips::INSVE_H;
3291 VecRC = &Mips::MSA128HRegClass;
3292 break;
3293 case 4:
3294 EltLog2Size = 2;
3295 InsertOp = Mips::INSERT_W;
3296 InsveOp = Mips::INSVE_W;
3297 VecRC = &Mips::MSA128WRegClass;
3298 break;
3299 case 8:
3300 EltLog2Size = 3;
3301 InsertOp = Mips::INSERT_D;
3302 InsveOp = Mips::INSVE_D;
3303 VecRC = &Mips::MSA128DRegClass;
3304 break;
3305 }
3306
3307 if (IsFP) {
3308 unsigned Wt = RegInfo.createVirtualRegister(VecRC);
3309 BuildMI(*BB, MI, DL, TII->get(Mips::SUBREG_TO_REG), Wt)
3310 .addImm(0)
3311 .addReg(SrcValReg)
3312 .addImm(EltSizeInBytes == 8 ? Mips::sub_64 : Mips::sub_lo);
3313 SrcValReg = Wt;
3314 }
3315
3316 // Convert the lane index into a byte index
3317 if (EltSizeInBytes != 1) {
3318 unsigned LaneTmp1 = RegInfo.createVirtualRegister(GPRRC);
Daniel Sandersd3bb2082016-06-15 08:43:23 +0000[diff] [blame]3319 BuildMI(*BB, MI, DL, TII->get(ShiftOp), LaneTmp1)
Daniel Sanderse296a0f2014-04-30 12:09:32 +0000[diff] [blame]3320 .addReg(LaneReg)
3321 .addImm(EltLog2Size);
3322 LaneReg = LaneTmp1;
3323 }
3324
3325 // Rotate bytes around so that the desired lane is element zero
3326 unsigned WdTmp1 = RegInfo.createVirtualRegister(VecRC);
3327 BuildMI(*BB, MI, DL, TII->get(Mips::SLD_B), WdTmp1)
3328 .addReg(SrcVecReg)
3329 .addReg(SrcVecReg)
Daniel Sandersd3bb2082016-06-15 08:43:23 +0000[diff] [blame]3330 .addReg(LaneReg, 0, SubRegIdx);
Daniel Sanderse296a0f2014-04-30 12:09:32 +0000[diff] [blame]3331
3332 unsigned WdTmp2 = RegInfo.createVirtualRegister(VecRC);
3333 if (IsFP) {
3334 // Use insve.df to insert to element zero
3335 BuildMI(*BB, MI, DL, TII->get(InsveOp), WdTmp2)
3336 .addReg(WdTmp1)
3337 .addImm(0)
3338 .addReg(SrcValReg)
3339 .addImm(0);
3340 } else {
3341 // Use insert.df to insert to element zero
3342 BuildMI(*BB, MI, DL, TII->get(InsertOp), WdTmp2)
3343 .addReg(WdTmp1)
3344 .addReg(SrcValReg)
3345 .addImm(0);
3346 }
3347
3348 // Rotate elements the rest of the way for a full rotation.
3349 // sld.df inteprets $rt modulo the number of columns so we only need to negate
3350 // the lane index to do this.
3351 unsigned LaneTmp2 = RegInfo.createVirtualRegister(GPRRC);
Daniel Sanders4160c802015-05-05 08:48:35 +0000[diff] [blame]3352 BuildMI(*BB, MI, DL, TII->get(Subtarget.isABI_N64() ? Mips::DSUB : Mips::SUB),
3353 LaneTmp2)
3354 .addReg(Subtarget.isABI_N64() ? Mips::ZERO_64 : Mips::ZERO)
Daniel Sanderse296a0f2014-04-30 12:09:32 +0000[diff] [blame]3355 .addReg(LaneReg);
3356 BuildMI(*BB, MI, DL, TII->get(Mips::SLD_B), Wd)
3357 .addReg(WdTmp2)
3358 .addReg(WdTmp2)
Daniel Sandersd3bb2082016-06-15 08:43:23 +0000[diff] [blame]3359 .addReg(LaneTmp2, 0, SubRegIdx);
Daniel Sanderse296a0f2014-04-30 12:09:32 +0000[diff] [blame]3360
Duncan P. N. Exon Smithe4f5e4f2016-06-30 22:52:52 +0000[diff] [blame]3361 MI.eraseFromParent(); // The pseudo instruction is gone now.
Daniel Sanderse296a0f2014-04-30 12:09:32 +0000[diff] [blame]3362 return BB;
3363}
3364
Daniel Sanders1dfddc72013-10-15 13:14:41 +0000[diff] [blame]3365// Emit the FILL_FW pseudo instruction.
3366//
3367// fill_fw_pseudo $wd, $fs
3368// =>
3369// implicit_def $wt1
3370// insert_subreg $wt2:subreg_lo, $wt1, $fs
3371// splati.w $wd, $wt2[0]
3372MachineBasicBlock *
Duncan P. N. Exon Smithe4f5e4f2016-06-30 22:52:52 +0000[diff] [blame]3373MipsSETargetLowering::emitFILL_FW(MachineInstr &MI,
Daniel Sanders1dfddc72013-10-15 13:14:41 +0000[diff] [blame]3374 MachineBasicBlock *BB) const {
Eric Christopher96e72c62015-01-29 23:27:36 +0000[diff] [blame]3375 const TargetInstrInfo *TII = Subtarget.getInstrInfo();
Daniel Sanders1dfddc72013-10-15 13:14:41 +0000[diff] [blame]3376 MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo();
Duncan P. N. Exon Smithe4f5e4f2016-06-30 22:52:52 +0000[diff] [blame]3377 DebugLoc DL = MI.getDebugLoc();
3378 unsigned Wd = MI.getOperand(0).getReg();
3379 unsigned Fs = MI.getOperand(1).getReg();
Simon Dardisf790ff32017-01-10 13:57:44 +0000[diff] [blame]3380 unsigned Wt1 = RegInfo.createVirtualRegister(&Mips::MSA128WRegClass);
3381 unsigned Wt2 = RegInfo.createVirtualRegister(&Mips::MSA128WRegClass);
Daniel Sanders1dfddc72013-10-15 13:14:41 +0000[diff] [blame]3382
3383 BuildMI(*BB, MI, DL, TII->get(Mips::IMPLICIT_DEF), Wt1);
3384 BuildMI(*BB, MI, DL, TII->get(Mips::INSERT_SUBREG), Wt2)
3385 .addReg(Wt1)
3386 .addReg(Fs)
3387 .addImm(Mips::sub_lo);
3388 BuildMI(*BB, MI, DL, TII->get(Mips::SPLATI_W), Wd).addReg(Wt2).addImm(0);
3389
Duncan P. N. Exon Smithe4f5e4f2016-06-30 22:52:52 +0000[diff] [blame]3390 MI.eraseFromParent(); // The pseudo instruction is gone now.
Daniel Sanders1dfddc72013-10-15 13:14:41 +0000[diff] [blame]3391 return BB;
3392}
3393
3394// Emit the FILL_FD pseudo instruction.
3395//
3396// fill_fd_pseudo $wd, $fs
3397// =>
3398// implicit_def $wt1
3399// insert_subreg $wt2:subreg_64, $wt1, $fs
3400// splati.d $wd, $wt2[0]
3401MachineBasicBlock *
Duncan P. N. Exon Smithe4f5e4f2016-06-30 22:52:52 +0000[diff] [blame]3402MipsSETargetLowering::emitFILL_FD(MachineInstr &MI,
Daniel Sanders1dfddc72013-10-15 13:14:41 +0000[diff] [blame]3403 MachineBasicBlock *BB) const {
Eric Christopher1c29a652014-07-18 22:55:25 +0000[diff] [blame]3404 assert(Subtarget.isFP64bit());
Daniel Sanders1dfddc72013-10-15 13:14:41 +0000[diff] [blame]3405
Eric Christopher96e72c62015-01-29 23:27:36 +0000[diff] [blame]3406 const TargetInstrInfo *TII = Subtarget.getInstrInfo();
Daniel Sanders1dfddc72013-10-15 13:14:41 +0000[diff] [blame]3407 MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo();
Duncan P. N. Exon Smithe4f5e4f2016-06-30 22:52:52 +0000[diff] [blame]3408 DebugLoc DL = MI.getDebugLoc();
3409 unsigned Wd = MI.getOperand(0).getReg();
3410 unsigned Fs = MI.getOperand(1).getReg();
Daniel Sanders1dfddc72013-10-15 13:14:41 +0000[diff] [blame]3411 unsigned Wt1 = RegInfo.createVirtualRegister(&Mips::MSA128DRegClass);
3412 unsigned Wt2 = RegInfo.createVirtualRegister(&Mips::MSA128DRegClass);
3413
3414 BuildMI(*BB, MI, DL, TII->get(Mips::IMPLICIT_DEF), Wt1);
3415 BuildMI(*BB, MI, DL, TII->get(Mips::INSERT_SUBREG), Wt2)
3416 .addReg(Wt1)
3417 .addReg(Fs)
3418 .addImm(Mips::sub_64);
3419 BuildMI(*BB, MI, DL, TII->get(Mips::SPLATI_D), Wd).addReg(Wt2).addImm(0);
Daniel Sandersa5150702013-09-27 12:31:32 +0000[diff] [blame]3420
Duncan P. N. Exon Smithe4f5e4f2016-06-30 22:52:52 +0000[diff] [blame]3421 MI.eraseFromParent(); // The pseudo instruction is gone now.
Daniel Sandersa5150702013-09-27 12:31:32 +0000[diff] [blame]3422 return BB;
3423}
Daniel Sandersa9521602013-10-23 10:36:52 +0000[diff] [blame]3424
Simon Dardis0e2ee3b2016-11-18 16:17:44 +0000[diff] [blame]3425// Emit the ST_F16_PSEDUO instruction to store a f16 value from an MSA
3426// register.
3427//
3428// STF16 MSA128F16:$wd, mem_simm10:$addr
3429// =>
3430// copy_u.h $rtemp,$wd[0]
3431// sh $rtemp, $addr
3432//
3433// Safety: We can't use st.h & co as they would over write the memory after
3434// the destination. It would require half floats be allocated 16 bytes(!) of
3435// space.
3436MachineBasicBlock *
3437MipsSETargetLowering::emitST_F16_PSEUDO(MachineInstr &MI,
3438 MachineBasicBlock *BB) const {
3439
3440 const TargetInstrInfo *TII = Subtarget.getInstrInfo();
3441 MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo();
3442 DebugLoc DL = MI.getDebugLoc();
3443 unsigned Ws = MI.getOperand(0).getReg();
3444 unsigned Rt = MI.getOperand(1).getReg();
3445 const MachineMemOperand &MMO = **MI.memoperands_begin();
3446 unsigned Imm = MMO.getOffset();
3447
3448 // Caution: A load via the GOT can expand to a GPR32 operand, a load via
3449 // spill and reload can expand as a GPR64 operand. Examine the
3450 // operand in detail and default to ABI.
3451 const TargetRegisterClass *RC =
3452 MI.getOperand(1).isReg() ? RegInfo.getRegClass(MI.getOperand(1).getReg())
3453 : (Subtarget.isABI_O32() ? &Mips::GPR32RegClass
3454 : &Mips::GPR64RegClass);
3455 const bool UsingMips32 = RC == &Mips::GPR32RegClass;
3456 unsigned Rs = RegInfo.createVirtualRegister(RC);
3457
3458 BuildMI(*BB, MI, DL, TII->get(Mips::COPY_U_H), Rs).addReg(Ws).addImm(0);
3459 BuildMI(*BB, MI, DL, TII->get(UsingMips32 ? Mips::SH : Mips::SH64))
3460 .addReg(Rs)
3461 .addReg(Rt)
3462 .addImm(Imm)
3463 .addMemOperand(BB->getParent()->getMachineMemOperand(
3464 &MMO, MMO.getOffset(), MMO.getSize()));
3465
3466 MI.eraseFromParent();
3467 return BB;
3468}
3469
3470// Emit the LD_F16_PSEDUO instruction to load a f16 value into an MSA register.
3471//
3472// LD_F16 MSA128F16:$wd, mem_simm10:$addr
3473// =>
3474// lh $rtemp, $addr
3475// fill.h $wd, $rtemp
3476//
3477// Safety: We can't use ld.h & co as they over-read from the source.
3478// Additionally, if the address is not modulo 16, 2 cases can occur:
3479// a) Segmentation fault as the load instruction reads from a memory page
3480// memory it's not supposed to.
3481// b) The load crosses an implementation specific boundary, requiring OS
3482// intervention.
3483//
3484MachineBasicBlock *
3485MipsSETargetLowering::emitLD_F16_PSEUDO(MachineInstr &MI,
3486 MachineBasicBlock *BB) const {
3487
3488 const TargetInstrInfo *TII = Subtarget.getInstrInfo();
3489 MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo();
3490 DebugLoc DL = MI.getDebugLoc();
3491 unsigned Wd = MI.getOperand(0).getReg();
3492
3493 // Caution: A load via the GOT can expand to a GPR32 operand, a load via
3494 // spill and reload can expand as a GPR64 operand. Examine the
3495 // operand in detail and default to ABI.
3496 const TargetRegisterClass *RC =
3497 MI.getOperand(1).isReg() ? RegInfo.getRegClass(MI.getOperand(1).getReg())
3498 : (Subtarget.isABI_O32() ? &Mips::GPR32RegClass
3499 : &Mips::GPR64RegClass);
3500
3501 const bool UsingMips32 = RC == &Mips::GPR32RegClass;
3502 unsigned Rt = RegInfo.createVirtualRegister(RC);
3503
3504 MachineInstrBuilder MIB =
3505 BuildMI(*BB, MI, DL, TII->get(UsingMips32 ? Mips::LH : Mips::LH64), Rt);
3506 for (unsigned i = 1; i < MI.getNumOperands(); i++)
3507 MIB.addOperand(MI.getOperand(i));
3508
3509 BuildMI(*BB, MI, DL, TII->get(Mips::FILL_H), Wd).addReg(Rt);
3510
3511 MI.eraseFromParent();
3512 return BB;
3513}
3514
3515// Emit the FPROUND_PSEUDO instruction.
3516//
3517// Round an FGR64Opnd, FGR32Opnd to an f16.
3518//
3519// Safety: Cycle the operand through the GPRs so the result always ends up
3520// the correct MSA register.
3521//
3522// FIXME: This copying is strictly unnecessary. If we could tie FGR32Opnd:$Fs
3523// / FGR64Opnd:$Fs and MSA128F16:$Wd to the same physical register
3524// (which they can be, as the MSA registers are defined to alias the
3525// FPU's 64 bit and 32 bit registers) the result can be accessed using
3526// the correct register class. That requires operands be tie-able across
3527// register classes which have a sub/super register class relationship.
3528//
3529// For FPG32Opnd:
3530//
3531// FPROUND MSA128F16:$wd, FGR32Opnd:$fs
3532// =>
3533// mfc1 $rtemp, $fs
3534// fill.w $rtemp, $wtemp
3535// fexdo.w $wd, $wtemp, $wtemp
3536//
3537// For FPG64Opnd on mips32r2+:
3538//
3539// FPROUND MSA128F16:$wd, FGR64Opnd:$fs
3540// =>
3541// mfc1 $rtemp, $fs
3542// fill.w $rtemp, $wtemp
3543// mfhc1 $rtemp2, $fs
3544// insert.w $wtemp[1], $rtemp2
3545// insert.w $wtemp[3], $rtemp2
3546// fexdo.w $wtemp2, $wtemp, $wtemp
3547// fexdo.h $wd, $temp2, $temp2
3548//
3549// For FGR64Opnd on mips64r2+:
3550//
3551// FPROUND MSA128F16:$wd, FGR64Opnd:$fs
3552// =>
3553// dmfc1 $rtemp, $fs
3554// fill.d $rtemp, $wtemp
3555// fexdo.w $wtemp2, $wtemp, $wtemp
3556// fexdo.h $wd, $wtemp2, $wtemp2
3557//
3558// Safety note: As $wtemp is UNDEF, we may provoke a spurious exception if the
3559// undef bits are "just right" and the exception enable bits are
3560// set. By using fill.w to replicate $fs into all elements over
3561// insert.w for one element, we avoid that potiential case. If
3562// fexdo.[hw] causes an exception in, the exception is valid and it
3563// occurs for all elements.
3564//
3565MachineBasicBlock *
3566MipsSETargetLowering::emitFPROUND_PSEUDO(MachineInstr &MI,
3567 MachineBasicBlock *BB,
3568 bool IsFGR64) const {
3569
3570 // Strictly speaking, we need MIPS32R5 to support MSA. We'll be generous
3571 // here. It's technically doable to support MIPS32 here, but the ISA forbids
3572 // it.
3573 assert(Subtarget.hasMSA() && Subtarget.hasMips32r2());
3574
3575 bool IsFGR64onMips64 = Subtarget.hasMips64() && IsFGR64;
3576
3577 const TargetInstrInfo *TII = Subtarget.getInstrInfo();
3578 DebugLoc DL = MI.getDebugLoc();
3579 unsigned Wd = MI.getOperand(0).getReg();
3580 unsigned Fs = MI.getOperand(1).getReg();
3581
3582 MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo();
3583 unsigned Wtemp = RegInfo.createVirtualRegister(&Mips::MSA128WRegClass);
3584 const TargetRegisterClass *GPRRC =
3585 IsFGR64onMips64 ? &Mips::GPR64RegClass : &Mips::GPR32RegClass;
3586 unsigned MFC1Opc = IsFGR64onMips64 ? Mips::DMFC1 : Mips::MFC1;
3587 unsigned FILLOpc = IsFGR64onMips64 ? Mips::FILL_D : Mips::FILL_W;
3588
3589 // Perform the register class copy as mentioned above.
3590 unsigned Rtemp = RegInfo.createVirtualRegister(GPRRC);
3591 BuildMI(*BB, MI, DL, TII->get(MFC1Opc), Rtemp).addReg(Fs);
3592 BuildMI(*BB, MI, DL, TII->get(FILLOpc), Wtemp).addReg(Rtemp);
3593 unsigned WPHI = Wtemp;
3594
3595 if (!Subtarget.hasMips64() && IsFGR64) {
3596 unsigned Rtemp2 = RegInfo.createVirtualRegister(GPRRC);
3597 BuildMI(*BB, MI, DL, TII->get(Mips::MFHC1_D64), Rtemp2).addReg(Fs);
3598 unsigned Wtemp2 = RegInfo.createVirtualRegister(&Mips::MSA128WRegClass);
3599 unsigned Wtemp3 = RegInfo.createVirtualRegister(&Mips::MSA128WRegClass);
3600 BuildMI(*BB, MI, DL, TII->get(Mips::INSERT_W), Wtemp2)
3601 .addReg(Wtemp)
3602 .addReg(Rtemp2)
3603 .addImm(1);
3604 BuildMI(*BB, MI, DL, TII->get(Mips::INSERT_W), Wtemp3)
3605 .addReg(Wtemp2)
3606 .addReg(Rtemp2)
3607 .addImm(3);
3608 WPHI = Wtemp3;
3609 }
3610
3611 if (IsFGR64) {
3612 unsigned Wtemp2 = RegInfo.createVirtualRegister(&Mips::MSA128WRegClass);
3613 BuildMI(*BB, MI, DL, TII->get(Mips::FEXDO_W), Wtemp2)
3614 .addReg(WPHI)
3615 .addReg(WPHI);
3616 WPHI = Wtemp2;
3617 }
3618
3619 BuildMI(*BB, MI, DL, TII->get(Mips::FEXDO_H), Wd).addReg(WPHI).addReg(WPHI);
3620
3621 MI.eraseFromParent();
3622 return BB;
3623}
3624
3625// Emit the FPEXTEND_PSEUDO instruction.
3626//
3627// Expand an f16 to either a FGR32Opnd or FGR64Opnd.
3628//
3629// Safety: Cycle the result through the GPRs so the result always ends up
3630// the correct floating point register.
3631//
3632// FIXME: This copying is strictly unnecessary. If we could tie FGR32Opnd:$Fd
3633// / FGR64Opnd:$Fd and MSA128F16:$Ws to the same physical register
3634// (which they can be, as the MSA registers are defined to alias the
3635// FPU's 64 bit and 32 bit registers) the result can be accessed using
3636// the correct register class. That requires operands be tie-able across
3637// register classes which have a sub/super register class relationship. I
3638// haven't checked.
3639//
3640// For FGR32Opnd:
3641//
3642// FPEXTEND FGR32Opnd:$fd, MSA128F16:$ws
3643// =>
3644// fexupr.w $wtemp, $ws
3645// copy_s.w $rtemp, $ws[0]
3646// mtc1 $rtemp, $fd
3647//
3648// For FGR64Opnd on Mips64:
3649//
3650// FPEXTEND FGR64Opnd:$fd, MSA128F16:$ws
3651// =>
3652// fexupr.w $wtemp, $ws
3653// fexupr.d $wtemp2, $wtemp
3654// copy_s.d $rtemp, $wtemp2s[0]
3655// dmtc1 $rtemp, $fd
3656//
3657// For FGR64Opnd on Mips32:
3658//
3659// FPEXTEND FGR64Opnd:$fd, MSA128F16:$ws
3660// =>
3661// fexupr.w $wtemp, $ws
3662// fexupr.d $wtemp2, $wtemp
3663// copy_s.w $rtemp, $wtemp2[0]
3664// mtc1 $rtemp, $ftemp
3665// copy_s.w $rtemp2, $wtemp2[1]
3666// $fd = mthc1 $rtemp2, $ftemp
3667//
3668MachineBasicBlock *
3669MipsSETargetLowering::emitFPEXTEND_PSEUDO(MachineInstr &MI,
3670 MachineBasicBlock *BB,
3671 bool IsFGR64) const {
3672
3673 // Strictly speaking, we need MIPS32R5 to support MSA. We'll be generous
3674 // here. It's technically doable to support MIPS32 here, but the ISA forbids
3675 // it.
3676 assert(Subtarget.hasMSA() && Subtarget.hasMips32r2());
3677
3678 bool IsFGR64onMips64 = Subtarget.hasMips64() && IsFGR64;
3679 bool IsFGR64onMips32 = !Subtarget.hasMips64() && IsFGR64;
3680
3681 const TargetInstrInfo *TII = Subtarget.getInstrInfo();
3682 DebugLoc DL = MI.getDebugLoc();
3683 unsigned Fd = MI.getOperand(0).getReg();
3684 unsigned Ws = MI.getOperand(1).getReg();
3685
3686 MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo();
3687 const TargetRegisterClass *GPRRC =
3688 IsFGR64onMips64 ? &Mips::GPR64RegClass : &Mips::GPR32RegClass;
3689 unsigned MTC1Opc = IsFGR64onMips64 ? Mips::DMTC1 : Mips::MTC1;
3690 unsigned COPYOpc = IsFGR64onMips64 ? Mips::COPY_S_D : Mips::COPY_S_W;
3691
3692 unsigned Wtemp = RegInfo.createVirtualRegister(&Mips::MSA128WRegClass);
3693 unsigned WPHI = Wtemp;
3694
3695 BuildMI(*BB, MI, DL, TII->get(Mips::FEXUPR_W), Wtemp).addReg(Ws);
3696 if (IsFGR64) {
3697 WPHI = RegInfo.createVirtualRegister(&Mips::MSA128DRegClass);
3698 BuildMI(*BB, MI, DL, TII->get(Mips::FEXUPR_D), WPHI).addReg(Wtemp);
3699 }
3700
3701 // Perform the safety regclass copy mentioned above.
3702 unsigned Rtemp = RegInfo.createVirtualRegister(GPRRC);
3703 unsigned FPRPHI = IsFGR64onMips32
3704 ? RegInfo.createVirtualRegister(&Mips::FGR64RegClass)
3705 : Fd;
3706 BuildMI(*BB, MI, DL, TII->get(COPYOpc), Rtemp).addReg(WPHI).addImm(0);
3707 BuildMI(*BB, MI, DL, TII->get(MTC1Opc), FPRPHI).addReg(Rtemp);
3708
3709 if (IsFGR64onMips32) {
3710 unsigned Rtemp2 = RegInfo.createVirtualRegister(GPRRC);
3711 BuildMI(*BB, MI, DL, TII->get(Mips::COPY_S_W), Rtemp2)
3712 .addReg(WPHI)
3713 .addImm(1);
3714 BuildMI(*BB, MI, DL, TII->get(Mips::MTHC1_D64), Fd)
3715 .addReg(FPRPHI)
3716 .addReg(Rtemp2);
3717 }
3718
3719 MI.eraseFromParent();
3720 return BB;
3721}
3722
Daniel Sandersa9521602013-10-23 10:36:52 +0000[diff] [blame]3723// Emit the FEXP2_W_1 pseudo instructions.
3724//
3725// fexp2_w_1_pseudo $wd, $wt
3726// =>
3727// ldi.w $ws, 1
3728// fexp2.w $wd, $ws, $wt
3729MachineBasicBlock *
Duncan P. N. Exon Smithe4f5e4f2016-06-30 22:52:52 +0000[diff] [blame]3730MipsSETargetLowering::emitFEXP2_W_1(MachineInstr &MI,
Daniel Sandersa9521602013-10-23 10:36:52 +0000[diff] [blame]3731 MachineBasicBlock *BB) const {
Eric Christopher96e72c62015-01-29 23:27:36 +0000[diff] [blame]3732 const TargetInstrInfo *TII = Subtarget.getInstrInfo();
Daniel Sandersa9521602013-10-23 10:36:52 +0000[diff] [blame]3733 MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo();
3734 const TargetRegisterClass *RC = &Mips::MSA128WRegClass;
3735 unsigned Ws1 = RegInfo.createVirtualRegister(RC);
3736 unsigned Ws2 = RegInfo.createVirtualRegister(RC);
Duncan P. N. Exon Smithe4f5e4f2016-06-30 22:52:52 +0000[diff] [blame]3737 DebugLoc DL = MI.getDebugLoc();
Daniel Sandersa9521602013-10-23 10:36:52 +0000[diff] [blame]3738
3739 // Splat 1.0 into a vector
3740 BuildMI(*BB, MI, DL, TII->get(Mips::LDI_W), Ws1).addImm(1);
3741 BuildMI(*BB, MI, DL, TII->get(Mips::FFINT_U_W), Ws2).addReg(Ws1);
3742
3743 // Emit 1.0 * fexp2(Wt)
Duncan P. N. Exon Smithe4f5e4f2016-06-30 22:52:52 +0000[diff] [blame]3744 BuildMI(*BB, MI, DL, TII->get(Mips::FEXP2_W), MI.getOperand(0).getReg())
Daniel Sandersa9521602013-10-23 10:36:52 +0000[diff] [blame]3745 .addReg(Ws2)
Duncan P. N. Exon Smithe4f5e4f2016-06-30 22:52:52 +0000[diff] [blame]3746 .addReg(MI.getOperand(1).getReg());
Daniel Sandersa9521602013-10-23 10:36:52 +0000[diff] [blame]3747
Duncan P. N. Exon Smithe4f5e4f2016-06-30 22:52:52 +0000[diff] [blame]3748 MI.eraseFromParent(); // The pseudo instruction is gone now.
Daniel Sandersa9521602013-10-23 10:36:52 +0000[diff] [blame]3749 return BB;
3750}
3751
3752// Emit the FEXP2_D_1 pseudo instructions.
3753//
3754// fexp2_d_1_pseudo $wd, $wt
3755// =>
3756// ldi.d $ws, 1
3757// fexp2.d $wd, $ws, $wt
3758MachineBasicBlock *
Duncan P. N. Exon Smithe4f5e4f2016-06-30 22:52:52 +0000[diff] [blame]3759MipsSETargetLowering::emitFEXP2_D_1(MachineInstr &MI,
Daniel Sandersa9521602013-10-23 10:36:52 +0000[diff] [blame]3760 MachineBasicBlock *BB) const {
Eric Christopher96e72c62015-01-29 23:27:36 +0000[diff] [blame]3761 const TargetInstrInfo *TII = Subtarget.getInstrInfo();
Daniel Sandersa9521602013-10-23 10:36:52 +0000[diff] [blame]3762 MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo();
3763 const TargetRegisterClass *RC = &Mips::MSA128DRegClass;
3764 unsigned Ws1 = RegInfo.createVirtualRegister(RC);
3765 unsigned Ws2 = RegInfo.createVirtualRegister(RC);
Duncan P. N. Exon Smithe4f5e4f2016-06-30 22:52:52 +0000[diff] [blame]3766 DebugLoc DL = MI.getDebugLoc();
Daniel Sandersa9521602013-10-23 10:36:52 +0000[diff] [blame]3767
3768 // Splat 1.0 into a vector
3769 BuildMI(*BB, MI, DL, TII->get(Mips::LDI_D), Ws1).addImm(1);
3770 BuildMI(*BB, MI, DL, TII->get(Mips::FFINT_U_D), Ws2).addReg(Ws1);
3771
3772 // Emit 1.0 * fexp2(Wt)
Duncan P. N. Exon Smithe4f5e4f2016-06-30 22:52:52 +0000[diff] [blame]3773 BuildMI(*BB, MI, DL, TII->get(Mips::FEXP2_D), MI.getOperand(0).getReg())
Daniel Sandersa9521602013-10-23 10:36:52 +0000[diff] [blame]3774 .addReg(Ws2)
Duncan P. N. Exon Smithe4f5e4f2016-06-30 22:52:52 +0000[diff] [blame]3775 .addReg(MI.getOperand(1).getReg());
Daniel Sandersa9521602013-10-23 10:36:52 +0000[diff] [blame]3776
Duncan P. N. Exon Smithe4f5e4f2016-06-30 22:52:52 +0000[diff] [blame]3777 MI.eraseFromParent(); // The pseudo instruction is gone now.
Daniel Sandersa9521602013-10-23 10:36:52 +0000[diff] [blame]3778 return BB;
3779}