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gerrit-public.fairphone.software / toolchain / llvm-project / 11cafc82b72a80fb9a7266bbda7fc7a0cc1b51a0 / . / llvm / lib / Target / AArch64 / AArch64.td
blob: cfda0162d8856708d49abfe74d5334b7f9f00ee0 [file] [log] [blame]
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1//=- AArch64.td - Describe the AArch64 Target Machine --------*- tablegen -*-=//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10//
11//===----------------------------------------------------------------------===//
12
13//===----------------------------------------------------------------------===//
Pankaj Godea67fea42016-06-15 17:24:52 +0000[diff] [blame]14// Target-independent interfaces which we are implementing.
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]15//===----------------------------------------------------------------------===//
16
17include "llvm/Target/Target.td"
18
19//===----------------------------------------------------------------------===//
20// AArch64 Subtarget features.
21//
22
23def FeatureFPARMv8 : SubtargetFeature<"fp-armv8", "HasFPARMv8", "true",
24 "Enable ARMv8 FP">;
25
26def FeatureNEON : SubtargetFeature<"neon", "HasNEON", "true",
27 "Enable Advanced SIMD instructions", [FeatureFPARMv8]>;
28
29def FeatureCrypto : SubtargetFeature<"crypto", "HasCrypto", "true",
James Molloy9d423342017-04-05 10:44:38 +0000[diff] [blame]30 "Enable cryptographic instructions", [FeatureNEON]>;
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]31
32def FeatureCRC : SubtargetFeature<"crc", "HasCRC", "true",
33 "Enable ARMv8 CRC-32 checksum instructions">;
34
Sjoerd Meijerd906bf12016-06-03 14:03:27 +0000[diff] [blame]35def FeatureRAS : SubtargetFeature<"ras", "HasRAS", "true",
36 "Enable ARMv8 Reliability, Availability and Serviceability Extensions">;
37
Joel Jones75818bc2016-11-30 22:25:24 +0000[diff] [blame]38def FeatureLSE : SubtargetFeature<"lse", "HasLSE", "true",
39 "Enable ARMv8.1 Large System Extension (LSE) atomic instructions">;
40
Chad Rosier58fb5f52017-01-16 16:28:43 +0000[diff] [blame]41def FeatureRDM : SubtargetFeature<"rdm", "HasRDM", "true",
42 "Enable ARMv8.1 Rounding Double Multiply Add/Subtract instructions">;
43
Ahmed Bougachab0ff6432015-09-01 16:23:45 +0000[diff] [blame]44def FeaturePerfMon : SubtargetFeature<"perfmon", "HasPerfMon", "true",
45 "Enable ARMv8 PMUv3 Performance Monitors extension">;
46
Oliver Stannard7cc0c4e2015-11-26 15:23:32 +0000[diff] [blame]47def FeatureFullFP16 : SubtargetFeature<"fullfp16", "HasFullFP16", "true",
48 "Full FP16", [FeatureFPARMv8]>;
49
Oliver Stannarda34e4702015-12-01 10:48:51 +0000[diff] [blame]50def FeatureSPE : SubtargetFeature<"spe", "HasSPE", "true",
51 "Enable Statistical Profiling extension">;
52
Amara Emerson9f3a2452017-07-13 15:19:56 +0000[diff] [blame]53def FeatureSVE : SubtargetFeature<"sve", "HasSVE", "true",
54 "Enable Scalable Vector Extension (SVE) instructions">;
55
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]56/// Cyclone has register move instructions which are "free".
57def FeatureZCRegMove : SubtargetFeature<"zcm", "HasZeroCycleRegMove", "true",
58 "Has zero-cycle register moves">;
59
60/// Cyclone has instructions which zero registers for "free".
61def FeatureZCZeroing : SubtargetFeature<"zcz", "HasZeroCycleZeroing", "true",
62 "Has zero-cycle zeroing instructions">;
63
Akira Hatanakaf53b0402015-07-29 14:17:26 +0000[diff] [blame]64def FeatureStrictAlign : SubtargetFeature<"strict-align",
65 "StrictAlign", "true",
66 "Disallow all unaligned memory "
67 "access">;
68
Akira Hatanaka0d4c9ea2015-07-25 00:18:31 +0000[diff] [blame]69def FeatureReserveX18 : SubtargetFeature<"reserve-x18", "ReserveX18", "true",
70 "Reserve X18, making it unavailable "
71 "as a GPR">;
72
Matthias Braun651cff42016-06-02 18:03:53 +0000[diff] [blame]73def FeatureUseAA : SubtargetFeature<"use-aa", "UseAA", "true",
74 "Use alias analysis during codegen">;
75
76def FeatureBalanceFPOps : SubtargetFeature<"balance-fp-ops", "BalanceFPOps",
77 "true",
78 "balance mix of odd and even D-registers for fp multiply(-accumulate) ops">;
79
80def FeaturePredictableSelectIsExpensive : SubtargetFeature<
81 "predictable-select-expensive", "PredictableSelectIsExpensive", "true",
82 "Prefer likely predicted branches over selects">;
83
84def FeatureCustomCheapAsMoveHandling : SubtargetFeature<"custom-cheap-as-move",
85 "CustomAsCheapAsMove", "true",
86 "Use custom code for TargetInstrInfo::isAsCheapAsAMove()">;
87
88def FeaturePostRAScheduler : SubtargetFeature<"use-postra-scheduler",
89 "UsePostRAScheduler", "true", "Schedule again after register allocation">;
90
91def FeatureSlowMisaligned128Store : SubtargetFeature<"slow-misaligned-128store",
92 "Misaligned128StoreIsSlow", "true", "Misaligned 128 bit stores are slow">;
93
Evandro Menezes7784cac2017-01-24 17:34:31 +0000[diff] [blame]94def FeatureSlowPaired128 : SubtargetFeature<"slow-paired-128",
95 "Paired128IsSlow", "true", "Paired 128 bit loads and stores are slow">;
Matthias Braun651cff42016-06-02 18:03:53 +0000[diff] [blame]96
97def FeatureAlternateSExtLoadCVTF32Pattern : SubtargetFeature<
98 "alternate-sextload-cvt-f32-pattern", "UseAlternateSExtLoadCVTF32Pattern",
99 "true", "Use alternative pattern for sextload convert to f32">;
100
Matthias Braun46a52382016-10-04 19:28:21 +0000[diff] [blame]101def FeatureArithmeticBccFusion : SubtargetFeature<
102 "arith-bcc-fusion", "HasArithmeticBccFusion", "true",
103 "CPU fuses arithmetic+bcc operations">;
104
105def FeatureArithmeticCbzFusion : SubtargetFeature<
106 "arith-cbz-fusion", "HasArithmeticCbzFusion", "true",
107 "CPU fuses arithmetic + cbz/cbnz operations">;
Matthias Braun651cff42016-06-02 18:03:53 +0000[diff] [blame]108
Evandro Menezesb21fb292017-02-01 02:54:39 +0000[diff] [blame]109def FeatureFuseAES : SubtargetFeature<
110 "fuse-aes", "HasFuseAES", "true",
111 "CPU fuses AES crypto operations">;
112
Evandro Menezes455382e2017-02-01 02:54:42 +0000[diff] [blame]113def FeatureFuseLiterals : SubtargetFeature<
114 "fuse-literals", "HasFuseLiterals", "true",
115 "CPU fuses literal generation operations">;
116
Matthias Braun651cff42016-06-02 18:03:53 +0000[diff] [blame]117def FeatureDisableLatencySchedHeuristic : SubtargetFeature<
118 "disable-latency-sched-heuristic", "DisableLatencySchedHeuristic", "true",
119 "Disable latency scheduling heuristic">;
120
Evandro Menezeseff2bd92016-10-24 16:14:58 +0000[diff] [blame]121def FeatureUseRSqrt : SubtargetFeature<
122 "use-reciprocal-square-root", "UseRSqrt", "true",
123 "Use the reciprocal square root approximation">;
Sanne Woudad4658ee2017-03-28 10:02:56 +0000[diff] [blame]124
125def FeatureNoNegativeImmediates : SubtargetFeature<"no-neg-immediates",
126 "NegativeImmediates", "false",
127 "Convert immediates and instructions "
128 "to their negated or complemented "
129 "equivalent when the immediate does "
130 "not fit in the encoding.">;
131
Balaram Makam2aba753e2017-03-31 18:16:53 +0000[diff] [blame]132def FeatureLSLFast : SubtargetFeature<
133 "lsl-fast", "HasLSLFast", "true",
134 "CPU has a fastpath logical shift of up to 3 places">;
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]135//===----------------------------------------------------------------------===//
Vladimir Sukharev439328e2015-04-01 14:49:29 +0000[diff] [blame]136// Architectures.
137//
138
139def HasV8_1aOps : SubtargetFeature<"v8.1a", "HasV8_1aOps", "true",
Chad Rosier58fb5f52017-01-16 16:28:43 +0000[diff] [blame]140 "Support ARM v8.1a instructions", [FeatureCRC, FeatureLSE, FeatureRDM]>;
Vladimir Sukharev439328e2015-04-01 14:49:29 +0000[diff] [blame]141
Oliver Stannard7cc0c4e2015-11-26 15:23:32 +0000[diff] [blame]142def HasV8_2aOps : SubtargetFeature<"v8.2a", "HasV8_2aOps", "true",
Sjoerd Meijerd906bf12016-06-03 14:03:27 +0000[diff] [blame]143 "Support ARM v8.2a instructions", [HasV8_1aOps, FeatureRAS]>;
Oliver Stannard7cc0c4e2015-11-26 15:23:32 +0000[diff] [blame]144
Vladimir Sukharev439328e2015-04-01 14:49:29 +0000[diff] [blame]145//===----------------------------------------------------------------------===//
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]146// Register File Description
147//===----------------------------------------------------------------------===//
148
149include "AArch64RegisterInfo.td"
Daniel Sandersd64d50242017-01-19 11:15:55 +0000[diff] [blame]150include "AArch64RegisterBanks.td"
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]151include "AArch64CallingConvention.td"
152
153//===----------------------------------------------------------------------===//
154// Instruction Descriptions
155//===----------------------------------------------------------------------===//
156
157include "AArch64Schedule.td"
158include "AArch64InstrInfo.td"
159
160def AArch64InstrInfo : InstrInfo;
161
162//===----------------------------------------------------------------------===//
Tim Northovere6ae6762016-07-05 21:23:04 +0000[diff] [blame]163// Named operands for MRS/MSR/TLBI/...
164//===----------------------------------------------------------------------===//
165
166include "AArch64SystemOperands.td"
167
168//===----------------------------------------------------------------------===//
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]169// AArch64 Processors supported.
170//
171include "AArch64SchedA53.td"
Chad Rosier2205d4e2014-06-11 21:06:56 +0000[diff] [blame]172include "AArch64SchedA57.td"
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]173include "AArch64SchedCyclone.td"
Chad Rosierd34c26e2016-11-29 20:00:27 +0000[diff] [blame]174include "AArch64SchedFalkor.td"
Chad Rosiercd2be7f2016-02-12 15:51:51 +0000[diff] [blame]175include "AArch64SchedKryo.td"
Chad Rosierd34c26e2016-11-29 20:00:27 +0000[diff] [blame]176include "AArch64SchedM1.td"
Joel Jonesab0f3b42017-02-17 18:34:24 +0000[diff] [blame]177include "AArch64SchedThunderX.td"
Joel Jones28520882017-03-07 19:42:40 +0000[diff] [blame]178include "AArch64SchedThunderX2T99.td"
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]179
Christof Douma8b5dc2c2015-12-02 11:53:44 +0000[diff] [blame]180def ProcA35 : SubtargetFeature<"a35", "ARMProcFamily", "CortexA35",
Matthias Braun651cff42016-06-02 18:03:53 +0000[diff] [blame]181 "Cortex-A35 ARM processors", [
Christof Douma8b5dc2c2015-12-02 11:53:44 +0000[diff] [blame]182 FeatureCRC,
Matthias Braun651cff42016-06-02 18:03:53 +0000[diff] [blame]183 FeatureCrypto,
184 FeatureFPARMv8,
185 FeatureNEON,
186 FeaturePerfMon
187 ]>;
Christof Douma8b5dc2c2015-12-02 11:53:44 +0000[diff] [blame]188
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]189def ProcA53 : SubtargetFeature<"a53", "ARMProcFamily", "CortexA53",
Matthias Braun651cff42016-06-02 18:03:53 +0000[diff] [blame]190 "Cortex-A53 ARM processors", [
191 FeatureBalanceFPOps,
Ahmed Bougachab0ff6432015-09-01 16:23:45 +0000[diff] [blame]192 FeatureCRC,
Matthias Braun651cff42016-06-02 18:03:53 +0000[diff] [blame]193 FeatureCrypto,
194 FeatureCustomCheapAsMoveHandling,
195 FeatureFPARMv8,
Florian Hahnff25b6d2017-05-31 15:50:03 +0000[diff] [blame]196 FeatureFuseAES,
Matthias Braun651cff42016-06-02 18:03:53 +0000[diff] [blame]197 FeatureNEON,
198 FeaturePerfMon,
199 FeaturePostRAScheduler,
200 FeatureUseAA
201 ]>;
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]202
203def ProcA57 : SubtargetFeature<"a57", "ARMProcFamily", "CortexA57",
Matthias Braun651cff42016-06-02 18:03:53 +0000[diff] [blame]204 "Cortex-A57 ARM processors", [
205 FeatureBalanceFPOps,
Ahmed Bougachab0ff6432015-09-01 16:23:45 +0000[diff] [blame]206 FeatureCRC,
Matthias Braun651cff42016-06-02 18:03:53 +0000[diff] [blame]207 FeatureCrypto,
208 FeatureCustomCheapAsMoveHandling,
209 FeatureFPARMv8,
Evandro Menezesb21fb292017-02-01 02:54:39 +0000[diff] [blame]210 FeatureFuseAES,
Evandro Menezes455382e2017-02-01 02:54:42 +0000[diff] [blame]211 FeatureFuseLiterals,
Matthias Braun651cff42016-06-02 18:03:53 +0000[diff] [blame]212 FeatureNEON,
213 FeaturePerfMon,
214 FeaturePostRAScheduler,
215 FeaturePredictableSelectIsExpensive
216 ]>;
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]217
Silviu Barangaaee40fc2016-06-21 15:53:54 +0000[diff] [blame]218def ProcA72 : SubtargetFeature<"a72", "ARMProcFamily", "CortexA72",
219 "Cortex-A72 ARM processors", [
220 FeatureCRC,
221 FeatureCrypto,
222 FeatureFPARMv8,
Florian Hahnaf91e7e2017-05-15 15:15:22 +0000[diff] [blame]223 FeatureFuseAES,
Silviu Barangaaee40fc2016-06-21 15:53:54 +0000[diff] [blame]224 FeatureNEON,
225 FeaturePerfMon
226 ]>;
227
228def ProcA73 : SubtargetFeature<"a73", "ARMProcFamily", "CortexA73",
229 "Cortex-A73 ARM processors", [
230 FeatureCRC,
231 FeatureCrypto,
232 FeatureFPARMv8,
Florian Hahn064a2f92017-05-31 15:25:25 +0000[diff] [blame]233 FeatureFuseAES,
Silviu Barangaaee40fc2016-06-21 15:53:54 +0000[diff] [blame]234 FeatureNEON,
235 FeaturePerfMon
236 ]>;
237
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]238def ProcCyclone : SubtargetFeature<"cyclone", "ARMProcFamily", "Cyclone",
Matthias Braun651cff42016-06-02 18:03:53 +0000[diff] [blame]239 "Cyclone", [
240 FeatureAlternateSExtLoadCVTF32Pattern,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]241 FeatureCrypto,
Matthias Braun651cff42016-06-02 18:03:53 +0000[diff] [blame]242 FeatureDisableLatencySchedHeuristic,
243 FeatureFPARMv8,
Matthias Braun46a52382016-10-04 19:28:21 +0000[diff] [blame]244 FeatureArithmeticBccFusion,
245 FeatureArithmeticCbzFusion,
Matthias Braun651cff42016-06-02 18:03:53 +0000[diff] [blame]246 FeatureNEON,
Ahmed Bougachab0ff6432015-09-01 16:23:45 +0000[diff] [blame]247 FeaturePerfMon,
Matthias Braun651cff42016-06-02 18:03:53 +0000[diff] [blame]248 FeatureSlowMisaligned128Store,
249 FeatureZCRegMove,
250 FeatureZCZeroing
251 ]>;
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]252
MinSeong Kima7385eb2016-01-05 12:51:59 +0000[diff] [blame]253def ProcExynosM1 : SubtargetFeature<"exynosm1", "ARMProcFamily", "ExynosM1",
Evandro Menezesca837032016-10-26 22:06:20 +0000[diff] [blame]254 "Samsung Exynos-M1 processors",
Evandro Menezes7784cac2017-01-24 17:34:31 +0000[diff] [blame]255 [FeatureSlowPaired128,
Evandro Menezesca837032016-10-26 22:06:20 +0000[diff] [blame]256 FeatureCRC,
257 FeatureCrypto,
258 FeatureCustomCheapAsMoveHandling,
259 FeatureFPARMv8,
Evandro Menezesb21fb292017-02-01 02:54:39 +0000[diff] [blame]260 FeatureFuseAES,
Evandro Menezesca837032016-10-26 22:06:20 +0000[diff] [blame]261 FeatureNEON,
262 FeaturePerfMon,
263 FeaturePostRAScheduler,
Evandro Menezes1b48bac2016-12-16 00:18:00 +0000[diff] [blame]264 FeatureSlowMisaligned128Store,
Evandro Menezesca837032016-10-26 22:06:20 +0000[diff] [blame]265 FeatureUseRSqrt,
266 FeatureZCZeroing]>;
267
268def ProcExynosM2 : SubtargetFeature<"exynosm2", "ARMProcFamily", "ExynosM1",
Evandro Menezesaeec7802016-12-13 23:31:41 +0000[diff] [blame]269 "Samsung Exynos-M2/M3 processors",
Evandro Menezes7784cac2017-01-24 17:34:31 +0000[diff] [blame]270 [FeatureSlowPaired128,
Evandro Menezesca837032016-10-26 22:06:20 +0000[diff] [blame]271 FeatureCRC,
272 FeatureCrypto,
273 FeatureCustomCheapAsMoveHandling,
274 FeatureFPARMv8,
275 FeatureNEON,
276 FeaturePerfMon,
277 FeaturePostRAScheduler,
Evandro Menezes1b48bac2016-12-16 00:18:00 +0000[diff] [blame]278 FeatureSlowMisaligned128Store,
Evandro Menezesca837032016-10-26 22:06:20 +0000[diff] [blame]279 FeatureZCZeroing]>;
MinSeong Kima7385eb2016-01-05 12:51:59 +0000[diff] [blame]280
Chad Rosiercd2be7f2016-02-12 15:51:51 +0000[diff] [blame]281def ProcKryo : SubtargetFeature<"kryo", "ARMProcFamily", "Kryo",
Matthias Braun651cff42016-06-02 18:03:53 +0000[diff] [blame]282 "Qualcomm Kryo processors", [
Chad Rosiercd2be7f2016-02-12 15:51:51 +0000[diff] [blame]283 FeatureCRC,
Matthias Braun651cff42016-06-02 18:03:53 +0000[diff] [blame]284 FeatureCrypto,
285 FeatureCustomCheapAsMoveHandling,
286 FeatureFPARMv8,
Matthias Braun651cff42016-06-02 18:03:53 +0000[diff] [blame]287 FeatureNEON,
288 FeaturePerfMon,
289 FeaturePostRAScheduler,
Haicheng Wu1e395742016-07-12 02:04:01 +0000[diff] [blame]290 FeaturePredictableSelectIsExpensive,
Balaram Makam2aba753e2017-03-31 18:16:53 +0000[diff] [blame]291 FeatureZCZeroing,
292 FeatureLSLFast
Matthias Braun651cff42016-06-02 18:03:53 +0000[diff] [blame]293 ]>;
Chad Rosiercd2be7f2016-02-12 15:51:51 +0000[diff] [blame]294
Chad Rosier201fc1e2016-11-15 21:34:12 +0000[diff] [blame]295def ProcFalkor : SubtargetFeature<"falkor", "ARMProcFamily", "Falkor",
296 "Qualcomm Falkor processors", [
297 FeatureCRC,
298 FeatureCrypto,
Chad Rosier63687e402017-01-04 21:26:23 +0000[diff] [blame]299 FeatureCustomCheapAsMoveHandling,
Chad Rosier201fc1e2016-11-15 21:34:12 +0000[diff] [blame]300 FeatureFPARMv8,
301 FeatureNEON,
Chad Rosier63687e402017-01-04 21:26:23 +0000[diff] [blame]302 FeaturePerfMon,
303 FeaturePostRAScheduler,
304 FeaturePredictableSelectIsExpensive,
Chad Rosier58fb5f52017-01-16 16:28:43 +0000[diff] [blame]305 FeatureRDM,
Balaram Makam2aba753e2017-03-31 18:16:53 +0000[diff] [blame]306 FeatureZCZeroing,
307 FeatureLSLFast
Chad Rosier201fc1e2016-11-15 21:34:12 +0000[diff] [blame]308 ]>;
309
Joel Jones28520882017-03-07 19:42:40 +0000[diff] [blame]310def ProcThunderX2T99 : SubtargetFeature<"thunderx2t99", "ARMProcFamily",
311 "ThunderX2T99",
312 "Cavium ThunderX2 processors", [
313 FeatureCRC,
314 FeatureCrypto,
315 FeatureFPARMv8,
316 FeatureArithmeticBccFusion,
317 FeatureNEON,
318 FeaturePostRAScheduler,
319 FeaturePredictableSelectIsExpensive,
320 FeatureLSE,
321 HasV8_1aOps]>;
Pankaj Gode0aab2e32016-06-20 11:13:31 +0000[diff] [blame]322
Joel Jonesab0f3b42017-02-17 18:34:24 +0000[diff] [blame]323def ProcThunderX : SubtargetFeature<"thunderx", "ARMProcFamily", "ThunderX",
324 "Cavium ThunderX processors", [
325 FeatureCRC,
326 FeatureCrypto,
327 FeatureFPARMv8,
328 FeaturePerfMon,
329 FeaturePostRAScheduler,
330 FeaturePredictableSelectIsExpensive,
331 FeatureNEON]>;
332
333def ProcThunderXT88 : SubtargetFeature<"thunderxt88", "ARMProcFamily",
334 "ThunderXT88",
335 "Cavium ThunderX processors", [
336 FeatureCRC,
337 FeatureCrypto,
338 FeatureFPARMv8,
339 FeaturePerfMon,
340 FeaturePostRAScheduler,
341 FeaturePredictableSelectIsExpensive,
342 FeatureNEON]>;
343
344def ProcThunderXT81 : SubtargetFeature<"thunderxt81", "ARMProcFamily",
345 "ThunderXT81",
346 "Cavium ThunderX processors", [
347 FeatureCRC,
348 FeatureCrypto,
349 FeatureFPARMv8,
350 FeaturePerfMon,
351 FeaturePostRAScheduler,
352 FeaturePredictableSelectIsExpensive,
353 FeatureNEON]>;
354
355def ProcThunderXT83 : SubtargetFeature<"thunderxt83", "ARMProcFamily",
356 "ThunderXT83",
357 "Cavium ThunderX processors", [
358 FeatureCRC,
359 FeatureCrypto,
360 FeatureFPARMv8,
361 FeaturePerfMon,
362 FeaturePostRAScheduler,
363 FeaturePredictableSelectIsExpensive,
364 FeatureNEON]>;
365
Matthias Braun651cff42016-06-02 18:03:53 +0000[diff] [blame]366def : ProcessorModel<"generic", NoSchedModel, [
Matthias Braun651cff42016-06-02 18:03:53 +0000[diff] [blame]367 FeatureFPARMv8,
Florian Hahn0a26d2c2017-06-15 09:31:23 +0000[diff] [blame]368 FeatureFuseAES,
Matthias Braun651cff42016-06-02 18:03:53 +0000[diff] [blame]369 FeatureNEON,
370 FeaturePerfMon,
371 FeaturePostRAScheduler
372 ]>;
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]373
Chad Rosier8e11fbd2017-01-24 18:08:10 +0000[diff] [blame]374// FIXME: Cortex-A35 is currently modeled as a Cortex-A53.
Christof Douma8b5dc2c2015-12-02 11:53:44 +0000[diff] [blame]375def : ProcessorModel<"cortex-a35", CortexA53Model, [ProcA35]>;
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]376def : ProcessorModel<"cortex-a53", CortexA53Model, [ProcA53]>;
Chad Rosier2205d4e2014-06-11 21:06:56 +0000[diff] [blame]377def : ProcessorModel<"cortex-a57", CortexA57Model, [ProcA57]>;
Chad Rosier8e11fbd2017-01-24 18:08:10 +0000[diff] [blame]378// FIXME: Cortex-A72 and Cortex-A73 are currently modeled as a Cortex-A57.
Silviu Barangaaee40fc2016-06-21 15:53:54 +0000[diff] [blame]379def : ProcessorModel<"cortex-a72", CortexA57Model, [ProcA72]>;
380def : ProcessorModel<"cortex-a73", CortexA57Model, [ProcA73]>;
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]381def : ProcessorModel<"cyclone", CycloneModel, [ProcCyclone]>;
Evandro Menezesd761ca22016-02-06 00:01:41 +0000[diff] [blame]382def : ProcessorModel<"exynos-m1", ExynosM1Model, [ProcExynosM1]>;
Evandro Menezesca837032016-10-26 22:06:20 +0000[diff] [blame]383def : ProcessorModel<"exynos-m2", ExynosM1Model, [ProcExynosM2]>;
Evandro Menezesaeec7802016-12-13 23:31:41 +0000[diff] [blame]384def : ProcessorModel<"exynos-m3", ExynosM1Model, [ProcExynosM2]>;
Chad Rosierd34c26e2016-11-29 20:00:27 +0000[diff] [blame]385def : ProcessorModel<"falkor", FalkorModel, [ProcFalkor]>;
Chad Rosiercd2be7f2016-02-12 15:51:51 +0000[diff] [blame]386def : ProcessorModel<"kryo", KryoModel, [ProcKryo]>;
Joel Jonesab0f3b42017-02-17 18:34:24 +0000[diff] [blame]387// Cavium ThunderX/ThunderX T8X Processors
388def : ProcessorModel<"thunderx", ThunderXT8XModel, [ProcThunderX]>;
389def : ProcessorModel<"thunderxt88", ThunderXT8XModel, [ProcThunderXT88]>;
390def : ProcessorModel<"thunderxt81", ThunderXT8XModel, [ProcThunderXT81]>;
391def : ProcessorModel<"thunderxt83", ThunderXT8XModel, [ProcThunderXT83]>;
Joel Jones28520882017-03-07 19:42:40 +0000[diff] [blame]392// Cavium ThunderX2T9X Processors. Formerly Broadcom Vulcan.
393def : ProcessorModel<"thunderx2t99", ThunderX2T99Model, [ProcThunderX2T99]>;
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]394
395//===----------------------------------------------------------------------===//
396// Assembly parser
397//===----------------------------------------------------------------------===//
398
399def GenericAsmParserVariant : AsmParserVariant {
400 int Variant = 0;
401 string Name = "generic";
Colin LeMahieu8a0453e2015-11-09 00:31:07 +0000[diff] [blame]402 string BreakCharacters = ".";
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]403}
404
405def AppleAsmParserVariant : AsmParserVariant {
406 int Variant = 1;
407 string Name = "apple-neon";
Colin LeMahieu8a0453e2015-11-09 00:31:07 +0000[diff] [blame]408 string BreakCharacters = ".";
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]409}
410
411//===----------------------------------------------------------------------===//
412// Assembly printer
413//===----------------------------------------------------------------------===//
414// AArch64 Uses the MC printer for asm output, so make sure the TableGen
415// AsmWriter bits get associated with the correct class.
416def GenericAsmWriter : AsmWriter {
417 string AsmWriterClassName = "InstPrinter";
Akira Hatanakab46d0232015-03-27 20:36:02 +0000[diff] [blame]418 int PassSubtarget = 1;
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]419 int Variant = 0;
420 bit isMCAsmWriter = 1;
421}
422
423def AppleAsmWriter : AsmWriter {
424 let AsmWriterClassName = "AppleInstPrinter";
Akira Hatanakab46d0232015-03-27 20:36:02 +0000[diff] [blame]425 int PassSubtarget = 1;
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]426 int Variant = 1;
427 int isMCAsmWriter = 1;
428}
429
430//===----------------------------------------------------------------------===//
431// Target Declaration
432//===----------------------------------------------------------------------===//
433
434def AArch64 : Target {
435 let InstructionSet = AArch64InstrInfo;
436 let AssemblyParserVariants = [GenericAsmParserVariant, AppleAsmParserVariant];
437 let AssemblyWriters = [GenericAsmWriter, AppleAsmWriter];
438}