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gerrit-public.fairphone.software / toolchain / llvm-project / 13e6ccf341145080ae7cc94c9148368ed3f11402 / . / llvm / lib / Target / Mips / MicroMipsInstrInfo.td
blob: 249d712045fd992c5ebd3d6962168c9da39d26dd [file] [log] [blame]
Akira Hatanakabe6a8182013-04-19 19:03:11 +0000[diff] [blame]1let isCodeGenOnly = 1 in {
2 /// Arithmetic Instructions (ALU Immediate)
Akira Hatanaka13e6ccf2013-08-06 23:08:38 +0000[diff] [blame^]3 def ADDiu_MM : MMRel, ArithLogicI<"addiu", simm16, GPR32Opnd>,
Akira Hatanakabe6a8182013-04-19 19:03:11 +0000[diff] [blame]4 ADDI_FM_MM<0xc>;
Akira Hatanaka13e6ccf2013-08-06 23:08:38 +0000[diff] [blame^]5 def ADDi_MM : MMRel, ArithLogicI<"addi", simm16, GPR32Opnd>,
Akira Hatanakabe6a8182013-04-19 19:03:11 +0000[diff] [blame]6 ADDI_FM_MM<0x4>;
Akira Hatanaka13e6ccf2013-08-06 23:08:38 +0000[diff] [blame^]7 def SLTi_MM : MMRel, SetCC_I<"slti", setlt, simm16, immSExt16, GPR32Opnd>,
Akira Hatanakabe6a8182013-04-19 19:03:11 +0000[diff] [blame]8 SLTI_FM_MM<0x24>;
Akira Hatanaka13e6ccf2013-08-06 23:08:38 +0000[diff] [blame^]9 def SLTiu_MM : MMRel, SetCC_I<"sltiu", setult, simm16, immSExt16, GPR32Opnd>,
Akira Hatanakabe6a8182013-04-19 19:03:11 +0000[diff] [blame]10 SLTI_FM_MM<0x2c>;
Akira Hatanaka13e6ccf2013-08-06 23:08:38 +0000[diff] [blame^]11 def ANDi_MM : MMRel, ArithLogicI<"andi", uimm16, GPR32Opnd>,
Akira Hatanakabe6a8182013-04-19 19:03:11 +0000[diff] [blame]12 ADDI_FM_MM<0x34>;
Akira Hatanaka13e6ccf2013-08-06 23:08:38 +0000[diff] [blame^]13 def ORi_MM : MMRel, ArithLogicI<"ori", uimm16, GPR32Opnd>,
Akira Hatanakabe6a8182013-04-19 19:03:11 +0000[diff] [blame]14 ADDI_FM_MM<0x14>;
Akira Hatanaka13e6ccf2013-08-06 23:08:38 +0000[diff] [blame^]15 def XORi_MM : MMRel, ArithLogicI<"xori", uimm16, GPR32Opnd>,
Akira Hatanakabe6a8182013-04-19 19:03:11 +0000[diff] [blame]16 ADDI_FM_MM<0x1c>;
Akira Hatanaka13e6ccf2013-08-06 23:08:38 +0000[diff] [blame^]17 def LUi_MM : MMRel, LoadUpper<"lui", GPR32Opnd, uimm16>, LUI_FM_MM;
Akira Hatanakabe6a8182013-04-19 19:03:11 +0000[diff] [blame]18
19 /// Arithmetic Instructions (3-Operand, R-Type)
Akira Hatanaka13e6ccf2013-08-06 23:08:38 +0000[diff] [blame^]20 def ADDu_MM : MMRel, ArithLogicR<"addu", GPR32Opnd>, ADD_FM_MM<0, 0x150>;
21 def SUBu_MM : MMRel, ArithLogicR<"subu", GPR32Opnd>, ADD_FM_MM<0, 0x1d0>;
22 def MUL_MM : MMRel, ArithLogicR<"mul", GPR32Opnd>, ADD_FM_MM<0, 0x210>;
23 def ADD_MM : MMRel, ArithLogicR<"add", GPR32Opnd>, ADD_FM_MM<0, 0x110>;
24 def SUB_MM : MMRel, ArithLogicR<"sub", GPR32Opnd>, ADD_FM_MM<0, 0x190>;
25 def SLT_MM : MMRel, SetCC_R<"slt", setlt, GPR32Opnd>, ADD_FM_MM<0, 0x350>;
26 def SLTu_MM : MMRel, SetCC_R<"sltu", setult, GPR32Opnd>,
Akira Hatanakabe6a8182013-04-19 19:03:11 +0000[diff] [blame]27 ADD_FM_MM<0, 0x390>;
Akira Hatanaka13e6ccf2013-08-06 23:08:38 +0000[diff] [blame^]28 def AND_MM : MMRel, ArithLogicR<"and", GPR32Opnd, 1, IIAlu, and>,
Akira Hatanakabe6a8182013-04-19 19:03:11 +0000[diff] [blame]29 ADD_FM_MM<0, 0x250>;
Akira Hatanaka13e6ccf2013-08-06 23:08:38 +0000[diff] [blame^]30 def OR_MM : MMRel, ArithLogicR<"or", GPR32Opnd, 1, IIAlu, or>,
Akira Hatanakabe6a8182013-04-19 19:03:11 +0000[diff] [blame]31 ADD_FM_MM<0, 0x290>;
Akira Hatanaka13e6ccf2013-08-06 23:08:38 +0000[diff] [blame^]32 def XOR_MM : MMRel, ArithLogicR<"xor", GPR32Opnd, 1, IIAlu, xor>,
Akira Hatanakabe6a8182013-04-19 19:03:11 +0000[diff] [blame]33 ADD_FM_MM<0, 0x310>;
Akira Hatanaka13e6ccf2013-08-06 23:08:38 +0000[diff] [blame^]34 def NOR_MM : MMRel, LogicNOR<"nor", GPR32Opnd>, ADD_FM_MM<0, 0x2d0>;
35 def MULT_MM : MMRel, Mult<"mult", IIImul, GPR32Opnd, [HI, LO]>,
Akira Hatanakabe6a8182013-04-19 19:03:11 +0000[diff] [blame]36 MULT_FM_MM<0x22c>;
Akira Hatanaka13e6ccf2013-08-06 23:08:38 +0000[diff] [blame^]37 def MULTu_MM : MMRel, Mult<"multu", IIImul, GPR32Opnd, [HI, LO]>,
Akira Hatanakabe6a8182013-04-19 19:03:11 +0000[diff] [blame]38 MULT_FM_MM<0x26c>;
Akira Hatanakacd9b74a2013-04-25 01:11:15 +0000[diff] [blame]39
40 /// Shift Instructions
Akira Hatanaka13e6ccf2013-08-06 23:08:38 +0000[diff] [blame^]41 def SLL_MM : MMRel, shift_rotate_imm<"sll", shamt, GPR32Opnd>,
Akira Hatanakacd9b74a2013-04-25 01:11:15 +0000[diff] [blame]42 SRA_FM_MM<0, 0>;
Akira Hatanaka13e6ccf2013-08-06 23:08:38 +0000[diff] [blame^]43 def SRL_MM : MMRel, shift_rotate_imm<"srl", shamt, GPR32Opnd>,
Akira Hatanakacd9b74a2013-04-25 01:11:15 +0000[diff] [blame]44 SRA_FM_MM<0x40, 0>;
Akira Hatanaka13e6ccf2013-08-06 23:08:38 +0000[diff] [blame^]45 def SRA_MM : MMRel, shift_rotate_imm<"sra", shamt, GPR32Opnd>,
Akira Hatanakacd9b74a2013-04-25 01:11:15 +0000[diff] [blame]46 SRA_FM_MM<0x80, 0>;
Akira Hatanaka13e6ccf2013-08-06 23:08:38 +0000[diff] [blame^]47 def SLLV_MM : MMRel, shift_rotate_reg<"sllv", GPR32Opnd>,
Akira Hatanakacd9b74a2013-04-25 01:11:15 +0000[diff] [blame]48 SRLV_FM_MM<0x10, 0>;
Akira Hatanaka13e6ccf2013-08-06 23:08:38 +0000[diff] [blame^]49 def SRLV_MM : MMRel, shift_rotate_reg<"srlv", GPR32Opnd>,
Akira Hatanakacd9b74a2013-04-25 01:11:15 +0000[diff] [blame]50 SRLV_FM_MM<0x50, 0>;
Akira Hatanaka13e6ccf2013-08-06 23:08:38 +0000[diff] [blame^]51 def SRAV_MM : MMRel, shift_rotate_reg<"srav", GPR32Opnd>,
Akira Hatanakacd9b74a2013-04-25 01:11:15 +0000[diff] [blame]52 SRLV_FM_MM<0x90, 0>;
Akira Hatanaka13e6ccf2013-08-06 23:08:38 +0000[diff] [blame^]53 def ROTR_MM : MMRel, shift_rotate_imm<"rotr", shamt, GPR32Opnd>,
Akira Hatanakacd9b74a2013-04-25 01:11:15 +0000[diff] [blame]54 SRA_FM_MM<0xc0, 0>;
Akira Hatanaka13e6ccf2013-08-06 23:08:38 +0000[diff] [blame^]55 def ROTRV_MM : MMRel, shift_rotate_reg<"rotrv", GPR32Opnd>,
Akira Hatanakacd9b74a2013-04-25 01:11:15 +0000[diff] [blame]56 SRLV_FM_MM<0xd0, 0>;
Akira Hatanakaf0aa6c92013-04-25 01:21:25 +0000[diff] [blame]57
58 /// Load and Store Instructions - aligned
Akira Hatanaka13e6ccf2013-08-06 23:08:38 +0000[diff] [blame^]59 defm LB_MM : LoadM<"lb", GPR32Opnd, sextloadi8>, MMRel, LW_FM_MM<0x7>;
60 defm LBu_MM : LoadM<"lbu", GPR32Opnd, zextloadi8>, MMRel, LW_FM_MM<0x5>;
61 defm LH_MM : LoadM<"lh", GPR32Opnd, sextloadi16>, MMRel, LW_FM_MM<0xf>;
62 defm LHu_MM : LoadM<"lhu", GPR32Opnd, zextloadi16>, MMRel, LW_FM_MM<0xd>;
63 defm LW_MM : LoadM<"lw", GPR32Opnd>, MMRel, LW_FM_MM<0x3f>;
64 defm SB_MM : StoreM<"sb", GPR32Opnd, truncstorei8>, MMRel, LW_FM_MM<0x6>;
65 defm SH_MM : StoreM<"sh", GPR32Opnd, truncstorei16>, MMRel, LW_FM_MM<0xe>;
66 defm SW_MM : StoreM<"sw", GPR32Opnd>, MMRel, LW_FM_MM<0x3e>;
Akira Hatanakabe6a8182013-04-19 19:03:11 +0000[diff] [blame]67}