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Chris Lattner6b379da2003-09-23 15:13:04 +00001//===-- PhyRegAlloc.h - Graph Coloring Register Allocator -------*- c++ -*-===//
2//
3// This is the main entry point for register allocation.
4//
5// Notes:
6// * RegisterClasses: Each RegClass accepts a
7// TargetRegClass which contains machine specific info about that register
8// class. The code in the RegClass is machine independent and they use
9// access functions in the TargetRegClass object passed into it to get
10// machine specific info.
11//
12// * Machine dependent work: All parts of the register coloring algorithm
13// except coloring of an individual node are machine independent.
14//
15//===----------------------------------------------------------------------===//
Ruchira Sasankaf5788aa2001-09-08 14:22:50 +000016
Brian Gaeke58dabb42003-09-21 02:31:25 +000017#ifndef PHYREGALLOC_H
18#define PHYREGALLOC_H
Ruchira Sasankaf5788aa2001-09-08 14:22:50 +000019
Chris Lattnere80612a2003-09-01 20:12:17 +000020#include "LiveRangeInfo.h"
Brian Gaekee1061012003-09-21 01:23:46 +000021#include "llvm/Pass.h"
Vikram S. Adve91e75d82003-07-29 19:37:41 +000022#include "llvm/CodeGen/MachineBasicBlock.h"
Brian Gaekee1061012003-09-21 01:23:46 +000023#include "llvm/Target/TargetRegInfo.h"
24#include "llvm/Target/TargetMachine.h"
Chris Lattner50cf8f12002-04-28 20:40:16 +000025#include <map>
26
Misha Brukman7ae7f842002-10-28 00:28:31 +000027class MachineFunction;
Chris Lattnerf9986852002-04-27 07:27:19 +000028class FunctionLiveVarInfo;
Chris Lattnerb0da8b22002-02-04 05:52:08 +000029class MachineInstr;
Chris Lattner002958c2002-04-28 16:19:42 +000030class LoopInfo;
Chris Lattner19a7cb22003-01-15 19:56:21 +000031class RegClass;
Brian Gaeke1542a8b2003-09-24 18:08:54 +000032class Constant;
Ruchira Sasanka9c38dbc2001-10-28 18:15:12 +000033
34//----------------------------------------------------------------------------
35// Class AddedInstrns:
36// When register allocator inserts new instructions in to the existing
37// instruction stream, it does NOT directly modify the instruction stream.
38// Rather, it creates an object of AddedInstrns and stick it in the
39// AddedInstrMap for an existing instruction. This class contains two vectors
40// to store such instructions added before and after an existing instruction.
41//----------------------------------------------------------------------------
42
Chris Lattner30e23da2002-04-09 05:13:04 +000043struct AddedInstrns {
Chris Lattnerb1e39b52002-10-28 19:43:23 +000044 std::vector<MachineInstr*> InstrnsBefore;//Insts added BEFORE an existing inst
45 std::vector<MachineInstr*> InstrnsAfter; //Insts added AFTER an existing inst
Brian Gaekee1061012003-09-21 01:23:46 +000046 inline void clear () { InstrnsBefore.clear (); InstrnsAfter.clear (); }
Ruchira Sasankaf5788aa2001-09-08 14:22:50 +000047};
48
Ruchira Sasanka9c38dbc2001-10-28 18:15:12 +000049//----------------------------------------------------------------------------
Ruchira Sasanka9c38dbc2001-10-28 18:15:12 +000050// class PhyRegAlloc:
Brian Gaekee1061012003-09-21 01:23:46 +000051// Main class the register allocator. Call runOnFunction() to allocate
Chris Lattnerf739fa82002-04-08 22:03:57 +000052// registers for a Function.
Ruchira Sasanka9c38dbc2001-10-28 18:15:12 +000053//----------------------------------------------------------------------------
54
Brian Gaekee1061012003-09-21 01:23:46 +000055class PhyRegAlloc : public FunctionPass {
Chris Lattner7f74a562002-01-20 22:54:45 +000056 std::vector<RegClass *> RegClassList; // vector of register classes
Ruchira Sasankaf5788aa2001-09-08 14:22:50 +000057 const TargetMachine &TM; // target machine
Chris Lattnerb1e39b52002-10-28 19:43:23 +000058 const Function *Fn; // name of the function we work on
Brian Gaekee1061012003-09-21 01:23:46 +000059 MachineFunction *MF; // descriptor for method's native code
60 FunctionLiveVarInfo *LVI; // LV information for this method
Ruchira Sasankaf5788aa2001-09-08 14:22:50 +000061 // (already computed for BBs)
Brian Gaekee1061012003-09-21 01:23:46 +000062 LiveRangeInfo *LRI; // LR info (will be computed)
Chris Lattnerf9781b52002-12-29 03:13:05 +000063 const TargetRegInfo &MRI; // Machine Register information
Ruchira Sasankaf5788aa2001-09-08 14:22:50 +000064 const unsigned NumOfRegClasses; // recorded here for efficiency
65
Brian Gaekec8a9ec02003-09-16 15:36:50 +000066 // Map to indicate whether operands of each MachineInstr have been
67 // updated according to their assigned colors. This is only used in
68 // assertion checking (debug builds).
Vikram S. Adve24ce4d82003-05-31 07:41:54 +000069 std::map<const MachineInstr *, bool> OperandsColoredMap;
Ruchira Sasankaca632ed2001-11-03 17:14:44 +000070
Chris Lattner76014b92002-10-29 17:08:05 +000071 // AddedInstrMap - Used to store instrns added in this phase
72 std::map<const MachineInstr *, AddedInstrns> AddedInstrMap;
73
Chris Lattner92f5fb52003-08-05 22:09:31 +000074 // ScratchRegsUsed - Contains scratch register uses for a particular MI.
75 typedef std::multimap<const MachineInstr*, int> ScratchRegsUsedTy;
76 ScratchRegsUsedTy ScratchRegsUsed;
77
Vikram S. Adve40221aa2002-04-25 04:46:28 +000078 AddedInstrns AddedInstrAtEntry; // to store instrns added at entry
Brian Gaekee1061012003-09-21 01:23:46 +000079 const LoopInfo *LoopDepthCalc; // to calculate loop depths
Ruchira Sasankaf5788aa2001-09-08 14:22:50 +000080
Brian Gaeke1542a8b2003-09-24 18:08:54 +000081 std::map<const Function *, Constant *> FnAllocState;
82
Chris Lattnere62a2a72003-08-05 22:03:27 +000083 PhyRegAlloc(const PhyRegAlloc&); // DO NOT IMPLEMENT
84 void operator=(const PhyRegAlloc&); // DO NOT IMPLEMENT
Chris Lattner669a74c2002-02-04 17:38:48 +000085public:
Brian Gaekee1061012003-09-21 01:23:46 +000086 inline PhyRegAlloc (const TargetMachine &TM_) :
87 TM (TM_), MRI (TM.getRegInfo ()),
88 NumOfRegClasses (MRI.getNumOfRegClasses ()) { }
89 virtual ~PhyRegAlloc() { }
Chris Lattner669a74c2002-02-04 17:38:48 +000090
Brian Gaekee1061012003-09-21 01:23:46 +000091 /// runOnFunction - Main method called for allocating registers.
92 ///
93 virtual bool runOnFunction (Function &F);
Vikram S. Advececde712002-03-18 03:26:48 +000094
Brian Gaeke1542a8b2003-09-24 18:08:54 +000095 virtual bool doFinalization (Module &M);
96
Chris Lattner6b379da2003-09-23 15:13:04 +000097 virtual void getAnalysisUsage (AnalysisUsage &AU) const;
Brian Gaekee1061012003-09-21 01:23:46 +000098
99 const char *getPassName () const {
100 return "Traditional graph-coloring reg. allocator";
101 }
Brian Gaeke43593b82003-09-21 02:24:09 +0000102
103 inline const RegClass* getRegClassByID(unsigned id) const {
Vikram S. Adveabcd8d72003-07-25 21:00:13 +0000104 return RegClassList[id];
Vikram S. Advececde712002-03-18 03:26:48 +0000105 }
Brian Gaeke43593b82003-09-21 02:24:09 +0000106 inline RegClass *getRegClassByID(unsigned id) { return RegClassList[id]; }
Vikram S. Adve91e75d82003-07-29 19:37:41 +0000107
Chris Lattner669a74c2002-02-04 17:38:48 +0000108private:
Chris Lattnerb1def732002-02-05 02:51:01 +0000109 void addInterference(const Value *Def, const ValueSet *LVSet,
110 bool isCallInst);
Brian Gaekee1061012003-09-21 01:23:46 +0000111 bool markAllocatedRegs(MachineInstr* MInst);
Ruchira Sasankaf5788aa2001-09-08 14:22:50 +0000112
113 void addInterferencesForArgs();
114 void createIGNodeListsAndIGs();
115 void buildInterferenceGraphs();
Brian Gaeke1542a8b2003-09-24 18:08:54 +0000116 void saveState();
Ruchira Sasanka5b8971f2001-10-16 01:23:19 +0000117
Chris Lattnere62a2a72003-08-05 22:03:27 +0000118 void setCallInterferences(const MachineInstr *MI,
119 const ValueSet *LVSetAft);
Ruchira Sasankaf5788aa2001-09-08 14:22:50 +0000120
Ruchira Sasanka33b0d852001-10-23 21:38:42 +0000121 void move2DelayedInstr(const MachineInstr *OrigMI,
Chris Lattnere62a2a72003-08-05 22:03:27 +0000122 const MachineInstr *DelayedMI);
Ruchira Sasanka33b0d852001-10-23 21:38:42 +0000123
Ruchira Sasanka53516cd2001-10-19 21:42:06 +0000124 void markUnusableSugColors();
Ruchira Sasanka9c38dbc2001-10-28 18:15:12 +0000125 void allocateStackSpace4SpilledLRs();
126
Chris Lattnere62a2a72003-08-05 22:03:27 +0000127 void insertCode4SpilledLR(const LiveRange *LR,
128 MachineBasicBlock::iterator& MII,
129 MachineBasicBlock &MBB, unsigned OpNum);
Ruchira Sasanka53516cd2001-10-19 21:42:06 +0000130
Vikram S. Adve91e75d82003-07-29 19:37:41 +0000131 // Method for inserting caller saving code. The caller must save all the
132 // volatile registers live across a call.
133 void insertCallerSavingCode(std::vector<MachineInstr*>& instrnsBefore,
134 std::vector<MachineInstr*>& instrnsAfter,
135 MachineInstr *CallMI,
136 const BasicBlock *BB);
137
Ruchira Sasankaf5788aa2001-09-08 14:22:50 +0000138 void colorIncomingArgs();
Ruchira Sasanka560b0ad2001-09-30 23:19:57 +0000139 void colorCallRetArgs();
Ruchira Sasankaf5788aa2001-09-08 14:22:50 +0000140 void updateMachineCode();
Vikram S. Adve91e75d82003-07-29 19:37:41 +0000141 void updateInstruction(MachineBasicBlock::iterator& MII,
142 MachineBasicBlock &MBB);
Ruchira Sasanka560b0ad2001-09-30 23:19:57 +0000143
Chris Lattnere62a2a72003-08-05 22:03:27 +0000144 int getUsableUniRegAtMI(int RegType, const ValueSet *LVSetBef,
145 MachineInstr *MI,
Vikram S. Advebeb36402002-07-08 22:39:36 +0000146 std::vector<MachineInstr*>& MIBef,
147 std::vector<MachineInstr*>& MIAft);
148
Vikram S. Adve91e75d82003-07-29 19:37:41 +0000149 // Callback method used to find unused registers.
150 // LVSetBef is the live variable set to search for an unused register.
Chris Lattnere62a2a72003-08-05 22:03:27 +0000151 // If it is not specified, the LV set before the current MI is used.
Vikram S. Adve91e75d82003-07-29 19:37:41 +0000152 // This is sufficient as long as no new copy instructions are generated
153 // to copy the free register to memory.
154 //
Chris Lattnere62a2a72003-08-05 22:03:27 +0000155 int getUnusedUniRegAtMI(RegClass *RC, int RegType,
156 const MachineInstr *MI,
Vikram S. Adve91e75d82003-07-29 19:37:41 +0000157 const ValueSet *LVSetBef = 0);
158
Chris Lattnere62a2a72003-08-05 22:03:27 +0000159 void setRelRegsUsedByThisInst(RegClass *RC, int RegType,
160 const MachineInstr *MI);
Vikram S. Adveabcd8d72003-07-25 21:00:13 +0000161
Chris Lattnere62a2a72003-08-05 22:03:27 +0000162 int getUniRegNotUsedByThisInst(RegClass *RC, int RegType,
163 const MachineInstr *MI);
Ruchira Sasanka9c38dbc2001-10-28 18:15:12 +0000164
Chris Lattnere62a2a72003-08-05 22:03:27 +0000165 void addInterf4PseudoInstr(const MachineInstr *MI);
Ruchira Sasankaf5788aa2001-09-08 14:22:50 +0000166};
167
Ruchira Sasankaf5788aa2001-09-08 14:22:50 +0000168#endif