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gerrit-public.fairphone.software / toolchain / llvm-project / 16596471d936af603845a3c688d25ad56322fc54 / . / llvm / test / CodeGen / Mips / llvm-ir / select-flt.ll
blob: c0ac43f662f401884d6e83c90533fbb30089a8ab [file] [log] [blame]
Simon Dardis16596472018-02-22 11:53:01 +0000[diff] [blame^]1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc < %s -mtriple=mips-unknown-linux-gnu -mcpu=mips2 -verify-machineinstrs | FileCheck %s \
3; RUN: -check-prefixes=M2
4; RUN: llc < %s -mtriple=mips-unknown-linux-gnu -mcpu=mips32 -verify-machineinstrs | FileCheck %s \
5; RUN: -check-prefixes=CMOV32R1
6; RUN: llc < %s -mtriple=mips-unknown-linux-gnu -mcpu=mips32r2 -verify-machineinstrs | FileCheck %s \
7; RUN: -check-prefixes=CMOV32R2
8; RUN: llc < %s -mtriple=mips-unknown-linux-gnu -mcpu=mips32r3 -verify-machineinstrs | FileCheck %s \
9; RUN: -check-prefixes=CMOV32R2
10; RUN: llc < %s -mtriple=mips-unknown-linux-gnu -mcpu=mips32r5 -verify-machineinstrs | FileCheck %s \
11; RUN: -check-prefixes=CMOV32R2
12; RUN: llc < %s -mtriple=mips-unknown-linux-gnu -mcpu=mips32r6 -verify-machineinstrs | FileCheck %s \
13; RUN: -check-prefixes=32R6
14; RUN: llc < %s -mtriple=mips64-unknown-linux-gnu -mcpu=mips3 -verify-machineinstrs | FileCheck %s \
15; RUN: -check-prefixes=M3
16; RUN: llc < %s -mtriple=mips64-unknown-linux-gnu -mcpu=mips4 -verify-machineinstrs | FileCheck %s \
17; RUN: -check-prefixes=CMOV64
18; RUN: llc < %s -mtriple=mips64-unknown-linux-gnu -mcpu=mips64 -verify-machineinstrs | FileCheck %s \
19; RUN: -check-prefixes=CMOV64
20; RUN: llc < %s -mtriple=mips64-unknown-linux-gnu -mcpu=mips64r2 -verify-machineinstrs | FileCheck %s \
21; RUN: -check-prefixes=CMOV64
22; RUN: llc < %s -mtriple=mips64-unknown-linux-gnu -mcpu=mips64r3 -verify-machineinstrs | FileCheck %s \
23; RUN: -check-prefixes=CMOV64
24; RUN: llc < %s -mtriple=mips64-unknown-linux-gnu -mcpu=mips64r5 -verify-machineinstrs | FileCheck %s \
25; RUN: -check-prefixes=CMOV64
26; RUN: llc < %s -mtriple=mips64-unknown-linux-gnu -mcpu=mips64r6 -verify-machineinstrs | FileCheck %s \
27; RUN: -check-prefixes=64R6
28; RUN: llc < %s -mtriple=mips-unknown-linux-gnu -mcpu=mips32r3 -mattr=+micromips -verify-machineinstrs | FileCheck %s \
29; RUN: -check-prefixes=MM32R3
30; RUN: llc < %s -mtriple=mips-unknown-linux-gnu -mcpu=mips32r6 -mattr=+micromips -verify-machineinstrs | FileCheck %s \
31; RUN: -check-prefixes=MM32R6
Vasileios Kalintirisa0520372016-02-01 15:19:35 +0000[diff] [blame]32
Vasileios Kalintiris36901dd2016-03-01 20:25:43 +0000[diff] [blame]33define float @tst_select_i1_float(i1 signext %s, float %x, float %y) {
Simon Dardis16596472018-02-22 11:53:01 +0000[diff] [blame^]34; M2-LABEL: tst_select_i1_float:
35; M2: # %bb.0: # %entry
36; M2-NEXT: andi $1, $4, 1
37; M2-NEXT: bnez $1, $BB0_2
38; M2-NEXT: nop
39; M2-NEXT: # %bb.1: # %entry
40; M2-NEXT: jr $ra
41; M2-NEXT: mtc1 $6, $f0
42; M2-NEXT: $BB0_2:
43; M2-NEXT: jr $ra
44; M2-NEXT: mtc1 $5, $f0
45;
46; CMOV32R1-LABEL: tst_select_i1_float:
47; CMOV32R1: # %bb.0: # %entry
48; CMOV32R1-NEXT: mtc1 $6, $f0
49; CMOV32R1-NEXT: andi $1, $4, 1
50; CMOV32R1-NEXT: mtc1 $5, $f1
51; CMOV32R1-NEXT: jr $ra
52; CMOV32R1-NEXT: movn.s $f0, $f1, $1
53;
54; CMOV32R2-LABEL: tst_select_i1_float:
55; CMOV32R2: # %bb.0: # %entry
56; CMOV32R2-NEXT: mtc1 $6, $f0
57; CMOV32R2-NEXT: andi $1, $4, 1
58; CMOV32R2-NEXT: mtc1 $5, $f1
59; CMOV32R2-NEXT: jr $ra
60; CMOV32R2-NEXT: movn.s $f0, $f1, $1
61;
62; 32R6-LABEL: tst_select_i1_float:
63; 32R6: # %bb.0: # %entry
64; 32R6-NEXT: mtc1 $5, $f1
65; 32R6-NEXT: mtc1 $6, $f2
66; 32R6-NEXT: mtc1 $4, $f0
67; 32R6-NEXT: jr $ra
68; 32R6-NEXT: sel.s $f0, $f2, $f1
69;
70; M3-LABEL: tst_select_i1_float:
71; M3: # %bb.0: # %entry
72; M3-NEXT: andi $1, $4, 1
73; M3-NEXT: bnez $1, .LBB0_2
74; M3-NEXT: nop
75; M3-NEXT: # %bb.1: # %entry
76; M3-NEXT: mov.s $f13, $f14
77; M3-NEXT: .LBB0_2: # %entry
78; M3-NEXT: jr $ra
79; M3-NEXT: mov.s $f0, $f13
80;
81; CMOV64-LABEL: tst_select_i1_float:
82; CMOV64: # %bb.0: # %entry
83; CMOV64-NEXT: andi $1, $4, 1
84; CMOV64-NEXT: movn.s $f14, $f13, $1
85; CMOV64-NEXT: jr $ra
86; CMOV64-NEXT: mov.s $f0, $f14
87;
88; 64R6-LABEL: tst_select_i1_float:
89; 64R6: # %bb.0: # %entry
90; 64R6-NEXT: mtc1 $4, $f0
91; 64R6-NEXT: jr $ra
92; 64R6-NEXT: sel.s $f0, $f14, $f13
93;
94; MM32R3-LABEL: tst_select_i1_float:
95; MM32R3: # %bb.0: # %entry
96; MM32R3-NEXT: mtc1 $6, $f0
97; MM32R3-NEXT: andi16 $2, $4, 1
98; MM32R3-NEXT: mtc1 $5, $f1
99; MM32R3-NEXT: jr $ra
100; MM32R3-NEXT: movn.s $f0, $f1, $2
101;
102; MM32R6-LABEL: tst_select_i1_float:
103; MM32R6: # %bb.0: # %entry
104; MM32R6-NEXT: mtc1 $5, $f1
105; MM32R6-NEXT: mtc1 $6, $f2
106; MM32R6-NEXT: mtc1 $4, $f0
107; MM32R6-NEXT: sel.s $f0, $f2, $f1
108; MM32R6-NEXT: jrc $ra
Vasileios Kalintirisa0520372016-02-01 15:19:35 +0000[diff] [blame]109entry:
Vasileios Kalintirisa0520372016-02-01 15:19:35 +0000[diff] [blame]110 %r = select i1 %s, float %x, float %y
111 ret float %r
112}
113
Vasileios Kalintiris36901dd2016-03-01 20:25:43 +0000[diff] [blame]114define float @tst_select_i1_float_reordered(float %x, float %y,
Simon Dardis16596472018-02-22 11:53:01 +0000[diff] [blame^]115; M2-LABEL: tst_select_i1_float_reordered:
116; M2: # %bb.0: # %entry
117; M2-NEXT: andi $1, $6, 1
118; M2-NEXT: bnez $1, $BB1_2
119; M2-NEXT: nop
120; M2-NEXT: # %bb.1: # %entry
121; M2-NEXT: mov.s $f12, $f14
122; M2-NEXT: $BB1_2: # %entry
123; M2-NEXT: jr $ra
124; M2-NEXT: mov.s $f0, $f12
125;
126; CMOV32R1-LABEL: tst_select_i1_float_reordered:
127; CMOV32R1: # %bb.0: # %entry
128; CMOV32R1-NEXT: andi $1, $6, 1
129; CMOV32R1-NEXT: movn.s $f14, $f12, $1
130; CMOV32R1-NEXT: jr $ra
131; CMOV32R1-NEXT: mov.s $f0, $f14
132;
133; CMOV32R2-LABEL: tst_select_i1_float_reordered:
134; CMOV32R2: # %bb.0: # %entry
135; CMOV32R2-NEXT: andi $1, $6, 1
136; CMOV32R2-NEXT: movn.s $f14, $f12, $1
137; CMOV32R2-NEXT: jr $ra
138; CMOV32R2-NEXT: mov.s $f0, $f14
139;
140; 32R6-LABEL: tst_select_i1_float_reordered:
141; 32R6: # %bb.0: # %entry
142; 32R6-NEXT: mtc1 $6, $f0
143; 32R6-NEXT: jr $ra
144; 32R6-NEXT: sel.s $f0, $f14, $f12
145;
146; M3-LABEL: tst_select_i1_float_reordered:
147; M3: # %bb.0: # %entry
148; M3-NEXT: andi $1, $6, 1
149; M3-NEXT: bnez $1, .LBB1_2
150; M3-NEXT: nop
151; M3-NEXT: # %bb.1: # %entry
152; M3-NEXT: mov.s $f12, $f13
153; M3-NEXT: .LBB1_2: # %entry
154; M3-NEXT: jr $ra
155; M3-NEXT: mov.s $f0, $f12
156;
157; CMOV64-LABEL: tst_select_i1_float_reordered:
158; CMOV64: # %bb.0: # %entry
159; CMOV64-NEXT: andi $1, $6, 1
160; CMOV64-NEXT: movn.s $f13, $f12, $1
161; CMOV64-NEXT: jr $ra
162; CMOV64-NEXT: mov.s $f0, $f13
163;
164; 64R6-LABEL: tst_select_i1_float_reordered:
165; 64R6: # %bb.0: # %entry
166; 64R6-NEXT: mtc1 $6, $f0
167; 64R6-NEXT: jr $ra
168; 64R6-NEXT: sel.s $f0, $f13, $f12
169;
170; MM32R3-LABEL: tst_select_i1_float_reordered:
171; MM32R3: # %bb.0: # %entry
172; MM32R3-NEXT: andi16 $2, $6, 1
173; MM32R3-NEXT: movn.s $f14, $f12, $2
174; MM32R3-NEXT: jr $ra
175; MM32R3-NEXT: mov.s $f0, $f14
176;
177; MM32R6-LABEL: tst_select_i1_float_reordered:
178; MM32R6: # %bb.0: # %entry
179; MM32R6-NEXT: mtc1 $6, $f0
180; MM32R6-NEXT: sel.s $f0, $f14, $f12
181; MM32R6-NEXT: jrc $ra
Vasileios Kalintiris36901dd2016-03-01 20:25:43 +0000[diff] [blame]182 i1 signext %s) {
Vasileios Kalintirisa0520372016-02-01 15:19:35 +0000[diff] [blame]183entry:
Vasileios Kalintirisa0520372016-02-01 15:19:35 +0000[diff] [blame]184 %r = select i1 %s, float %x, float %y
185 ret float %r
186}
187
188define float @tst_select_fcmp_olt_float(float %x, float %y) {
Simon Dardis16596472018-02-22 11:53:01 +0000[diff] [blame^]189; M2-LABEL: tst_select_fcmp_olt_float:
190; M2: # %bb.0: # %entry
191; M2-NEXT: c.olt.s $f12, $f14
192; M2-NEXT: bc1t $BB2_2
193; M2-NEXT: nop
194; M2-NEXT: # %bb.1: # %entry
195; M2-NEXT: mov.s $f12, $f14
196; M2-NEXT: $BB2_2: # %entry
197; M2-NEXT: jr $ra
198; M2-NEXT: mov.s $f0, $f12
199;
200; CMOV32R1-LABEL: tst_select_fcmp_olt_float:
201; CMOV32R1: # %bb.0: # %entry
202; CMOV32R1-NEXT: c.olt.s $f12, $f14
203; CMOV32R1-NEXT: movt.s $f14, $f12, $fcc0
204; CMOV32R1-NEXT: jr $ra
205; CMOV32R1-NEXT: mov.s $f0, $f14
206;
207; CMOV32R2-LABEL: tst_select_fcmp_olt_float:
208; CMOV32R2: # %bb.0: # %entry
209; CMOV32R2-NEXT: c.olt.s $f12, $f14
210; CMOV32R2-NEXT: movt.s $f14, $f12, $fcc0
211; CMOV32R2-NEXT: jr $ra
212; CMOV32R2-NEXT: mov.s $f0, $f14
213;
214; 32R6-LABEL: tst_select_fcmp_olt_float:
215; 32R6: # %bb.0: # %entry
216; 32R6-NEXT: cmp.lt.s $f0, $f12, $f14
217; 32R6-NEXT: jr $ra
218; 32R6-NEXT: sel.s $f0, $f14, $f12
219;
220; M3-LABEL: tst_select_fcmp_olt_float:
221; M3: # %bb.0: # %entry
222; M3-NEXT: c.olt.s $f12, $f13
223; M3-NEXT: bc1t .LBB2_2
224; M3-NEXT: nop
225; M3-NEXT: # %bb.1: # %entry
226; M3-NEXT: mov.s $f12, $f13
227; M3-NEXT: .LBB2_2: # %entry
228; M3-NEXT: jr $ra
229; M3-NEXT: mov.s $f0, $f12
230;
231; CMOV64-LABEL: tst_select_fcmp_olt_float:
232; CMOV64: # %bb.0: # %entry
233; CMOV64-NEXT: c.olt.s $f12, $f13
234; CMOV64-NEXT: movt.s $f13, $f12, $fcc0
235; CMOV64-NEXT: jr $ra
236; CMOV64-NEXT: mov.s $f0, $f13
237;
238; 64R6-LABEL: tst_select_fcmp_olt_float:
239; 64R6: # %bb.0: # %entry
240; 64R6-NEXT: cmp.lt.s $f0, $f12, $f13
241; 64R6-NEXT: jr $ra
242; 64R6-NEXT: sel.s $f0, $f13, $f12
243;
244; MM32R3-LABEL: tst_select_fcmp_olt_float:
245; MM32R3: # %bb.0: # %entry
246; MM32R3-NEXT: c.olt.s $f12, $f14
247; MM32R3-NEXT: movt.s $f14, $f12, $fcc0
248; MM32R3-NEXT: jr $ra
249; MM32R3-NEXT: mov.s $f0, $f14
250;
251; MM32R6-LABEL: tst_select_fcmp_olt_float:
252; MM32R6: # %bb.0: # %entry
253; MM32R6-NEXT: cmp.lt.s $f0, $f12, $f14
254; MM32R6-NEXT: sel.s $f0, $f14, $f12
255; MM32R6-NEXT: jrc $ra
Vasileios Kalintirisa0520372016-02-01 15:19:35 +0000[diff] [blame]256entry:
Vasileios Kalintirisa0520372016-02-01 15:19:35 +0000[diff] [blame]257 %s = fcmp olt float %x, %y
258 %r = select i1 %s, float %x, float %y
259 ret float %r
260}
261
262define float @tst_select_fcmp_ole_float(float %x, float %y) {
Simon Dardis16596472018-02-22 11:53:01 +0000[diff] [blame^]263; M2-LABEL: tst_select_fcmp_ole_float:
264; M2: # %bb.0: # %entry
265; M2-NEXT: c.ole.s $f12, $f14
266; M2-NEXT: bc1t $BB3_2
267; M2-NEXT: nop
268; M2-NEXT: # %bb.1: # %entry
269; M2-NEXT: mov.s $f12, $f14
270; M2-NEXT: $BB3_2: # %entry
271; M2-NEXT: jr $ra
272; M2-NEXT: mov.s $f0, $f12
273;
274; CMOV32R1-LABEL: tst_select_fcmp_ole_float:
275; CMOV32R1: # %bb.0: # %entry
276; CMOV32R1-NEXT: c.ole.s $f12, $f14
277; CMOV32R1-NEXT: movt.s $f14, $f12, $fcc0
278; CMOV32R1-NEXT: jr $ra
279; CMOV32R1-NEXT: mov.s $f0, $f14
280;
281; CMOV32R2-LABEL: tst_select_fcmp_ole_float:
282; CMOV32R2: # %bb.0: # %entry
283; CMOV32R2-NEXT: c.ole.s $f12, $f14
284; CMOV32R2-NEXT: movt.s $f14, $f12, $fcc0
285; CMOV32R2-NEXT: jr $ra
286; CMOV32R2-NEXT: mov.s $f0, $f14
287;
288; 32R6-LABEL: tst_select_fcmp_ole_float:
289; 32R6: # %bb.0: # %entry
290; 32R6-NEXT: cmp.le.s $f0, $f12, $f14
291; 32R6-NEXT: jr $ra
292; 32R6-NEXT: sel.s $f0, $f14, $f12
293;
294; M3-LABEL: tst_select_fcmp_ole_float:
295; M3: # %bb.0: # %entry
296; M3-NEXT: c.ole.s $f12, $f13
297; M3-NEXT: bc1t .LBB3_2
298; M3-NEXT: nop
299; M3-NEXT: # %bb.1: # %entry
300; M3-NEXT: mov.s $f12, $f13
301; M3-NEXT: .LBB3_2: # %entry
302; M3-NEXT: jr $ra
303; M3-NEXT: mov.s $f0, $f12
304;
305; CMOV64-LABEL: tst_select_fcmp_ole_float:
306; CMOV64: # %bb.0: # %entry
307; CMOV64-NEXT: c.ole.s $f12, $f13
308; CMOV64-NEXT: movt.s $f13, $f12, $fcc0
309; CMOV64-NEXT: jr $ra
310; CMOV64-NEXT: mov.s $f0, $f13
311;
312; 64R6-LABEL: tst_select_fcmp_ole_float:
313; 64R6: # %bb.0: # %entry
314; 64R6-NEXT: cmp.le.s $f0, $f12, $f13
315; 64R6-NEXT: jr $ra
316; 64R6-NEXT: sel.s $f0, $f13, $f12
317;
318; MM32R3-LABEL: tst_select_fcmp_ole_float:
319; MM32R3: # %bb.0: # %entry
320; MM32R3-NEXT: c.ole.s $f12, $f14
321; MM32R3-NEXT: movt.s $f14, $f12, $fcc0
322; MM32R3-NEXT: jr $ra
323; MM32R3-NEXT: mov.s $f0, $f14
324;
325; MM32R6-LABEL: tst_select_fcmp_ole_float:
326; MM32R6: # %bb.0: # %entry
327; MM32R6-NEXT: cmp.le.s $f0, $f12, $f14
328; MM32R6-NEXT: sel.s $f0, $f14, $f12
329; MM32R6-NEXT: jrc $ra
Vasileios Kalintirisa0520372016-02-01 15:19:35 +0000[diff] [blame]330entry:
Vasileios Kalintirisa0520372016-02-01 15:19:35 +0000[diff] [blame]331 %s = fcmp ole float %x, %y
332 %r = select i1 %s, float %x, float %y
333 ret float %r
334}
335
336define float @tst_select_fcmp_ogt_float(float %x, float %y) {
Simon Dardis16596472018-02-22 11:53:01 +0000[diff] [blame^]337; M2-LABEL: tst_select_fcmp_ogt_float:
338; M2: # %bb.0: # %entry
339; M2-NEXT: c.ule.s $f12, $f14
340; M2-NEXT: bc1f $BB4_2
341; M2-NEXT: nop
342; M2-NEXT: # %bb.1: # %entry
343; M2-NEXT: mov.s $f12, $f14
344; M2-NEXT: $BB4_2: # %entry
345; M2-NEXT: jr $ra
346; M2-NEXT: mov.s $f0, $f12
347;
348; CMOV32R1-LABEL: tst_select_fcmp_ogt_float:
349; CMOV32R1: # %bb.0: # %entry
350; CMOV32R1-NEXT: c.ule.s $f12, $f14
351; CMOV32R1-NEXT: movf.s $f14, $f12, $fcc0
352; CMOV32R1-NEXT: jr $ra
353; CMOV32R1-NEXT: mov.s $f0, $f14
354;
355; CMOV32R2-LABEL: tst_select_fcmp_ogt_float:
356; CMOV32R2: # %bb.0: # %entry
357; CMOV32R2-NEXT: c.ule.s $f12, $f14
358; CMOV32R2-NEXT: movf.s $f14, $f12, $fcc0
359; CMOV32R2-NEXT: jr $ra
360; CMOV32R2-NEXT: mov.s $f0, $f14
361;
362; 32R6-LABEL: tst_select_fcmp_ogt_float:
363; 32R6: # %bb.0: # %entry
364; 32R6-NEXT: cmp.lt.s $f0, $f14, $f12
365; 32R6-NEXT: jr $ra
366; 32R6-NEXT: sel.s $f0, $f14, $f12
367;
368; M3-LABEL: tst_select_fcmp_ogt_float:
369; M3: # %bb.0: # %entry
370; M3-NEXT: c.ule.s $f12, $f13
371; M3-NEXT: bc1f .LBB4_2
372; M3-NEXT: nop
373; M3-NEXT: # %bb.1: # %entry
374; M3-NEXT: mov.s $f12, $f13
375; M3-NEXT: .LBB4_2: # %entry
376; M3-NEXT: jr $ra
377; M3-NEXT: mov.s $f0, $f12
378;
379; CMOV64-LABEL: tst_select_fcmp_ogt_float:
380; CMOV64: # %bb.0: # %entry
381; CMOV64-NEXT: c.ule.s $f12, $f13
382; CMOV64-NEXT: movf.s $f13, $f12, $fcc0
383; CMOV64-NEXT: jr $ra
384; CMOV64-NEXT: mov.s $f0, $f13
385;
386; 64R6-LABEL: tst_select_fcmp_ogt_float:
387; 64R6: # %bb.0: # %entry
388; 64R6-NEXT: cmp.lt.s $f0, $f13, $f12
389; 64R6-NEXT: jr $ra
390; 64R6-NEXT: sel.s $f0, $f13, $f12
391;
392; MM32R3-LABEL: tst_select_fcmp_ogt_float:
393; MM32R3: # %bb.0: # %entry
394; MM32R3-NEXT: c.ule.s $f12, $f14
395; MM32R3-NEXT: movf.s $f14, $f12, $fcc0
396; MM32R3-NEXT: jr $ra
397; MM32R3-NEXT: mov.s $f0, $f14
398;
399; MM32R6-LABEL: tst_select_fcmp_ogt_float:
400; MM32R6: # %bb.0: # %entry
401; MM32R6-NEXT: cmp.lt.s $f0, $f14, $f12
402; MM32R6-NEXT: sel.s $f0, $f14, $f12
403; MM32R6-NEXT: jrc $ra
Vasileios Kalintirisa0520372016-02-01 15:19:35 +0000[diff] [blame]404entry:
Vasileios Kalintirisa0520372016-02-01 15:19:35 +0000[diff] [blame]405 %s = fcmp ogt float %x, %y
406 %r = select i1 %s, float %x, float %y
407 ret float %r
408}
409
410define float @tst_select_fcmp_oge_float(float %x, float %y) {
Simon Dardis16596472018-02-22 11:53:01 +0000[diff] [blame^]411; M2-LABEL: tst_select_fcmp_oge_float:
412; M2: # %bb.0: # %entry
413; M2-NEXT: c.ult.s $f12, $f14
414; M2-NEXT: bc1f $BB5_2
415; M2-NEXT: nop
416; M2-NEXT: # %bb.1: # %entry
417; M2-NEXT: mov.s $f12, $f14
418; M2-NEXT: $BB5_2: # %entry
419; M2-NEXT: jr $ra
420; M2-NEXT: mov.s $f0, $f12
421;
422; CMOV32R1-LABEL: tst_select_fcmp_oge_float:
423; CMOV32R1: # %bb.0: # %entry
424; CMOV32R1-NEXT: c.ult.s $f12, $f14
425; CMOV32R1-NEXT: movf.s $f14, $f12, $fcc0
426; CMOV32R1-NEXT: jr $ra
427; CMOV32R1-NEXT: mov.s $f0, $f14
428;
429; CMOV32R2-LABEL: tst_select_fcmp_oge_float:
430; CMOV32R2: # %bb.0: # %entry
431; CMOV32R2-NEXT: c.ult.s $f12, $f14
432; CMOV32R2-NEXT: movf.s $f14, $f12, $fcc0
433; CMOV32R2-NEXT: jr $ra
434; CMOV32R2-NEXT: mov.s $f0, $f14
435;
436; 32R6-LABEL: tst_select_fcmp_oge_float:
437; 32R6: # %bb.0: # %entry
438; 32R6-NEXT: cmp.le.s $f0, $f14, $f12
439; 32R6-NEXT: jr $ra
440; 32R6-NEXT: sel.s $f0, $f14, $f12
441;
442; M3-LABEL: tst_select_fcmp_oge_float:
443; M3: # %bb.0: # %entry
444; M3-NEXT: c.ult.s $f12, $f13
445; M3-NEXT: bc1f .LBB5_2
446; M3-NEXT: nop
447; M3-NEXT: # %bb.1: # %entry
448; M3-NEXT: mov.s $f12, $f13
449; M3-NEXT: .LBB5_2: # %entry
450; M3-NEXT: jr $ra
451; M3-NEXT: mov.s $f0, $f12
452;
453; CMOV64-LABEL: tst_select_fcmp_oge_float:
454; CMOV64: # %bb.0: # %entry
455; CMOV64-NEXT: c.ult.s $f12, $f13
456; CMOV64-NEXT: movf.s $f13, $f12, $fcc0
457; CMOV64-NEXT: jr $ra
458; CMOV64-NEXT: mov.s $f0, $f13
459;
460; 64R6-LABEL: tst_select_fcmp_oge_float:
461; 64R6: # %bb.0: # %entry
462; 64R6-NEXT: cmp.le.s $f0, $f13, $f12
463; 64R6-NEXT: jr $ra
464; 64R6-NEXT: sel.s $f0, $f13, $f12
465;
466; MM32R3-LABEL: tst_select_fcmp_oge_float:
467; MM32R3: # %bb.0: # %entry
468; MM32R3-NEXT: c.ult.s $f12, $f14
469; MM32R3-NEXT: movf.s $f14, $f12, $fcc0
470; MM32R3-NEXT: jr $ra
471; MM32R3-NEXT: mov.s $f0, $f14
472;
473; MM32R6-LABEL: tst_select_fcmp_oge_float:
474; MM32R6: # %bb.0: # %entry
475; MM32R6-NEXT: cmp.le.s $f0, $f14, $f12
476; MM32R6-NEXT: sel.s $f0, $f14, $f12
477; MM32R6-NEXT: jrc $ra
Vasileios Kalintirisa0520372016-02-01 15:19:35 +0000[diff] [blame]478entry:
Vasileios Kalintirisa0520372016-02-01 15:19:35 +0000[diff] [blame]479 %s = fcmp oge float %x, %y
480 %r = select i1 %s, float %x, float %y
481 ret float %r
482}
483
484define float @tst_select_fcmp_oeq_float(float %x, float %y) {
Simon Dardis16596472018-02-22 11:53:01 +0000[diff] [blame^]485; M2-LABEL: tst_select_fcmp_oeq_float:
486; M2: # %bb.0: # %entry
487; M2-NEXT: c.eq.s $f12, $f14
488; M2-NEXT: bc1t $BB6_2
489; M2-NEXT: nop
490; M2-NEXT: # %bb.1: # %entry
491; M2-NEXT: mov.s $f12, $f14
492; M2-NEXT: $BB6_2: # %entry
493; M2-NEXT: jr $ra
494; M2-NEXT: mov.s $f0, $f12
495;
496; CMOV32R1-LABEL: tst_select_fcmp_oeq_float:
497; CMOV32R1: # %bb.0: # %entry
498; CMOV32R1-NEXT: c.eq.s $f12, $f14
499; CMOV32R1-NEXT: movt.s $f14, $f12, $fcc0
500; CMOV32R1-NEXT: jr $ra
501; CMOV32R1-NEXT: mov.s $f0, $f14
502;
503; CMOV32R2-LABEL: tst_select_fcmp_oeq_float:
504; CMOV32R2: # %bb.0: # %entry
505; CMOV32R2-NEXT: c.eq.s $f12, $f14
506; CMOV32R2-NEXT: movt.s $f14, $f12, $fcc0
507; CMOV32R2-NEXT: jr $ra
508; CMOV32R2-NEXT: mov.s $f0, $f14
509;
510; 32R6-LABEL: tst_select_fcmp_oeq_float:
511; 32R6: # %bb.0: # %entry
512; 32R6-NEXT: cmp.eq.s $f0, $f12, $f14
513; 32R6-NEXT: jr $ra
514; 32R6-NEXT: sel.s $f0, $f14, $f12
515;
516; M3-LABEL: tst_select_fcmp_oeq_float:
517; M3: # %bb.0: # %entry
518; M3-NEXT: c.eq.s $f12, $f13
519; M3-NEXT: bc1t .LBB6_2
520; M3-NEXT: nop
521; M3-NEXT: # %bb.1: # %entry
522; M3-NEXT: mov.s $f12, $f13
523; M3-NEXT: .LBB6_2: # %entry
524; M3-NEXT: jr $ra
525; M3-NEXT: mov.s $f0, $f12
526;
527; CMOV64-LABEL: tst_select_fcmp_oeq_float:
528; CMOV64: # %bb.0: # %entry
529; CMOV64-NEXT: c.eq.s $f12, $f13
530; CMOV64-NEXT: movt.s $f13, $f12, $fcc0
531; CMOV64-NEXT: jr $ra
532; CMOV64-NEXT: mov.s $f0, $f13
533;
534; 64R6-LABEL: tst_select_fcmp_oeq_float:
535; 64R6: # %bb.0: # %entry
536; 64R6-NEXT: cmp.eq.s $f0, $f12, $f13
537; 64R6-NEXT: jr $ra
538; 64R6-NEXT: sel.s $f0, $f13, $f12
539;
540; MM32R3-LABEL: tst_select_fcmp_oeq_float:
541; MM32R3: # %bb.0: # %entry
542; MM32R3-NEXT: c.eq.s $f12, $f14
543; MM32R3-NEXT: movt.s $f14, $f12, $fcc0
544; MM32R3-NEXT: jr $ra
545; MM32R3-NEXT: mov.s $f0, $f14
546;
547; MM32R6-LABEL: tst_select_fcmp_oeq_float:
548; MM32R6: # %bb.0: # %entry
549; MM32R6-NEXT: cmp.eq.s $f0, $f12, $f14
550; MM32R6-NEXT: sel.s $f0, $f14, $f12
551; MM32R6-NEXT: jrc $ra
Vasileios Kalintirisa0520372016-02-01 15:19:35 +0000[diff] [blame]552entry:
Vasileios Kalintirisa0520372016-02-01 15:19:35 +0000[diff] [blame]553 %s = fcmp oeq float %x, %y
554 %r = select i1 %s, float %x, float %y
555 ret float %r
556}
557
558define float @tst_select_fcmp_one_float(float %x, float %y) {
Simon Dardis16596472018-02-22 11:53:01 +0000[diff] [blame^]559; M2-LABEL: tst_select_fcmp_one_float:
560; M2: # %bb.0: # %entry
561; M2-NEXT: c.ueq.s $f12, $f14
562; M2-NEXT: bc1f $BB7_2
563; M2-NEXT: nop
564; M2-NEXT: # %bb.1: # %entry
565; M2-NEXT: mov.s $f12, $f14
566; M2-NEXT: $BB7_2: # %entry
567; M2-NEXT: jr $ra
568; M2-NEXT: mov.s $f0, $f12
569;
570; CMOV32R1-LABEL: tst_select_fcmp_one_float:
571; CMOV32R1: # %bb.0: # %entry
572; CMOV32R1-NEXT: c.ueq.s $f12, $f14
573; CMOV32R1-NEXT: movf.s $f14, $f12, $fcc0
574; CMOV32R1-NEXT: jr $ra
575; CMOV32R1-NEXT: mov.s $f0, $f14
576;
577; CMOV32R2-LABEL: tst_select_fcmp_one_float:
578; CMOV32R2: # %bb.0: # %entry
579; CMOV32R2-NEXT: c.ueq.s $f12, $f14
580; CMOV32R2-NEXT: movf.s $f14, $f12, $fcc0
581; CMOV32R2-NEXT: jr $ra
582; CMOV32R2-NEXT: mov.s $f0, $f14
583;
584; 32R6-LABEL: tst_select_fcmp_one_float:
585; 32R6: # %bb.0: # %entry
586; 32R6-NEXT: cmp.ueq.s $f0, $f12, $f14
587; 32R6-NEXT: mfc1 $1, $f0
588; 32R6-NEXT: not $1, $1
589; 32R6-NEXT: mtc1 $1, $f0
590; 32R6-NEXT: jr $ra
591; 32R6-NEXT: sel.s $f0, $f14, $f12
592;
593; M3-LABEL: tst_select_fcmp_one_float:
594; M3: # %bb.0: # %entry
595; M3-NEXT: c.ueq.s $f12, $f13
596; M3-NEXT: bc1f .LBB7_2
597; M3-NEXT: nop
598; M3-NEXT: # %bb.1: # %entry
599; M3-NEXT: mov.s $f12, $f13
600; M3-NEXT: .LBB7_2: # %entry
601; M3-NEXT: jr $ra
602; M3-NEXT: mov.s $f0, $f12
603;
604; CMOV64-LABEL: tst_select_fcmp_one_float:
605; CMOV64: # %bb.0: # %entry
606; CMOV64-NEXT: c.ueq.s $f12, $f13
607; CMOV64-NEXT: movf.s $f13, $f12, $fcc0
608; CMOV64-NEXT: jr $ra
609; CMOV64-NEXT: mov.s $f0, $f13
610;
611; 64R6-LABEL: tst_select_fcmp_one_float:
612; 64R6: # %bb.0: # %entry
613; 64R6-NEXT: cmp.ueq.s $f0, $f12, $f13
614; 64R6-NEXT: mfc1 $1, $f0
615; 64R6-NEXT: not $1, $1
616; 64R6-NEXT: mtc1 $1, $f0
617; 64R6-NEXT: jr $ra
618; 64R6-NEXT: sel.s $f0, $f13, $f12
619;
620; MM32R3-LABEL: tst_select_fcmp_one_float:
621; MM32R3: # %bb.0: # %entry
622; MM32R3-NEXT: c.ueq.s $f12, $f14
623; MM32R3-NEXT: movf.s $f14, $f12, $fcc0
624; MM32R3-NEXT: jr $ra
625; MM32R3-NEXT: mov.s $f0, $f14
626;
627; MM32R6-LABEL: tst_select_fcmp_one_float:
628; MM32R6: # %bb.0: # %entry
629; MM32R6-NEXT: cmp.ueq.s $f0, $f12, $f14
630; MM32R6-NEXT: mfc1 $1, $f0
631; MM32R6-NEXT: not $1, $1
632; MM32R6-NEXT: mtc1 $1, $f0
633; MM32R6-NEXT: sel.s $f0, $f14, $f12
634; MM32R6-NEXT: jrc $ra
Vasileios Kalintirisa0520372016-02-01 15:19:35 +0000[diff] [blame]635entry:
Vasileios Kalintirisa0520372016-02-01 15:19:35 +0000[diff] [blame]636 %s = fcmp one float %x, %y
637 %r = select i1 %s, float %x, float %y
638 ret float %r
639}