Gitiles
Code Review Sign In
gerrit-public.fairphone.software / toolchain / llvm-project / 36901dd1c3b27b5a954c6f78b8ae7d6580ce2e12 / . / llvm / test / CodeGen / Mips / llvm-ir / select-flt.ll
blob: 173055a5ef5f00e069b1b89e8918680e16f3ed4b [file] [log] [blame]
Vasileios Kalintirisa0520372016-02-01 15:19:35 +0000[diff] [blame]1; RUN: llc < %s -march=mips -mcpu=mips2 | FileCheck %s \
2; RUN: -check-prefix=ALL -check-prefix=M2 -check-prefix=M2-M3
3; RUN: llc < %s -march=mips -mcpu=mips32 | FileCheck %s \
4; RUN: -check-prefix=ALL -check-prefix=CMOV \
5; RUN: -check-prefix=CMOV-32 -check-prefix=CMOV-32R1
6; RUN: llc < %s -march=mips -mcpu=mips32r2 | FileCheck %s \
7; RUN: -check-prefix=ALL -check-prefix=CMOV \
8; RUN: -check-prefix=CMOV-32 -check-prefix=CMOV-32R2-R5
9; RUN: llc < %s -march=mips -mcpu=mips32r3 | FileCheck %s \
10; RUN: -check-prefix=ALL -check-prefix=CMOV \
11; RUN: -check-prefix=CMOV-32 -check-prefix=CMOV-32R2-R5
12; RUN: llc < %s -march=mips -mcpu=mips32r5 | FileCheck %s \
13; RUN: -check-prefix=ALL -check-prefix=CMOV \
14; RUN: -check-prefix=CMOV-32 -check-prefix=CMOV-32R2-R5
15; RUN: llc < %s -march=mips -mcpu=mips32r6 | FileCheck %s \
16; RUN: -check-prefix=ALL -check-prefix=SEL -check-prefix=SEL-32
17; RUN: llc < %s -march=mips64 -mcpu=mips3 | FileCheck %s \
18; RUN: -check-prefix=ALL -check-prefix=M3 -check-prefix=M2-M3
19; RUN: llc < %s -march=mips64 -mcpu=mips4 | FileCheck %s \
20; RUN: -check-prefix=ALL -check-prefix=CMOV -check-prefix=CMOV-64
21; RUN: llc < %s -march=mips64 -mcpu=mips64 | FileCheck %s \
22; RUN: -check-prefix=ALL -check-prefix=CMOV -check-prefix=CMOV-64
23; RUN: llc < %s -march=mips64 -mcpu=mips64r2 | FileCheck %s \
24; RUN: -check-prefix=ALL -check-prefix=CMOV -check-prefix=CMOV-64
25; RUN: llc < %s -march=mips64 -mcpu=mips64r3 | FileCheck %s \
26; RUN: -check-prefix=ALL -check-prefix=CMOV -check-prefix=CMOV-64
27; RUN: llc < %s -march=mips64 -mcpu=mips64r5 | FileCheck %s \
28; RUN: -check-prefix=ALL -check-prefix=CMOV -check-prefix=CMOV-64
29; RUN: llc < %s -march=mips64 -mcpu=mips64r6 | FileCheck %s \
30; RUN: -check-prefix=ALL -check-prefix=SEL -check-prefix=SEL-64
31
Vasileios Kalintiris36901dd2016-03-01 20:25:43 +0000[diff] [blame^]32define float @tst_select_i1_float(i1 signext %s, float %x, float %y) {
Vasileios Kalintirisa0520372016-02-01 15:19:35 +0000[diff] [blame]33entry:
34 ; ALL-LABEL: tst_select_i1_float:
35
36 ; M2-M3: andi $[[T0:[0-9]+]], $4, 1
37 ; M2-M3: bnez $[[T0]], $[[BB0:BB[0-9_]+]]
38 ; M2-M3: nop
39 ; M2: jr $ra
40 ; M2: mtc1 $6, $f0
41 ; M3: mov.s $f13, $f14
42 ; M2-M3: $[[BB0]]:
43 ; M2-M3: jr $ra
44 ; M2: mtc1 $5, $f0
45 ; M3: mov.s $f0, $f13
46
47 ; CMOV-32: mtc1 $6, $f0
48 ; CMOV-32: mtc1 $5, $f1
49 ; CMOV-32: andi $[[T0:[0-9]+]], $4, 1
50 ; CMOV-32: movn.s $f0, $f1, $[[T0]]
51
52 ; SEL-32: mtc1 $5, $[[F0:f[0-9]+]]
53 ; SEL-32: mtc1 $6, $[[F1:f[0-9]+]]
Vasileios Kalintiris36901dd2016-03-01 20:25:43 +0000[diff] [blame^]54 ; SEL-32: mtc1 $4, $f0
Vasileios Kalintirisa0520372016-02-01 15:19:35 +0000[diff] [blame]55 ; SEL-32: sel.s $f0, $[[F1]], $[[F0]]
56
57 ; CMOV-64: andi $[[T0:[0-9]+]], $4, 1
58 ; CMOV-64: movn.s $f14, $f13, $[[T0]]
59 ; CMOV-64: mov.s $f0, $f14
60
Vasileios Kalintiris36901dd2016-03-01 20:25:43 +0000[diff] [blame^]61 ; SEL-64: mtc1 $4, $f0
Vasileios Kalintirisa0520372016-02-01 15:19:35 +0000[diff] [blame]62 ; SEL-64: sel.s $f0, $f14, $f13
63 %r = select i1 %s, float %x, float %y
64 ret float %r
65}
66
Vasileios Kalintiris36901dd2016-03-01 20:25:43 +0000[diff] [blame^]67define float @tst_select_i1_float_reordered(float %x, float %y,
68 i1 signext %s) {
Vasileios Kalintirisa0520372016-02-01 15:19:35 +0000[diff] [blame]69entry:
70 ; ALL-LABEL: tst_select_i1_float_reordered:
71
72 ; M2-M3: andi $[[T0:[0-9]+]], $6, 1
73 ; M2-M3: bnez $[[T0]], $[[BB0:BB[0-9_]+]]
74 ; M2-M3: nop
75 ; M2: mov.s $f12, $f14
76 ; M3: mov.s $f12, $f13
77 ; M2-M3: $[[BB0]]:
78 ; M2-M3: jr $ra
79 ; M2-M3: mov.s $f0, $f12
80
81 ; CMOV-32: andi $[[T0:[0-9]+]], $6, 1
82 ; CMOV-32: movn.s $f14, $f12, $[[T0]]
83 ; CMOV-32: mov.s $f0, $f14
84
Vasileios Kalintiris36901dd2016-03-01 20:25:43 +0000[diff] [blame^]85 ; SEL-32: mtc1 $6, $f0
Vasileios Kalintirisa0520372016-02-01 15:19:35 +0000[diff] [blame]86 ; SEL-32: sel.s $f0, $f14, $f12
87
88 ; CMOV-64: andi $[[T0:[0-9]+]], $6, 1
89 ; CMOV-64: movn.s $f13, $f12, $[[T0]]
90 ; CMOV-64: mov.s $f0, $f13
91
Vasileios Kalintiris36901dd2016-03-01 20:25:43 +0000[diff] [blame^]92 ; SEL-64: mtc1 $6, $f0
Vasileios Kalintirisa0520372016-02-01 15:19:35 +0000[diff] [blame]93 ; SEL-64: sel.s $f0, $f13, $f12
94 %r = select i1 %s, float %x, float %y
95 ret float %r
96}
97
98define float @tst_select_fcmp_olt_float(float %x, float %y) {
99entry:
100 ; ALL-LABEL: tst_select_fcmp_olt_float:
101
102 ; M2: c.olt.s $f12, $f14
103 ; M3: c.olt.s $f12, $f13
104 ; M2-M3: bc1t $[[BB0:BB[0-9_]+]]
105 ; M2-M3: nop
106 ; M2: mov.s $f12, $f14
107 ; M3: mov.s $f12, $f13
108 ; M2-M3: $[[BB0]]:
109 ; M2-M3: jr $ra
110 ; M2-M3: mov.s $f0, $f12
111
112 ; CMOV-32: c.olt.s $f12, $f14
113 ; CMOV-32: movt.s $f14, $f12, $fcc0
114 ; CMOV-32: mov.s $f0, $f14
115
116 ; SEL-32: cmp.lt.s $f0, $f12, $f14
117 ; SEL-32: sel.s $f0, $f14, $f12
118
119 ; CMOV-64: c.olt.s $f12, $f13
120 ; CMOV-64: movt.s $f13, $f12, $fcc0
121 ; CMOV-64: mov.s $f0, $f13
122
123 ; SEL-64: cmp.lt.s $f0, $f12, $f13
124 ; SEL-64: sel.s $f0, $f13, $f12
125 %s = fcmp olt float %x, %y
126 %r = select i1 %s, float %x, float %y
127 ret float %r
128}
129
130define float @tst_select_fcmp_ole_float(float %x, float %y) {
131entry:
132 ; ALL-LABEL: tst_select_fcmp_ole_float:
133
134 ; M2: c.ole.s $f12, $f14
135 ; M3: c.ole.s $f12, $f13
136 ; M2-M3: bc1t $[[BB0:BB[0-9_]+]]
137 ; M2-M3: nop
138 ; M2: mov.s $f12, $f14
139 ; M3: mov.s $f12, $f13
140 ; M2-M3: $[[BB0]]:
141 ; M2-M3: jr $ra
142 ; M2-M3: mov.s $f0, $f12
143
144 ; CMOV-32: c.ole.s $f12, $f14
145 ; CMOV-32: movt.s $f14, $f12, $fcc0
146 ; CMOV-32: mov.s $f0, $f14
147
148 ; SEL-32: cmp.le.s $f0, $f12, $f14
149 ; SEL-32: sel.s $f0, $f14, $f12
150
151 ; CMOV-64: c.ole.s $f12, $f13
152 ; CMOV-64: movt.s $f13, $f12, $fcc0
153 ; CMOV-64: mov.s $f0, $f13
154
155 ; SEL-64: cmp.le.s $f0, $f12, $f13
156 ; SEL-64: sel.s $f0, $f13, $f12
157 %s = fcmp ole float %x, %y
158 %r = select i1 %s, float %x, float %y
159 ret float %r
160}
161
162define float @tst_select_fcmp_ogt_float(float %x, float %y) {
163entry:
164 ; ALL-LABEL: tst_select_fcmp_ogt_float:
165
166 ; M2: c.ule.s $f12, $f14
167 ; M3: c.ule.s $f12, $f13
168 ; M2-M3: bc1f $[[BB0:BB[0-9_]+]]
169 ; M2-M3: nop
170 ; M2: mov.s $f12, $f14
171 ; M3: mov.s $f12, $f13
172 ; M2-M3: $[[BB0]]:
173 ; M2-M3: jr $ra
174 ; M2-M3: mov.s $f0, $f12
175
176 ; CMOV-32: c.ule.s $f12, $f14
177 ; CMOV-32: movf.s $f14, $f12, $fcc0
178 ; CMOV-32: mov.s $f0, $f14
179
180 ; SEL-32: cmp.lt.s $f0, $f14, $f12
181 ; SEL-32: sel.s $f0, $f14, $f12
182
183 ; CMOV-64: c.ule.s $f12, $f13
184 ; CMOV-64: movf.s $f13, $f12, $fcc0
185 ; CMOV-64: mov.s $f0, $f13
186
187 ; SEL-64: cmp.lt.s $f0, $f13, $f12
188 ; SEL-64: sel.s $f0, $f13, $f12
189 %s = fcmp ogt float %x, %y
190 %r = select i1 %s, float %x, float %y
191 ret float %r
192}
193
194define float @tst_select_fcmp_oge_float(float %x, float %y) {
195entry:
196 ; ALL-LABEL: tst_select_fcmp_oge_float:
197
198 ; M2: c.ult.s $f12, $f14
199 ; M3: c.ult.s $f12, $f13
200 ; M2-M3: bc1f $[[BB0:BB[0-9_]+]]
201 ; M2-M3: nop
202 ; M2: mov.s $f12, $f14
203 ; M3: mov.s $f12, $f13
204 ; M2-M3: $[[BB0]]:
205 ; M2-M3: jr $ra
206 ; M2-M3: mov.s $f0, $f12
207
208 ; CMOV-32: c.ult.s $f12, $f14
209 ; CMOV-32: movf.s $f14, $f12, $fcc0
210 ; CMOV-32: mov.s $f0, $f14
211
212 ; SEL-32: cmp.le.s $f0, $f14, $f12
213 ; SEL-32: sel.s $f0, $f14, $f12
214
215 ; CMOV-64: c.ult.s $f12, $f13
216 ; CMOV-64: movf.s $f13, $f12, $fcc0
217 ; CMOV-64: mov.s $f0, $f13
218
219 ; SEL-64: cmp.le.s $f0, $f13, $f12
220 ; SEL-64: sel.s $f0, $f13, $f12
221 %s = fcmp oge float %x, %y
222 %r = select i1 %s, float %x, float %y
223 ret float %r
224}
225
226define float @tst_select_fcmp_oeq_float(float %x, float %y) {
227entry:
228 ; ALL-LABEL: tst_select_fcmp_oeq_float:
229
230 ; M2: c.eq.s $f12, $f14
231 ; M3: c.eq.s $f12, $f13
232 ; M2-M3: bc1t $[[BB0:BB[0-9_]+]]
233 ; M2-M3: nop
234 ; M2: mov.s $f12, $f14
235 ; M3: mov.s $f12, $f13
236 ; M2-M3: $[[BB0]]:
237 ; M2-M3: jr $ra
238 ; M2-M3: mov.s $f0, $f12
239
240 ; CMOV-32: c.eq.s $f12, $f14
241 ; CMOV-32: movt.s $f14, $f12, $fcc0
242 ; CMOV-32: mov.s $f0, $f14
243
244 ; SEL-32: cmp.eq.s $f0, $f12, $f14
245 ; SEL-32: sel.s $f0, $f14, $f12
246
247 ; CMOV-64: c.eq.s $f12, $f13
248 ; CMOV-64: movt.s $f13, $f12, $fcc0
249 ; CMOV-64: mov.s $f0, $f13
250
251 ; SEL-64: cmp.eq.s $f0, $f12, $f13
252 ; SEL-64: sel.s $f0, $f13, $f12
253 %s = fcmp oeq float %x, %y
254 %r = select i1 %s, float %x, float %y
255 ret float %r
256}
257
258define float @tst_select_fcmp_one_float(float %x, float %y) {
259entry:
260 ; ALL-LABEL: tst_select_fcmp_one_float:
261
262 ; M2: c.ueq.s $f12, $f14
263 ; M3: c.ueq.s $f12, $f13
264 ; M2-M3: bc1f $[[BB0:BB[0-9_]+]]
265 ; M2-M3: nop
266 ; M2: mov.s $f12, $f14
267 ; M3: mov.s $f12, $f13
268 ; M2-M3: $[[BB0]]:
269 ; M2-M3: jr $ra
270 ; M2-M3: mov.s $f0, $f12
271
272 ; CMOV-32: c.ueq.s $f12, $f14
273 ; CMOV-32: movf.s $f14, $f12, $fcc0
274 ; CMOV-32: mov.s $f0, $f14
275
276 ; SEL-32: cmp.ueq.s $f0, $f12, $f14
277 ; SEL-32: mfc1 $[[T0:[0-9]+]], $f0
278 ; SEL-32: not $[[T0]], $[[T0]]
279 ; SEL-32: mtc1 $[[T0:[0-9]+]], $f0
280 ; SEL-32: sel.s $f0, $f14, $f12
281
282 ; CMOV-64: c.ueq.s $f12, $f13
283 ; CMOV-64: movf.s $f13, $f12, $fcc0
284 ; CMOV-64: mov.s $f0, $f13
285
286 ; SEL-64: cmp.ueq.s $f0, $f12, $f13
287 ; SEL-64: mfc1 $[[T0:[0-9]+]], $f0
288 ; SEL-64: not $[[T0]], $[[T0]]
289 ; SEL-64: mtc1 $[[T0:[0-9]+]], $f0
290 ; SEL-64: sel.s $f0, $f13, $f12
291
292 %s = fcmp one float %x, %y
293 %r = select i1 %s, float %x, float %y
294 ret float %r
295}