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Jia Liuf54f60f2012-02-28 07:46:26 +00001//===-- MipsInstrFPU.td - Mips FPU Instruction Information -*- tablegen -*-===//
Bruno Cardoso Lopesc9c3f492008-07-05 19:05:21 +00002//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
Akira Hatanakae2489122011-04-15 21:51:11 +00008//===----------------------------------------------------------------------===//
Bruno Cardoso Lopesc9c3f492008-07-05 19:05:21 +00009//
Eric Christopher5dc19f92011-05-09 18:16:46 +000010// This file describes the Mips FPU instruction set.
Bruno Cardoso Lopesc9c3f492008-07-05 19:05:21 +000011//
Akira Hatanakae2489122011-04-15 21:51:11 +000012//===----------------------------------------------------------------------===//
Bruno Cardoso Lopesc9c3f492008-07-05 19:05:21 +000013
Akira Hatanakae2489122011-04-15 21:51:11 +000014//===----------------------------------------------------------------------===//
Bruno Cardoso Lopes7ceec572008-07-09 04:45:36 +000015// Floating Point Instructions
Bruno Cardoso Lopesc9c3f492008-07-05 19:05:21 +000016// ------------------------
17// * 64bit fp:
18// - 32 64-bit registers (default mode)
19// - 16 even 32-bit registers (32-bit compatible mode) for
20// single and double access.
21// * 32bit fp:
22// - 16 even 32-bit registers - single and double (aliased)
23// - 32 32-bit registers (within single-only mode)
Akira Hatanakae2489122011-04-15 21:51:11 +000024//===----------------------------------------------------------------------===//
Bruno Cardoso Lopesc9c3f492008-07-05 19:05:21 +000025
Bruno Cardoso Lopes7ceec572008-07-09 04:45:36 +000026// Floating Point Compare and Branch
Akira Hatanakaa5352702011-03-31 18:26:17 +000027def SDT_MipsFPBrcond : SDTypeProfile<0, 2, [SDTCisInt<0>,
28 SDTCisVT<1, OtherVT>]>;
29def SDT_MipsFPCmp : SDTypeProfile<0, 3, [SDTCisSameAs<0, 1>, SDTCisFP<1>,
Akira Hatanakaf25c37e2011-09-22 23:31:54 +000030 SDTCisVT<2, i32>]>;
Akira Hatanakaa5352702011-03-31 18:26:17 +000031def SDT_MipsCMovFP : SDTypeProfile<1, 2, [SDTCisSameAs<0, 1>,
32 SDTCisSameAs<1, 2>]>;
Akira Hatanaka252f54f2013-05-16 21:17:15 +000033def SDT_MipsTruncIntFP : SDTypeProfile<1, 1, [SDTCisFP<0>, SDTCisFP<1>]>;
Akira Hatanaka27916972011-04-15 19:52:08 +000034def SDT_MipsBuildPairF64 : SDTypeProfile<1, 2, [SDTCisVT<0, f64>,
35 SDTCisVT<1, i32>,
36 SDTCisSameAs<1, 2>]>;
37def SDT_MipsExtractElementF64 : SDTypeProfile<1, 2, [SDTCisVT<0, i32>,
38 SDTCisVT<1, f64>,
Akira Hatanakaf25c37e2011-09-22 23:31:54 +000039 SDTCisVT<2, i32>]>;
Bruno Cardoso Lopesa72a5052009-05-27 17:23:44 +000040
Akira Hatanakaa5352702011-03-31 18:26:17 +000041def MipsFPCmp : SDNode<"MipsISD::FPCmp", SDT_MipsFPCmp, [SDNPOutGlue]>;
42def MipsCMovFP_T : SDNode<"MipsISD::CMovFP_T", SDT_MipsCMovFP, [SDNPInGlue]>;
43def MipsCMovFP_F : SDNode<"MipsISD::CMovFP_F", SDT_MipsCMovFP, [SDNPInGlue]>;
Bruno Cardoso Lopesed874ef2011-03-04 17:51:39 +000044def MipsFPBrcond : SDNode<"MipsISD::FPBrcond", SDT_MipsFPBrcond,
Akira Hatanakaa5352702011-03-31 18:26:17 +000045 [SDNPHasChain, SDNPOptInGlue]>;
Akira Hatanaka252f54f2013-05-16 21:17:15 +000046def MipsTruncIntFP : SDNode<"MipsISD::TruncIntFP", SDT_MipsTruncIntFP>;
Akira Hatanaka27916972011-04-15 19:52:08 +000047def MipsBuildPairF64 : SDNode<"MipsISD::BuildPairF64", SDT_MipsBuildPairF64>;
48def MipsExtractElementF64 : SDNode<"MipsISD::ExtractElementF64",
49 SDT_MipsExtractElementF64>;
Bruno Cardoso Lopesc9c3f492008-07-05 19:05:21 +000050
51// Operand for printing out a condition code.
Akira Hatanaka71928e62012-04-17 18:03:21 +000052let PrintMethod = "printFCCOperand", DecoderMethod = "DecodeCondCode" in
Bruno Cardoso Lopesc9c3f492008-07-05 19:05:21 +000053 def condcode : Operand<i32>;
54
Akira Hatanakae2489122011-04-15 21:51:11 +000055//===----------------------------------------------------------------------===//
Bruno Cardoso Lopesc9c3f492008-07-05 19:05:21 +000056// Feature predicates.
Akira Hatanakae2489122011-04-15 21:51:11 +000057//===----------------------------------------------------------------------===//
Bruno Cardoso Lopesc9c3f492008-07-05 19:05:21 +000058
Akira Hatanakad8ab16b2012-06-14 21:03:23 +000059def IsFP64bit : Predicate<"Subtarget.isFP64bit()">,
60 AssemblerPredicate<"FeatureFP64Bit">;
61def NotFP64bit : Predicate<"!Subtarget.isFP64bit()">,
62 AssemblerPredicate<"!FeatureFP64Bit">;
63def IsSingleFloat : Predicate<"Subtarget.isSingleFloat()">,
64 AssemblerPredicate<"FeatureSingleFloat">;
65def IsNotSingleFloat : Predicate<"!Subtarget.isSingleFloat()">,
66 AssemblerPredicate<"!FeatureSingleFloat">;
Bruno Cardoso Lopesc9c3f492008-07-05 19:05:21 +000067
Akira Hatanaka60f7a8e2012-02-25 00:21:52 +000068// FP immediate patterns.
69def fpimm0 : PatLeaf<(fpimm), [{
70 return N->isExactlyValue(+0.0);
71}]>;
72
73def fpimm0neg : PatLeaf<(fpimm), [{
74 return N->isExactlyValue(-0.0);
75}]>;
76
Akira Hatanakae2489122011-04-15 21:51:11 +000077//===----------------------------------------------------------------------===//
Bruno Cardoso Lopesc9c3f492008-07-05 19:05:21 +000078// Instruction Class Templates
79//
Bruno Cardoso Lopesed874ef2011-03-04 17:51:39 +000080// A set of multiclasses is used to address the register usage.
Bruno Cardoso Lopesc9c3f492008-07-05 19:05:21 +000081//
Jakob Stoklund Olesen67289582011-09-28 23:59:28 +000082// S32 - single precision in 16 32bit even fp registers
Bruno Cardoso Lopes9b9586a2009-03-21 00:05:07 +000083// single precision in 32 32bit fp registers in SingleOnly mode
Jakob Stoklund Olesen67289582011-09-28 23:59:28 +000084// S64 - single precision in 32 64bit fp registers (In64BitMode)
Bruno Cardoso Lopes9b9586a2009-03-21 00:05:07 +000085// D32 - double precision in 16 32bit even fp registers
86// D64 - double precision in 32 64bit fp registers (In64BitMode)
Bruno Cardoso Lopesc9c3f492008-07-05 19:05:21 +000087//
Jakob Stoklund Olesen67289582011-09-28 23:59:28 +000088// Only S32 and D32 are supported right now.
Akira Hatanakae2489122011-04-15 21:51:11 +000089//===----------------------------------------------------------------------===//
Bruno Cardoso Lopesc9c3f492008-07-05 19:05:21 +000090
Akira Hatanaka29b51382012-12-13 01:07:37 +000091class ADDS_FT<string opstr, RegisterClass RC, InstrItinClass Itin, bit IsComm,
92 SDPatternOperator OpNode= null_frag> :
93 InstSE<(outs RC:$fd), (ins RC:$fs, RC:$ft),
94 !strconcat(opstr, "\t$fd, $fs, $ft"),
95 [(set RC:$fd, (OpNode RC:$fs, RC:$ft))], Itin, FrmFR> {
96 let isCommutable = IsComm;
97}
98
99multiclass ADDS_M<string opstr, InstrItinClass Itin, bit IsComm,
100 SDPatternOperator OpNode = null_frag> {
101 def _D32 : ADDS_FT<opstr, AFGR64, Itin, IsComm, OpNode>,
102 Requires<[NotFP64bit, HasStdEnc]>;
103 def _D64 : ADDS_FT<opstr, FGR64, Itin, IsComm, OpNode>,
104 Requires<[IsFP64bit, HasStdEnc]> {
105 string DecoderNamespace = "Mips64";
106 }
107}
108
Akira Hatanakadea8f612012-12-13 01:14:07 +0000109class ABSS_FT<string opstr, RegisterClass DstRC, RegisterClass SrcRC,
110 InstrItinClass Itin, SDPatternOperator OpNode= null_frag> :
111 InstSE<(outs DstRC:$fd), (ins SrcRC:$fs), !strconcat(opstr, "\t$fd, $fs"),
Akira Hatanaka28aed9c2013-01-25 00:20:39 +0000112 [(set DstRC:$fd, (OpNode SrcRC:$fs))], Itin, FrmFR>,
113 NeverHasSideEffects;
Akira Hatanakadea8f612012-12-13 01:14:07 +0000114
115multiclass ABSS_M<string opstr, InstrItinClass Itin,
116 SDPatternOperator OpNode= null_frag> {
117 def _D32 : ABSS_FT<opstr, AFGR64, AFGR64, Itin, OpNode>,
118 Requires<[NotFP64bit, HasStdEnc]>;
119 def _D64 : ABSS_FT<opstr, FGR64, FGR64, Itin, OpNode>,
120 Requires<[IsFP64bit, HasStdEnc]> {
121 string DecoderNamespace = "Mips64";
122 }
123}
124
125multiclass ROUND_M<string opstr, InstrItinClass Itin> {
126 def _D32 : ABSS_FT<opstr, FGR32, AFGR64, Itin>,
127 Requires<[NotFP64bit, HasStdEnc]>;
128 def _D64 : ABSS_FT<opstr, FGR32, FGR64, Itin>,
129 Requires<[IsFP64bit, HasStdEnc]> {
130 let DecoderNamespace = "Mips64";
131 }
132}
133
Akira Hatanaka2b75dde2012-12-13 01:16:49 +0000134class MFC1_FT<string opstr, RegisterClass DstRC, RegisterClass SrcRC,
135 InstrItinClass Itin, SDPatternOperator OpNode= null_frag> :
136 InstSE<(outs DstRC:$rt), (ins SrcRC:$fs), !strconcat(opstr, "\t$rt, $fs"),
137 [(set DstRC:$rt, (OpNode SrcRC:$fs))], Itin, FrmFR>;
138
139class MTC1_FT<string opstr, RegisterClass DstRC, RegisterClass SrcRC,
140 InstrItinClass Itin, SDPatternOperator OpNode= null_frag> :
141 InstSE<(outs DstRC:$fs), (ins SrcRC:$rt), !strconcat(opstr, "\t$rt, $fs"),
142 [(set DstRC:$fs, (OpNode SrcRC:$rt))], Itin, FrmFR>;
143
Jack Carter873c7242013-01-12 01:03:14 +0000144class MFC1_FT_CCR<string opstr, RegisterClass DstRC, RegisterOperand SrcRC,
145 InstrItinClass Itin, SDPatternOperator OpNode= null_frag> :
146 InstSE<(outs DstRC:$rt), (ins SrcRC:$fs), !strconcat(opstr, "\t$rt, $fs"),
147 [(set DstRC:$rt, (OpNode SrcRC:$fs))], Itin, FrmFR>;
148
149class MTC1_FT_CCR<string opstr, RegisterOperand DstRC, RegisterClass SrcRC,
150 InstrItinClass Itin, SDPatternOperator OpNode= null_frag> :
151 InstSE<(outs DstRC:$fs), (ins SrcRC:$rt), !strconcat(opstr, "\t$rt, $fs"),
152 [(set DstRC:$fs, (OpNode SrcRC:$rt))], Itin, FrmFR>;
153
Vladimir Medic233dd512013-06-24 10:05:34 +0000154class LW_FT<string opstr, RegisterOperand RC, InstrItinClass Itin,
Akira Hatanaka92994f42012-12-13 01:24:00 +0000155 Operand MemOpnd, SDPatternOperator OpNode= null_frag> :
156 InstSE<(outs RC:$rt), (ins MemOpnd:$addr), !strconcat(opstr, "\t$rt, $addr"),
Akira Hatanaka69fb3d12013-02-15 21:20:45 +0000157 [(set RC:$rt, (OpNode addrDefault:$addr))], Itin, FrmFI> {
Akira Hatanaka92994f42012-12-13 01:24:00 +0000158 let DecoderMethod = "DecodeFMem";
Akira Hatanaka9edae022013-05-13 18:23:35 +0000159 let mayLoad = 1;
Akira Hatanaka92994f42012-12-13 01:24:00 +0000160}
161
Vladimir Medic233dd512013-06-24 10:05:34 +0000162class SW_FT<string opstr, RegisterOperand RC, InstrItinClass Itin,
Akira Hatanaka92994f42012-12-13 01:24:00 +0000163 Operand MemOpnd, SDPatternOperator OpNode= null_frag> :
164 InstSE<(outs), (ins RC:$rt, MemOpnd:$addr), !strconcat(opstr, "\t$rt, $addr"),
Akira Hatanaka69fb3d12013-02-15 21:20:45 +0000165 [(OpNode RC:$rt, addrDefault:$addr)], Itin, FrmFI> {
Akira Hatanaka92994f42012-12-13 01:24:00 +0000166 let DecoderMethod = "DecodeFMem";
Akira Hatanaka9edae022013-05-13 18:23:35 +0000167 let mayStore = 1;
Akira Hatanaka92994f42012-12-13 01:24:00 +0000168}
Akira Hatanaka2b75dde2012-12-13 01:16:49 +0000169
Akira Hatanakab0d4acb2012-12-13 01:27:48 +0000170class MADDS_FT<string opstr, RegisterClass RC, InstrItinClass Itin,
171 SDPatternOperator OpNode = null_frag> :
172 InstSE<(outs RC:$fd), (ins RC:$fr, RC:$fs, RC:$ft),
173 !strconcat(opstr, "\t$fd, $fr, $fs, $ft"),
174 [(set RC:$fd, (OpNode (fmul RC:$fs, RC:$ft), RC:$fr))], Itin, FrmFR>;
175
176class NMADDS_FT<string opstr, RegisterClass RC, InstrItinClass Itin,
177 SDPatternOperator OpNode = null_frag> :
178 InstSE<(outs RC:$fd), (ins RC:$fr, RC:$fs, RC:$ft),
179 !strconcat(opstr, "\t$fd, $fr, $fs, $ft"),
180 [(set RC:$fd, (fsub fpimm0, (OpNode (fmul RC:$fs, RC:$ft), RC:$fr)))],
181 Itin, FrmFR>;
182
Vladimir Medic233dd512013-06-24 10:05:34 +0000183class LWXC1_FT<string opstr, RegisterOperand DRC, RegisterOperand PRC,
Akira Hatanakacd3dfd22012-12-13 01:30:49 +0000184 InstrItinClass Itin, SDPatternOperator OpNode = null_frag> :
185 InstSE<(outs DRC:$fd), (ins PRC:$base, PRC:$index),
186 !strconcat(opstr, "\t$fd, ${index}(${base})"),
Akira Hatanaka69fb3d12013-02-15 21:20:45 +0000187 [(set DRC:$fd, (OpNode (add PRC:$base, PRC:$index)))], Itin, FrmFI> {
188 let AddedComplexity = 20;
189}
Akira Hatanakacd3dfd22012-12-13 01:30:49 +0000190
Vladimir Medic233dd512013-06-24 10:05:34 +0000191class SWXC1_FT<string opstr, RegisterOperand DRC, RegisterOperand PRC,
Akira Hatanakacd3dfd22012-12-13 01:30:49 +0000192 InstrItinClass Itin, SDPatternOperator OpNode = null_frag> :
193 InstSE<(outs), (ins DRC:$fs, PRC:$base, PRC:$index),
194 !strconcat(opstr, "\t$fs, ${index}(${base})"),
Akira Hatanaka69fb3d12013-02-15 21:20:45 +0000195 [(OpNode DRC:$fs, (add PRC:$base, PRC:$index))], Itin, FrmFI> {
196 let AddedComplexity = 20;
197}
Akira Hatanakacd3dfd22012-12-13 01:30:49 +0000198
Akira Hatanakafd9163b2012-12-13 01:32:36 +0000199class BC1F_FT<string opstr, InstrItinClass Itin,
200 SDPatternOperator Op = null_frag> :
201 InstSE<(outs), (ins brtarget:$offset), !strconcat(opstr, "\t$offset"),
202 [(MipsFPBrcond Op, bb:$offset)], Itin, FrmFI> {
203 let isBranch = 1;
204 let isTerminator = 1;
205 let hasDelaySlot = 1;
206 let Defs = [AT];
207 let Uses = [FCR31];
208}
209
Akira Hatanaka79e1cdb2012-12-13 01:34:09 +0000210class CEQS_FT<string typestr, RegisterClass RC, InstrItinClass Itin,
211 SDPatternOperator OpNode = null_frag> :
212 InstSE<(outs), (ins RC:$fs, RC:$ft, condcode:$cond),
213 !strconcat("c.$cond.", typestr, "\t$fs, $ft"),
214 [(OpNode RC:$fs, RC:$ft, imm:$cond)], Itin, FrmFR> {
215 let Defs = [FCR31];
216}
217
Akira Hatanakae2489122011-04-15 21:51:11 +0000218//===----------------------------------------------------------------------===//
Bruno Cardoso Lopes7ceec572008-07-09 04:45:36 +0000219// Floating Point Instructions
Akira Hatanakae2489122011-04-15 21:51:11 +0000220//===----------------------------------------------------------------------===//
Akira Hatanakadea8f612012-12-13 01:14:07 +0000221def ROUND_W_S : ABSS_FT<"round.w.s", FGR32, FGR32, IIFcvt>, ABSS_FM<0xc, 16>;
222def TRUNC_W_S : ABSS_FT<"trunc.w.s", FGR32, FGR32, IIFcvt>, ABSS_FM<0xd, 16>;
223def CEIL_W_S : ABSS_FT<"ceil.w.s", FGR32, FGR32, IIFcvt>, ABSS_FM<0xe, 16>;
224def FLOOR_W_S : ABSS_FT<"floor.w.s", FGR32, FGR32, IIFcvt>, ABSS_FM<0xf, 16>;
Akira Hatanaka28aed9c2013-01-25 00:20:39 +0000225def CVT_W_S : ABSS_FT<"cvt.w.s", FGR32, FGR32, IIFcvt>, ABSS_FM<0x24, 16>;
Akira Hatanaka13ae13b2011-10-08 03:19:38 +0000226
Akira Hatanakadea8f612012-12-13 01:14:07 +0000227defm ROUND_W : ROUND_M<"round.w.d", IIFcvt>, ABSS_FM<0xc, 17>;
228defm TRUNC_W : ROUND_M<"trunc.w.d", IIFcvt>, ABSS_FM<0xd, 17>;
229defm CEIL_W : ROUND_M<"ceil.w.d", IIFcvt>, ABSS_FM<0xe, 17>;
230defm FLOOR_W : ROUND_M<"floor.w.d", IIFcvt>, ABSS_FM<0xf, 17>;
Akira Hatanaka28aed9c2013-01-25 00:20:39 +0000231defm CVT_W : ROUND_M<"cvt.w.d", IIFcvt>, ABSS_FM<0x24, 17>;
Akira Hatanakae986a592012-12-13 00:29:29 +0000232
233let Predicates = [IsFP64bit, HasStdEnc], DecoderNamespace = "Mips64" in {
Akira Hatanakadea8f612012-12-13 01:14:07 +0000234 def ROUND_L_S : ABSS_FT<"round.l.s", FGR64, FGR32, IIFcvt>, ABSS_FM<0x8, 16>;
235 def ROUND_L_D64 : ABSS_FT<"round.l.d", FGR64, FGR64, IIFcvt>,
236 ABSS_FM<0x8, 17>;
237 def TRUNC_L_S : ABSS_FT<"trunc.l.s", FGR64, FGR32, IIFcvt>, ABSS_FM<0x9, 16>;
238 def TRUNC_L_D64 : ABSS_FT<"trunc.l.d", FGR64, FGR64, IIFcvt>,
239 ABSS_FM<0x9, 17>;
240 def CEIL_L_S : ABSS_FT<"ceil.l.s", FGR64, FGR32, IIFcvt>, ABSS_FM<0xa, 16>;
241 def CEIL_L_D64 : ABSS_FT<"ceil.l.d", FGR64, FGR64, IIFcvt>, ABSS_FM<0xa, 17>;
242 def FLOOR_L_S : ABSS_FT<"floor.l.s", FGR64, FGR32, IIFcvt>, ABSS_FM<0xb, 16>;
243 def FLOOR_L_D64 : ABSS_FT<"floor.l.d", FGR64, FGR64, IIFcvt>,
244 ABSS_FM<0xb, 17>;
Akira Hatanakae986a592012-12-13 00:29:29 +0000245}
246
Akira Hatanakadea8f612012-12-13 01:14:07 +0000247def CVT_S_W : ABSS_FT<"cvt.s.w", FGR32, FGR32, IIFcvt>, ABSS_FM<0x20, 20>;
Akira Hatanaka28aed9c2013-01-25 00:20:39 +0000248def CVT_L_S : ABSS_FT<"cvt.l.s", FGR64, FGR32, IIFcvt>, ABSS_FM<0x25, 16>;
249def CVT_L_D64: ABSS_FT<"cvt.l.d", FGR64, FGR64, IIFcvt>, ABSS_FM<0x25, 17>;
Akira Hatanaka13ae13b2011-10-08 03:19:38 +0000250
Akira Hatanaka28aed9c2013-01-25 00:20:39 +0000251let Predicates = [NotFP64bit, HasStdEnc] in {
Akira Hatanakadea8f612012-12-13 01:14:07 +0000252 def CVT_S_D32 : ABSS_FT<"cvt.s.d", FGR32, AFGR64, IIFcvt>, ABSS_FM<0x20, 17>;
253 def CVT_D32_W : ABSS_FT<"cvt.d.w", AFGR64, FGR32, IIFcvt>, ABSS_FM<0x21, 20>;
254 def CVT_D32_S : ABSS_FT<"cvt.d.s", AFGR64, FGR32, IIFcvt>, ABSS_FM<0x21, 16>;
Akira Hatanaka13ae13b2011-10-08 03:19:38 +0000255}
256
Akira Hatanaka28aed9c2013-01-25 00:20:39 +0000257let Predicates = [IsFP64bit, HasStdEnc], DecoderNamespace = "Mips64" in {
Akira Hatanaka21bab5b2013-05-16 18:42:42 +0000258 def CVT_S_D64 : ABSS_FT<"cvt.s.d", FGR32, FGR64, IIFcvt>, ABSS_FM<0x20, 17>;
259 def CVT_S_L : ABSS_FT<"cvt.s.l", FGR32, FGR64, IIFcvt>, ABSS_FM<0x20, 21>;
260 def CVT_D64_W : ABSS_FT<"cvt.d.w", FGR64, FGR32, IIFcvt>, ABSS_FM<0x21, 20>;
261 def CVT_D64_S : ABSS_FT<"cvt.d.s", FGR64, FGR32, IIFcvt>, ABSS_FM<0x21, 16>;
262 def CVT_D64_L : ABSS_FT<"cvt.d.l", FGR64, FGR64, IIFcvt>, ABSS_FM<0x21, 21>;
Akira Hatanaka13ae13b2011-10-08 03:19:38 +0000263}
Bruno Cardoso Lopesc9c3f492008-07-05 19:05:21 +0000264
Akira Hatanaka39d40f72013-05-16 19:48:37 +0000265let isPseudo = 1, isCodeGenOnly = 1 in {
266 def PseudoCVT_S_W : ABSS_FT<"", FGR32, CPURegs, IIFcvt>;
267 def PseudoCVT_D32_W : ABSS_FT<"", AFGR64, CPURegs, IIFcvt>;
268 def PseudoCVT_S_L : ABSS_FT<"", FGR64, CPU64Regs, IIFcvt>;
269 def PseudoCVT_D64_W : ABSS_FT<"", FGR64, CPURegs, IIFcvt>;
270 def PseudoCVT_D64_L : ABSS_FT<"", FGR64, CPU64Regs, IIFcvt>;
271}
272
Akira Hatanaka97e179f2012-12-07 03:06:09 +0000273let Predicates = [NoNaNsFPMath, HasStdEnc] in {
Akira Hatanakadea8f612012-12-13 01:14:07 +0000274 def FABS_S : ABSS_FT<"abs.s", FGR32, FGR32, IIFcvt, fabs>, ABSS_FM<0x5, 16>;
275 def FNEG_S : ABSS_FT<"neg.s", FGR32, FGR32, IIFcvt, fneg>, ABSS_FM<0x7, 16>;
276 defm FABS : ABSS_M<"abs.d", IIFcvt, fabs>, ABSS_FM<0x5, 17>;
277 defm FNEG : ABSS_M<"neg.d", IIFcvt, fneg>, ABSS_FM<0x7, 17>;
Akira Hatanaka47ad6742012-04-11 22:59:08 +0000278}
Akira Hatanakae986a592012-12-13 00:29:29 +0000279
Akira Hatanakadea8f612012-12-13 01:14:07 +0000280def FSQRT_S : ABSS_FT<"sqrt.s", FGR32, FGR32, IIFsqrtSingle, fsqrt>,
281 ABSS_FM<0x4, 16>;
282defm FSQRT : ABSS_M<"sqrt.d", IIFsqrtDouble, fsqrt>, ABSS_FM<0x4, 17>;
Bruno Cardoso Lopesc9c3f492008-07-05 19:05:21 +0000283
284// The odd-numbered registers are only referenced when doing loads,
285// stores, and moves between floating-point and integer registers.
Bruno Cardoso Lopesed874ef2011-03-04 17:51:39 +0000286// When defining instructions, we reference all 32-bit registers,
Bruno Cardoso Lopesc9c3f492008-07-05 19:05:21 +0000287// regardless of register aliasing.
Bruno Cardoso Lopes2312a3a2011-10-18 17:50:36 +0000288
Bruno Cardoso Lopes2312a3a2011-10-18 17:50:36 +0000289/// Move Control Registers From/To CPU Registers
Jack Carter873c7242013-01-12 01:03:14 +0000290def CFC1 : MFC1_FT_CCR<"cfc1", CPURegs, CCROpnd, IIFmove>, MFC1_FM<2>;
291def CTC1 : MTC1_FT_CCR<"ctc1", CCROpnd, CPURegs, IIFmove>, MFC1_FM<6>;
Akira Hatanaka2b75dde2012-12-13 01:16:49 +0000292def MFC1 : MFC1_FT<"mfc1", CPURegs, FGR32, IIFmove, bitconvert>, MFC1_FM<0>;
293def MTC1 : MTC1_FT<"mtc1", FGR32, CPURegs, IIFmove, bitconvert>, MFC1_FM<4>;
294def DMFC1 : MFC1_FT<"dmfc1", CPU64Regs, FGR64, IIFmove, bitconvert>, MFC1_FM<1>;
295def DMTC1 : MTC1_FT<"dmtc1", FGR64, CPU64Regs, IIFmove, bitconvert>, MFC1_FM<5>;
Akira Hatanaka1537e292011-11-07 21:32:58 +0000296
Akira Hatanakadea8f612012-12-13 01:14:07 +0000297def FMOV_S : ABSS_FT<"mov.s", FGR32, FGR32, IIFmove>, ABSS_FM<0x6, 16>;
298def FMOV_D32 : ABSS_FT<"mov.d", AFGR64, AFGR64, IIFmove>, ABSS_FM<0x6, 17>,
Akira Hatanaka97e179f2012-12-07 03:06:09 +0000299 Requires<[NotFP64bit, HasStdEnc]>;
Akira Hatanakadea8f612012-12-13 01:14:07 +0000300def FMOV_D64 : ABSS_FT<"mov.d", FGR64, FGR64, IIFmove>, ABSS_FM<0x6, 17>,
Akira Hatanaka97e179f2012-12-07 03:06:09 +0000301 Requires<[IsFP64bit, HasStdEnc]> {
Akira Hatanaka71928e62012-04-17 18:03:21 +0000302 let DecoderNamespace = "Mips64";
303}
Bruno Cardoso Lopes7ee71912010-01-30 18:29:19 +0000304
Bruno Cardoso Lopes7ceec572008-07-09 04:45:36 +0000305/// Floating Point Memory Instructions
Akira Hatanaka97e179f2012-12-07 03:06:09 +0000306let Predicates = [IsN64, HasStdEnc], DecoderNamespace = "Mips64" in {
Vladimir Medic233dd512013-06-24 10:05:34 +0000307 def LWC1_P8 : LW_FT<"lwc1", FGR32RegsOpnd, IILoad, mem64, load>, LW_FM<0x31>;
308 def SWC1_P8 : SW_FT<"swc1", FGR32RegsOpnd, IIStore, mem64, store>,
309 LW_FM<0x39>;
310 def LDC164_P8 : LW_FT<"ldc1", FGR64RegsOpnd, IILoad, mem64, load>,
311 LW_FM<0x35> {
Akira Hatanaka71928e62012-04-17 18:03:21 +0000312 let isCodeGenOnly =1;
313 }
Vladimir Medic233dd512013-06-24 10:05:34 +0000314 def SDC164_P8 : SW_FT<"sdc1", FGR64RegsOpnd, IIStore, mem64, store>,
315 LW_FM<0x3d> {
Akira Hatanaka71928e62012-04-17 18:03:21 +0000316 let isCodeGenOnly =1;
317 }
Bruno Cardoso Lopesc9c3f492008-07-05 19:05:21 +0000318}
319
Akira Hatanaka97e179f2012-12-07 03:06:09 +0000320let Predicates = [NotN64, HasStdEnc] in {
Vladimir Medic233dd512013-06-24 10:05:34 +0000321 def LWC1 : LW_FT<"lwc1", FGR32RegsOpnd, IILoad, mem, load>, LW_FM<0x31>;
322 def SWC1 : SW_FT<"swc1", FGR32RegsOpnd, IIStore, mem, store>, LW_FM<0x39>;
Akira Hatanaka3c5cab42012-02-27 19:09:08 +0000323}
324
Akira Hatanaka97e179f2012-12-07 03:06:09 +0000325let Predicates = [NotN64, HasMips64, HasStdEnc],
Akira Hatanaka4ce7c402012-07-31 18:16:49 +0000326 DecoderNamespace = "Mips64" in {
Vladimir Medic233dd512013-06-24 10:05:34 +0000327 def LDC164 : LW_FT<"ldc1", FGR64RegsOpnd, IILoad, mem, load>, LW_FM<0x35>;
328 def SDC164 : SW_FT<"sdc1", FGR64RegsOpnd, IIStore, mem, store>, LW_FM<0x3d>;
Akira Hatanaka3c5cab42012-02-27 19:09:08 +0000329}
330
Akira Hatanaka97e179f2012-12-07 03:06:09 +0000331let Predicates = [NotN64, NotMips64, HasStdEnc] in {
Akira Hatanaka9edae022013-05-13 18:23:35 +0000332 let isPseudo = 1, isCodeGenOnly = 1 in {
Vladimir Medic233dd512013-06-24 10:05:34 +0000333 def PseudoLDC1 : LW_FT<"", AFGR64RegsOpnd, IILoad, mem, load>;
334 def PseudoSDC1 : SW_FT<"", AFGR64RegsOpnd, IIStore, mem, store>;
Akira Hatanaka9edae022013-05-13 18:23:35 +0000335 }
Vladimir Medic233dd512013-06-24 10:05:34 +0000336 def LDC1 : LW_FT<"ldc1", AFGR64RegsOpnd, IILoad, mem>, LW_FM<0x35>;
337 def SDC1 : SW_FT<"sdc1", AFGR64RegsOpnd, IIStore, mem>, LW_FM<0x3d>;
Akira Hatanakab6d72cb2011-10-11 01:12:52 +0000338}
Bruno Cardoso Lopesc9c3f492008-07-05 19:05:21 +0000339
Akira Hatanaka330d9012012-02-28 02:55:02 +0000340// Indexed loads and stores.
Akira Hatanaka97e179f2012-12-07 03:06:09 +0000341let Predicates = [HasFPIdx, HasStdEnc] in {
Vladimir Medic233dd512013-06-24 10:05:34 +0000342 def LWXC1 : LWXC1_FT<"lwxc1", FGR32RegsOpnd, CPURegsOpnd, IILoad, load>,
343 LWXC1_FM<0>;
344 def SWXC1 : SWXC1_FT<"swxc1", FGR32RegsOpnd, CPURegsOpnd, IIStore, store>,
345 SWXC1_FM<8>;
Akira Hatanaka330d9012012-02-28 02:55:02 +0000346}
347
Akira Hatanaka97e179f2012-12-07 03:06:09 +0000348let Predicates = [HasMips32r2, NotMips64, HasStdEnc] in {
Vladimir Medic233dd512013-06-24 10:05:34 +0000349 def LDXC1 : LWXC1_FT<"ldxc1", AFGR64RegsOpnd, CPURegsOpnd, IILoad, load>,
350 LWXC1_FM<1>;
351 def SDXC1 : SWXC1_FT<"sdxc1", AFGR64RegsOpnd, CPURegsOpnd, IIStore, store>,
352 SWXC1_FM<9>;
Akira Hatanaka330d9012012-02-28 02:55:02 +0000353}
354
Akira Hatanaka97e179f2012-12-07 03:06:09 +0000355let Predicates = [HasMips64, NotN64, HasStdEnc], DecoderNamespace="Mips64" in {
Vladimir Medic233dd512013-06-24 10:05:34 +0000356 def LDXC164 : LWXC1_FT<"ldxc1", FGR64RegsOpnd, CPURegsOpnd, IILoad, load>,
357 LWXC1_FM<1>;
358 def SDXC164 : SWXC1_FT<"sdxc1", FGR64RegsOpnd, CPURegsOpnd, IIStore, store>,
359 SWXC1_FM<9>;
Akira Hatanaka330d9012012-02-28 02:55:02 +0000360}
361
362// n64
Akira Hatanaka97e179f2012-12-07 03:06:09 +0000363let Predicates = [IsN64, HasStdEnc], isCodeGenOnly=1 in {
Vladimir Medic233dd512013-06-24 10:05:34 +0000364 def LWXC1_P8 : LWXC1_FT<"lwxc1", FGR32RegsOpnd, CPU64RegsOpnd, IILoad, load>,
365 LWXC1_FM<0>;
366 def LDXC164_P8 : LWXC1_FT<"ldxc1", FGR64RegsOpnd, CPU64RegsOpnd, IILoad,
367 load>, LWXC1_FM<1>;
368 def SWXC1_P8 : SWXC1_FT<"swxc1", FGR32RegsOpnd, CPU64RegsOpnd, IIStore,
369 store>, SWXC1_FM<8>;
370 def SDXC164_P8 : SWXC1_FT<"sdxc1", FGR64RegsOpnd, CPU64RegsOpnd, IIStore,
371 store>, SWXC1_FM<9>;
Akira Hatanaka330d9012012-02-28 02:55:02 +0000372}
373
Akira Hatanaka4ce7c402012-07-31 18:16:49 +0000374// Load/store doubleword indexed unaligned.
Akira Hatanaka97e179f2012-12-07 03:06:09 +0000375let Predicates = [NotMips64, HasStdEnc] in {
Vladimir Medic233dd512013-06-24 10:05:34 +0000376 def LUXC1 : LWXC1_FT<"luxc1", AFGR64RegsOpnd, CPURegsOpnd, IILoad>,
377 LWXC1_FM<0x5>;
378 def SUXC1 : SWXC1_FT<"suxc1", AFGR64RegsOpnd, CPURegsOpnd, IIStore>,
379 SWXC1_FM<0xd>;
Akira Hatanaka4ce7c402012-07-31 18:16:49 +0000380}
381
Akira Hatanaka97e179f2012-12-07 03:06:09 +0000382let Predicates = [HasMips64, HasStdEnc],
Akira Hatanaka4ce7c402012-07-31 18:16:49 +0000383 DecoderNamespace="Mips64" in {
Vladimir Medic233dd512013-06-24 10:05:34 +0000384 def LUXC164 : LWXC1_FT<"luxc1", FGR64RegsOpnd, CPURegsOpnd, IILoad>,
385 LWXC1_FM<0x5>;
386 def SUXC164 : SWXC1_FT<"suxc1", FGR64RegsOpnd, CPURegsOpnd, IIStore>,
387 SWXC1_FM<0xd>;
Akira Hatanaka4ce7c402012-07-31 18:16:49 +0000388}
389
Bruno Cardoso Lopesc9c3f492008-07-05 19:05:21 +0000390/// Floating-point Aritmetic
Akira Hatanaka29b51382012-12-13 01:07:37 +0000391def FADD_S : ADDS_FT<"add.s", FGR32, IIFadd, 1, fadd>, ADDS_FM<0x00, 16>;
392defm FADD : ADDS_M<"add.d", IIFadd, 1, fadd>, ADDS_FM<0x00, 17>;
393def FDIV_S : ADDS_FT<"div.s", FGR32, IIFdivSingle, 0, fdiv>, ADDS_FM<0x03, 16>;
394defm FDIV : ADDS_M<"div.d", IIFdivDouble, 0, fdiv>, ADDS_FM<0x03, 17>;
395def FMUL_S : ADDS_FT<"mul.s", FGR32, IIFmulSingle, 1, fmul>, ADDS_FM<0x02, 16>;
396defm FMUL : ADDS_M<"mul.d", IIFmulDouble, 1, fmul>, ADDS_FM<0x02, 17>;
397def FSUB_S : ADDS_FT<"sub.s", FGR32, IIFadd, 0, fsub>, ADDS_FM<0x01, 16>;
398defm FSUB : ADDS_M<"sub.d", IIFadd, 0, fsub>, ADDS_FM<0x01, 17>;
Bruno Cardoso Lopesc9c3f492008-07-05 19:05:21 +0000399
Akira Hatanaka97e179f2012-12-07 03:06:09 +0000400let Predicates = [HasMips32r2, HasStdEnc] in {
Akira Hatanakab0d4acb2012-12-13 01:27:48 +0000401 def MADD_S : MADDS_FT<"madd.s", FGR32, IIFmulSingle, fadd>, MADDS_FM<4, 0>;
402 def MSUB_S : MADDS_FT<"msub.s", FGR32, IIFmulSingle, fsub>, MADDS_FM<5, 0>;
Akira Hatanaka60f7a8e2012-02-25 00:21:52 +0000403}
404
Akira Hatanaka97e179f2012-12-07 03:06:09 +0000405let Predicates = [HasMips32r2, NoNaNsFPMath, HasStdEnc] in {
Akira Hatanakab0d4acb2012-12-13 01:27:48 +0000406 def NMADD_S : NMADDS_FT<"nmadd.s", FGR32, IIFmulSingle, fadd>, MADDS_FM<6, 0>;
407 def NMSUB_S : NMADDS_FT<"nmsub.s", FGR32, IIFmulSingle, fsub>, MADDS_FM<7, 0>;
Akira Hatanaka60f7a8e2012-02-25 00:21:52 +0000408}
409
Akira Hatanaka97e179f2012-12-07 03:06:09 +0000410let Predicates = [HasMips32r2, NotFP64bit, HasStdEnc] in {
Akira Hatanakab0d4acb2012-12-13 01:27:48 +0000411 def MADD_D32 : MADDS_FT<"madd.d", AFGR64, IIFmulDouble, fadd>, MADDS_FM<4, 1>;
412 def MSUB_D32 : MADDS_FT<"msub.d", AFGR64, IIFmulDouble, fsub>, MADDS_FM<5, 1>;
Akira Hatanaka60f7a8e2012-02-25 00:21:52 +0000413}
414
Akira Hatanaka97e179f2012-12-07 03:06:09 +0000415let Predicates = [HasMips32r2, NotFP64bit, NoNaNsFPMath, HasStdEnc] in {
Akira Hatanakab0d4acb2012-12-13 01:27:48 +0000416 def NMADD_D32 : NMADDS_FT<"nmadd.d", AFGR64, IIFmulDouble, fadd>,
417 MADDS_FM<6, 1>;
418 def NMSUB_D32 : NMADDS_FT<"nmsub.d", AFGR64, IIFmulDouble, fsub>,
419 MADDS_FM<7, 1>;
Akira Hatanaka60f7a8e2012-02-25 00:21:52 +0000420}
421
Akira Hatanaka97e179f2012-12-07 03:06:09 +0000422let Predicates = [HasMips32r2, IsFP64bit, HasStdEnc], isCodeGenOnly=1 in {
Akira Hatanakab0d4acb2012-12-13 01:27:48 +0000423 def MADD_D64 : MADDS_FT<"madd.d", FGR64, IIFmulDouble, fadd>, MADDS_FM<4, 1>;
424 def MSUB_D64 : MADDS_FT<"msub.d", FGR64, IIFmulDouble, fsub>, MADDS_FM<5, 1>;
Akira Hatanaka60f7a8e2012-02-25 00:21:52 +0000425}
426
Akira Hatanaka97e179f2012-12-07 03:06:09 +0000427let Predicates = [HasMips32r2, IsFP64bit, NoNaNsFPMath, HasStdEnc],
Akira Hatanakacdf4fd82012-05-22 03:10:09 +0000428 isCodeGenOnly=1 in {
Akira Hatanakab0d4acb2012-12-13 01:27:48 +0000429 def NMADD_D64 : NMADDS_FT<"nmadd.d", FGR64, IIFmulDouble, fadd>,
430 MADDS_FM<6, 1>;
431 def NMSUB_D64 : NMADDS_FT<"nmsub.d", FGR64, IIFmulDouble, fsub>,
432 MADDS_FM<7, 1>;
Akira Hatanaka60f7a8e2012-02-25 00:21:52 +0000433}
434
Akira Hatanakae2489122011-04-15 21:51:11 +0000435//===----------------------------------------------------------------------===//
Bruno Cardoso Lopes7ceec572008-07-09 04:45:36 +0000436// Floating Point Branch Codes
Akira Hatanakae2489122011-04-15 21:51:11 +0000437//===----------------------------------------------------------------------===//
Bruno Cardoso Lopesed874ef2011-03-04 17:51:39 +0000438// Mips branch codes. These correspond to condcode in MipsInstrInfo.h.
Bruno Cardoso Lopesc9c3f492008-07-05 19:05:21 +0000439// They must be kept in synch.
440def MIPS_BRANCH_F : PatLeaf<(i32 0)>;
441def MIPS_BRANCH_T : PatLeaf<(i32 1)>;
Bruno Cardoso Lopesc9c3f492008-07-05 19:05:21 +0000442
Akira Hatanaka71928e62012-04-17 18:03:21 +0000443let DecoderMethod = "DecodeBC1" in {
Akira Hatanakafd9163b2012-12-13 01:32:36 +0000444def BC1F : BC1F_FT<"bc1f", IIBranch, MIPS_BRANCH_F>, BC1F_FM<0, 0>;
445def BC1T : BC1F_FT<"bc1t", IIBranch, MIPS_BRANCH_T>, BC1F_FM<0, 1>;
Akira Hatanaka71928e62012-04-17 18:03:21 +0000446}
Akira Hatanakae2489122011-04-15 21:51:11 +0000447//===----------------------------------------------------------------------===//
Bruno Cardoso Lopes7ceec572008-07-09 04:45:36 +0000448// Floating Point Flag Conditions
Akira Hatanakae2489122011-04-15 21:51:11 +0000449//===----------------------------------------------------------------------===//
Bruno Cardoso Lopesed874ef2011-03-04 17:51:39 +0000450// Mips condition codes. They must correspond to condcode in MipsInstrInfo.h.
Bruno Cardoso Lopesc9c3f492008-07-05 19:05:21 +0000451// They must be kept in synch.
452def MIPS_FCOND_F : PatLeaf<(i32 0)>;
453def MIPS_FCOND_UN : PatLeaf<(i32 1)>;
Akira Hatanakaa5352702011-03-31 18:26:17 +0000454def MIPS_FCOND_OEQ : PatLeaf<(i32 2)>;
Bruno Cardoso Lopesc9c3f492008-07-05 19:05:21 +0000455def MIPS_FCOND_UEQ : PatLeaf<(i32 3)>;
456def MIPS_FCOND_OLT : PatLeaf<(i32 4)>;
457def MIPS_FCOND_ULT : PatLeaf<(i32 5)>;
458def MIPS_FCOND_OLE : PatLeaf<(i32 6)>;
459def MIPS_FCOND_ULE : PatLeaf<(i32 7)>;
460def MIPS_FCOND_SF : PatLeaf<(i32 8)>;
461def MIPS_FCOND_NGLE : PatLeaf<(i32 9)>;
462def MIPS_FCOND_SEQ : PatLeaf<(i32 10)>;
463def MIPS_FCOND_NGL : PatLeaf<(i32 11)>;
464def MIPS_FCOND_LT : PatLeaf<(i32 12)>;
465def MIPS_FCOND_NGE : PatLeaf<(i32 13)>;
466def MIPS_FCOND_LE : PatLeaf<(i32 14)>;
467def MIPS_FCOND_NGT : PatLeaf<(i32 15)>;
468
469/// Floating Point Compare
Akira Hatanaka79e1cdb2012-12-13 01:34:09 +0000470def FCMP_S32 : CEQS_FT<"s", FGR32, IIFcmp, MipsFPCmp>, CEQS_FM<16>;
471def FCMP_D32 : CEQS_FT<"d", AFGR64, IIFcmp, MipsFPCmp>, CEQS_FM<17>,
472 Requires<[NotFP64bit, HasStdEnc]>;
473let DecoderNamespace = "Mips64" in
474def FCMP_D64 : CEQS_FT<"d", FGR64, IIFcmp, MipsFPCmp>, CEQS_FM<17>,
475 Requires<[IsFP64bit, HasStdEnc]>;
Akira Hatanakaa5352702011-03-31 18:26:17 +0000476
Akira Hatanakae2489122011-04-15 21:51:11 +0000477//===----------------------------------------------------------------------===//
Bruno Cardoso Lopese683bba2008-07-29 19:05:28 +0000478// Floating Point Pseudo-Instructions
Akira Hatanakae2489122011-04-15 21:51:11 +0000479//===----------------------------------------------------------------------===//
Jack Carter873c7242013-01-12 01:03:14 +0000480def MOVCCRToCCR : PseudoSE<(outs CCR:$dst), (ins CCROpnd:$src), []>;
Bruno Cardoso Lopesa72a5052009-05-27 17:23:44 +0000481
Akira Hatanaka27916972011-04-15 19:52:08 +0000482// This pseudo instr gets expanded into 2 mtc1 instrs after register
483// allocation.
484def BuildPairF64 :
Akira Hatanakaa66d6762012-07-31 19:13:07 +0000485 PseudoSE<(outs AFGR64:$dst),
Akira Hatanakab1527b72012-12-20 04:20:09 +0000486 (ins CPURegs:$lo, CPURegs:$hi),
Akira Hatanakaa66d6762012-07-31 19:13:07 +0000487 [(set AFGR64:$dst, (MipsBuildPairF64 CPURegs:$lo, CPURegs:$hi))]>;
Akira Hatanaka27916972011-04-15 19:52:08 +0000488
489// This pseudo instr gets expanded into 2 mfc1 instrs after register
490// allocation.
491// if n is 0, lower part of src is extracted.
492// if n is 1, higher part of src is extracted.
493def ExtractElementF64 :
Akira Hatanakab1527b72012-12-20 04:20:09 +0000494 PseudoSE<(outs CPURegs:$dst), (ins AFGR64:$src, i32imm:$n),
Akira Hatanakaa66d6762012-07-31 19:13:07 +0000495 [(set CPURegs:$dst, (MipsExtractElementF64 AFGR64:$src, imm:$n))]>;
Akira Hatanaka27916972011-04-15 19:52:08 +0000496
Akira Hatanakae2489122011-04-15 21:51:11 +0000497//===----------------------------------------------------------------------===//
Bruno Cardoso Lopes7ceec572008-07-09 04:45:36 +0000498// Floating Point Patterns
Akira Hatanakae2489122011-04-15 21:51:11 +0000499//===----------------------------------------------------------------------===//
Akira Hatanakad8ab16b2012-06-14 21:03:23 +0000500def : MipsPat<(f32 fpimm0), (MTC1 ZERO)>;
501def : MipsPat<(f32 fpimm0neg), (FNEG_S (MTC1 ZERO))>;
Bruno Cardoso Lopes2d7ddea2008-07-30 19:00:31 +0000502
Akira Hatanaka39d40f72013-05-16 19:48:37 +0000503def : MipsPat<(f32 (sint_to_fp CPURegs:$src)), (PseudoCVT_S_W CPURegs:$src)>;
Akira Hatanaka252f54f2013-05-16 21:17:15 +0000504def : MipsPat<(MipsTruncIntFP FGR32:$src), (TRUNC_W_S FGR32:$src)>;
Bruno Cardoso Lopes2d7ddea2008-07-30 19:00:31 +0000505
Akira Hatanaka97e179f2012-12-07 03:06:09 +0000506let Predicates = [NotFP64bit, HasStdEnc] in {
Akira Hatanakad8ab16b2012-06-14 21:03:23 +0000507 def : MipsPat<(f64 (sint_to_fp CPURegs:$src)),
Akira Hatanaka39d40f72013-05-16 19:48:37 +0000508 (PseudoCVT_D32_W CPURegs:$src)>;
Akira Hatanaka252f54f2013-05-16 21:17:15 +0000509 def : MipsPat<(MipsTruncIntFP AFGR64:$src), (TRUNC_W_D32 AFGR64:$src)>;
Akira Hatanakad8ab16b2012-06-14 21:03:23 +0000510 def : MipsPat<(f32 (fround AFGR64:$src)), (CVT_S_D32 AFGR64:$src)>;
511 def : MipsPat<(f64 (fextend FGR32:$src)), (CVT_D32_S FGR32:$src)>;
Bruno Cardoso Lopesa72a5052009-05-27 17:23:44 +0000512}
513
Akira Hatanaka97e179f2012-12-07 03:06:09 +0000514let Predicates = [IsFP64bit, HasStdEnc] in {
Akira Hatanakad8ab16b2012-06-14 21:03:23 +0000515 def : MipsPat<(f64 fpimm0), (DMTC1 ZERO_64)>;
516 def : MipsPat<(f64 fpimm0neg), (FNEG_D64 (DMTC1 ZERO_64))>;
Akira Hatanaka2216f732011-11-07 21:38:58 +0000517
Akira Hatanakad8ab16b2012-06-14 21:03:23 +0000518 def : MipsPat<(f64 (sint_to_fp CPURegs:$src)),
Akira Hatanaka39d40f72013-05-16 19:48:37 +0000519 (PseudoCVT_D64_W CPURegs:$src)>;
Akira Hatanakad8ab16b2012-06-14 21:03:23 +0000520 def : MipsPat<(f32 (sint_to_fp CPU64Regs:$src)),
Akira Hatanaka39d40f72013-05-16 19:48:37 +0000521 (EXTRACT_SUBREG (PseudoCVT_S_L CPU64Regs:$src), sub_32)>;
Akira Hatanakad8ab16b2012-06-14 21:03:23 +0000522 def : MipsPat<(f64 (sint_to_fp CPU64Regs:$src)),
Akira Hatanaka39d40f72013-05-16 19:48:37 +0000523 (PseudoCVT_D64_L CPU64Regs:$src)>;
Akira Hatanaka2216f732011-11-07 21:38:58 +0000524
Akira Hatanaka252f54f2013-05-16 21:17:15 +0000525 def : MipsPat<(MipsTruncIntFP FGR64:$src), (TRUNC_W_D64 FGR64:$src)>;
526 def : MipsPat<(MipsTruncIntFP FGR32:$src), (TRUNC_L_S FGR32:$src)>;
527 def : MipsPat<(MipsTruncIntFP FGR64:$src), (TRUNC_L_D64 FGR64:$src)>;
Akira Hatanaka2216f732011-11-07 21:38:58 +0000528
Akira Hatanakad8ab16b2012-06-14 21:03:23 +0000529 def : MipsPat<(f32 (fround FGR64:$src)), (CVT_S_D64 FGR64:$src)>;
530 def : MipsPat<(f64 (fextend FGR32:$src)), (CVT_D64_S FGR32:$src)>;
Akira Hatanaka4705b0c2012-02-16 17:48:20 +0000531}
Akira Hatanaka69fb3d12013-02-15 21:20:45 +0000532
Akira Hatanakab1457302013-03-30 02:01:48 +0000533// Patterns for loads/stores with a reg+imm operand.
Akira Hatanaka69fb3d12013-02-15 21:20:45 +0000534let AddedComplexity = 40 in {
535 let Predicates = [IsN64, HasStdEnc] in {
Akira Hatanakab1457302013-03-30 02:01:48 +0000536 def : LoadRegImmPat<LWC1_P8, f32, load>;
537 def : StoreRegImmPat<SWC1_P8, f32>;
538 def : LoadRegImmPat<LDC164_P8, f64, load>;
539 def : StoreRegImmPat<SDC164_P8, f64>;
Akira Hatanaka69fb3d12013-02-15 21:20:45 +0000540 }
541
542 let Predicates = [NotN64, HasStdEnc] in {
Akira Hatanakab1457302013-03-30 02:01:48 +0000543 def : LoadRegImmPat<LWC1, f32, load>;
544 def : StoreRegImmPat<SWC1, f32>;
Akira Hatanaka69fb3d12013-02-15 21:20:45 +0000545 }
546
547 let Predicates = [NotN64, HasMips64, HasStdEnc] in {
Akira Hatanakab1457302013-03-30 02:01:48 +0000548 def : LoadRegImmPat<LDC164, f64, load>;
549 def : StoreRegImmPat<SDC164, f64>;
Akira Hatanaka69fb3d12013-02-15 21:20:45 +0000550 }
551
552 let Predicates = [NotN64, NotMips64, HasStdEnc] in {
Akira Hatanaka9edae022013-05-13 18:23:35 +0000553 def : LoadRegImmPat<PseudoLDC1, f64, load>;
554 def : StoreRegImmPat<PseudoSDC1, f64>;
Akira Hatanaka69fb3d12013-02-15 21:20:45 +0000555 }
556}