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gerrit-public.fairphone.software / toolchain / llvm-project / 268b51a188b718debaaa7f758200246f1039cfb9 / . / llvm / lib / Target / AMDGPU / SIIntrinsics.td
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Tom Stellard75aadc22012-12-11 21:25:42 +0000[diff] [blame]1//===-- SIIntrinsics.td - SI Intrinsic defs ----------------*- tablegen -*-===//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// SI Intrinsic Definitions
11//
12//===----------------------------------------------------------------------===//
13
14
15let TargetPrefix = "SI", isTarget = 1 in {
16
Michel Danzer8d696172013-07-10 16:36:52 +0000[diff] [blame]17 def int_SI_tid : Intrinsic <[llvm_i32_ty], [], [IntrNoMem]>;
Tom Stellard75aadc22012-12-11 21:25:42 +0000[diff] [blame]18 def int_SI_packf16 : Intrinsic <[llvm_i32_ty], [llvm_float_ty, llvm_float_ty], [IntrNoMem]>;
19 def int_SI_export : Intrinsic <[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty], []>;
Tom Stellard9fa17912013-08-14 23:24:45 +0000[diff] [blame]20 def int_SI_load_const : Intrinsic <[llvm_float_ty], [llvm_anyint_ty, llvm_i32_ty], [IntrNoMem]>;
21 def int_SI_vs_load_input : Intrinsic <[llvm_v4f32_ty], [llvm_anyint_ty, llvm_i16_ty, llvm_i32_ty], [IntrNoMem]> ;
Tom Stellard75aadc22012-12-11 21:25:42 +0000[diff] [blame]22
Tom Stellardafcf12f2013-09-12 02:55:14 +0000[diff] [blame]23 // Fully-flexible TBUFFER_STORE_FORMAT_* except for the ADDR64 bit, which is not exposed
24 def int_SI_tbuffer_store : Intrinsic <
25 [],
26 [llvm_anyint_ty, // rsrc(SGPR)
27 llvm_anyint_ty, // vdata(VGPR), overloaded for types i32, v2i32, v4i32
28 llvm_i32_ty, // num_channels(imm), selects opcode suffix: 1=X, 2=XY, 3=XYZ, 4=XYZW
29 llvm_i32_ty, // vaddr(VGPR)
30 llvm_i32_ty, // soffset(SGPR)
31 llvm_i32_ty, // inst_offset(imm)
32 llvm_i32_ty, // dfmt(imm)
33 llvm_i32_ty, // nfmt(imm)
34 llvm_i32_ty, // offen(imm)
35 llvm_i32_ty, // idxen(imm)
36 llvm_i32_ty, // glc(imm)
37 llvm_i32_ty, // slc(imm)
38 llvm_i32_ty], // tfe(imm)
39 []>;
40
Michel Danzer13736222014-01-27 07:20:51 +0000[diff] [blame]41 // Fully-flexible BUFFER_LOAD_DWORD_* except for the ADDR64 bit, which is not exposed
42 def int_SI_buffer_load_dword : Intrinsic <
43 [llvm_anyint_ty], // vdata(VGPR), overloaded for types i32, v2i32, v4i32
44 [llvm_anyint_ty, // rsrc(SGPR)
45 llvm_anyint_ty, // vaddr(VGPR)
46 llvm_i32_ty, // soffset(SGPR)
47 llvm_i32_ty, // inst_offset(imm)
48 llvm_i32_ty, // offen(imm)
49 llvm_i32_ty, // idxen(imm)
50 llvm_i32_ty, // glc(imm)
51 llvm_i32_ty, // slc(imm)
52 llvm_i32_ty], // tfe(imm)
53 [IntrReadArgMem]>;
54
Michel Danzer6064f572014-01-27 07:20:44 +0000[diff] [blame]55 def int_SI_sendmsg : Intrinsic <[], [llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>;
56
Marek Olsak51b8e7b2014-06-18 22:00:29 +0000[diff] [blame]57 // Fully-flexible SAMPLE instruction.
58 class SampleRaw : Intrinsic <
59 [llvm_v4f32_ty], // vdata(VGPR)
60 [llvm_anyint_ty, // vaddr(VGPR)
Marek Olsakeac50622014-07-11 17:11:52 +0000[diff] [blame]61 llvm_v8i32_ty, // rsrc(SGPR)
62 llvm_v4i32_ty, // sampler(SGPR)
Marek Olsak51b8e7b2014-06-18 22:00:29 +0000[diff] [blame]63 llvm_i32_ty, // dmask(imm)
64 llvm_i32_ty, // unorm(imm)
65 llvm_i32_ty, // r128(imm)
66 llvm_i32_ty, // da(imm)
67 llvm_i32_ty, // glc(imm)
68 llvm_i32_ty, // slc(imm)
69 llvm_i32_ty, // tfe(imm)
70 llvm_i32_ty], // lwe(imm)
71 [IntrNoMem]>;
72
Marek Olsakd8ecaee2014-07-11 17:11:46 +0000[diff] [blame]73 // Image instruction without a sampler.
74 class Image : Intrinsic <
75 [llvm_v4f32_ty], // vdata(VGPR)
76 [llvm_anyint_ty, // vaddr(VGPR)
Marek Olsakeac50622014-07-11 17:11:52 +0000[diff] [blame]77 llvm_v8i32_ty, // rsrc(SGPR)
Marek Olsakd8ecaee2014-07-11 17:11:46 +0000[diff] [blame]78 llvm_i32_ty, // dmask(imm)
79 llvm_i32_ty, // unorm(imm)
80 llvm_i32_ty, // r128(imm)
81 llvm_i32_ty, // da(imm)
82 llvm_i32_ty, // glc(imm)
83 llvm_i32_ty, // slc(imm)
84 llvm_i32_ty, // tfe(imm)
85 llvm_i32_ty], // lwe(imm)
86 [IntrNoMem]>;
87
88 // Basic sample
89 def int_SI_image_sample : SampleRaw;
90 def int_SI_image_sample_cl : SampleRaw;
91 def int_SI_image_sample_d : SampleRaw;
92 def int_SI_image_sample_d_cl : SampleRaw;
93 def int_SI_image_sample_l : SampleRaw;
94 def int_SI_image_sample_b : SampleRaw;
95 def int_SI_image_sample_b_cl : SampleRaw;
96 def int_SI_image_sample_lz : SampleRaw;
97 def int_SI_image_sample_cd : SampleRaw;
98 def int_SI_image_sample_cd_cl : SampleRaw;
99
100 // Sample with comparison
101 def int_SI_image_sample_c : SampleRaw;
102 def int_SI_image_sample_c_cl : SampleRaw;
103 def int_SI_image_sample_c_d : SampleRaw;
104 def int_SI_image_sample_c_d_cl : SampleRaw;
105 def int_SI_image_sample_c_l : SampleRaw;
106 def int_SI_image_sample_c_b : SampleRaw;
107 def int_SI_image_sample_c_b_cl : SampleRaw;
108 def int_SI_image_sample_c_lz : SampleRaw;
109 def int_SI_image_sample_c_cd : SampleRaw;
110 def int_SI_image_sample_c_cd_cl : SampleRaw;
111
112 // Sample with offsets
113 def int_SI_image_sample_o : SampleRaw;
114 def int_SI_image_sample_cl_o : SampleRaw;
115 def int_SI_image_sample_d_o : SampleRaw;
116 def int_SI_image_sample_d_cl_o : SampleRaw;
117 def int_SI_image_sample_l_o : SampleRaw;
118 def int_SI_image_sample_b_o : SampleRaw;
119 def int_SI_image_sample_b_cl_o : SampleRaw;
120 def int_SI_image_sample_lz_o : SampleRaw;
121 def int_SI_image_sample_cd_o : SampleRaw;
122 def int_SI_image_sample_cd_cl_o : SampleRaw;
123
124 // Sample with comparison and offsets
125 def int_SI_image_sample_c_o : SampleRaw;
126 def int_SI_image_sample_c_cl_o : SampleRaw;
127 def int_SI_image_sample_c_d_o : SampleRaw;
128 def int_SI_image_sample_c_d_cl_o : SampleRaw;
129 def int_SI_image_sample_c_l_o : SampleRaw;
130 def int_SI_image_sample_c_b_o : SampleRaw;
131 def int_SI_image_sample_c_b_cl_o : SampleRaw;
132 def int_SI_image_sample_c_lz_o : SampleRaw;
133 def int_SI_image_sample_c_cd_o : SampleRaw;
134 def int_SI_image_sample_c_cd_cl_o : SampleRaw;
Tom Stellard75aadc22012-12-11 21:25:42 +0000[diff] [blame]135
Marek Olsak51b8e7b2014-06-18 22:00:29 +0000[diff] [blame]136 // Basic gather4
137 def int_SI_gather4 : SampleRaw;
138 def int_SI_gather4_cl : SampleRaw;
139 def int_SI_gather4_l : SampleRaw;
140 def int_SI_gather4_b : SampleRaw;
141 def int_SI_gather4_b_cl : SampleRaw;
142 def int_SI_gather4_lz : SampleRaw;
143
144 // Gather4 with comparison
145 def int_SI_gather4_c : SampleRaw;
146 def int_SI_gather4_c_cl : SampleRaw;
147 def int_SI_gather4_c_l : SampleRaw;
148 def int_SI_gather4_c_b : SampleRaw;
149 def int_SI_gather4_c_b_cl : SampleRaw;
150 def int_SI_gather4_c_lz : SampleRaw;
151
152 // Gather4 with offsets
153 def int_SI_gather4_o : SampleRaw;
154 def int_SI_gather4_cl_o : SampleRaw;
155 def int_SI_gather4_l_o : SampleRaw;
156 def int_SI_gather4_b_o : SampleRaw;
157 def int_SI_gather4_b_cl_o : SampleRaw;
158 def int_SI_gather4_lz_o : SampleRaw;
159
160 // Gather4 with comparison and offsets
161 def int_SI_gather4_c_o : SampleRaw;
162 def int_SI_gather4_c_cl_o : SampleRaw;
163 def int_SI_gather4_c_l_o : SampleRaw;
164 def int_SI_gather4_c_b_o : SampleRaw;
165 def int_SI_gather4_c_b_cl_o : SampleRaw;
166 def int_SI_gather4_c_lz_o : SampleRaw;
167
168 def int_SI_getlod : SampleRaw;
169
Marek Olsakd8ecaee2014-07-11 17:11:46 +0000[diff] [blame]170 // Image instrinsics.
171 def int_SI_image_load : Image;
172 def int_SI_image_load_mip : Image;
173 def int_SI_getresinfo : Image;
Tom Stellard353b3362013-05-06 23:02:12 +0000[diff] [blame]174
Marek Olsakd8ecaee2014-07-11 17:11:46 +0000[diff] [blame]175 // Deprecated image and sample intrinsics.
176 class Sample : Intrinsic <[llvm_v4f32_ty], [llvm_anyvector_ty, llvm_v32i8_ty, llvm_anyint_ty, llvm_i32_ty], [IntrNoMem]>;
177
178 def int_SI_sample : Sample;
179 def int_SI_sampleb : Sample;
180 def int_SI_sampled : Sample;
181 def int_SI_samplel : Sample;
182 def int_SI_imageload : Intrinsic <[llvm_v4i32_ty], [llvm_anyvector_ty, llvm_v32i8_ty, llvm_i32_ty], [IntrNoMem]>;
Tom Stellardf787ef12013-05-06 23:02:19 +0000[diff] [blame]183 def int_SI_resinfo : Intrinsic <[llvm_v4i32_ty], [llvm_i32_ty, llvm_v32i8_ty, llvm_i32_ty], [IntrNoMem]>;
184
Tom Stellard75aadc22012-12-11 21:25:42 +0000[diff] [blame]185 /* Interpolation Intrinsics */
186
Christian Konig727d06d2013-03-26 14:03:57 +0000[diff] [blame]187 def int_SI_fs_constant : Intrinsic <[llvm_float_ty], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>;
188 def int_SI_fs_interp : Intrinsic <[llvm_float_ty], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_v2i32_ty], [IntrNoMem]>;
Tom Stellardf8794352012-12-19 22:10:31 +0000[diff] [blame]189
190 /* Control flow Intrinsics */
191
192 def int_SI_if : Intrinsic<[llvm_i64_ty], [llvm_i1_ty, llvm_empty_ty], []>;
193 def int_SI_else : Intrinsic<[llvm_i64_ty], [llvm_i64_ty, llvm_empty_ty], []>;
194 def int_SI_break : Intrinsic<[llvm_i64_ty], [llvm_i64_ty], []>;
195 def int_SI_if_break : Intrinsic<[llvm_i64_ty], [llvm_i1_ty, llvm_i64_ty], []>;
196 def int_SI_else_break : Intrinsic<[llvm_i64_ty], [llvm_i64_ty, llvm_i64_ty], []>;
197 def int_SI_loop : Intrinsic<[], [llvm_i64_ty, llvm_empty_ty], []>;
198 def int_SI_end_cf : Intrinsic<[], [llvm_i64_ty], []>;
Tom Stellard75aadc22012-12-11 21:25:42 +0000[diff] [blame]199}