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Christian Konig72d5d5c2013-02-21 15:16:44 +00001//===-- SIInstrInfo.td - SI Instruction Infos -------------*- tablegen -*--===//
Tom Stellard75aadc22012-12-11 21:25:42 +00002//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9
Tom Stellardc721a232014-05-16 20:56:47 +000010// Execpt for the NONE field, this must be kept in sync with the SISubtarget enum
11// in AMDGPUMCInstLower.h
12def SISubtarget {
13 int NONE = -1;
14 int SI = 0;
15}
16
Tom Stellard75aadc22012-12-11 21:25:42 +000017//===----------------------------------------------------------------------===//
Tom Stellard75aadc22012-12-11 21:25:42 +000018// SI DAG Nodes
19//===----------------------------------------------------------------------===//
20
Tom Stellard9fa17912013-08-14 23:24:45 +000021def SIload_constant : SDNode<"AMDGPUISD::LOAD_CONSTANT",
Tom Stellard868fd922014-04-17 21:00:11 +000022 SDTypeProfile<1, 2, [SDTCisVT<0, f32>, SDTCisVT<1, v4i32>, SDTCisVT<2, i32>]>,
Tom Stellard9fa17912013-08-14 23:24:45 +000023 [SDNPMayLoad, SDNPMemOperand]
24>;
25
Tom Stellardafcf12f2013-09-12 02:55:14 +000026def SItbuffer_store : SDNode<"AMDGPUISD::TBUFFER_STORE_FORMAT",
27 SDTypeProfile<0, 13,
Tom Stellard868fd922014-04-17 21:00:11 +000028 [SDTCisVT<0, v4i32>, // rsrc(SGPR)
Tom Stellardafcf12f2013-09-12 02:55:14 +000029 SDTCisVT<1, iAny>, // vdata(VGPR)
30 SDTCisVT<2, i32>, // num_channels(imm)
31 SDTCisVT<3, i32>, // vaddr(VGPR)
32 SDTCisVT<4, i32>, // soffset(SGPR)
33 SDTCisVT<5, i32>, // inst_offset(imm)
34 SDTCisVT<6, i32>, // dfmt(imm)
35 SDTCisVT<7, i32>, // nfmt(imm)
36 SDTCisVT<8, i32>, // offen(imm)
37 SDTCisVT<9, i32>, // idxen(imm)
38 SDTCisVT<10, i32>, // glc(imm)
39 SDTCisVT<11, i32>, // slc(imm)
40 SDTCisVT<12, i32> // tfe(imm)
41 ]>,
42 [SDNPMayStore, SDNPMemOperand, SDNPHasChain]
43>;
44
Tom Stellard9fa17912013-08-14 23:24:45 +000045def SIload_input : SDNode<"AMDGPUISD::LOAD_INPUT",
Tom Stellard868fd922014-04-17 21:00:11 +000046 SDTypeProfile<1, 3, [SDTCisVT<0, v4f32>, SDTCisVT<1, v4i32>, SDTCisVT<2, i16>,
Tom Stellard9fa17912013-08-14 23:24:45 +000047 SDTCisVT<3, i32>]>
48>;
49
50class SDSample<string opcode> : SDNode <opcode,
Tom Stellard67850652013-08-14 23:24:53 +000051 SDTypeProfile<1, 4, [SDTCisVT<0, v4f32>, SDTCisVT<2, v32i8>,
Tom Stellard868fd922014-04-17 21:00:11 +000052 SDTCisVT<3, v4i32>, SDTCisVT<4, i32>]>
Tom Stellard9fa17912013-08-14 23:24:45 +000053>;
54
55def SIsample : SDSample<"AMDGPUISD::SAMPLE">;
56def SIsampleb : SDSample<"AMDGPUISD::SAMPLEB">;
57def SIsampled : SDSample<"AMDGPUISD::SAMPLED">;
58def SIsamplel : SDSample<"AMDGPUISD::SAMPLEL">;
59
Tom Stellard067c8152014-07-21 14:01:14 +000060def SIconstdata_ptr : SDNode<
61 "AMDGPUISD::CONST_DATA_PTR", SDTypeProfile <1, 0, [SDTCisVT<0, i64>]>
62>;
63
Tom Stellard26075d52013-02-07 19:39:38 +000064// Transformation function, extract the lower 32bit of a 64bit immediate
65def LO32 : SDNodeXForm<imm, [{
66 return CurDAG->getTargetConstant(N->getZExtValue() & 0xffffffff, MVT::i32);
67}]>;
68
Tom Stellardab8a8c82013-07-12 18:15:02 +000069def LO32f : SDNodeXForm<fpimm, [{
Benjamin Kramerc22c7902013-07-12 20:18:05 +000070 APInt V = N->getValueAPF().bitcastToAPInt().trunc(32);
71 return CurDAG->getTargetConstantFP(APFloat(APFloat::IEEEsingle, V), MVT::f32);
Tom Stellardab8a8c82013-07-12 18:15:02 +000072}]>;
73
Tom Stellard26075d52013-02-07 19:39:38 +000074// Transformation function, extract the upper 32bit of a 64bit immediate
75def HI32 : SDNodeXForm<imm, [{
76 return CurDAG->getTargetConstant(N->getZExtValue() >> 32, MVT::i32);
77}]>;
78
Tom Stellardab8a8c82013-07-12 18:15:02 +000079def HI32f : SDNodeXForm<fpimm, [{
Benjamin Kramerc22c7902013-07-12 20:18:05 +000080 APInt V = N->getValueAPF().bitcastToAPInt().lshr(32).trunc(32);
81 return CurDAG->getTargetConstantFP(APFloat(APFloat::IEEEsingle, V), MVT::f32);
Tom Stellardab8a8c82013-07-12 18:15:02 +000082}]>;
83
Tom Stellard044e4182014-02-06 18:36:34 +000084def IMM8bitDWORD : PatLeaf <(imm),
85 [{return (N->getZExtValue() & ~0x3FC) == 0;}]
Tom Stellard89093802013-02-07 19:39:40 +000086>;
87
Tom Stellard044e4182014-02-06 18:36:34 +000088def as_dword_i32imm : SDNodeXForm<imm, [{
89 return CurDAG->getTargetConstant(N->getZExtValue() >> 2, MVT::i32);
90}]>;
91
Tom Stellardafcf12f2013-09-12 02:55:14 +000092def as_i1imm : SDNodeXForm<imm, [{
93 return CurDAG->getTargetConstant(N->getZExtValue(), MVT::i1);
94}]>;
95
96def as_i8imm : SDNodeXForm<imm, [{
97 return CurDAG->getTargetConstant(N->getZExtValue(), MVT::i8);
98}]>;
99
Tom Stellard07a10a32013-06-03 17:39:43 +0000100def as_i16imm : SDNodeXForm<imm, [{
101 return CurDAG->getTargetConstant(N->getSExtValue(), MVT::i16);
102}]>;
103
Tom Stellard044e4182014-02-06 18:36:34 +0000104def as_i32imm: SDNodeXForm<imm, [{
105 return CurDAG->getTargetConstant(N->getSExtValue(), MVT::i32);
106}]>;
107
Matt Arsenault99ed7892014-03-19 22:19:49 +0000108def IMM8bit : PatLeaf <(imm),
109 [{return isUInt<8>(N->getZExtValue());}]
110>;
111
Tom Stellard07a10a32013-06-03 17:39:43 +0000112def IMM12bit : PatLeaf <(imm),
113 [{return isUInt<12>(N->getZExtValue());}]
Tom Stellard89093802013-02-07 19:39:40 +0000114>;
115
Matt Arsenault99ed7892014-03-19 22:19:49 +0000116def IMM16bit : PatLeaf <(imm),
117 [{return isUInt<16>(N->getZExtValue());}]
118>;
119
Tom Stellardd6cb8e82014-05-09 16:42:21 +0000120def IMM32bit : PatLeaf <(imm),
121 [{return isUInt<32>(N->getZExtValue());}]
122>;
123
Tom Stellarde2367942014-02-06 18:36:41 +0000124def mubuf_vaddr_offset : PatFrag<
125 (ops node:$ptr, node:$offset, node:$imm_offset),
126 (add (add node:$ptr, node:$offset), node:$imm_offset)
127>;
128
Christian Konigf82901a2013-02-26 17:52:23 +0000129class InlineImm <ValueType vt> : PatLeaf <(vt imm), [{
Tom Stellard7ed0b522014-04-03 20:19:27 +0000130 return isInlineImmediate(N);
Christian Konigb559b072013-02-16 11:28:36 +0000131}]>;
132
Tom Stellarddf94dc32013-08-14 23:24:24 +0000133class SGPRImm <dag frag> : PatLeaf<frag, [{
134 if (TM.getSubtarget<AMDGPUSubtarget>().getGeneration() <
135 AMDGPUSubtarget::SOUTHERN_ISLANDS) {
136 return false;
137 }
138 const SIRegisterInfo *SIRI =
Eric Christopherd9134482014-08-04 21:25:23 +0000139 static_cast<const SIRegisterInfo*>(TM.getSubtargetImpl()->getRegisterInfo());
Tom Stellarddf94dc32013-08-14 23:24:24 +0000140 for (SDNode::use_iterator U = N->use_begin(), E = SDNode::use_end();
141 U != E; ++U) {
142 if (SIRI->isSGPRClass(getOperandRegClass(*U, U.getOperandNo()))) {
143 return true;
144 }
145 }
146 return false;
147}]>;
148
Tom Stellard01825af2014-07-21 14:01:08 +0000149//===----------------------------------------------------------------------===//
150// Custom Operands
151//===----------------------------------------------------------------------===//
152
Matt Arsenaulta98cd6a2013-12-19 05:32:55 +0000153def FRAMEri32 : Operand<iPTR> {
Matt Arsenault06028dd2014-05-01 16:37:52 +0000154 let MIOperandInfo = (ops i32:$ptr, i32imm:$index);
Tom Stellard81d871d2013-11-13 23:36:50 +0000155}
156
Tom Stellard01825af2014-07-21 14:01:08 +0000157def sopp_brtarget : Operand<OtherVT> {
158 let EncoderMethod = "getSOPPBrEncoding";
159 let OperandType = "OPERAND_PCREL";
160}
161
Tom Stellardb4a313a2014-08-01 00:32:39 +0000162include "SIInstrFormats.td"
163
Tom Stellard229d5e62014-08-05 14:48:12 +0000164let OperandType = "OPERAND_IMMEDIATE" in {
165
166def offen : Operand<i1> {
167 let PrintMethod = "printOffen";
168}
169def idxen : Operand<i1> {
170 let PrintMethod = "printIdxen";
171}
172def addr64 : Operand<i1> {
173 let PrintMethod = "printAddr64";
174}
175def mbuf_offset : Operand<i16> {
176 let PrintMethod = "printMBUFOffset";
177}
178def glc : Operand <i1> {
179 let PrintMethod = "printGLC";
180}
181def slc : Operand <i1> {
182 let PrintMethod = "printSLC";
183}
184def tfe : Operand <i1> {
185 let PrintMethod = "printTFE";
186}
187
188} // End OperandType = "OPERAND_IMMEDIATE"
189
Christian Konig72d5d5c2013-02-21 15:16:44 +0000190//===----------------------------------------------------------------------===//
Tom Stellardb02c2682014-06-24 23:33:07 +0000191// Complex patterns
192//===----------------------------------------------------------------------===//
193
Tom Stellard85e8b6d2014-08-22 18:49:33 +0000194def DS1Addr1Offset : ComplexPattern<i32, 2, "SelectDS1Addr1Offset">;
Tom Stellardf3fc5552014-08-22 18:49:35 +0000195def DS64Bit4ByteAligned : ComplexPattern<i32, 3, "SelectDS64Bit4ByteAligned">;
Tom Stellard85e8b6d2014-08-22 18:49:33 +0000196
Tom Stellardb02094e2014-07-21 15:45:01 +0000197def MUBUFAddr32 : ComplexPattern<i64, 9, "SelectMUBUFAddr32">;
Tom Stellardb02c2682014-06-24 23:33:07 +0000198def MUBUFAddr64 : ComplexPattern<i64, 3, "SelectMUBUFAddr64">;
Tom Stellard7980fc82014-09-25 18:30:26 +0000199def MUBUFAddr64Atomic : ComplexPattern<i64, 4, "SelectMUBUFAddr64">;
Tom Stellardb02094e2014-07-21 15:45:01 +0000200def MUBUFScratch : ComplexPattern<i64, 4, "SelectMUBUFScratch">;
Tom Stellard155bbb72014-08-11 22:18:17 +0000201def MUBUFOffset : ComplexPattern<i64, 6, "SelectMUBUFOffset">;
Tom Stellard7980fc82014-09-25 18:30:26 +0000202def MUBUFOffsetAtomic : ComplexPattern<i64, 4, "SelectMUBUFOffset">;
Tom Stellardb02c2682014-06-24 23:33:07 +0000203
Tom Stellardb4a313a2014-08-01 00:32:39 +0000204def VOP3Mods0 : ComplexPattern<untyped, 4, "SelectVOP3Mods0">;
205def VOP3Mods : ComplexPattern<untyped, 2, "SelectVOP3Mods">;
206
Tom Stellardb02c2682014-06-24 23:33:07 +0000207//===----------------------------------------------------------------------===//
Christian Konig72d5d5c2013-02-21 15:16:44 +0000208// SI assembler operands
209//===----------------------------------------------------------------------===//
Tom Stellard75aadc22012-12-11 21:25:42 +0000210
Christian Konigeabf8332013-02-21 15:16:49 +0000211def SIOperand {
212 int ZERO = 0x80;
Christian Konigd3039962013-02-26 17:52:09 +0000213 int VCC = 0x6A;
Matt Arsenault3f981402014-09-15 15:41:53 +0000214 int FLAT_SCR = 0x68;
Tom Stellard75aadc22012-12-11 21:25:42 +0000215}
216
Tom Stellardb4a313a2014-08-01 00:32:39 +0000217def SRCMODS {
218 int NONE = 0;
219}
220
221def DSTCLAMP {
222 int NONE = 0;
223}
224
225def DSTOMOD {
226 int NONE = 0;
227}
Tom Stellard75aadc22012-12-11 21:25:42 +0000228
Christian Konig72d5d5c2013-02-21 15:16:44 +0000229//===----------------------------------------------------------------------===//
230//
231// SI Instruction multiclass helpers.
232//
233// Instructions with _32 take 32-bit operands.
234// Instructions with _64 take 64-bit operands.
235//
236// VOP_* instructions can use either a 32-bit or 64-bit encoding. The 32-bit
237// encoding is the standard encoding, but instruction that make use of
238// any of the instruction modifiers must use the 64-bit encoding.
239//
240// Instructions with _e32 use the 32-bit encoding.
241// Instructions with _e64 use the 64-bit encoding.
242//
243//===----------------------------------------------------------------------===//
244
245//===----------------------------------------------------------------------===//
246// Scalar classes
247//===----------------------------------------------------------------------===//
248
Christian Konige0130a22013-02-21 15:17:13 +0000249class SOP1_32 <bits<8> op, string opName, list<dag> pattern> : SOP1 <
250 op, (outs SReg_32:$dst), (ins SSrc_32:$src0),
251 opName#" $dst, $src0", pattern
252>;
Christian Konig72d5d5c2013-02-21 15:16:44 +0000253
Christian Konige0130a22013-02-21 15:17:13 +0000254class SOP1_64 <bits<8> op, string opName, list<dag> pattern> : SOP1 <
255 op, (outs SReg_64:$dst), (ins SSrc_64:$src0),
256 opName#" $dst, $src0", pattern
257>;
Christian Konig72d5d5c2013-02-21 15:16:44 +0000258
Matt Arsenault8333e432014-06-10 19:18:24 +0000259// 64-bit input, 32-bit output.
260class SOP1_32_64 <bits<8> op, string opName, list<dag> pattern> : SOP1 <
261 op, (outs SReg_32:$dst), (ins SSrc_64:$src0),
262 opName#" $dst, $src0", pattern
263>;
264
Christian Konige0130a22013-02-21 15:17:13 +0000265class SOP2_32 <bits<7> op, string opName, list<dag> pattern> : SOP2 <
266 op, (outs SReg_32:$dst), (ins SSrc_32:$src0, SSrc_32:$src1),
267 opName#" $dst, $src0, $src1", pattern
268>;
Christian Konig72d5d5c2013-02-21 15:16:44 +0000269
Christian Konige0130a22013-02-21 15:17:13 +0000270class SOP2_64 <bits<7> op, string opName, list<dag> pattern> : SOP2 <
271 op, (outs SReg_64:$dst), (ins SSrc_64:$src0, SSrc_64:$src1),
272 opName#" $dst, $src0, $src1", pattern
273>;
Christian Konig72d5d5c2013-02-21 15:16:44 +0000274
Tom Stellard82166022013-11-13 23:36:37 +0000275class SOP2_SHIFT_64 <bits<7> op, string opName, list<dag> pattern> : SOP2 <
276 op, (outs SReg_64:$dst), (ins SSrc_64:$src0, SSrc_32:$src1),
277 opName#" $dst, $src0, $src1", pattern
278>;
279
Christian Konig72d5d5c2013-02-21 15:16:44 +0000280
Matt Arsenault0cb92e12014-04-11 19:25:18 +0000281class SOPC_Helper <bits<7> op, RegisterClass rc, ValueType vt,
282 string opName, PatLeaf cond> : SOPC <
283 op, (outs SCCReg:$dst), (ins rc:$src0, rc:$src1),
284 opName#" $dst, $src0, $src1", []>;
285
286class SOPC_32<bits<7> op, string opName, PatLeaf cond = COND_NULL>
287 : SOPC_Helper<op, SSrc_32, i32, opName, cond>;
288
289class SOPC_64<bits<7> op, string opName, PatLeaf cond = COND_NULL>
290 : SOPC_Helper<op, SSrc_64, i64, opName, cond>;
Christian Konig72d5d5c2013-02-21 15:16:44 +0000291
Christian Konige0130a22013-02-21 15:17:13 +0000292class SOPK_32 <bits<5> op, string opName, list<dag> pattern> : SOPK <
293 op, (outs SReg_32:$dst), (ins i16imm:$src0),
294 opName#" $dst, $src0", pattern
295>;
Christian Konig72d5d5c2013-02-21 15:16:44 +0000296
Christian Konige0130a22013-02-21 15:17:13 +0000297class SOPK_64 <bits<5> op, string opName, list<dag> pattern> : SOPK <
298 op, (outs SReg_64:$dst), (ins i16imm:$src0),
299 opName#" $dst, $src0", pattern
300>;
Christian Konig72d5d5c2013-02-21 15:16:44 +0000301
Christian Konig9c7afd12013-03-18 11:33:50 +0000302multiclass SMRD_Helper <bits<5> op, string asm, RegisterClass baseClass,
303 RegisterClass dstClass> {
Christian Konig72d5d5c2013-02-21 15:16:44 +0000304 def _IMM : SMRD <
305 op, 1, (outs dstClass:$dst),
Matt Arsenault4d7d3832014-04-15 22:32:49 +0000306 (ins baseClass:$sbase, u32imm:$offset),
Christian Konige0130a22013-02-21 15:17:13 +0000307 asm#" $dst, $sbase, $offset", []
Christian Konig72d5d5c2013-02-21 15:16:44 +0000308 >;
309
310 def _SGPR : SMRD <
311 op, 0, (outs dstClass:$dst),
Christian Konig9c7afd12013-03-18 11:33:50 +0000312 (ins baseClass:$sbase, SReg_32:$soff),
Christian Konige0130a22013-02-21 15:17:13 +0000313 asm#" $dst, $sbase, $soff", []
Christian Konig72d5d5c2013-02-21 15:16:44 +0000314 >;
315}
316
317//===----------------------------------------------------------------------===//
318// Vector ALU classes
319//===----------------------------------------------------------------------===//
320
Tom Stellardb4a313a2014-08-01 00:32:39 +0000321// This must always be right before the operand being input modified.
322def InputMods : OperandWithDefaultOps <i32, (ops (i32 0))> {
323 let PrintMethod = "printOperandAndMods";
324}
325def InputModsNoDefault : Operand <i32> {
326 let PrintMethod = "printOperandAndMods";
327}
328
329class getNumSrcArgs<ValueType Src1, ValueType Src2> {
330 int ret =
331 !if (!eq(Src1.Value, untyped.Value), 1, // VOP1
332 !if (!eq(Src2.Value, untyped.Value), 2, // VOP2
333 3)); // VOP3
334}
335
336// Returns the register class to use for the destination of VOP[123C]
337// instructions for the given VT.
338class getVALUDstForVT<ValueType VT> {
339 RegisterClass ret = !if(!eq(VT.Size, 32), VReg_32, VReg_64);
340}
341
342// Returns the register class to use for source 0 of VOP[12C]
343// instructions for the given VT.
344class getVOPSrc0ForVT<ValueType VT> {
345 RegisterClass ret = !if(!eq(VT.Size, 32), VSrc_32, VSrc_64);
346}
347
348// Returns the register class to use for source 1 of VOP[12C] for the
349// given VT.
350class getVOPSrc1ForVT<ValueType VT> {
351 RegisterClass ret = !if(!eq(VT.Size, 32), VReg_32, VReg_64);
352}
353
354// Returns the register classes for the source arguments of a VOP[12C]
355// instruction for the given SrcVTs.
356class getInRC32 <list<ValueType> SrcVT> {
357 list<RegisterClass> ret = [
358 getVOPSrc0ForVT<SrcVT[0]>.ret,
359 getVOPSrc1ForVT<SrcVT[1]>.ret
360 ];
361}
362
363// Returns the register class to use for sources of VOP3 instructions for the
364// given VT.
365class getVOP3SrcForVT<ValueType VT> {
Tom Stellard73ae1cb2014-09-23 21:26:25 +0000366 RegisterClass ret = !if(!eq(VT.Size, 32), VCSrc_32, VCSrc_64);
Tom Stellardb4a313a2014-08-01 00:32:39 +0000367}
368
369// Returns the register classes for the source arguments of a VOP3
370// instruction for the given SrcVTs.
371class getInRC64 <list<ValueType> SrcVT> {
372 list<RegisterClass> ret = [
373 getVOP3SrcForVT<SrcVT[0]>.ret,
374 getVOP3SrcForVT<SrcVT[1]>.ret,
375 getVOP3SrcForVT<SrcVT[2]>.ret
376 ];
377}
378
379// Returns 1 if the source arguments have modifiers, 0 if they do not.
380class hasModifiers<ValueType SrcVT> {
381 bit ret = !if(!eq(SrcVT.Value, f32.Value), 1,
382 !if(!eq(SrcVT.Value, f64.Value), 1, 0));
383}
384
385// Returns the input arguments for VOP[12C] instructions for the given SrcVT.
386class getIns32 <RegisterClass Src0RC, RegisterClass Src1RC, int NumSrcArgs> {
387 dag ret = !if(!eq(NumSrcArgs, 1), (ins Src0RC:$src0), // VOP1
388 !if(!eq(NumSrcArgs, 2), (ins Src0RC:$src0, Src1RC:$src1), // VOP2
389 (ins)));
390}
391
392// Returns the input arguments for VOP3 instructions for the given SrcVT.
393class getIns64 <RegisterClass Src0RC, RegisterClass Src1RC,
394 RegisterClass Src2RC, int NumSrcArgs,
395 bit HasModifiers> {
396
397 dag ret =
398 !if (!eq(NumSrcArgs, 1),
399 !if (!eq(HasModifiers, 1),
400 // VOP1 with modifiers
401 (ins InputModsNoDefault:$src0_modifiers, Src0RC:$src0,
402 i32imm:$clamp, i32imm:$omod)
403 /* else */,
404 // VOP1 without modifiers
405 (ins Src0RC:$src0)
406 /* endif */ ),
407 !if (!eq(NumSrcArgs, 2),
408 !if (!eq(HasModifiers, 1),
409 // VOP 2 with modifiers
410 (ins InputModsNoDefault:$src0_modifiers, Src0RC:$src0,
411 InputModsNoDefault:$src1_modifiers, Src1RC:$src1,
412 i32imm:$clamp, i32imm:$omod)
413 /* else */,
414 // VOP2 without modifiers
415 (ins Src0RC:$src0, Src1RC:$src1)
416 /* endif */ )
417 /* NumSrcArgs == 3 */,
418 !if (!eq(HasModifiers, 1),
419 // VOP3 with modifiers
420 (ins InputModsNoDefault:$src0_modifiers, Src0RC:$src0,
421 InputModsNoDefault:$src1_modifiers, Src1RC:$src1,
422 InputModsNoDefault:$src2_modifiers, Src2RC:$src2,
423 i32imm:$clamp, i32imm:$omod)
424 /* else */,
425 // VOP3 without modifiers
426 (ins Src0RC:$src0, Src1RC:$src1, Src2RC:$src2)
427 /* endif */ )));
428}
429
430// Returns the assembly string for the inputs and outputs of a VOP[12C]
431// instruction. This does not add the _e32 suffix, so it can be reused
432// by getAsm64.
433class getAsm32 <int NumSrcArgs> {
434 string src1 = ", $src1";
435 string src2 = ", $src2";
436 string ret = " $dst, $src0"#
437 !if(!eq(NumSrcArgs, 1), "", src1)#
438 !if(!eq(NumSrcArgs, 3), src2, "");
439}
440
441// Returns the assembly string for the inputs and outputs of a VOP3
442// instruction.
443class getAsm64 <int NumSrcArgs, bit HasModifiers> {
444 string src0 = "$src0_modifiers,";
445 string src1 = !if(!eq(NumSrcArgs, 1), "", " $src1_modifiers,");
446 string src2 = !if(!eq(NumSrcArgs, 3), " $src2_modifiers,", "");
447 string ret =
448 !if(!eq(HasModifiers, 0),
449 getAsm32<NumSrcArgs>.ret,
450 " $dst, "#src0#src1#src2#" $clamp, $omod");
451}
452
453
454class VOPProfile <list<ValueType> _ArgVT> {
455
456 field list<ValueType> ArgVT = _ArgVT;
457
458 field ValueType DstVT = ArgVT[0];
459 field ValueType Src0VT = ArgVT[1];
460 field ValueType Src1VT = ArgVT[2];
461 field ValueType Src2VT = ArgVT[3];
462 field RegisterClass DstRC = getVALUDstForVT<DstVT>.ret;
463 field RegisterClass Src0RC32 = getVOPSrc0ForVT<Src0VT>.ret;
464 field RegisterClass Src1RC32 = getVOPSrc1ForVT<Src1VT>.ret;
465 field RegisterClass Src0RC64 = getVOP3SrcForVT<Src0VT>.ret;
466 field RegisterClass Src1RC64 = getVOP3SrcForVT<Src1VT>.ret;
467 field RegisterClass Src2RC64 = getVOP3SrcForVT<Src2VT>.ret;
468
469 field int NumSrcArgs = getNumSrcArgs<Src1VT, Src2VT>.ret;
470 field bit HasModifiers = hasModifiers<Src0VT>.ret;
471
472 field dag Outs = (outs DstRC:$dst);
473
474 field dag Ins32 = getIns32<Src0RC32, Src1RC32, NumSrcArgs>.ret;
475 field dag Ins64 = getIns64<Src0RC64, Src1RC64, Src2RC64, NumSrcArgs,
476 HasModifiers>.ret;
477
Matt Arsenault9215b172014-08-03 05:27:14 +0000478 field string Asm32 = "_e32"#getAsm32<NumSrcArgs>.ret;
Tom Stellardb4a313a2014-08-01 00:32:39 +0000479 field string Asm64 = getAsm64<NumSrcArgs, HasModifiers>.ret;
480}
481
482def VOP_F32_F32 : VOPProfile <[f32, f32, untyped, untyped]>;
483def VOP_F32_F64 : VOPProfile <[f32, f64, untyped, untyped]>;
484def VOP_F32_I32 : VOPProfile <[f32, i32, untyped, untyped]>;
485def VOP_F64_F32 : VOPProfile <[f64, f32, untyped, untyped]>;
486def VOP_F64_F64 : VOPProfile <[f64, f64, untyped, untyped]>;
487def VOP_F64_I32 : VOPProfile <[f64, i32, untyped, untyped]>;
488def VOP_I32_F32 : VOPProfile <[i32, f32, untyped, untyped]>;
489def VOP_I32_F64 : VOPProfile <[i32, f64, untyped, untyped]>;
490def VOP_I32_I32 : VOPProfile <[i32, i32, untyped, untyped]>;
491
492def VOP_F32_F32_F32 : VOPProfile <[f32, f32, f32, untyped]>;
493def VOP_F32_F32_I32 : VOPProfile <[f32, f32, i32, untyped]>;
494def VOP_F64_F64_F64 : VOPProfile <[f64, f64, f64, untyped]>;
495def VOP_F64_F64_I32 : VOPProfile <[f64, f64, i32, untyped]>;
496def VOP_I32_F32_F32 : VOPProfile <[i32, f32, f32, untyped]>;
497def VOP_I32_I32_I32 : VOPProfile <[i32, i32, i32, untyped]>;
498def VOP_I32_I32_I32_VCC : VOPProfile <[i32, i32, i32, untyped]> {
Tom Stellard73ae1cb2014-09-23 21:26:25 +0000499 let Src0RC32 = VCSrc_32;
Tom Stellardb4a313a2014-08-01 00:32:39 +0000500}
501def VOP_I64_I64_I32 : VOPProfile <[i64, i64, i32, untyped]>;
502def VOP_I64_I64_I64 : VOPProfile <[i64, i64, i64, untyped]>;
503
504def VOP_F32_F32_F32_F32 : VOPProfile <[f32, f32, f32, f32]>;
505def VOP_F64_F64_F64_F64 : VOPProfile <[f64, f64, f64, f64]>;
506def VOP_I32_I32_I32_I32 : VOPProfile <[i32, i32, i32, i32]>;
507def VOP_I64_I32_I32_I64 : VOPProfile <[i64, i32, i32, i64]>;
508
509
Christian Konigf741fbf2013-02-26 17:52:42 +0000510class VOP <string opName> {
511 string OpName = opName;
512}
513
Christian Konig3c145802013-03-27 09:12:59 +0000514class VOP2_REV <string revOp, bit isOrig> {
515 string RevOp = revOp;
516 bit IsOrig = isOrig;
517}
518
Matt Arsenault9903ccf2014-09-08 15:07:27 +0000519class AtomicNoRet <string noRetOp, bit isRet> {
520 string NoRetOp = noRetOp;
521 bit IsRet = isRet;
522}
523
Tom Stellardc721a232014-05-16 20:56:47 +0000524class SIMCInstr <string pseudo, int subtarget> {
525 string PseudoInstr = pseudo;
526 int Subtarget = subtarget;
527}
528
Tom Stellardb4a313a2014-08-01 00:32:39 +0000529class VOP3DisableFields <bit HasSrc1, bit HasSrc2, bit HasModifiers> {
530
531 bits<2> src0_modifiers = !if(HasModifiers, ?, 0);
532 bits<2> src1_modifiers = !if(HasModifiers, !if(HasSrc1, ?, 0), 0);
533 bits<2> src2_modifiers = !if(HasModifiers, !if(HasSrc2, ? ,0) ,0);
534 bits<2> omod = !if(HasModifiers, ?, 0);
535 bits<1> clamp = !if(HasModifiers, ?, 0);
536 bits<9> src1 = !if(HasSrc1, ?, 0);
537 bits<9> src2 = !if(HasSrc2, ?, 0);
538}
539
Tom Stellardbda32c92014-07-21 17:44:29 +0000540class VOP3_Pseudo <dag outs, dag ins, list<dag> pattern, string opName> :
541 VOP3Common <outs, ins, "", pattern>,
542 VOP <opName>,
543 SIMCInstr<opName, SISubtarget.NONE> {
544 let isPseudo = 1;
545}
546
547class VOP3_Real_si <bits<9> op, dag outs, dag ins, string asm, string opName> :
548 VOP3 <op, outs, ins, asm, []>,
549 SIMCInstr<opName, SISubtarget.SI>;
550
Tom Stellardc721a232014-05-16 20:56:47 +0000551multiclass VOP3_m <bits<9> op, dag outs, dag ins, string asm, list<dag> pattern,
Tom Stellardb4a313a2014-08-01 00:32:39 +0000552 string opName, int NumSrcArgs, bit HasMods = 1> {
Tom Stellardc721a232014-05-16 20:56:47 +0000553
Tom Stellardbda32c92014-07-21 17:44:29 +0000554 def "" : VOP3_Pseudo <outs, ins, pattern, opName>;
Tom Stellardc721a232014-05-16 20:56:47 +0000555
Tom Stellardb4a313a2014-08-01 00:32:39 +0000556 def _si : VOP3_Real_si <op, outs, ins, asm, opName>,
557 VOP3DisableFields<!if(!eq(NumSrcArgs, 1), 0, 1),
558 !if(!eq(NumSrcArgs, 2), 0, 1),
559 HasMods>;
Tom Stellardc721a232014-05-16 20:56:47 +0000560
561}
562
Tom Stellardbda32c92014-07-21 17:44:29 +0000563multiclass VOP3_1_m <bits<8> op, dag outs, dag ins, string asm,
Tom Stellardb4a313a2014-08-01 00:32:39 +0000564 list<dag> pattern, string opName, bit HasMods = 1> {
Tom Stellardbda32c92014-07-21 17:44:29 +0000565
566 def "" : VOP3_Pseudo <outs, ins, pattern, opName>;
567
Tom Stellardb4a313a2014-08-01 00:32:39 +0000568 def _si : VOP3_Real_si <
569 {1, 1, op{6}, op{5}, op{4}, op{3}, op{2}, op{1}, op{0}},
570 outs, ins, asm, opName>,
571 VOP3DisableFields<0, 0, HasMods>;
Tom Stellardbda32c92014-07-21 17:44:29 +0000572}
573
Tom Stellardb4a313a2014-08-01 00:32:39 +0000574multiclass VOP3_2_m <bits<9> op, dag outs, dag ins, string asm,
575 list<dag> pattern, string opName, string revOp,
576 bit HasMods = 1, bit UseFullOp = 0> {
577
578 def "" : VOP3_Pseudo <outs, ins, pattern, opName>,
579 VOP2_REV<revOp#"_e64", !eq(revOp, opName)>;
580
581 def _si : VOP3_Real_si <op,
582 outs, ins, asm, opName>,
583 VOP2_REV<revOp#"_e64_si", !eq(revOp, opName)>,
584 VOP3DisableFields<1, 0, HasMods>;
585}
586
587multiclass VOP3b_2_m <bits<9> op, dag outs, dag ins, string asm,
588 list<dag> pattern, string opName, string revOp,
589 bit HasMods = 1, bit UseFullOp = 0> {
590 def "" : VOP3_Pseudo <outs, ins, pattern, opName>,
591 VOP2_REV<revOp#"_e64", !eq(revOp, opName)>;
592
593 // The VOP2 variant puts the carry out into VCC, the VOP3 variant
594 // can write it into any SGPR. We currently don't use the carry out,
595 // so for now hardcode it to VCC as well.
596 let sdst = SIOperand.VCC, Defs = [VCC] in {
597 def _si : VOP3b <op, outs, ins, asm, pattern>,
598 VOP3DisableFields<1, 0, HasMods>,
599 SIMCInstr<opName, SISubtarget.SI>,
600 VOP2_REV<revOp#"_e64_si", !eq(revOp, opName)>;
601 } // End sdst = SIOperand.VCC, Defs = [VCC]
602}
603
604multiclass VOP3_C_m <bits<8> op, dag outs, dag ins, string asm,
605 list<dag> pattern, string opName,
606 bit HasMods, bit defExec> {
Tom Stellardbda32c92014-07-21 17:44:29 +0000607
608 def "" : VOP3_Pseudo <outs, ins, pattern, opName>;
609
Tom Stellardbda32c92014-07-21 17:44:29 +0000610 def _si : VOP3_Real_si <
Tom Stellardb4a313a2014-08-01 00:32:39 +0000611 {0, op{7}, op{6}, op{5}, op{4}, op{3}, op{2}, op{1}, op{0}},
612 outs, ins, asm, opName>,
613 VOP3DisableFields<1, 0, HasMods> {
614 let Defs = !if(defExec, [EXEC], []);
Christian Konigd3039962013-02-26 17:52:09 +0000615 }
616}
617
Tom Stellardb4a313a2014-08-01 00:32:39 +0000618multiclass VOP1_Helper <bits<8> op, string opName, dag outs,
619 dag ins32, string asm32, list<dag> pat32,
620 dag ins64, string asm64, list<dag> pat64,
621 bit HasMods> {
Christian Konigb19849a2013-02-21 15:17:04 +0000622
Tom Stellardb4a313a2014-08-01 00:32:39 +0000623 def _e32 : VOP1 <op, outs, ins32, opName#asm32, pat32>, VOP<opName>;
624
625 defm _e64 : VOP3_1_m <op, outs, ins64, opName#"_e64"#asm64, pat64, opName, HasMods>;
Christian Konig72d5d5c2013-02-21 15:16:44 +0000626}
627
Tom Stellardb4a313a2014-08-01 00:32:39 +0000628multiclass VOP1Inst <bits<8> op, string opName, VOPProfile P,
629 SDPatternOperator node = null_frag> : VOP1_Helper <
630 op, opName, P.Outs,
631 P.Ins32, P.Asm32, [],
632 P.Ins64, P.Asm64,
633 !if(P.HasModifiers,
634 [(set P.DstVT:$dst, (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0,
635 i32:$src0_modifiers, i32:$clamp, i32:$omod))))],
636 [(set P.DstVT:$dst, (node P.Src0VT:$src0))]),
637 P.HasModifiers
Tom Stellardc721a232014-05-16 20:56:47 +0000638>;
Christian Konigf5754a02013-02-21 15:17:09 +0000639
Tom Stellardb4a313a2014-08-01 00:32:39 +0000640class VOP2_e32 <bits<6> op, string opName, dag outs, dag ins, string asm,
641 list<dag> pattern, string revOp> :
642 VOP2 <op, outs, ins, opName#asm, pattern>,
643 VOP <opName>,
644 VOP2_REV<revOp#"_e32", !eq(revOp, opName)>;
Tom Stellard1cfd7a52013-05-20 15:02:12 +0000645
Tom Stellardb4a313a2014-08-01 00:32:39 +0000646multiclass VOP2_Helper <bits<6> op, string opName, dag outs,
647 dag ins32, string asm32, list<dag> pat32,
648 dag ins64, string asm64, list<dag> pat64,
649 string revOp, bit HasMods> {
650 def _e32 : VOP2_e32 <op, opName, outs, ins32, asm32, pat32, revOp>;
651
652 defm _e64 : VOP3_2_m <
653 {1, 0, 0, op{5}, op{4}, op{3}, op{2}, op{1}, op{0}},
654 outs, ins64, opName#"_e64"#asm64, pat64, opName, revOp, HasMods
655 >;
Tom Stellard1cfd7a52013-05-20 15:02:12 +0000656}
657
Tom Stellardb4a313a2014-08-01 00:32:39 +0000658multiclass VOP2Inst <bits<6> op, string opName, VOPProfile P,
659 SDPatternOperator node = null_frag,
660 string revOp = opName> : VOP2_Helper <
661 op, opName, P.Outs,
662 P.Ins32, P.Asm32, [],
663 P.Ins64, P.Asm64,
664 !if(P.HasModifiers,
665 [(set P.DstVT:$dst,
666 (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers,
667 i32:$clamp, i32:$omod)),
668 (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers))))],
669 [(set P.DstVT:$dst, (node P.Src0VT:$src0, P.Src1VT:$src1))]),
670 revOp, P.HasModifiers
671>;
672
673multiclass VOP2b_Helper <bits<6> op, string opName, dag outs,
674 dag ins32, string asm32, list<dag> pat32,
675 dag ins64, string asm64, list<dag> pat64,
676 string revOp, bit HasMods> {
677
678 def _e32 : VOP2_e32 <op, opName, outs, ins32, asm32, pat32, revOp>;
679
680 defm _e64 : VOP3b_2_m <
681 {1, 0, 0, op{5}, op{4}, op{3}, op{2}, op{1}, op{0}},
682 outs, ins64, opName#"_e64"#asm64, pat64, opName, revOp, HasMods
683 >;
684}
685
686multiclass VOP2bInst <bits<6> op, string opName, VOPProfile P,
687 SDPatternOperator node = null_frag,
688 string revOp = opName> : VOP2b_Helper <
689 op, opName, P.Outs,
690 P.Ins32, P.Asm32, [],
691 P.Ins64, P.Asm64,
692 !if(P.HasModifiers,
693 [(set P.DstVT:$dst,
694 (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers,
695 i32:$clamp, i32:$omod)),
696 (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers))))],
697 [(set P.DstVT:$dst, (node P.Src0VT:$src0, P.Src1VT:$src1))]),
698 revOp, P.HasModifiers
699>;
700
701multiclass VOPC_Helper <bits<8> op, string opName,
702 dag ins32, string asm32, list<dag> pat32,
703 dag out64, dag ins64, string asm64, list<dag> pat64,
704 bit HasMods, bit DefExec> {
705 def _e32 : VOPC <op, ins32, opName#asm32, pat32>, VOP <opName> {
706 let Defs = !if(DefExec, [EXEC], []);
707 }
708
709 defm _e64 : VOP3_C_m <op, out64, ins64, opName#"_e64"#asm64, pat64, opName,
710 HasMods, DefExec>;
711}
712
713multiclass VOPCInst <bits<8> op, string opName,
714 VOPProfile P, PatLeaf cond = COND_NULL,
715 bit DefExec = 0> : VOPC_Helper <
716 op, opName,
717 P.Ins32, P.Asm32, [],
718 (outs SReg_64:$dst), P.Ins64, P.Asm64,
719 !if(P.HasModifiers,
720 [(set i1:$dst,
721 (setcc (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers,
722 i32:$clamp, i32:$omod)),
723 (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers)),
724 cond))],
725 [(set i1:$dst, (setcc P.Src0VT:$src0, P.Src1VT:$src1, cond))]),
726 P.HasModifiers, DefExec
727>;
728
729multiclass VOPC_F32 <bits<8> op, string opName, PatLeaf cond = COND_NULL> :
730 VOPCInst <op, opName, VOP_F32_F32_F32, cond>;
731
732multiclass VOPC_F64 <bits<8> op, string opName, PatLeaf cond = COND_NULL> :
733 VOPCInst <op, opName, VOP_F64_F64_F64, cond>;
734
735multiclass VOPC_I32 <bits<8> op, string opName, PatLeaf cond = COND_NULL> :
736 VOPCInst <op, opName, VOP_I32_I32_I32, cond>;
737
738multiclass VOPC_I64 <bits<8> op, string opName, PatLeaf cond = COND_NULL> :
739 VOPCInst <op, opName, VOP_I64_I64_I64, cond>;
Christian Konigf5754a02013-02-21 15:17:09 +0000740
Matt Arsenaultf2b0aeb2014-06-23 18:28:28 +0000741
Tom Stellardb4a313a2014-08-01 00:32:39 +0000742multiclass VOPCX <bits<8> op, string opName, VOPProfile P,
743 PatLeaf cond = COND_NULL>
744 : VOPCInst <op, opName, P, cond, 1>;
745
746multiclass VOPCX_F32 <bits<8> op, string opName, PatLeaf cond = COND_NULL> :
747 VOPCX <op, opName, VOP_F32_F32_F32, cond>;
748
749multiclass VOPCX_F64 <bits<8> op, string opName, PatLeaf cond = COND_NULL> :
750 VOPCX <op, opName, VOP_F64_F64_F64, cond>;
751
752multiclass VOPCX_I32 <bits<8> op, string opName, PatLeaf cond = COND_NULL> :
753 VOPCX <op, opName, VOP_I32_I32_I32, cond>;
754
755multiclass VOPCX_I64 <bits<8> op, string opName, PatLeaf cond = COND_NULL> :
756 VOPCX <op, opName, VOP_I64_I64_I64, cond>;
757
758multiclass VOP3_Helper <bits<9> op, string opName, dag outs, dag ins, string asm,
759 list<dag> pat, int NumSrcArgs, bit HasMods> : VOP3_m <
760 op, outs, ins, opName#asm, pat, opName, NumSrcArgs, HasMods
761>;
762
763multiclass VOP3Inst <bits<9> op, string opName, VOPProfile P,
764 SDPatternOperator node = null_frag> : VOP3_Helper <
765 op, opName, P.Outs, P.Ins64, P.Asm64,
766 !if(!eq(P.NumSrcArgs, 3),
767 !if(P.HasModifiers,
768 [(set P.DstVT:$dst,
769 (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers,
770 i32:$clamp, i32:$omod)),
771 (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers)),
772 (P.Src2VT (VOP3Mods P.Src2VT:$src2, i32:$src2_modifiers))))],
773 [(set P.DstVT:$dst, (node P.Src0VT:$src0, P.Src1VT:$src1,
774 P.Src2VT:$src2))]),
775 !if(!eq(P.NumSrcArgs, 2),
776 !if(P.HasModifiers,
777 [(set P.DstVT:$dst,
778 (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers,
779 i32:$clamp, i32:$omod)),
780 (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers))))],
781 [(set P.DstVT:$dst, (node P.Src0VT:$src0, P.Src1VT:$src1))])
782 /* P.NumSrcArgs == 1 */,
783 !if(P.HasModifiers,
784 [(set P.DstVT:$dst,
785 (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers,
786 i32:$clamp, i32:$omod))))],
787 [(set P.DstVT:$dst, (node P.Src0VT:$src0))]))),
788 P.NumSrcArgs, P.HasModifiers
789>;
790
791multiclass VOP3b_Helper <bits<9> op, RegisterClass vrc, RegisterClass arc,
792 string opName, list<dag> pattern> :
793 VOP3b_2_m <
Matt Arsenaultf2b0aeb2014-06-23 18:28:28 +0000794 op, (outs vrc:$dst0, SReg_64:$dst1),
795 (ins arc:$src0, arc:$src1, arc:$src2,
796 InstFlag:$abs, InstFlag:$clamp, InstFlag:$omod, InstFlag:$neg),
Tom Stellardb4a313a2014-08-01 00:32:39 +0000797 opName#" $dst0, $dst1, $src0, $src1, $src2, $abs, $clamp, $omod, $neg", pattern,
798 opName, opName, 1, 1
799>;
Matt Arsenaultf2b0aeb2014-06-23 18:28:28 +0000800
Tom Stellardb4a313a2014-08-01 00:32:39 +0000801multiclass VOP3b_64 <bits<9> op, string opName, list<dag> pattern> :
Matt Arsenaultf2b0aeb2014-06-23 18:28:28 +0000802 VOP3b_Helper <op, VReg_64, VSrc_64, opName, pattern>;
803
Tom Stellardb4a313a2014-08-01 00:32:39 +0000804multiclass VOP3b_32 <bits<9> op, string opName, list<dag> pattern> :
Matt Arsenaultf2b0aeb2014-06-23 18:28:28 +0000805 VOP3b_Helper <op, VReg_32, VSrc_32, opName, pattern>;
806
Matt Arsenault8675db12014-08-29 16:01:14 +0000807
808class Vop3ModPat<Instruction Inst, VOPProfile P, SDPatternOperator node> : Pat<
809 (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers, i32:$clamp, i32:$omod)),
810 (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers)),
811 (P.Src2VT (VOP3Mods P.Src2VT:$src2, i32:$src2_modifiers))),
812 (Inst i32:$src0_modifiers, P.Src0VT:$src0,
813 i32:$src1_modifiers, P.Src1VT:$src1,
814 i32:$src2_modifiers, P.Src2VT:$src2,
815 i32:$clamp,
816 i32:$omod)>;
817
Christian Konig72d5d5c2013-02-21 15:16:44 +0000818//===----------------------------------------------------------------------===//
819// Vector I/O classes
820//===----------------------------------------------------------------------===//
821
Matt Arsenault9cd8c382014-03-19 22:19:39 +0000822class DS_1A <bits<8> op, dag outs, dag ins, string asm, list<dag> pat> :
823 DS <op, outs, ins, asm, pat> {
824 bits<16> offset;
825
Matt Arsenault99ed7892014-03-19 22:19:49 +0000826 // Single load interpret the 2 i8imm operands as a single i16 offset.
Matt Arsenault9cd8c382014-03-19 22:19:39 +0000827 let offset0 = offset{7-0};
828 let offset1 = offset{15-8};
829}
830
831class DS_Load_Helper <bits<8> op, string asm, RegisterClass regClass> : DS_1A <
Michel Danzer1c454302013-07-10 16:36:43 +0000832 op,
833 (outs regClass:$vdst),
Matt Arsenault4d7d3832014-04-15 22:32:49 +0000834 (ins i1imm:$gds, VReg_32:$addr, u16imm:$offset),
Matt Arsenault547aff22014-03-19 22:19:43 +0000835 asm#" $vdst, $addr, $offset, [M0]",
Michel Danzer1c454302013-07-10 16:36:43 +0000836 []> {
Matt Arsenault9cd8c382014-03-19 22:19:39 +0000837 let data0 = 0;
838 let data1 = 0;
Michel Danzer1c454302013-07-10 16:36:43 +0000839 let mayLoad = 1;
840 let mayStore = 0;
841}
842
Matt Arsenaultdd78b802014-03-19 22:19:56 +0000843class DS_Load2_Helper <bits<8> op, string asm, RegisterClass regClass> : DS <
844 op,
845 (outs regClass:$vdst),
Matt Arsenault4d7d3832014-04-15 22:32:49 +0000846 (ins i1imm:$gds, VReg_32:$addr, u8imm:$offset0, u8imm:$offset1),
Matt Arsenaultcdcdb872014-08-01 17:00:26 +0000847 asm#" $vdst, $addr, $offset0, $offset1, [M0]",
Matt Arsenaultdd78b802014-03-19 22:19:56 +0000848 []> {
849 let data0 = 0;
850 let data1 = 0;
851 let mayLoad = 1;
852 let mayStore = 0;
853}
854
Matt Arsenault9cd8c382014-03-19 22:19:39 +0000855class DS_Store_Helper <bits<8> op, string asm, RegisterClass regClass> : DS_1A <
Michel Danzer1c454302013-07-10 16:36:43 +0000856 op,
857 (outs),
Matt Arsenault4d7d3832014-04-15 22:32:49 +0000858 (ins i1imm:$gds, VReg_32:$addr, regClass:$data0, u16imm:$offset),
Matt Arsenault547aff22014-03-19 22:19:43 +0000859 asm#" $addr, $data0, $offset [M0]",
Michel Danzer1c454302013-07-10 16:36:43 +0000860 []> {
Matt Arsenault9cd8c382014-03-19 22:19:39 +0000861 let data1 = 0;
Michel Danzer1c454302013-07-10 16:36:43 +0000862 let mayStore = 1;
863 let mayLoad = 0;
864 let vdst = 0;
865}
866
Tom Stellard05105142014-08-22 18:49:28 +0000867class DS_Store2_Helper <bits<8> op, string asm, RegisterClass regClass> : DS <
Matt Arsenaultdd78b802014-03-19 22:19:56 +0000868 op,
869 (outs),
Matt Arsenaultfa097f82014-08-04 18:49:22 +0000870 (ins i1imm:$gds, VReg_32:$addr, regClass:$data0, regClass:$data1,
871 u8imm:$offset0, u8imm:$offset1),
Matt Arsenaultdd78b802014-03-19 22:19:56 +0000872 asm#" $addr, $data0, $data1, $offset0, $offset1 [M0]",
873 []> {
874 let mayStore = 1;
875 let mayLoad = 0;
876 let vdst = 0;
877}
878
Matt Arsenault8c6613d2014-06-11 18:08:39 +0000879// 1 address, 1 data.
Matt Arsenault9903ccf2014-09-08 15:07:27 +0000880class DS_1A1D_RET <bits<8> op, string asm, RegisterClass rc, string noRetOp = ""> : DS_1A <
Tom Stellard13c68ef2013-09-05 18:38:09 +0000881 op,
882 (outs rc:$vdst),
Matt Arsenaultcaa0ec22014-06-11 18:08:54 +0000883 (ins i1imm:$gds, VReg_32:$addr, rc:$data0, u16imm:$offset),
Matt Arsenault9903ccf2014-09-08 15:07:27 +0000884 asm#" $vdst, $addr, $data0, $offset, [M0]", []>,
885 AtomicNoRet<noRetOp, 1> {
Matt Arsenault9cd8c382014-03-19 22:19:39 +0000886
887 let data1 = 0;
Tom Stellard13c68ef2013-09-05 18:38:09 +0000888 let mayStore = 1;
889 let mayLoad = 1;
Matt Arsenault7ac9c4a2014-09-08 15:07:31 +0000890
891 let hasPostISelHook = 1; // Adjusted to no return version.
Tom Stellard13c68ef2013-09-05 18:38:09 +0000892}
893
Matt Arsenault8c6613d2014-06-11 18:08:39 +0000894// 1 address, 2 data.
Matt Arsenault9903ccf2014-09-08 15:07:27 +0000895class DS_1A2D_RET <bits<8> op, string asm, RegisterClass rc, string noRetOp = ""> : DS_1A <
Matt Arsenault8c6613d2014-06-11 18:08:39 +0000896 op,
897 (outs rc:$vdst),
Matt Arsenaultcaa0ec22014-06-11 18:08:54 +0000898 (ins i1imm:$gds, VReg_32:$addr, rc:$data0, rc:$data1, u16imm:$offset),
Matt Arsenault8c6613d2014-06-11 18:08:39 +0000899 asm#" $vdst, $addr, $data0, $data1, $offset, [M0]",
Matt Arsenault9903ccf2014-09-08 15:07:27 +0000900 []>,
901 AtomicNoRet<noRetOp, 1> {
Matt Arsenault8c6613d2014-06-11 18:08:39 +0000902 let mayStore = 1;
903 let mayLoad = 1;
Matt Arsenault7ac9c4a2014-09-08 15:07:31 +0000904
905 let hasPostISelHook = 1; // Adjusted to no return version.
Matt Arsenault8c6613d2014-06-11 18:08:39 +0000906}
907
908// 1 address, 2 data.
Matt Arsenault9903ccf2014-09-08 15:07:27 +0000909class DS_1A2D_NORET <bits<8> op, string asm, RegisterClass rc, string noRetOp = asm> : DS_1A <
Matt Arsenault8c6613d2014-06-11 18:08:39 +0000910 op,
911 (outs),
Matt Arsenaultcaa0ec22014-06-11 18:08:54 +0000912 (ins i1imm:$gds, VReg_32:$addr, rc:$data0, rc:$data1, u16imm:$offset),
Matt Arsenault8c6613d2014-06-11 18:08:39 +0000913 asm#" $addr, $data0, $data1, $offset, [M0]",
Matt Arsenault9903ccf2014-09-08 15:07:27 +0000914 []>,
915 AtomicNoRet<noRetOp, 0> {
Matt Arsenault8c6613d2014-06-11 18:08:39 +0000916 let mayStore = 1;
917 let mayLoad = 1;
918}
919
920// 1 address, 1 data.
Matt Arsenault9903ccf2014-09-08 15:07:27 +0000921class DS_1A1D_NORET <bits<8> op, string asm, RegisterClass rc, string noRetOp = asm> : DS_1A <
Matt Arsenault8c6613d2014-06-11 18:08:39 +0000922 op,
923 (outs),
Matt Arsenaultcaa0ec22014-06-11 18:08:54 +0000924 (ins i1imm:$gds, VReg_32:$addr, rc:$data0, u16imm:$offset),
Matt Arsenault8c6613d2014-06-11 18:08:39 +0000925 asm#" $addr, $data0, $offset, [M0]",
Matt Arsenault9903ccf2014-09-08 15:07:27 +0000926 []>,
927 AtomicNoRet<noRetOp, 0> {
Matt Arsenault8c6613d2014-06-11 18:08:39 +0000928
929 let data1 = 0;
930 let mayStore = 1;
931 let mayLoad = 1;
932}
933
Tom Stellard7980fc82014-09-25 18:30:26 +0000934class MUBUFAddr64Table <bit is_addr64, string suffix = ""> {
Tom Stellard155bbb72014-08-11 22:18:17 +0000935
936 bit IsAddr64 = is_addr64;
Tom Stellard7980fc82014-09-25 18:30:26 +0000937 string OpName = NAME # suffix;
Tom Stellard155bbb72014-08-11 22:18:17 +0000938}
939
Christian Konig72d5d5c2013-02-21 15:16:44 +0000940class MTBUF_Store_Helper <bits<3> op, string asm, RegisterClass regClass> : MTBUF <
941 op,
Tom Stellard75aadc22012-12-11 21:25:42 +0000942 (outs),
Matt Arsenault4d7d3832014-04-15 22:32:49 +0000943 (ins regClass:$vdata, u16imm:$offset, i1imm:$offen, i1imm:$idxen, i1imm:$glc,
Christian Konig72d5d5c2013-02-21 15:16:44 +0000944 i1imm:$addr64, i8imm:$dfmt, i8imm:$nfmt, VReg_32:$vaddr,
Christian Konig84652962013-03-01 09:46:17 +0000945 SReg_128:$srsrc, i1imm:$slc, i1imm:$tfe, SSrc_32:$soffset),
Christian Konig08e768b2013-02-21 15:17:17 +0000946 asm#" $vdata, $offset, $offen, $idxen, $glc, $addr64, $dfmt,"
947 #" $nfmt, $vaddr, $srsrc, $slc, $tfe, $soffset",
Christian Konig72d5d5c2013-02-21 15:16:44 +0000948 []> {
949 let mayStore = 1;
Tom Stellard75aadc22012-12-11 21:25:42 +0000950 let mayLoad = 0;
Tom Stellard75aadc22012-12-11 21:25:42 +0000951}
Tom Stellard75aadc22012-12-11 21:25:42 +0000952
Tom Stellard7980fc82014-09-25 18:30:26 +0000953class MUBUFAtomicAddr64 <bits<7> op, dag outs, dag ins, string asm, list<dag> pattern>
954 : MUBUF <op, outs, ins, asm, pattern> {
955
956 let offen = 0;
957 let idxen = 0;
958 let addr64 = 1;
959 let tfe = 0;
960 let lds = 0;
961 let soffset = 128;
962}
963
964class MUBUFAtomicOffset <bits<7> op, dag outs, dag ins, string asm, list<dag> pattern>
965 : MUBUF <op, outs, ins, asm, pattern> {
966
967 let offen = 0;
968 let idxen = 0;
969 let addr64 = 0;
970 let tfe = 0;
971 let lds = 0;
972 let vaddr = 0;
973}
974
975multiclass MUBUF_Atomic <bits<7> op, string name, RegisterClass rc,
976 ValueType vt, SDPatternOperator atomic> {
977
978 let mayStore = 1, mayLoad = 1, hasPostISelHook = 1 in {
979
980 // No return variants
981 let glc = 0 in {
982
983 def _ADDR64 : MUBUFAtomicAddr64 <
984 op, (outs),
985 (ins rc:$vdata, SReg_128:$srsrc, VReg_64:$vaddr,
986 mbuf_offset:$offset, slc:$slc),
987 name#" $vdata, $vaddr, $srsrc, 0 addr64"#"$offset"#"$slc", []
988 >, MUBUFAddr64Table<1>, AtomicNoRet<NAME#"_ADDR64", 0>;
989
990 def _OFFSET : MUBUFAtomicOffset <
991 op, (outs),
992 (ins rc:$vdata, SReg_128:$srsrc, mbuf_offset:$offset,
993 SSrc_32:$soffset, slc:$slc),
994 name#" $vdata, $srsrc, $soffset"#"$offset"#"$slc", []
995 >, MUBUFAddr64Table<0>, AtomicNoRet<NAME#"_OFFSET", 0>;
996 } // glc = 0
997
998 // Variant that return values
999 let glc = 1, Constraints = "$vdata = $vdata_in",
1000 DisableEncoding = "$vdata_in" in {
1001
1002 def _RTN_ADDR64 : MUBUFAtomicAddr64 <
1003 op, (outs rc:$vdata),
1004 (ins rc:$vdata_in, SReg_128:$srsrc, VReg_64:$vaddr,
1005 mbuf_offset:$offset, slc:$slc),
1006 name#" $vdata, $vaddr, $srsrc, 0 addr64"#"$offset"#" glc"#"$slc",
1007 [(set vt:$vdata,
1008 (atomic (MUBUFAddr64Atomic v4i32:$srsrc, i64:$vaddr, i16:$offset,
1009 i1:$slc), vt:$vdata_in))]
1010 >, MUBUFAddr64Table<1, "_RTN">, AtomicNoRet<NAME#"_ADDR64", 1>;
1011
1012 def _RTN_OFFSET : MUBUFAtomicOffset <
1013 op, (outs rc:$vdata),
1014 (ins rc:$vdata_in, SReg_128:$srsrc, mbuf_offset:$offset,
1015 SSrc_32:$soffset, slc:$slc),
1016 name#" $vdata, $srsrc, $soffset"#"$offset"#" glc $slc",
1017 [(set vt:$vdata,
1018 (atomic (MUBUFOffsetAtomic v4i32:$srsrc, i32:$soffset, i16:$offset,
1019 i1:$slc), vt:$vdata_in))]
1020 >, MUBUFAddr64Table<0, "_RTN">, AtomicNoRet<NAME#"_OFFSET", 1>;
1021
1022 } // glc = 1
1023
1024 } // mayStore = 1, mayLoad = 1, hasPostISelHook = 1
1025}
1026
Tom Stellard7c1838d2014-07-02 20:53:56 +00001027multiclass MUBUF_Load_Helper <bits<7> op, string asm, RegisterClass regClass,
1028 ValueType load_vt = i32,
1029 SDPatternOperator ld = null_frag> {
Tom Stellardf1ee7162013-05-20 15:02:31 +00001030
Michel Danzer13736222014-01-27 07:20:51 +00001031 let lds = 0, mayLoad = 1 in {
Tom Stellardf1ee7162013-05-20 15:02:31 +00001032
Michel Danzer13736222014-01-27 07:20:51 +00001033 let addr64 = 0 in {
Tom Stellardf1ee7162013-05-20 15:02:31 +00001034
Tom Stellard8e44d942014-07-21 15:44:55 +00001035 let offen = 0, idxen = 0, vaddr = 0 in {
Michel Danzer13736222014-01-27 07:20:51 +00001036 def _OFFSET : MUBUF <op, (outs regClass:$vdata),
Tom Stellard8e44d942014-07-21 15:44:55 +00001037 (ins SReg_128:$srsrc,
Tom Stellard229d5e62014-08-05 14:48:12 +00001038 mbuf_offset:$offset, SSrc_32:$soffset, glc:$glc,
1039 slc:$slc, tfe:$tfe),
Tom Stellard155bbb72014-08-11 22:18:17 +00001040 asm#" $vdata, $srsrc, $soffset"#"$offset"#"$glc"#"$slc"#"$tfe",
1041 [(set load_vt:$vdata, (ld (MUBUFOffset v4i32:$srsrc,
1042 i32:$soffset, i16:$offset,
1043 i1:$glc, i1:$slc, i1:$tfe)))]>,
1044 MUBUFAddr64Table<0>;
Michel Danzer13736222014-01-27 07:20:51 +00001045 }
Tom Stellardf1ee7162013-05-20 15:02:31 +00001046
Tom Stellardb02094e2014-07-21 15:45:01 +00001047 let offen = 1, idxen = 0 in {
Michel Danzer13736222014-01-27 07:20:51 +00001048 def _OFFEN : MUBUF <op, (outs regClass:$vdata),
1049 (ins SReg_128:$srsrc, VReg_32:$vaddr,
Tom Stellard229d5e62014-08-05 14:48:12 +00001050 SSrc_32:$soffset, mbuf_offset:$offset, glc:$glc, slc:$slc,
1051 tfe:$tfe),
1052 asm#" $vdata, $vaddr, $srsrc, $soffset offen"#"$offset"#"$glc"#"$slc"#"$tfe", []>;
Michel Danzer13736222014-01-27 07:20:51 +00001053 }
1054
1055 let offen = 0, idxen = 1 in {
1056 def _IDXEN : MUBUF <op, (outs regClass:$vdata),
1057 (ins SReg_128:$srsrc, VReg_32:$vaddr,
Tom Stellard229d5e62014-08-05 14:48:12 +00001058 mbuf_offset:$offset, SSrc_32:$soffset, glc:$glc,
1059 slc:$slc, tfe:$tfe),
1060 asm#" $vdata, $vaddr, $srsrc, $soffset idxen"#"$offset"#"$glc"#"$slc"#"$tfe", []>;
Michel Danzer13736222014-01-27 07:20:51 +00001061 }
1062
1063 let offen = 1, idxen = 1 in {
1064 def _BOTHEN : MUBUF <op, (outs regClass:$vdata),
1065 (ins SReg_128:$srsrc, VReg_64:$vaddr,
Tom Stellard229d5e62014-08-05 14:48:12 +00001066 SSrc_32:$soffset, glc:$glc, slc:$slc, tfe:$tfe),
1067 asm#" $vdata, $vaddr, $srsrc, $soffset, idxen offen"#"$glc"#"$slc"#"$tfe", []>;
Michel Danzer13736222014-01-27 07:20:51 +00001068 }
1069 }
1070
1071 let offen = 0, idxen = 0, addr64 = 1, glc = 0, slc = 0, tfe = 0, soffset = 128 /* ZERO */ in {
1072 def _ADDR64 : MUBUF <op, (outs regClass:$vdata),
Tom Stellard229d5e62014-08-05 14:48:12 +00001073 (ins SReg_128:$srsrc, VReg_64:$vaddr, mbuf_offset:$offset),
1074 asm#" $vdata, $vaddr, $srsrc, 0 addr64"#"$offset",
Tom Stellard7c1838d2014-07-02 20:53:56 +00001075 [(set load_vt:$vdata, (ld (MUBUFAddr64 v4i32:$srsrc,
Tom Stellard155bbb72014-08-11 22:18:17 +00001076 i64:$vaddr, i16:$offset)))]>, MUBUFAddr64Table<1>;
Michel Danzer13736222014-01-27 07:20:51 +00001077 }
Tom Stellardf1ee7162013-05-20 15:02:31 +00001078 }
Tom Stellard75aadc22012-12-11 21:25:42 +00001079}
1080
Tom Stellardb02094e2014-07-21 15:45:01 +00001081multiclass MUBUF_Store_Helper <bits<7> op, string name, RegisterClass vdataClass,
1082 ValueType store_vt, SDPatternOperator st> {
Tom Stellard754f80f2013-04-05 23:31:51 +00001083
Tom Stellardddea4862014-08-11 22:18:14 +00001084 let addr64 = 0, lds = 0 in {
1085
1086 def "" : MUBUF <
1087 op, (outs),
1088 (ins vdataClass:$vdata, SReg_128:$srsrc, VReg_32:$vaddr, SSrc_32:$soffset,
1089 mbuf_offset:$offset, offen:$offen, idxen:$idxen, glc:$glc, slc:$slc,
1090 tfe:$tfe),
1091 name#" $vdata, $vaddr, $srsrc, $soffset"#"$offen"#"$idxen"#"$offset"#
1092 "$glc"#"$slc"#"$tfe",
1093 []
1094 >;
1095
Tom Stellard155bbb72014-08-11 22:18:17 +00001096 let offen = 0, idxen = 0, vaddr = 0 in {
1097 def _OFFSET : MUBUF <
1098 op, (outs),
1099 (ins vdataClass:$vdata, SReg_128:$srsrc, mbuf_offset:$offset,
1100 SSrc_32:$soffset, glc:$glc, slc:$slc, tfe:$tfe),
1101 name#" $vdata, $srsrc, $soffset"#"$offset"#"$glc"#"$slc"#"$tfe",
1102 [(st store_vt:$vdata, (MUBUFOffset v4i32:$srsrc, i32:$soffset,
1103 i16:$offset, i1:$glc, i1:$slc,
1104 i1:$tfe))]
1105 >, MUBUFAddr64Table<0>;
1106 } // offen = 0, idxen = 0, vaddr = 0
1107
Tom Stellardddea4862014-08-11 22:18:14 +00001108 let offen = 1, idxen = 0 in {
1109 def _OFFEN : MUBUF <
1110 op, (outs),
1111 (ins vdataClass:$vdata, SReg_128:$srsrc, VReg_32:$vaddr, SSrc_32:$soffset,
1112 mbuf_offset:$offset, glc:$glc, slc:$slc, tfe:$tfe),
1113 name#" $vdata, $vaddr, $srsrc, $soffset offen"#"$offset"#
1114 "$glc"#"$slc"#"$tfe",
1115 []
1116 >;
1117 } // end offen = 1, idxen = 0
1118
1119 } // End addr64 = 0, lds = 0
Tom Stellard754f80f2013-04-05 23:31:51 +00001120
Tom Stellardb02094e2014-07-21 15:45:01 +00001121 def _ADDR64 : MUBUF <
1122 op, (outs),
Tom Stellard229d5e62014-08-05 14:48:12 +00001123 (ins vdataClass:$vdata, SReg_128:$srsrc, VReg_64:$vaddr, mbuf_offset:$offset),
1124 name#" $vdata, $vaddr, $srsrc, 0 addr64"#"$offset",
Tom Stellardb02094e2014-07-21 15:45:01 +00001125 [(st store_vt:$vdata,
Tom Stellard155bbb72014-08-11 22:18:17 +00001126 (MUBUFAddr64 v4i32:$srsrc, i64:$vaddr, i16:$offset))]>, MUBUFAddr64Table<1>
1127 {
Tom Stellardb02094e2014-07-21 15:45:01 +00001128
1129 let mayLoad = 0;
1130 let mayStore = 1;
1131
1132 // Encoding
1133 let offen = 0;
1134 let idxen = 0;
1135 let glc = 0;
1136 let addr64 = 1;
1137 let lds = 0;
1138 let slc = 0;
1139 let tfe = 0;
1140 let soffset = 128; // ZERO
1141 }
Tom Stellard754f80f2013-04-05 23:31:51 +00001142}
1143
Matt Arsenault3f981402014-09-15 15:41:53 +00001144class FLAT_Load_Helper <bits<7> op, string asm, RegisterClass regClass> :
1145 FLAT <op, (outs regClass:$data),
1146 (ins VReg_64:$addr),
1147 asm#" $data, $addr, [M0, FLAT_SCRATCH]", []> {
1148 let glc = 0;
1149 let slc = 0;
1150 let tfe = 0;
1151 let mayLoad = 1;
1152}
1153
1154class FLAT_Store_Helper <bits<7> op, string name, RegisterClass vdataClass> :
1155 FLAT <op, (outs), (ins vdataClass:$data, VReg_64:$addr),
1156 name#" $data, $addr, [M0, FLAT_SCRATCH]",
1157 []> {
1158
1159 let mayLoad = 0;
1160 let mayStore = 1;
1161
1162 // Encoding
1163 let glc = 0;
1164 let slc = 0;
1165 let tfe = 0;
1166}
1167
Christian Konig72d5d5c2013-02-21 15:16:44 +00001168class MTBUF_Load_Helper <bits<3> op, string asm, RegisterClass regClass> : MTBUF <
1169 op,
1170 (outs regClass:$dst),
Matt Arsenault4d7d3832014-04-15 22:32:49 +00001171 (ins u16imm:$offset, i1imm:$offen, i1imm:$idxen, i1imm:$glc, i1imm:$addr64,
Christian Konig84652962013-03-01 09:46:17 +00001172 i8imm:$dfmt, i8imm:$nfmt, VReg_32:$vaddr, SReg_128:$srsrc,
Christian Konig72d5d5c2013-02-21 15:16:44 +00001173 i1imm:$slc, i1imm:$tfe, SSrc_32:$soffset),
Christian Konig08e768b2013-02-21 15:17:17 +00001174 asm#" $dst, $offset, $offen, $idxen, $glc, $addr64, $dfmt,"
1175 #" $nfmt, $vaddr, $srsrc, $slc, $tfe, $soffset",
Christian Konig72d5d5c2013-02-21 15:16:44 +00001176 []> {
1177 let mayLoad = 1;
Tom Stellard75aadc22012-12-11 21:25:42 +00001178 let mayStore = 0;
Tom Stellard75aadc22012-12-11 21:25:42 +00001179}
1180
Tom Stellard682bfbc2013-10-10 17:11:24 +00001181class MIMG_Mask <string op, int channels> {
1182 string Op = op;
1183 int Channels = channels;
1184}
1185
Tom Stellard16a9a202013-08-14 23:24:17 +00001186class MIMG_NoSampler_Helper <bits<7> op, string asm,
Tom Stellard682bfbc2013-10-10 17:11:24 +00001187 RegisterClass dst_rc,
Tom Stellard16a9a202013-08-14 23:24:17 +00001188 RegisterClass src_rc> : MIMG <
Tom Stellard353b3362013-05-06 23:02:12 +00001189 op,
Tom Stellard682bfbc2013-10-10 17:11:24 +00001190 (outs dst_rc:$vdata),
Tom Stellard353b3362013-05-06 23:02:12 +00001191 (ins i32imm:$dmask, i1imm:$unorm, i1imm:$glc, i1imm:$da, i1imm:$r128,
Tom Stellard16a9a202013-08-14 23:24:17 +00001192 i1imm:$tfe, i1imm:$lwe, i1imm:$slc, src_rc:$vaddr,
Tom Stellard353b3362013-05-06 23:02:12 +00001193 SReg_256:$srsrc),
1194 asm#" $vdata, $dmask, $unorm, $glc, $da, $r128,"
1195 #" $tfe, $lwe, $slc, $vaddr, $srsrc",
1196 []> {
1197 let SSAMP = 0;
1198 let mayLoad = 1;
1199 let mayStore = 0;
1200 let hasPostISelHook = 1;
1201}
1202
Tom Stellard682bfbc2013-10-10 17:11:24 +00001203multiclass MIMG_NoSampler_Src_Helper <bits<7> op, string asm,
1204 RegisterClass dst_rc,
1205 int channels> {
1206 def _V1 : MIMG_NoSampler_Helper <op, asm, dst_rc, VReg_32>,
1207 MIMG_Mask<asm#"_V1", channels>;
1208 def _V2 : MIMG_NoSampler_Helper <op, asm, dst_rc, VReg_64>,
1209 MIMG_Mask<asm#"_V2", channels>;
1210 def _V4 : MIMG_NoSampler_Helper <op, asm, dst_rc, VReg_128>,
1211 MIMG_Mask<asm#"_V4", channels>;
1212}
1213
Tom Stellard16a9a202013-08-14 23:24:17 +00001214multiclass MIMG_NoSampler <bits<7> op, string asm> {
Tom Stellard682bfbc2013-10-10 17:11:24 +00001215 defm _V1 : MIMG_NoSampler_Src_Helper <op, asm, VReg_32, 1>;
1216 defm _V2 : MIMG_NoSampler_Src_Helper <op, asm, VReg_64, 2>;
1217 defm _V3 : MIMG_NoSampler_Src_Helper <op, asm, VReg_96, 3>;
1218 defm _V4 : MIMG_NoSampler_Src_Helper <op, asm, VReg_128, 4>;
Tom Stellard16a9a202013-08-14 23:24:17 +00001219}
1220
1221class MIMG_Sampler_Helper <bits<7> op, string asm,
Tom Stellard682bfbc2013-10-10 17:11:24 +00001222 RegisterClass dst_rc,
Tom Stellard16a9a202013-08-14 23:24:17 +00001223 RegisterClass src_rc> : MIMG <
Christian Konig72d5d5c2013-02-21 15:16:44 +00001224 op,
Tom Stellard682bfbc2013-10-10 17:11:24 +00001225 (outs dst_rc:$vdata),
Christian Konig72d5d5c2013-02-21 15:16:44 +00001226 (ins i32imm:$dmask, i1imm:$unorm, i1imm:$glc, i1imm:$da, i1imm:$r128,
Tom Stellard16a9a202013-08-14 23:24:17 +00001227 i1imm:$tfe, i1imm:$lwe, i1imm:$slc, src_rc:$vaddr,
Christian Konig84652962013-03-01 09:46:17 +00001228 SReg_256:$srsrc, SReg_128:$ssamp),
Christian Konig08e768b2013-02-21 15:17:17 +00001229 asm#" $vdata, $dmask, $unorm, $glc, $da, $r128,"
1230 #" $tfe, $lwe, $slc, $vaddr, $srsrc, $ssamp",
Christian Konig72d5d5c2013-02-21 15:16:44 +00001231 []> {
1232 let mayLoad = 1;
Tom Stellard75aadc22012-12-11 21:25:42 +00001233 let mayStore = 0;
Christian Konig8b1ed282013-04-10 08:39:16 +00001234 let hasPostISelHook = 1;
Tom Stellard75aadc22012-12-11 21:25:42 +00001235}
1236
Tom Stellard682bfbc2013-10-10 17:11:24 +00001237multiclass MIMG_Sampler_Src_Helper <bits<7> op, string asm,
1238 RegisterClass dst_rc,
1239 int channels> {
1240 def _V1 : MIMG_Sampler_Helper <op, asm, dst_rc, VReg_32>,
1241 MIMG_Mask<asm#"_V1", channels>;
1242 def _V2 : MIMG_Sampler_Helper <op, asm, dst_rc, VReg_64>,
1243 MIMG_Mask<asm#"_V2", channels>;
1244 def _V4 : MIMG_Sampler_Helper <op, asm, dst_rc, VReg_128>,
1245 MIMG_Mask<asm#"_V4", channels>;
1246 def _V8 : MIMG_Sampler_Helper <op, asm, dst_rc, VReg_256>,
1247 MIMG_Mask<asm#"_V8", channels>;
1248 def _V16 : MIMG_Sampler_Helper <op, asm, dst_rc, VReg_512>,
1249 MIMG_Mask<asm#"_V16", channels>;
1250}
1251
Tom Stellard16a9a202013-08-14 23:24:17 +00001252multiclass MIMG_Sampler <bits<7> op, string asm> {
Tom Stellard682bfbc2013-10-10 17:11:24 +00001253 defm _V1 : MIMG_Sampler_Src_Helper<op, asm, VReg_32, 1>;
1254 defm _V2 : MIMG_Sampler_Src_Helper<op, asm, VReg_64, 2>;
1255 defm _V3 : MIMG_Sampler_Src_Helper<op, asm, VReg_96, 3>;
1256 defm _V4 : MIMG_Sampler_Src_Helper<op, asm, VReg_128, 4>;
Tom Stellard16a9a202013-08-14 23:24:17 +00001257}
1258
Marek Olsak51b8e7b2014-06-18 22:00:29 +00001259class MIMG_Gather_Helper <bits<7> op, string asm,
1260 RegisterClass dst_rc,
1261 RegisterClass src_rc> : MIMG <
1262 op,
1263 (outs dst_rc:$vdata),
1264 (ins i32imm:$dmask, i1imm:$unorm, i1imm:$glc, i1imm:$da, i1imm:$r128,
1265 i1imm:$tfe, i1imm:$lwe, i1imm:$slc, src_rc:$vaddr,
1266 SReg_256:$srsrc, SReg_128:$ssamp),
1267 asm#" $vdata, $dmask, $unorm, $glc, $da, $r128,"
1268 #" $tfe, $lwe, $slc, $vaddr, $srsrc, $ssamp",
1269 []> {
1270 let mayLoad = 1;
1271 let mayStore = 0;
1272
1273 // DMASK was repurposed for GATHER4. 4 components are always
1274 // returned and DMASK works like a swizzle - it selects
1275 // the component to fetch. The only useful DMASK values are
1276 // 1=red, 2=green, 4=blue, 8=alpha. (e.g. 1 returns
1277 // (red,red,red,red) etc.) The ISA document doesn't mention
1278 // this.
1279 // Therefore, disable all code which updates DMASK by setting these two:
1280 let MIMG = 0;
1281 let hasPostISelHook = 0;
1282}
1283
1284multiclass MIMG_Gather_Src_Helper <bits<7> op, string asm,
1285 RegisterClass dst_rc,
1286 int channels> {
1287 def _V1 : MIMG_Gather_Helper <op, asm, dst_rc, VReg_32>,
1288 MIMG_Mask<asm#"_V1", channels>;
1289 def _V2 : MIMG_Gather_Helper <op, asm, dst_rc, VReg_64>,
1290 MIMG_Mask<asm#"_V2", channels>;
1291 def _V4 : MIMG_Gather_Helper <op, asm, dst_rc, VReg_128>,
1292 MIMG_Mask<asm#"_V4", channels>;
1293 def _V8 : MIMG_Gather_Helper <op, asm, dst_rc, VReg_256>,
1294 MIMG_Mask<asm#"_V8", channels>;
1295 def _V16 : MIMG_Gather_Helper <op, asm, dst_rc, VReg_512>,
1296 MIMG_Mask<asm#"_V16", channels>;
1297}
1298
1299multiclass MIMG_Gather <bits<7> op, string asm> {
1300 defm _V1 : MIMG_Gather_Src_Helper<op, asm, VReg_32, 1>;
1301 defm _V2 : MIMG_Gather_Src_Helper<op, asm, VReg_64, 2>;
1302 defm _V3 : MIMG_Gather_Src_Helper<op, asm, VReg_96, 3>;
1303 defm _V4 : MIMG_Gather_Src_Helper<op, asm, VReg_128, 4>;
1304}
1305
Christian Konigf741fbf2013-02-26 17:52:42 +00001306//===----------------------------------------------------------------------===//
1307// Vector instruction mappings
1308//===----------------------------------------------------------------------===//
1309
1310// Maps an opcode in e32 form to its e64 equivalent
1311def getVOPe64 : InstrMapping {
1312 let FilterClass = "VOP";
1313 let RowFields = ["OpName"];
1314 let ColFields = ["Size"];
1315 let KeyCol = ["4"];
1316 let ValueCols = [["8"]];
1317}
1318
Tom Stellard1aaad692014-07-21 16:55:33 +00001319// Maps an opcode in e64 form to its e32 equivalent
1320def getVOPe32 : InstrMapping {
1321 let FilterClass = "VOP";
1322 let RowFields = ["OpName"];
1323 let ColFields = ["Size"];
1324 let KeyCol = ["8"];
1325 let ValueCols = [["4"]];
1326}
1327
Christian Konig3c145802013-03-27 09:12:59 +00001328// Maps an original opcode to its commuted version
1329def getCommuteRev : InstrMapping {
1330 let FilterClass = "VOP2_REV";
1331 let RowFields = ["RevOp"];
1332 let ColFields = ["IsOrig"];
1333 let KeyCol = ["1"];
1334 let ValueCols = [["0"]];
1335}
1336
Tom Stellard682bfbc2013-10-10 17:11:24 +00001337def getMaskedMIMGOp : InstrMapping {
1338 let FilterClass = "MIMG_Mask";
1339 let RowFields = ["Op"];
1340 let ColFields = ["Channels"];
1341 let KeyCol = ["4"];
1342 let ValueCols = [["1"], ["2"], ["3"] ];
1343}
1344
Christian Konig3c145802013-03-27 09:12:59 +00001345// Maps an commuted opcode to its original version
1346def getCommuteOrig : InstrMapping {
1347 let FilterClass = "VOP2_REV";
1348 let RowFields = ["RevOp"];
1349 let ColFields = ["IsOrig"];
1350 let KeyCol = ["0"];
1351 let ValueCols = [["1"]];
1352}
1353
Tom Stellard5d7aaae2014-02-10 16:58:30 +00001354def isDS : InstrMapping {
1355 let FilterClass = "DS";
1356 let RowFields = ["Inst"];
1357 let ColFields = ["Size"];
1358 let KeyCol = ["8"];
1359 let ValueCols = [["8"]];
1360}
1361
Tom Stellardc721a232014-05-16 20:56:47 +00001362def getMCOpcode : InstrMapping {
1363 let FilterClass = "SIMCInstr";
1364 let RowFields = ["PseudoInstr"];
1365 let ColFields = ["Subtarget"];
1366 let KeyCol = [!cast<string>(SISubtarget.NONE)];
1367 let ValueCols = [[!cast<string>(SISubtarget.SI)]];
1368}
1369
Tom Stellard155bbb72014-08-11 22:18:17 +00001370def getAddr64Inst : InstrMapping {
1371 let FilterClass = "MUBUFAddr64Table";
Tom Stellard7980fc82014-09-25 18:30:26 +00001372 let RowFields = ["OpName"];
Tom Stellard155bbb72014-08-11 22:18:17 +00001373 let ColFields = ["IsAddr64"];
1374 let KeyCol = ["0"];
1375 let ValueCols = [["1"]];
1376}
1377
Matt Arsenault9903ccf2014-09-08 15:07:27 +00001378// Maps an atomic opcode to its version with a return value.
1379def getAtomicRetOp : InstrMapping {
1380 let FilterClass = "AtomicNoRet";
1381 let RowFields = ["NoRetOp"];
1382 let ColFields = ["IsRet"];
1383 let KeyCol = ["0"];
1384 let ValueCols = [["1"]];
1385}
1386
1387// Maps an atomic opcode to its returnless version.
1388def getAtomicNoRetOp : InstrMapping {
1389 let FilterClass = "AtomicNoRet";
1390 let RowFields = ["NoRetOp"];
1391 let ColFields = ["IsRet"];
1392 let KeyCol = ["1"];
1393 let ValueCols = [["0"]];
1394}
1395
Tom Stellard75aadc22012-12-11 21:25:42 +00001396include "SIInstructions.td"