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gerrit-public.fairphone.software / toolchain / llvm-project / 28a5cadb3ae0dfed9530dcbee8a0ec154f3f9f91 / . / llvm / test / CodeGen / RISCV / inline-asm.ll
blob: 58fabf868f8cc319bedd2f176ff07b1a8bb0346a [file] [log] [blame]
Alex Bradbury9330e642018-01-10 20:05:09 +0000[diff] [blame]1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
3; RUN: | FileCheck -check-prefix=RV32I %s
Alex Bradbury4efa0b62019-02-14 13:09:54 +0000[diff] [blame]4; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \
5; RUN: | FileCheck -check-prefix=RV64I %s
Alex Bradbury9330e642018-01-10 20:05:09 +0000[diff] [blame]6
7@gi = external global i32
8
Alex Bradbury5dabe032019-05-23 12:43:13 +0000[diff] [blame]9define i32 @constraint_r(i32 %a) nounwind {
Alex Bradbury9330e642018-01-10 20:05:09 +0000[diff] [blame]10; RV32I-LABEL: constraint_r:
11; RV32I: # %bb.0:
Alex Bradbury9330e642018-01-10 20:05:09 +0000[diff] [blame]12; RV32I-NEXT: lui a1, %hi(gi)
Alex Bradbury0171a9f2018-03-19 11:54:28 +0000[diff] [blame]13; RV32I-NEXT: lw a1, %lo(gi)(a1)
Alex Bradbury9330e642018-01-10 20:05:09 +0000[diff] [blame]14; RV32I-NEXT: #APP
15; RV32I-NEXT: add a0, a0, a1
16; RV32I-NEXT: #NO_APP
Alex Bradbury9330e642018-01-10 20:05:09 +0000[diff] [blame]17; RV32I-NEXT: ret
Alex Bradbury4efa0b62019-02-14 13:09:54 +0000[diff] [blame]18;
19; RV64I-LABEL: constraint_r:
20; RV64I: # %bb.0:
21; RV64I-NEXT: lui a1, %hi(gi)
22; RV64I-NEXT: lwu a1, %lo(gi)(a1)
23; RV64I-NEXT: #APP
24; RV64I-NEXT: add a0, a0, a1
25; RV64I-NEXT: #NO_APP
26; RV64I-NEXT: ret
Alex Bradbury9330e642018-01-10 20:05:09 +0000[diff] [blame]27 %1 = load i32, i32* @gi
28 %2 = tail call i32 asm "add $0, $1, $2", "=r,r,r"(i32 %a, i32 %1)
29 ret i32 %2
30}
31
Alex Bradbury5dabe032019-05-23 12:43:13 +0000[diff] [blame]32define i32 @constraint_i(i32 %a) nounwind {
Alex Bradbury9330e642018-01-10 20:05:09 +0000[diff] [blame]33; RV32I-LABEL: constraint_i:
34; RV32I: # %bb.0:
Alex Bradbury9330e642018-01-10 20:05:09 +0000[diff] [blame]35; RV32I-NEXT: #APP
36; RV32I-NEXT: addi a0, a0, 113
37; RV32I-NEXT: #NO_APP
Alex Bradbury9330e642018-01-10 20:05:09 +0000[diff] [blame]38; RV32I-NEXT: ret
Alex Bradbury4efa0b62019-02-14 13:09:54 +0000[diff] [blame]39;
40; RV64I-LABEL: constraint_i:
41; RV64I: # %bb.0:
42; RV64I-NEXT: #APP
43; RV64I-NEXT: addi a0, a0, 113
44; RV64I-NEXT: #NO_APP
45; RV64I-NEXT: ret
Alex Bradbury9330e642018-01-10 20:05:09 +0000[diff] [blame]46 %1 = load i32, i32* @gi
47 %2 = tail call i32 asm "addi $0, $1, $2", "=r,r,i"(i32 %a, i32 113)
48 ret i32 %2
49}
50
Alex Bradbury5dabe032019-05-23 12:43:13 +0000[diff] [blame]51define void @constraint_m(i32* %a) nounwind {
Alex Bradbury9330e642018-01-10 20:05:09 +0000[diff] [blame]52; RV32I-LABEL: constraint_m:
53; RV32I: # %bb.0:
Alex Bradbury9330e642018-01-10 20:05:09 +0000[diff] [blame]54; RV32I-NEXT: #APP
55; RV32I-NEXT: #NO_APP
Alex Bradbury9330e642018-01-10 20:05:09 +0000[diff] [blame]56; RV32I-NEXT: ret
Alex Bradbury4efa0b62019-02-14 13:09:54 +0000[diff] [blame]57;
58; RV64I-LABEL: constraint_m:
59; RV64I: # %bb.0:
60; RV64I-NEXT: #APP
61; RV64I-NEXT: #NO_APP
62; RV64I-NEXT: ret
Alex Bradbury9330e642018-01-10 20:05:09 +0000[diff] [blame]63 call void asm sideeffect "", "=*m"(i32* %a)
64 ret void
65}
66
Alex Bradbury5dabe032019-05-23 12:43:13 +0000[diff] [blame]67define i32 @constraint_m2(i32* %a) nounwind {
Alex Bradbury9330e642018-01-10 20:05:09 +0000[diff] [blame]68; RV32I-LABEL: constraint_m2:
69; RV32I: # %bb.0:
Alex Bradbury9330e642018-01-10 20:05:09 +0000[diff] [blame]70; RV32I-NEXT: #APP
71; RV32I-NEXT: lw a0, 0(a0)
72; RV32I-NEXT: #NO_APP
Alex Bradbury9330e642018-01-10 20:05:09 +0000[diff] [blame]73; RV32I-NEXT: ret
Alex Bradbury4efa0b62019-02-14 13:09:54 +0000[diff] [blame]74;
75; RV64I-LABEL: constraint_m2:
76; RV64I: # %bb.0:
77; RV64I-NEXT: #APP
78; RV64I-NEXT: lw a0, 0(a0)
79; RV64I-NEXT: #NO_APP
80; RV64I-NEXT: ret
Alex Bradbury9330e642018-01-10 20:05:09 +0000[diff] [blame]81 %1 = tail call i32 asm "lw $0, $1", "=r,*m"(i32* %a) nounwind
82 ret i32 %1
83}
84
Lewis Revill28a5cad2019-06-11 12:42:13 +0000[diff] [blame^]85define void @constraint_I() {
86; RV32I-LABEL: constraint_I:
87; RV32I: # %bb.0:
88; RV32I-NEXT: #APP
89; RV32I-NEXT: addi a0, a0, 2047
90; RV32I-NEXT: #NO_APP
91; RV32I-NEXT: #APP
92; RV32I-NEXT: addi a0, a0, -2048
93; RV32I-NEXT: #NO_APP
94; RV32I-NEXT: ret
95;
96; RV64I-LABEL: constraint_I:
97; RV64I: # %bb.0:
98; RV64I-NEXT: #APP
99; RV64I-NEXT: addi a0, a0, 2047
100; RV64I-NEXT: #NO_APP
101; RV64I-NEXT: #APP
102; RV64I-NEXT: addi a0, a0, -2048
103; RV64I-NEXT: #NO_APP
104; RV64I-NEXT: ret
105 tail call void asm sideeffect "addi a0, a0, $0", "I"(i32 2047)
106 tail call void asm sideeffect "addi a0, a0, $0", "I"(i32 -2048)
107 ret void
108}
109
110define void @constraint_J() {
111; RV32I-LABEL: constraint_J:
112; RV32I: # %bb.0:
113; RV32I-NEXT: #APP
114; RV32I-NEXT: addi a0, a0, 0
115; RV32I-NEXT: #NO_APP
116; RV32I-NEXT: ret
117;
118; RV64I-LABEL: constraint_J:
119; RV64I: # %bb.0:
120; RV64I-NEXT: #APP
121; RV64I-NEXT: addi a0, a0, 0
122; RV64I-NEXT: #NO_APP
123; RV64I-NEXT: ret
124 tail call void asm sideeffect "addi a0, a0, $0", "J"(i32 0)
125 ret void
126}
127
128define void @constraint_K() {
129; RV32I-LABEL: constraint_K:
130; RV32I: # %bb.0:
131; RV32I-NEXT: #APP
132; RV32I-NEXT: csrwi mstatus, 31
133; RV32I-NEXT: #NO_APP
134; RV32I-NEXT: #APP
135; RV32I-NEXT: csrwi mstatus, 0
136; RV32I-NEXT: #NO_APP
137; RV32I-NEXT: ret
138;
139; RV64I-LABEL: constraint_K:
140; RV64I: # %bb.0:
141; RV64I-NEXT: #APP
142; RV64I-NEXT: csrwi mstatus, 31
143; RV64I-NEXT: #NO_APP
144; RV64I-NEXT: #APP
145; RV64I-NEXT: csrwi mstatus, 0
146; RV64I-NEXT: #NO_APP
147; RV64I-NEXT: ret
148 tail call void asm sideeffect "csrwi mstatus, $0", "K"(i32 31)
149 tail call void asm sideeffect "csrwi mstatus, $0", "K"(i32 0)
150 ret void
151}
152
Alex Bradbury9330e642018-01-10 20:05:09 +0000[diff] [blame]153; TODO: expend tests for more complex constraints, out of range immediates etc