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Tom Stellard75aadc22012-12-11 21:25:42 +00001//===-- AMDGPU.h - MachineFunction passes hw codegen --------------*- C++ -*-=//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8/// \file
9//===----------------------------------------------------------------------===//
10
11#ifndef AMDGPU_H
12#define AMDGPU_H
13
Tom Stellard75aadc22012-12-11 21:25:42 +000014#include "llvm/Support/TargetRegistry.h"
15#include "llvm/Target/TargetMachine.h"
16
17namespace llvm {
18
Tom Stellarda6c6e1b2013-06-07 20:37:48 +000019class AMDGPUInstrPrinter;
Tom Stellard75aadc22012-12-11 21:25:42 +000020class AMDGPUTargetMachine;
Tom Stellarda6c6e1b2013-06-07 20:37:48 +000021class FunctionPass;
22class MCAsmInfo;
23class raw_ostream;
24class Target;
25class TargetMachine;
Tom Stellard75aadc22012-12-11 21:25:42 +000026
27// R600 Passes
Vincent Lejeunedec18752013-06-05 21:38:04 +000028FunctionPass *createR600VectorRegMerger(TargetMachine &tm);
Tom Stellarda6c6e1b2013-06-07 20:37:48 +000029FunctionPass *createR600TextureIntrinsicsReplacer();
Tom Stellard75aadc22012-12-11 21:25:42 +000030FunctionPass *createR600ExpandSpecialInstrsPass(TargetMachine &tm);
Vincent Lejeunef43bc572013-04-01 21:47:42 +000031FunctionPass *createR600EmitClauseMarkers(TargetMachine &tm);
Vincent Lejeune147700b2013-04-30 00:14:27 +000032FunctionPass *createR600Packetizer(TargetMachine &tm);
Vincent Lejeunebfaa63a62013-04-01 21:48:05 +000033FunctionPass *createR600ControlFlowFinalizer(TargetMachine &tm);
Tom Stellarda6c6e1b2013-06-07 20:37:48 +000034FunctionPass *createAMDGPUCFGStructurizerPass(TargetMachine &tm);
Tom Stellard75aadc22012-12-11 21:25:42 +000035
36// SI Passes
Tom Stellardf8794352012-12-19 22:10:31 +000037FunctionPass *createSIAnnotateControlFlowPass();
Tom Stellard75aadc22012-12-11 21:25:42 +000038FunctionPass *createSILowerControlFlowPass(TargetMachine &tm);
Tom Stellard2f7cdda2013-08-06 23:08:28 +000039FunctionPass *createSIFixSGPRCopiesPass(TargetMachine &tm);
Tom Stellard75aadc22012-12-11 21:25:42 +000040FunctionPass *createSICodeEmitterPass(formatted_raw_ostream &OS);
Tom Stellardc4cabef2013-01-18 21:15:53 +000041FunctionPass *createSIInsertWaits(TargetMachine &tm);
Tom Stellard75aadc22012-12-11 21:25:42 +000042
43// Passes common to R600 and SI
Tom Stellardf8794352012-12-19 22:10:31 +000044Pass *createAMDGPUStructurizeCFGPass();
Tom Stellard75aadc22012-12-11 21:25:42 +000045FunctionPass *createAMDGPUConvertToISAPass(TargetMachine &tm);
Tom Stellarda6c6e1b2013-06-07 20:37:48 +000046FunctionPass *createAMDGPUIndirectAddressingPass(TargetMachine &tm);
47FunctionPass *createAMDGPUISelDag(TargetMachine &tm);
48
Tom Stellard8b1e0212013-07-27 00:01:07 +000049/// \brief Creates an AMDGPU-specific Target Transformation Info pass.
50ImmutablePass *
51createAMDGPUTargetTransformInfoPass(const AMDGPUTargetMachine *TM);
52
Tom Stellarda6c6e1b2013-06-07 20:37:48 +000053extern Target TheAMDGPUTarget;
Tom Stellard75aadc22012-12-11 21:25:42 +000054
55} // End namespace llvm
56
57namespace ShaderType {
58 enum Type {
59 PIXEL = 0,
60 VERTEX = 1,
61 GEOMETRY = 2,
62 COMPUTE = 3
63 };
64}
65
Tom Stellarda6c6e1b2013-06-07 20:37:48 +000066/// OpenCL uses address spaces to differentiate between
67/// various memory regions on the hardware. On the CPU
68/// all of the address spaces point to the same memory,
69/// however on the GPU, each address space points to
70/// a seperate piece of memory that is unique from other
71/// memory locations.
72namespace AMDGPUAS {
73enum AddressSpaces {
74 PRIVATE_ADDRESS = 0, ///< Address space for private memory.
75 GLOBAL_ADDRESS = 1, ///< Address space for global memory (RAT0, VTX0).
76 CONSTANT_ADDRESS = 2, ///< Address space for constant memory
77 LOCAL_ADDRESS = 3, ///< Address space for local memory.
78 REGION_ADDRESS = 4, ///< Address space for region memory.
79 ADDRESS_NONE = 5, ///< Address space for unknown memory.
80 PARAM_D_ADDRESS = 6, ///< Address space for direct addressible parameter memory (CONST0)
81 PARAM_I_ADDRESS = 7, ///< Address space for indirect addressible parameter memory (VTX1)
Tom Stellard1e803092013-07-23 01:48:18 +000082
83 // Do not re-order the CONSTANT_BUFFER_* enums. Several places depend on this
84 // order to be able to dynamically index a constant buffer, for example:
85 //
86 // ConstantBufferAS = CONSTANT_BUFFER_0 + CBIdx
87
Tom Stellarda6c6e1b2013-06-07 20:37:48 +000088 CONSTANT_BUFFER_0 = 8,
89 CONSTANT_BUFFER_1 = 9,
90 CONSTANT_BUFFER_2 = 10,
91 CONSTANT_BUFFER_3 = 11,
92 CONSTANT_BUFFER_4 = 12,
93 CONSTANT_BUFFER_5 = 13,
94 CONSTANT_BUFFER_6 = 14,
95 CONSTANT_BUFFER_7 = 15,
96 CONSTANT_BUFFER_8 = 16,
97 CONSTANT_BUFFER_9 = 17,
98 CONSTANT_BUFFER_10 = 18,
99 CONSTANT_BUFFER_11 = 19,
100 CONSTANT_BUFFER_12 = 20,
101 CONSTANT_BUFFER_13 = 21,
102 CONSTANT_BUFFER_14 = 22,
103 CONSTANT_BUFFER_15 = 23,
104 LAST_ADDRESS = 24
105};
106
107} // namespace AMDGPUAS
108
Tom Stellard75aadc22012-12-11 21:25:42 +0000109#endif // AMDGPU_H