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Andrea Di Biagio3a6b0922018-03-08 13:05:02 +00001//===--------------------- BackendStatistics.h ------------------*- C++ -*-===//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9/// \file
10///
11/// This file implements a printer class for printing generic Backend
12/// statistics related to the dispatch logic, scheduler and retire unit.
13///
14/// Example:
15/// ========
16///
Andrea Di Biagio8af3fe82018-03-08 16:08:43 +000017/// Dynamic Dispatch Stall Cycles:
18/// RAT - Register unavailable: 0
19/// RCU - Retire tokens unavailable: 0
20/// SCHEDQ - Scheduler full: 42
21/// LQ - Load queue full: 0
22/// SQ - Store queue full: 0
23/// GROUP - Static restrictions on the dispatch group: 0
24///
25///
Andrea Di Biagio3a6b0922018-03-08 13:05:02 +000026/// Dispatch Logic - number of cycles where we saw N instructions dispatched:
27/// [# dispatched], [# cycles]
28/// 0, 15 (11.5%)
29/// 5, 4 (3.1%)
30///
31/// Schedulers - number of cycles where we saw N instructions issued:
32/// [# issued], [# cycles]
33/// 0, 7 (5.4%)
34/// 1, 4 (3.1%)
35/// 2, 8 (6.2%)
36///
37/// Retire Control Unit - number of cycles where we saw N instructions retired:
38/// [# retired], [# cycles]
39/// 0, 9 (6.9%)
40/// 1, 6 (4.6%)
41/// 2, 1 (0.8%)
42/// 4, 3 (2.3%)
43///
Andrea Di Biagio8af3fe82018-03-08 16:08:43 +000044///
45/// Scheduler's queue usage:
46/// JALU01, 0/20
47/// JFPU01, 18/18
48/// JLSAGU, 0/12
49///
Andrea Di Biagio3a6b0922018-03-08 13:05:02 +000050//===----------------------------------------------------------------------===//
51
52#ifndef LLVM_TOOLS_LLVM_MCA_BACKENDSTATISTICS_H
53#define LLVM_TOOLS_LLVM_MCA_BACKENDSTATISTICS_H
54
Andrea Di Biagio8af3fe82018-03-08 16:08:43 +000055#include "View.h"
Andrea Di Biagio91ab2ee2018-03-19 13:23:07 +000056#include "llvm/ADT/SmallVector.h"
Andrea Di Biagiofbf37cc2018-04-03 15:36:15 +000057#include "llvm/ADT/DenseMap.h"
Andrea Di Biagio09771ad2018-03-16 22:21:52 +000058#include "llvm/MC/MCSubtargetInfo.h"
Andrea Di Biagio3a6b0922018-03-08 13:05:02 +000059
60namespace mca {
61
Andrea Di Biagio8af3fe82018-03-08 16:08:43 +000062class BackendStatistics : public View {
Andrea Di Biagio09771ad2018-03-16 22:21:52 +000063 const llvm::MCSubtargetInfo &STI;
Andrea Di Biagio8af3fe82018-03-08 16:08:43 +000064
Andrea Di Biagiofbf37cc2018-04-03 15:36:15 +000065 using Histogram = llvm::DenseMap<unsigned, unsigned>;
Andrea Di Biagio3a6b0922018-03-08 13:05:02 +000066 Histogram DispatchGroupSizePerCycle;
67 Histogram RetiredPerCycle;
68 Histogram IssuedPerCycle;
69
70 unsigned NumDispatched;
71 unsigned NumIssued;
72 unsigned NumRetired;
73 unsigned NumCycles;
74
Andrea Di Biagio91ab2ee2018-03-19 13:23:07 +000075 // Counts dispatch stall events caused by unavailability of resources. There
76 // is one counter for every generic stall kind (see class HWStallEvent).
77 llvm::SmallVector<unsigned, 8> HWStalls;
78
Andrea Di Biagioa3f2e482018-03-20 18:20:39 +000079 // Tracks the usage of a scheduler's queue.
80 struct BufferUsage {
81 unsigned SlotsInUse;
82 unsigned MaxUsedSlots;
83 };
84
85 // There is a map entry for each buffered resource in the scheduling model.
86 // Every time a buffer is consumed/freed, this view updates the corresponding
87 // entry.
88 llvm::DenseMap<unsigned, BufferUsage> BufferedResources;
89
Andrea Di Biagio3a6b0922018-03-08 13:05:02 +000090 void updateHistograms() {
91 DispatchGroupSizePerCycle[NumDispatched]++;
92 IssuedPerCycle[NumIssued]++;
93 RetiredPerCycle[NumRetired]++;
94 NumDispatched = 0;
95 NumIssued = 0;
96 NumRetired = 0;
97 }
98
99 void printRetireUnitStatistics(llvm::raw_ostream &OS) const;
100 void printDispatchUnitStatistics(llvm::raw_ostream &OS) const;
101 void printSchedulerStatistics(llvm::raw_ostream &OS) const;
102
Andrea Di Biagio91ab2ee2018-03-19 13:23:07 +0000103 void printDispatchStalls(llvm::raw_ostream &OS) const;
Andrea Di Biagio8af3fe82018-03-08 16:08:43 +0000104 void printRCUStatistics(llvm::raw_ostream &OS, const Histogram &Histogram,
105 unsigned Cycles) const;
106 void printDispatchUnitUsage(llvm::raw_ostream &OS, const Histogram &Stats,
107 unsigned Cycles) const;
108 void printIssuePerCycle(const Histogram &IssuePerCycle,
109 unsigned TotalCycles) const;
Andrea Di Biagioa3f2e482018-03-20 18:20:39 +0000110 void printSchedulerUsage(llvm::raw_ostream &OS,
111 const llvm::MCSchedModel &SM) const;
Andrea Di Biagio8af3fe82018-03-08 16:08:43 +0000112
Andrea Di Biagio3a6b0922018-03-08 13:05:02 +0000113public:
Andrea Di Biagio12ef5262018-03-21 18:11:05 +0000114 BackendStatistics(const llvm::MCSubtargetInfo &sti)
Andrea Di Biagio94fafdf2018-03-24 16:05:36 +0000115 : STI(sti), NumDispatched(0), NumIssued(0), NumRetired(0), NumCycles(0),
Andrea Di Biagio8dabf4f2018-04-03 16:46:23 +0000116 HWStalls(HWStallEvent::LastGenericEvent) { }
Andrea Di Biagio3a6b0922018-03-08 13:05:02 +0000117
Clement Courbet844f22d2018-03-13 13:11:01 +0000118 void onInstructionEvent(const HWInstructionEvent &Event) override;
Andrea Di Biagio3a6b0922018-03-08 13:05:02 +0000119
120 void onCycleBegin(unsigned Cycle) override { NumCycles++; }
121
122 void onCycleEnd(unsigned Cycle) override { updateHistograms(); }
123
Andrea Di Biagio91ab2ee2018-03-19 13:23:07 +0000124 void onStallEvent(const HWStallEvent &Event) override {
125 if (Event.Type < HWStallEvent::LastGenericEvent)
126 HWStalls[Event.Type]++;
127 }
128
Andrea Di Biagioa3f2e482018-03-20 18:20:39 +0000129 // Increases the number of used scheduler queue slots of every buffered
130 // resource in the Buffers set.
Andrea Di Biagio04de0b42018-03-20 20:18:36 +0000131 void onReservedBuffers(llvm::ArrayRef<unsigned> Buffers) override;
Andrea Di Biagioa3f2e482018-03-20 18:20:39 +0000132
133 // Decreases by one the number of used scheduler queue slots of every
134 // buffered resource in the Buffers set.
Andrea Di Biagio04de0b42018-03-20 20:18:36 +0000135 void onReleasedBuffers(llvm::ArrayRef<unsigned> Buffers) override;
Andrea Di Biagioa3f2e482018-03-20 18:20:39 +0000136
Andrea Di Biagio8af3fe82018-03-08 16:08:43 +0000137 void printView(llvm::raw_ostream &OS) const override {
Andrea Di Biagio91ab2ee2018-03-19 13:23:07 +0000138 printDispatchStalls(OS);
Andrea Di Biagio3a6b0922018-03-08 13:05:02 +0000139 printDispatchUnitStatistics(OS);
140 printSchedulerStatistics(OS);
141 printRetireUnitStatistics(OS);
Andrea Di Biagioa3f2e482018-03-20 18:20:39 +0000142 printSchedulerUsage(OS, STI.getSchedModel());
Andrea Di Biagio3a6b0922018-03-08 13:05:02 +0000143 }
144};
Andrea Di Biagio3a6b0922018-03-08 13:05:02 +0000145} // namespace mca
146
147#endif