Andrea Di Biagio | 3a6b092 | 2018-03-08 13:05:02 +0000 | [diff] [blame] | 1 | //===--------------------- BackendStatistics.h ------------------*- C++ -*-===// |
| 2 | // |
| 3 | // The LLVM Compiler Infrastructure |
| 4 | // |
| 5 | // This file is distributed under the University of Illinois Open Source |
| 6 | // License. See LICENSE.TXT for details. |
| 7 | // |
| 8 | //===----------------------------------------------------------------------===// |
| 9 | /// \file |
| 10 | /// |
| 11 | /// This file implements a printer class for printing generic Backend |
| 12 | /// statistics related to the dispatch logic, scheduler and retire unit. |
| 13 | /// |
| 14 | /// Example: |
| 15 | /// ======== |
| 16 | /// |
Andrea Di Biagio | 8af3fe8 | 2018-03-08 16:08:43 +0000 | [diff] [blame] | 17 | /// Dynamic Dispatch Stall Cycles: |
| 18 | /// RAT - Register unavailable: 0 |
| 19 | /// RCU - Retire tokens unavailable: 0 |
| 20 | /// SCHEDQ - Scheduler full: 42 |
| 21 | /// LQ - Load queue full: 0 |
| 22 | /// SQ - Store queue full: 0 |
| 23 | /// GROUP - Static restrictions on the dispatch group: 0 |
| 24 | /// |
| 25 | /// |
Andrea Di Biagio | 3a6b092 | 2018-03-08 13:05:02 +0000 | [diff] [blame] | 26 | /// Dispatch Logic - number of cycles where we saw N instructions dispatched: |
| 27 | /// [# dispatched], [# cycles] |
| 28 | /// 0, 15 (11.5%) |
| 29 | /// 5, 4 (3.1%) |
| 30 | /// |
| 31 | /// Schedulers - number of cycles where we saw N instructions issued: |
| 32 | /// [# issued], [# cycles] |
| 33 | /// 0, 7 (5.4%) |
| 34 | /// 1, 4 (3.1%) |
| 35 | /// 2, 8 (6.2%) |
| 36 | /// |
| 37 | /// Retire Control Unit - number of cycles where we saw N instructions retired: |
| 38 | /// [# retired], [# cycles] |
| 39 | /// 0, 9 (6.9%) |
| 40 | /// 1, 6 (4.6%) |
| 41 | /// 2, 1 (0.8%) |
| 42 | /// 4, 3 (2.3%) |
| 43 | /// |
Andrea Di Biagio | 8af3fe8 | 2018-03-08 16:08:43 +0000 | [diff] [blame] | 44 | /// |
| 45 | /// Scheduler's queue usage: |
| 46 | /// JALU01, 0/20 |
| 47 | /// JFPU01, 18/18 |
| 48 | /// JLSAGU, 0/12 |
| 49 | /// |
Andrea Di Biagio | 3a6b092 | 2018-03-08 13:05:02 +0000 | [diff] [blame] | 50 | //===----------------------------------------------------------------------===// |
| 51 | |
| 52 | #ifndef LLVM_TOOLS_LLVM_MCA_BACKENDSTATISTICS_H |
| 53 | #define LLVM_TOOLS_LLVM_MCA_BACKENDSTATISTICS_H |
| 54 | |
Andrea Di Biagio | 8af3fe8 | 2018-03-08 16:08:43 +0000 | [diff] [blame] | 55 | #include "View.h" |
Andrea Di Biagio | 91ab2ee | 2018-03-19 13:23:07 +0000 | [diff] [blame] | 56 | #include "llvm/ADT/SmallVector.h" |
Andrea Di Biagio | fbf37cc | 2018-04-03 15:36:15 +0000 | [diff] [blame] | 57 | #include "llvm/ADT/DenseMap.h" |
Andrea Di Biagio | 09771ad | 2018-03-16 22:21:52 +0000 | [diff] [blame] | 58 | #include "llvm/MC/MCSubtargetInfo.h" |
Andrea Di Biagio | 3a6b092 | 2018-03-08 13:05:02 +0000 | [diff] [blame] | 59 | |
| 60 | namespace mca { |
| 61 | |
Andrea Di Biagio | 8af3fe8 | 2018-03-08 16:08:43 +0000 | [diff] [blame] | 62 | class BackendStatistics : public View { |
Andrea Di Biagio | 09771ad | 2018-03-16 22:21:52 +0000 | [diff] [blame] | 63 | const llvm::MCSubtargetInfo &STI; |
Andrea Di Biagio | 8af3fe8 | 2018-03-08 16:08:43 +0000 | [diff] [blame] | 64 | |
Andrea Di Biagio | fbf37cc | 2018-04-03 15:36:15 +0000 | [diff] [blame] | 65 | using Histogram = llvm::DenseMap<unsigned, unsigned>; |
Andrea Di Biagio | 3a6b092 | 2018-03-08 13:05:02 +0000 | [diff] [blame] | 66 | Histogram DispatchGroupSizePerCycle; |
| 67 | Histogram RetiredPerCycle; |
| 68 | Histogram IssuedPerCycle; |
| 69 | |
| 70 | unsigned NumDispatched; |
| 71 | unsigned NumIssued; |
| 72 | unsigned NumRetired; |
| 73 | unsigned NumCycles; |
| 74 | |
Andrea Di Biagio | 91ab2ee | 2018-03-19 13:23:07 +0000 | [diff] [blame] | 75 | // Counts dispatch stall events caused by unavailability of resources. There |
| 76 | // is one counter for every generic stall kind (see class HWStallEvent). |
| 77 | llvm::SmallVector<unsigned, 8> HWStalls; |
| 78 | |
Andrea Di Biagio | a3f2e48 | 2018-03-20 18:20:39 +0000 | [diff] [blame] | 79 | // Tracks the usage of a scheduler's queue. |
| 80 | struct BufferUsage { |
| 81 | unsigned SlotsInUse; |
| 82 | unsigned MaxUsedSlots; |
| 83 | }; |
| 84 | |
| 85 | // There is a map entry for each buffered resource in the scheduling model. |
| 86 | // Every time a buffer is consumed/freed, this view updates the corresponding |
| 87 | // entry. |
| 88 | llvm::DenseMap<unsigned, BufferUsage> BufferedResources; |
| 89 | |
Andrea Di Biagio | 3a6b092 | 2018-03-08 13:05:02 +0000 | [diff] [blame] | 90 | void updateHistograms() { |
| 91 | DispatchGroupSizePerCycle[NumDispatched]++; |
| 92 | IssuedPerCycle[NumIssued]++; |
| 93 | RetiredPerCycle[NumRetired]++; |
| 94 | NumDispatched = 0; |
| 95 | NumIssued = 0; |
| 96 | NumRetired = 0; |
| 97 | } |
| 98 | |
| 99 | void printRetireUnitStatistics(llvm::raw_ostream &OS) const; |
| 100 | void printDispatchUnitStatistics(llvm::raw_ostream &OS) const; |
| 101 | void printSchedulerStatistics(llvm::raw_ostream &OS) const; |
| 102 | |
Andrea Di Biagio | 91ab2ee | 2018-03-19 13:23:07 +0000 | [diff] [blame] | 103 | void printDispatchStalls(llvm::raw_ostream &OS) const; |
Andrea Di Biagio | 8af3fe8 | 2018-03-08 16:08:43 +0000 | [diff] [blame] | 104 | void printRCUStatistics(llvm::raw_ostream &OS, const Histogram &Histogram, |
| 105 | unsigned Cycles) const; |
| 106 | void printDispatchUnitUsage(llvm::raw_ostream &OS, const Histogram &Stats, |
| 107 | unsigned Cycles) const; |
| 108 | void printIssuePerCycle(const Histogram &IssuePerCycle, |
| 109 | unsigned TotalCycles) const; |
Andrea Di Biagio | a3f2e48 | 2018-03-20 18:20:39 +0000 | [diff] [blame] | 110 | void printSchedulerUsage(llvm::raw_ostream &OS, |
| 111 | const llvm::MCSchedModel &SM) const; |
Andrea Di Biagio | 8af3fe8 | 2018-03-08 16:08:43 +0000 | [diff] [blame] | 112 | |
Andrea Di Biagio | 3a6b092 | 2018-03-08 13:05:02 +0000 | [diff] [blame] | 113 | public: |
Andrea Di Biagio | 12ef526 | 2018-03-21 18:11:05 +0000 | [diff] [blame] | 114 | BackendStatistics(const llvm::MCSubtargetInfo &sti) |
Andrea Di Biagio | 94fafdf | 2018-03-24 16:05:36 +0000 | [diff] [blame] | 115 | : STI(sti), NumDispatched(0), NumIssued(0), NumRetired(0), NumCycles(0), |
Andrea Di Biagio | 8dabf4f | 2018-04-03 16:46:23 +0000 | [diff] [blame] | 116 | HWStalls(HWStallEvent::LastGenericEvent) { } |
Andrea Di Biagio | 3a6b092 | 2018-03-08 13:05:02 +0000 | [diff] [blame] | 117 | |
Clement Courbet | 844f22d | 2018-03-13 13:11:01 +0000 | [diff] [blame] | 118 | void onInstructionEvent(const HWInstructionEvent &Event) override; |
Andrea Di Biagio | 3a6b092 | 2018-03-08 13:05:02 +0000 | [diff] [blame] | 119 | |
| 120 | void onCycleBegin(unsigned Cycle) override { NumCycles++; } |
| 121 | |
| 122 | void onCycleEnd(unsigned Cycle) override { updateHistograms(); } |
| 123 | |
Andrea Di Biagio | 91ab2ee | 2018-03-19 13:23:07 +0000 | [diff] [blame] | 124 | void onStallEvent(const HWStallEvent &Event) override { |
| 125 | if (Event.Type < HWStallEvent::LastGenericEvent) |
| 126 | HWStalls[Event.Type]++; |
| 127 | } |
| 128 | |
Andrea Di Biagio | a3f2e48 | 2018-03-20 18:20:39 +0000 | [diff] [blame] | 129 | // Increases the number of used scheduler queue slots of every buffered |
| 130 | // resource in the Buffers set. |
Andrea Di Biagio | 04de0b4 | 2018-03-20 20:18:36 +0000 | [diff] [blame] | 131 | void onReservedBuffers(llvm::ArrayRef<unsigned> Buffers) override; |
Andrea Di Biagio | a3f2e48 | 2018-03-20 18:20:39 +0000 | [diff] [blame] | 132 | |
| 133 | // Decreases by one the number of used scheduler queue slots of every |
| 134 | // buffered resource in the Buffers set. |
Andrea Di Biagio | 04de0b4 | 2018-03-20 20:18:36 +0000 | [diff] [blame] | 135 | void onReleasedBuffers(llvm::ArrayRef<unsigned> Buffers) override; |
Andrea Di Biagio | a3f2e48 | 2018-03-20 18:20:39 +0000 | [diff] [blame] | 136 | |
Andrea Di Biagio | 8af3fe8 | 2018-03-08 16:08:43 +0000 | [diff] [blame] | 137 | void printView(llvm::raw_ostream &OS) const override { |
Andrea Di Biagio | 91ab2ee | 2018-03-19 13:23:07 +0000 | [diff] [blame] | 138 | printDispatchStalls(OS); |
Andrea Di Biagio | 3a6b092 | 2018-03-08 13:05:02 +0000 | [diff] [blame] | 139 | printDispatchUnitStatistics(OS); |
| 140 | printSchedulerStatistics(OS); |
| 141 | printRetireUnitStatistics(OS); |
Andrea Di Biagio | a3f2e48 | 2018-03-20 18:20:39 +0000 | [diff] [blame] | 142 | printSchedulerUsage(OS, STI.getSchedModel()); |
Andrea Di Biagio | 3a6b092 | 2018-03-08 13:05:02 +0000 | [diff] [blame] | 143 | } |
| 144 | }; |
Andrea Di Biagio | 3a6b092 | 2018-03-08 13:05:02 +0000 | [diff] [blame] | 145 | } // namespace mca |
| 146 | |
| 147 | #endif |