Tom Stellard | 45bb48e | 2015-06-13 03:28:10 +0000 | [diff] [blame] | 1 | set(LLVM_TARGET_DEFINITIONS AMDGPU.td) |
| 2 | |
| 3 | tablegen(LLVM AMDGPUGenRegisterInfo.inc -gen-register-info) |
| 4 | tablegen(LLVM AMDGPUGenInstrInfo.inc -gen-instr-info) |
| 5 | tablegen(LLVM AMDGPUGenDAGISel.inc -gen-dag-isel) |
| 6 | tablegen(LLVM AMDGPUGenCallingConv.inc -gen-callingconv) |
| 7 | tablegen(LLVM AMDGPUGenSubtargetInfo.inc -gen-subtarget) |
| 8 | tablegen(LLVM AMDGPUGenIntrinsics.inc -gen-tgt-intrinsic) |
| 9 | tablegen(LLVM AMDGPUGenMCCodeEmitter.inc -gen-emitter) |
| 10 | tablegen(LLVM AMDGPUGenDFAPacketizer.inc -gen-dfa-packetizer) |
| 11 | tablegen(LLVM AMDGPUGenAsmWriter.inc -gen-asm-writer) |
| 12 | tablegen(LLVM AMDGPUGenAsmMatcher.inc -gen-asm-matcher) |
Tom Stellard | e1818af | 2016-02-18 03:42:32 +0000 | [diff] [blame] | 13 | tablegen(LLVM AMDGPUGenDisassemblerTables.inc -gen-disassembler) |
Matt Arsenault | 11f7402 | 2016-10-06 17:19:11 +0000 | [diff] [blame] | 14 | tablegen(LLVM AMDGPUGenMCPseudoLowering.inc -gen-pseudo-lowering) |
Tom Stellard | 45bb48e | 2015-06-13 03:28:10 +0000 | [diff] [blame] | 15 | add_public_tablegen_target(AMDGPUCommonTableGen) |
| 16 | |
Tom Stellard | 000c5af | 2016-04-14 19:09:28 +0000 | [diff] [blame] | 17 | # List of all GlobalISel files. |
| 18 | set(GLOBAL_ISEL_FILES |
| 19 | AMDGPUCallLowering.cpp |
| 20 | ) |
| 21 | |
| 22 | # Add GlobalISel files to the dependencies if the user wants to build it. |
| 23 | if(LLVM_BUILD_GLOBAL_ISEL) |
| 24 | set(GLOBAL_ISEL_BUILD_FILES ${GLOBAL_ISEL_FILES}) |
| 25 | else() |
| 26 | set(GLOBAL_ISEL_BUILD_FILES"") |
| 27 | set(LLVM_OPTIONAL_SOURCES LLVMGlobalISel ${GLOBAL_ISEL_FILES}) |
| 28 | endif() |
| 29 | |
| 30 | |
Tom Stellard | 45bb48e | 2015-06-13 03:28:10 +0000 | [diff] [blame] | 31 | add_llvm_target(AMDGPUCodeGen |
| 32 | AMDILCFGStructurizer.cpp |
| 33 | AMDGPUAlwaysInlinePass.cpp |
Matt Arsenault | 3931948 | 2015-11-06 18:01:57 +0000 | [diff] [blame] | 34 | AMDGPUAnnotateKernelFeatures.cpp |
Tom Stellard | a6f24c6 | 2015-12-15 20:55:55 +0000 | [diff] [blame] | 35 | AMDGPUAnnotateUniformValues.cpp |
Tom Stellard | 45bb48e | 2015-06-13 03:28:10 +0000 | [diff] [blame] | 36 | AMDGPUAsmPrinter.cpp |
Matt Arsenault | 86de486 | 2016-06-24 07:07:55 +0000 | [diff] [blame] | 37 | AMDGPUCodeGenPrepare.cpp |
Tom Stellard | 45bb48e | 2015-06-13 03:28:10 +0000 | [diff] [blame] | 38 | AMDGPUFrameLowering.cpp |
Tom Stellard | c93fc11 | 2015-12-10 02:13:01 +0000 | [diff] [blame] | 39 | AMDGPUTargetObjectFile.cpp |
Tom Stellard | 45bb48e | 2015-06-13 03:28:10 +0000 | [diff] [blame] | 40 | AMDGPUIntrinsicInfo.cpp |
| 41 | AMDGPUISelDAGToDAG.cpp |
| 42 | AMDGPUMCInstLower.cpp |
| 43 | AMDGPUMachineFunction.cpp |
Stanislav Mekhanoshin | 50ea93a | 2016-12-08 19:46:04 +0000 | [diff] [blame] | 44 | AMDGPUUnifyMetadata.cpp |
Tom Stellard | fd25395 | 2015-08-07 23:19:30 +0000 | [diff] [blame] | 45 | AMDGPUOpenCLImageTypeLoweringPass.cpp |
Tom Stellard | 45bb48e | 2015-06-13 03:28:10 +0000 | [diff] [blame] | 46 | AMDGPUSubtarget.cpp |
| 47 | AMDGPUTargetMachine.cpp |
| 48 | AMDGPUTargetTransformInfo.cpp |
| 49 | AMDGPUISelLowering.cpp |
| 50 | AMDGPUInstrInfo.cpp |
| 51 | AMDGPUPromoteAlloca.cpp |
| 52 | AMDGPURegisterInfo.cpp |
Tom Stellard | cb6ba62 | 2016-04-30 00:23:06 +0000 | [diff] [blame] | 53 | GCNHazardRecognizer.cpp |
Tom Stellard | 0d23ebe | 2016-08-29 19:42:52 +0000 | [diff] [blame] | 54 | GCNSchedStrategy.cpp |
Tom Stellard | 45bb48e | 2015-06-13 03:28:10 +0000 | [diff] [blame] | 55 | R600ClauseMergePass.cpp |
| 56 | R600ControlFlowFinalizer.cpp |
| 57 | R600EmitClauseMarkers.cpp |
| 58 | R600ExpandSpecialInstrs.cpp |
Matt Arsenault | 43e92fe | 2016-06-24 06:30:11 +0000 | [diff] [blame] | 59 | R600FrameLowering.cpp |
Tom Stellard | 45bb48e | 2015-06-13 03:28:10 +0000 | [diff] [blame] | 60 | R600InstrInfo.cpp |
| 61 | R600ISelLowering.cpp |
| 62 | R600MachineFunctionInfo.cpp |
| 63 | R600MachineScheduler.cpp |
| 64 | R600OptimizeVectorRegisters.cpp |
| 65 | R600Packetizer.cpp |
| 66 | R600RegisterInfo.cpp |
Tom Stellard | 45bb48e | 2015-06-13 03:28:10 +0000 | [diff] [blame] | 67 | SIAnnotateControlFlow.cpp |
Konstantin Zhuravlyov | a791932 | 2016-05-10 18:33:41 +0000 | [diff] [blame] | 68 | SIDebuggerInsertNops.cpp |
Tom Stellard | 45bb48e | 2015-06-13 03:28:10 +0000 | [diff] [blame] | 69 | SIFixControlFlowLiveIntervals.cpp |
| 70 | SIFixSGPRCopies.cpp |
Tom Stellard | 45bb48e | 2015-06-13 03:28:10 +0000 | [diff] [blame] | 71 | SIFoldOperands.cpp |
Matt Arsenault | 0c90e95 | 2015-11-06 18:17:45 +0000 | [diff] [blame] | 72 | SIFrameLowering.cpp |
Matt Arsenault | 78fc9da | 2016-08-22 19:33:16 +0000 | [diff] [blame] | 73 | SIInsertSkips.cpp |
Tom Stellard | 45bb48e | 2015-06-13 03:28:10 +0000 | [diff] [blame] | 74 | SIInsertWaits.cpp |
| 75 | SIInstrInfo.cpp |
| 76 | SIISelLowering.cpp |
| 77 | SILoadStoreOptimizer.cpp |
| 78 | SILowerControlFlow.cpp |
| 79 | SILowerI1Copies.cpp |
| 80 | SIMachineFunctionInfo.cpp |
Nicolai Haehnle | 02c3291 | 2016-01-13 16:10:10 +0000 | [diff] [blame] | 81 | SIMachineScheduler.cpp |
Matt Arsenault | e674075 | 2016-09-29 01:44:16 +0000 | [diff] [blame] | 82 | SIOptimizeExecMasking.cpp |
Tom Stellard | 45bb48e | 2015-06-13 03:28:10 +0000 | [diff] [blame] | 83 | SIRegisterInfo.cpp |
| 84 | SIShrinkInstructions.cpp |
| 85 | SITypeRewriter.cpp |
Nicolai Haehnle | 213e87f | 2016-03-21 20:28:33 +0000 | [diff] [blame] | 86 | SIWholeQuadMode.cpp |
Tom Stellard | 000c5af | 2016-04-14 19:09:28 +0000 | [diff] [blame] | 87 | ${GLOBAL_ISEL_BUILD_FILES} |
Tom Stellard | 45bb48e | 2015-06-13 03:28:10 +0000 | [diff] [blame] | 88 | ) |
| 89 | |
| 90 | add_subdirectory(AsmParser) |
| 91 | add_subdirectory(InstPrinter) |
Tom Stellard | e1818af | 2016-02-18 03:42:32 +0000 | [diff] [blame] | 92 | add_subdirectory(Disassembler) |
Tom Stellard | 45bb48e | 2015-06-13 03:28:10 +0000 | [diff] [blame] | 93 | add_subdirectory(TargetInfo) |
| 94 | add_subdirectory(MCTargetDesc) |
Tom Stellard | 347ac79 | 2015-06-26 21:15:07 +0000 | [diff] [blame] | 95 | add_subdirectory(Utils) |