blob: 58b87e12912cfc7ec8b241772ccc9689b8fb7ec2 [file] [log] [blame]
Jim Grosbacheb431da2010-01-06 16:48:02 +00001//===----- AggressiveAntiDepBreaker.cpp - Anti-dep breaker ----------------===//
David Goodwinde11f362009-10-26 19:32:42 +00002//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file implements the AggressiveAntiDepBreaker class, which
11// implements register anti-dependence breaking during post-RA
12// scheduling. It attempts to break all anti-dependencies within a
13// block.
14//
15//===----------------------------------------------------------------------===//
16
David Goodwinde11f362009-10-26 19:32:42 +000017#include "AggressiveAntiDepBreaker.h"
18#include "llvm/CodeGen/MachineBasicBlock.h"
19#include "llvm/CodeGen/MachineFrameInfo.h"
20#include "llvm/CodeGen/MachineInstr.h"
Andrew Trick05ff4662012-06-06 20:29:31 +000021#include "llvm/CodeGen/RegisterClassInfo.h"
David Goodwine056d102009-10-26 22:31:16 +000022#include "llvm/Support/CommandLine.h"
David Goodwinde11f362009-10-26 19:32:42 +000023#include "llvm/Support/Debug.h"
24#include "llvm/Support/ErrorHandling.h"
25#include "llvm/Support/raw_ostream.h"
Chandler Carruthed0881b2012-12-03 16:50:05 +000026#include "llvm/Target/TargetInstrInfo.h"
Chandler Carruthed0881b2012-12-03 16:50:05 +000027#include "llvm/Target/TargetRegisterInfo.h"
David Goodwinde11f362009-10-26 19:32:42 +000028using namespace llvm;
29
Chandler Carruth1b9dde02014-04-22 02:02:50 +000030#define DEBUG_TYPE "post-RA-sched"
31
David Goodwindd1c6192009-11-19 23:12:37 +000032// If DebugDiv > 0 then only break antidep with (ID % DebugDiv) == DebugMod
33static cl::opt<int>
34DebugDiv("agg-antidep-debugdiv",
Bob Wilson67dd3a42010-04-09 21:38:26 +000035 cl::desc("Debug control for aggressive anti-dep breaker"),
36 cl::init(0), cl::Hidden);
David Goodwindd1c6192009-11-19 23:12:37 +000037static cl::opt<int>
38DebugMod("agg-antidep-debugmod",
Bob Wilson67dd3a42010-04-09 21:38:26 +000039 cl::desc("Debug control for aggressive anti-dep breaker"),
40 cl::init(0), cl::Hidden);
David Goodwindd1c6192009-11-19 23:12:37 +000041
David Goodwina45fe672009-12-09 17:18:22 +000042AggressiveAntiDepState::AggressiveAntiDepState(const unsigned TargetRegs,
43 MachineBasicBlock *BB) :
Bill Wendling51a9c0a2010-07-15 19:58:14 +000044 NumTargetRegs(TargetRegs), GroupNodes(TargetRegs, 0),
45 GroupNodeIndices(TargetRegs, 0),
46 KillIndices(TargetRegs, 0),
47 DefIndices(TargetRegs, 0)
48{
David Goodwina45fe672009-12-09 17:18:22 +000049 const unsigned BBSize = BB->size();
50 for (unsigned i = 0; i < NumTargetRegs; ++i) {
51 // Initialize all registers to be in their own group. Initially we
52 // assign the register to the same-indexed GroupNode.
53 GroupNodeIndices[i] = i;
54 // Initialize the indices to indicate that no registers are live.
55 KillIndices[i] = ~0u;
56 DefIndices[i] = BBSize;
57 }
David Goodwinde11f362009-10-26 19:32:42 +000058}
59
Bill Wendling5a8d15c2010-07-15 19:41:20 +000060unsigned AggressiveAntiDepState::GetGroup(unsigned Reg) {
David Goodwinde11f362009-10-26 19:32:42 +000061 unsigned Node = GroupNodeIndices[Reg];
62 while (GroupNodes[Node] != Node)
63 Node = GroupNodes[Node];
64
65 return Node;
66}
67
David Goodwinb9fe5d52009-11-13 19:52:48 +000068void AggressiveAntiDepState::GetGroupRegs(
69 unsigned Group,
70 std::vector<unsigned> &Regs,
71 std::multimap<unsigned, AggressiveAntiDepState::RegisterReference> *RegRefs)
David Goodwinde11f362009-10-26 19:32:42 +000072{
David Goodwina45fe672009-12-09 17:18:22 +000073 for (unsigned Reg = 0; Reg != NumTargetRegs; ++Reg) {
David Goodwinb9fe5d52009-11-13 19:52:48 +000074 if ((GetGroup(Reg) == Group) && (RegRefs->count(Reg) > 0))
David Goodwinde11f362009-10-26 19:32:42 +000075 Regs.push_back(Reg);
76 }
77}
78
David Goodwine056d102009-10-26 22:31:16 +000079unsigned AggressiveAntiDepState::UnionGroups(unsigned Reg1, unsigned Reg2)
David Goodwinde11f362009-10-26 19:32:42 +000080{
81 assert(GroupNodes[0] == 0 && "GroupNode 0 not parent!");
82 assert(GroupNodeIndices[0] == 0 && "Reg 0 not in Group 0!");
Jim Grosbacheb431da2010-01-06 16:48:02 +000083
David Goodwinde11f362009-10-26 19:32:42 +000084 // find group for each register
85 unsigned Group1 = GetGroup(Reg1);
86 unsigned Group2 = GetGroup(Reg2);
Jim Grosbacheb431da2010-01-06 16:48:02 +000087
David Goodwinde11f362009-10-26 19:32:42 +000088 // if either group is 0, then that must become the parent
89 unsigned Parent = (Group1 == 0) ? Group1 : Group2;
90 unsigned Other = (Parent == Group1) ? Group2 : Group1;
91 GroupNodes.at(Other) = Parent;
92 return Parent;
93}
Jim Grosbacheb431da2010-01-06 16:48:02 +000094
David Goodwine056d102009-10-26 22:31:16 +000095unsigned AggressiveAntiDepState::LeaveGroup(unsigned Reg)
David Goodwinde11f362009-10-26 19:32:42 +000096{
97 // Create a new GroupNode for Reg. Reg's existing GroupNode must
98 // stay as is because there could be other GroupNodes referring to
99 // it.
100 unsigned idx = GroupNodes.size();
101 GroupNodes.push_back(idx);
102 GroupNodeIndices[Reg] = idx;
103 return idx;
104}
105
David Goodwine056d102009-10-26 22:31:16 +0000106bool AggressiveAntiDepState::IsLive(unsigned Reg)
David Goodwinde11f362009-10-26 19:32:42 +0000107{
108 // KillIndex must be defined and DefIndex not defined for a register
109 // to be live.
110 return((KillIndices[Reg] != ~0u) && (DefIndices[Reg] == ~0u));
111}
112
Eric Christopherd9134482014-08-04 21:25:23 +0000113AggressiveAntiDepBreaker::AggressiveAntiDepBreaker(
114 MachineFunction &MFi, const RegisterClassInfo &RCI,
115 TargetSubtargetInfo::RegClassVector &CriticalPathRCs)
116 : AntiDepBreaker(), MF(MFi), MRI(MF.getRegInfo()),
Eric Christopherfc6de422014-08-05 02:39:49 +0000117 TII(MF.getSubtarget().getInstrInfo()),
118 TRI(MF.getSubtarget().getRegisterInfo()), RegClassInfo(RCI),
119 State(nullptr) {
David Goodwinb9fe5d52009-11-13 19:52:48 +0000120 /* Collect a bitset of all registers that are only broken if they
121 are on the critical path. */
122 for (unsigned i = 0, e = CriticalPathRCs.size(); i < e; ++i) {
123 BitVector CPSet = TRI->getAllocatableSet(MF, CriticalPathRCs[i]);
124 if (CriticalPathSet.none())
125 CriticalPathSet = CPSet;
126 else
127 CriticalPathSet |= CPSet;
128 }
Jim Grosbacheb431da2010-01-06 16:48:02 +0000129
David Greene75a2efb2009-12-24 00:14:25 +0000130 DEBUG(dbgs() << "AntiDep Critical-Path Registers:");
Jim Grosbacheb431da2010-01-06 16:48:02 +0000131 DEBUG(for (int r = CriticalPathSet.find_first(); r != -1;
David Goodwinb9fe5d52009-11-13 19:52:48 +0000132 r = CriticalPathSet.find_next(r))
David Greene75a2efb2009-12-24 00:14:25 +0000133 dbgs() << " " << TRI->getName(r));
134 DEBUG(dbgs() << '\n');
David Goodwine056d102009-10-26 22:31:16 +0000135}
136
137AggressiveAntiDepBreaker::~AggressiveAntiDepBreaker() {
138 delete State;
David Goodwine056d102009-10-26 22:31:16 +0000139}
140
141void AggressiveAntiDepBreaker::StartBlock(MachineBasicBlock *BB) {
Craig Topperc0196b12014-04-14 00:51:57 +0000142 assert(!State);
David Goodwina45fe672009-12-09 17:18:22 +0000143 State = new AggressiveAntiDepState(TRI->getNumRegs(), BB);
David Goodwine056d102009-10-26 22:31:16 +0000144
Evan Cheng7f8e5632011-12-07 07:15:52 +0000145 bool IsReturnBlock = (!BB->empty() && BB->back().isReturn());
Bill Wendling030b0282010-07-15 18:43:09 +0000146 std::vector<unsigned> &KillIndices = State->GetKillIndices();
147 std::vector<unsigned> &DefIndices = State->GetDefIndices();
David Goodwine056d102009-10-26 22:31:16 +0000148
Jakob Stoklund Olesenc3386792013-02-05 18:21:52 +0000149 // Examine the live-in regs of all successors.
Evan Chengf128bdc2010-06-16 07:35:02 +0000150 for (MachineBasicBlock::succ_iterator SI = BB->succ_begin(),
151 SE = BB->succ_end(); SI != SE; ++SI)
152 for (MachineBasicBlock::livein_iterator I = (*SI)->livein_begin(),
153 E = (*SI)->livein_end(); I != E; ++I) {
Jakob Stoklund Olesen54038d72012-06-01 23:28:30 +0000154 for (MCRegAliasIterator AI(*I, TRI, true); AI.isValid(); ++AI) {
155 unsigned Reg = *AI;
Jakob Stoklund Olesenbe1c8d32010-12-14 23:23:15 +0000156 State->UnionGroups(Reg, 0);
157 KillIndices[Reg] = BB->size();
158 DefIndices[Reg] = ~0u;
Evan Chengf128bdc2010-06-16 07:35:02 +0000159 }
160 }
161
David Goodwine056d102009-10-26 22:31:16 +0000162 // Mark live-out callee-saved registers. In a return block this is
163 // all callee-saved registers. In non-return this is any
164 // callee-saved register that is not saved in the prolog.
165 const MachineFrameInfo *MFI = MF.getFrameInfo();
166 BitVector Pristine = MFI->getPristineRegs(BB);
Craig Topper840beec2014-04-04 05:16:06 +0000167 for (const MCPhysReg *I = TRI->getCalleeSavedRegs(&MF); *I; ++I) {
David Goodwine056d102009-10-26 22:31:16 +0000168 unsigned Reg = *I;
169 if (!IsReturnBlock && !Pristine.test(Reg)) continue;
Jakob Stoklund Olesen54038d72012-06-01 23:28:30 +0000170 for (MCRegAliasIterator AI(Reg, TRI, true); AI.isValid(); ++AI) {
171 unsigned AliasReg = *AI;
David Goodwine056d102009-10-26 22:31:16 +0000172 State->UnionGroups(AliasReg, 0);
173 KillIndices[AliasReg] = BB->size();
174 DefIndices[AliasReg] = ~0u;
175 }
176 }
177}
178
179void AggressiveAntiDepBreaker::FinishBlock() {
180 delete State;
Craig Topperc0196b12014-04-14 00:51:57 +0000181 State = nullptr;
David Goodwine056d102009-10-26 22:31:16 +0000182}
183
184void AggressiveAntiDepBreaker::Observe(MachineInstr *MI, unsigned Count,
Bob Wilson67dd3a42010-04-09 21:38:26 +0000185 unsigned InsertPosIndex) {
David Goodwine056d102009-10-26 22:31:16 +0000186 assert(Count < InsertPosIndex && "Instruction index out of expected range!");
187
David Goodwinfaa76602009-10-29 23:30:59 +0000188 std::set<unsigned> PassthruRegs;
189 GetPassthruRegs(MI, PassthruRegs);
190 PrescanInstruction(MI, Count, PassthruRegs);
191 ScanInstruction(MI, Count);
192
David Greene75a2efb2009-12-24 00:14:25 +0000193 DEBUG(dbgs() << "Observe: ");
David Goodwine056d102009-10-26 22:31:16 +0000194 DEBUG(MI->dump());
David Greene75a2efb2009-12-24 00:14:25 +0000195 DEBUG(dbgs() << "\tRegs:");
David Goodwine056d102009-10-26 22:31:16 +0000196
Bill Wendling030b0282010-07-15 18:43:09 +0000197 std::vector<unsigned> &DefIndices = State->GetDefIndices();
David Goodwina45fe672009-12-09 17:18:22 +0000198 for (unsigned Reg = 0; Reg != TRI->getNumRegs(); ++Reg) {
David Goodwine056d102009-10-26 22:31:16 +0000199 // If Reg is current live, then mark that it can't be renamed as
200 // we don't know the extent of its live-range anymore (now that it
201 // has been scheduled). If it is not live but was defined in the
202 // previous schedule region, then set its def index to the most
203 // conservative location (i.e. the beginning of the previous
204 // schedule region).
205 if (State->IsLive(Reg)) {
206 DEBUG(if (State->GetGroup(Reg) != 0)
Jim Grosbacheb431da2010-01-06 16:48:02 +0000207 dbgs() << " " << TRI->getName(Reg) << "=g" <<
David Goodwine056d102009-10-26 22:31:16 +0000208 State->GetGroup(Reg) << "->g0(region live-out)");
209 State->UnionGroups(Reg, 0);
Jim Grosbacheb431da2010-01-06 16:48:02 +0000210 } else if ((DefIndices[Reg] < InsertPosIndex)
211 && (DefIndices[Reg] >= Count)) {
David Goodwine056d102009-10-26 22:31:16 +0000212 DefIndices[Reg] = Count;
213 }
214 }
David Greene75a2efb2009-12-24 00:14:25 +0000215 DEBUG(dbgs() << '\n');
David Goodwine056d102009-10-26 22:31:16 +0000216}
217
David Goodwinde11f362009-10-26 19:32:42 +0000218bool AggressiveAntiDepBreaker::IsImplicitDefUse(MachineInstr *MI,
Bob Wilson67dd3a42010-04-09 21:38:26 +0000219 MachineOperand& MO)
David Goodwinde11f362009-10-26 19:32:42 +0000220{
221 if (!MO.isReg() || !MO.isImplicit())
222 return false;
223
224 unsigned Reg = MO.getReg();
225 if (Reg == 0)
226 return false;
227
Craig Topperc0196b12014-04-14 00:51:57 +0000228 MachineOperand *Op = nullptr;
David Goodwinde11f362009-10-26 19:32:42 +0000229 if (MO.isDef())
230 Op = MI->findRegisterUseOperand(Reg, true);
231 else
232 Op = MI->findRegisterDefOperand(Reg);
233
Craig Topperc0196b12014-04-14 00:51:57 +0000234 return(Op && Op->isImplicit());
David Goodwinde11f362009-10-26 19:32:42 +0000235}
236
237void AggressiveAntiDepBreaker::GetPassthruRegs(MachineInstr *MI,
238 std::set<unsigned>& PassthruRegs) {
239 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
240 MachineOperand &MO = MI->getOperand(i);
241 if (!MO.isReg()) continue;
Jim Grosbacheb431da2010-01-06 16:48:02 +0000242 if ((MO.isDef() && MI->isRegTiedToUseOperand(i)) ||
David Goodwinde11f362009-10-26 19:32:42 +0000243 IsImplicitDefUse(MI, MO)) {
244 const unsigned Reg = MO.getReg();
Chad Rosierabdb1d62013-05-22 23:17:36 +0000245 for (MCSubRegIterator SubRegs(Reg, TRI, /*IncludeSelf=*/true);
246 SubRegs.isValid(); ++SubRegs)
Jakob Stoklund Olesen54038d72012-06-01 23:28:30 +0000247 PassthruRegs.insert(*SubRegs);
David Goodwinde11f362009-10-26 19:32:42 +0000248 }
249 }
250}
251
David Goodwin80a03cc2009-11-20 19:32:48 +0000252/// AntiDepEdges - Return in Edges the anti- and output- dependencies
253/// in SU that we want to consider for breaking.
Dan Gohman35bc4d42010-04-19 23:11:58 +0000254static void AntiDepEdges(const SUnit *SU, std::vector<const SDep*>& Edges) {
David Goodwin80a03cc2009-11-20 19:32:48 +0000255 SmallSet<unsigned, 4> RegSet;
Dan Gohman35bc4d42010-04-19 23:11:58 +0000256 for (SUnit::const_pred_iterator P = SU->Preds.begin(), PE = SU->Preds.end();
David Goodwinde11f362009-10-26 19:32:42 +0000257 P != PE; ++P) {
David Goodwinda83f7d2009-11-12 19:08:21 +0000258 if ((P->getKind() == SDep::Anti) || (P->getKind() == SDep::Output)) {
David Blaikie70573dc2014-11-19 07:49:26 +0000259 if (RegSet.insert(P->getReg()).second)
David Goodwinde11f362009-10-26 19:32:42 +0000260 Edges.push_back(&*P);
David Goodwinde11f362009-10-26 19:32:42 +0000261 }
262 }
263}
264
David Goodwinb9fe5d52009-11-13 19:52:48 +0000265/// CriticalPathStep - Return the next SUnit after SU on the bottom-up
266/// critical path.
Dan Gohman35bc4d42010-04-19 23:11:58 +0000267static const SUnit *CriticalPathStep(const SUnit *SU) {
Craig Topperc0196b12014-04-14 00:51:57 +0000268 const SDep *Next = nullptr;
David Goodwinb9fe5d52009-11-13 19:52:48 +0000269 unsigned NextDepth = 0;
270 // Find the predecessor edge with the greatest depth.
Craig Topperc0196b12014-04-14 00:51:57 +0000271 if (SU) {
Dan Gohman35bc4d42010-04-19 23:11:58 +0000272 for (SUnit::const_pred_iterator P = SU->Preds.begin(), PE = SU->Preds.end();
David Goodwinb9fe5d52009-11-13 19:52:48 +0000273 P != PE; ++P) {
Dan Gohman35bc4d42010-04-19 23:11:58 +0000274 const SUnit *PredSU = P->getSUnit();
David Goodwinb9fe5d52009-11-13 19:52:48 +0000275 unsigned PredLatency = P->getLatency();
276 unsigned PredTotalLatency = PredSU->getDepth() + PredLatency;
277 // In the case of a latency tie, prefer an anti-dependency edge over
278 // other types of edges.
279 if (NextDepth < PredTotalLatency ||
280 (NextDepth == PredTotalLatency && P->getKind() == SDep::Anti)) {
281 NextDepth = PredTotalLatency;
282 Next = &*P;
283 }
284 }
285 }
286
Craig Topperc0196b12014-04-14 00:51:57 +0000287 return (Next) ? Next->getSUnit() : nullptr;
David Goodwinb9fe5d52009-11-13 19:52:48 +0000288}
289
David Goodwin9f1b2d42009-10-29 19:17:04 +0000290void AggressiveAntiDepBreaker::HandleLastUse(unsigned Reg, unsigned KillIdx,
Jim Grosbacheb431da2010-01-06 16:48:02 +0000291 const char *tag,
292 const char *header,
David Goodwindd1c6192009-11-19 23:12:37 +0000293 const char *footer) {
Bill Wendling030b0282010-07-15 18:43:09 +0000294 std::vector<unsigned> &KillIndices = State->GetKillIndices();
295 std::vector<unsigned> &DefIndices = State->GetDefIndices();
Jim Grosbacheb431da2010-01-06 16:48:02 +0000296 std::multimap<unsigned, AggressiveAntiDepState::RegisterReference>&
David Goodwin9f1b2d42009-10-29 19:17:04 +0000297 RegRefs = State->GetRegRefs();
298
Hal Finkel34c94d52015-01-28 14:44:14 +0000299 // FIXME: We must leave subregisters of live super registers as live, so that
300 // we don't clear out the register tracking information for subregisters of
301 // super registers we're still tracking (and with which we're unioning
302 // subregister definitions).
303 for (MCRegAliasIterator AI(Reg, TRI, true); AI.isValid(); ++AI)
304 if (TRI->isSuperRegister(Reg, *AI) && State->IsLive(*AI)) {
305 DEBUG(if (!header && footer) dbgs() << footer);
306 return;
307 }
308
David Goodwin9f1b2d42009-10-29 19:17:04 +0000309 if (!State->IsLive(Reg)) {
310 KillIndices[Reg] = KillIdx;
311 DefIndices[Reg] = ~0u;
312 RegRefs.erase(Reg);
313 State->LeaveGroup(Reg);
Craig Topperc0196b12014-04-14 00:51:57 +0000314 DEBUG(if (header) {
315 dbgs() << header << TRI->getName(Reg); header = nullptr; });
David Greene75a2efb2009-12-24 00:14:25 +0000316 DEBUG(dbgs() << "->g" << State->GetGroup(Reg) << tag);
David Goodwin9f1b2d42009-10-29 19:17:04 +0000317 }
318 // Repeat for subregisters.
Jakob Stoklund Olesen54038d72012-06-01 23:28:30 +0000319 for (MCSubRegIterator SubRegs(Reg, TRI); SubRegs.isValid(); ++SubRegs) {
320 unsigned SubregReg = *SubRegs;
David Goodwin9f1b2d42009-10-29 19:17:04 +0000321 if (!State->IsLive(SubregReg)) {
322 KillIndices[SubregReg] = KillIdx;
323 DefIndices[SubregReg] = ~0u;
324 RegRefs.erase(SubregReg);
325 State->LeaveGroup(SubregReg);
Craig Topperc0196b12014-04-14 00:51:57 +0000326 DEBUG(if (header) {
327 dbgs() << header << TRI->getName(Reg); header = nullptr; });
David Greene75a2efb2009-12-24 00:14:25 +0000328 DEBUG(dbgs() << " " << TRI->getName(SubregReg) << "->g" <<
David Goodwin9f1b2d42009-10-29 19:17:04 +0000329 State->GetGroup(SubregReg) << tag);
330 }
331 }
David Goodwindd1c6192009-11-19 23:12:37 +0000332
Craig Topperc0196b12014-04-14 00:51:57 +0000333 DEBUG(if (!header && footer) dbgs() << footer);
David Goodwin9f1b2d42009-10-29 19:17:04 +0000334}
335
Jim Grosbacheb431da2010-01-06 16:48:02 +0000336void AggressiveAntiDepBreaker::PrescanInstruction(MachineInstr *MI,
337 unsigned Count,
Bob Wilson67dd3a42010-04-09 21:38:26 +0000338 std::set<unsigned>& PassthruRegs) {
Bill Wendling030b0282010-07-15 18:43:09 +0000339 std::vector<unsigned> &DefIndices = State->GetDefIndices();
Jim Grosbacheb431da2010-01-06 16:48:02 +0000340 std::multimap<unsigned, AggressiveAntiDepState::RegisterReference>&
David Goodwine056d102009-10-26 22:31:16 +0000341 RegRefs = State->GetRegRefs();
342
David Goodwin9f1b2d42009-10-29 19:17:04 +0000343 // Handle dead defs by simulating a last-use of the register just
Chris Lattner0ab5e2c2011-04-15 05:18:47 +0000344 // after the def. A dead def can occur because the def is truly
David Goodwin9f1b2d42009-10-29 19:17:04 +0000345 // dead, or because only a subregister is live at the def. If we
346 // don't do this the dead def will be incorrectly merged into the
347 // previous def.
David Goodwinde11f362009-10-26 19:32:42 +0000348 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
349 MachineOperand &MO = MI->getOperand(i);
350 if (!MO.isReg() || !MO.isDef()) continue;
351 unsigned Reg = MO.getReg();
352 if (Reg == 0) continue;
Jim Grosbacheb431da2010-01-06 16:48:02 +0000353
David Goodwindd1c6192009-11-19 23:12:37 +0000354 HandleLastUse(Reg, Count + 1, "", "\tDead Def: ", "\n");
David Goodwinde11f362009-10-26 19:32:42 +0000355 }
356
David Greene75a2efb2009-12-24 00:14:25 +0000357 DEBUG(dbgs() << "\tDef Groups:");
David Goodwinde11f362009-10-26 19:32:42 +0000358 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
359 MachineOperand &MO = MI->getOperand(i);
360 if (!MO.isReg() || !MO.isDef()) continue;
361 unsigned Reg = MO.getReg();
362 if (Reg == 0) continue;
363
Jim Grosbacheb431da2010-01-06 16:48:02 +0000364 DEBUG(dbgs() << " " << TRI->getName(Reg) << "=g" << State->GetGroup(Reg));
David Goodwinde11f362009-10-26 19:32:42 +0000365
David Goodwin9f1b2d42009-10-29 19:17:04 +0000366 // If MI's defs have a special allocation requirement, don't allow
David Goodwinde11f362009-10-26 19:32:42 +0000367 // any def registers to be changed. Also assume all registers
368 // defined in a call must not be changed (ABI).
Evan Cheng7f8e5632011-12-07 07:15:52 +0000369 if (MI->isCall() || MI->hasExtraDefRegAllocReq() ||
Evan Chengf128bdc2010-06-16 07:35:02 +0000370 TII->isPredicated(MI)) {
David Greene75a2efb2009-12-24 00:14:25 +0000371 DEBUG(if (State->GetGroup(Reg) != 0) dbgs() << "->g0(alloc-req)");
David Goodwine056d102009-10-26 22:31:16 +0000372 State->UnionGroups(Reg, 0);
David Goodwinde11f362009-10-26 19:32:42 +0000373 }
374
375 // Any aliased that are live at this point are completely or
David Goodwin9f1b2d42009-10-29 19:17:04 +0000376 // partially defined here, so group those aliases with Reg.
Jakob Stoklund Olesen54038d72012-06-01 23:28:30 +0000377 for (MCRegAliasIterator AI(Reg, TRI, false); AI.isValid(); ++AI) {
378 unsigned AliasReg = *AI;
David Goodwine056d102009-10-26 22:31:16 +0000379 if (State->IsLive(AliasReg)) {
380 State->UnionGroups(Reg, AliasReg);
Jim Grosbacheb431da2010-01-06 16:48:02 +0000381 DEBUG(dbgs() << "->g" << State->GetGroup(Reg) << "(via " <<
David Goodwinde11f362009-10-26 19:32:42 +0000382 TRI->getName(AliasReg) << ")");
383 }
384 }
Jim Grosbacheb431da2010-01-06 16:48:02 +0000385
David Goodwinde11f362009-10-26 19:32:42 +0000386 // Note register reference...
Craig Topperc0196b12014-04-14 00:51:57 +0000387 const TargetRegisterClass *RC = nullptr;
David Goodwinde11f362009-10-26 19:32:42 +0000388 if (i < MI->getDesc().getNumOperands())
Jakob Stoklund Olesen3c52f022012-05-07 22:10:26 +0000389 RC = TII->getRegClass(MI->getDesc(), i, TRI, MF);
David Goodwine056d102009-10-26 22:31:16 +0000390 AggressiveAntiDepState::RegisterReference RR = { &MO, RC };
David Goodwinde11f362009-10-26 19:32:42 +0000391 RegRefs.insert(std::make_pair(Reg, RR));
392 }
393
David Greene75a2efb2009-12-24 00:14:25 +0000394 DEBUG(dbgs() << '\n');
David Goodwin9f1b2d42009-10-29 19:17:04 +0000395
396 // Scan the register defs for this instruction and update
397 // live-ranges.
398 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
399 MachineOperand &MO = MI->getOperand(i);
400 if (!MO.isReg() || !MO.isDef()) continue;
401 unsigned Reg = MO.getReg();
402 if (Reg == 0) continue;
David Goodwindd1c6192009-11-19 23:12:37 +0000403 // Ignore KILLs and passthru registers for liveness...
Chris Lattnerb06015a2010-02-09 19:54:29 +0000404 if (MI->isKill() || (PassthruRegs.count(Reg) != 0))
David Goodwindd1c6192009-11-19 23:12:37 +0000405 continue;
David Goodwin9f1b2d42009-10-29 19:17:04 +0000406
David Goodwindd1c6192009-11-19 23:12:37 +0000407 // Update def for Reg and aliases.
Hal Finkel121caf62014-02-26 20:20:30 +0000408 for (MCRegAliasIterator AI(Reg, TRI, true); AI.isValid(); ++AI) {
409 // We need to be careful here not to define already-live super registers.
410 // If the super register is already live, then this definition is not
411 // a definition of the whole super register (just a partial insertion
412 // into it). Earlier subregister definitions (which we've not yet visited
413 // because we're iterating bottom-up) need to be linked to the same group
414 // as this definition.
415 if (TRI->isSuperRegister(Reg, *AI) && State->IsLive(*AI))
416 continue;
417
Jakob Stoklund Olesen54038d72012-06-01 23:28:30 +0000418 DefIndices[*AI] = Count;
Hal Finkel121caf62014-02-26 20:20:30 +0000419 }
David Goodwin9f1b2d42009-10-29 19:17:04 +0000420 }
David Goodwinde11f362009-10-26 19:32:42 +0000421}
422
423void AggressiveAntiDepBreaker::ScanInstruction(MachineInstr *MI,
Bob Wilson67dd3a42010-04-09 21:38:26 +0000424 unsigned Count) {
David Greene75a2efb2009-12-24 00:14:25 +0000425 DEBUG(dbgs() << "\tUse Groups:");
Jim Grosbacheb431da2010-01-06 16:48:02 +0000426 std::multimap<unsigned, AggressiveAntiDepState::RegisterReference>&
David Goodwine056d102009-10-26 22:31:16 +0000427 RegRefs = State->GetRegRefs();
David Goodwinde11f362009-10-26 19:32:42 +0000428
Evan Chengf128bdc2010-06-16 07:35:02 +0000429 // If MI's uses have special allocation requirement, don't allow
430 // any use registers to be changed. Also assume all registers
431 // used in a call must not be changed (ABI).
432 // FIXME: The issue with predicated instruction is more complex. We are being
433 // conservatively here because the kill markers cannot be trusted after
434 // if-conversion:
435 // %R6<def> = LDR %SP, %reg0, 92, pred:14, pred:%reg0; mem:LD4[FixedStack14]
436 // ...
437 // STR %R0, %R6<kill>, %reg0, 0, pred:0, pred:%CPSR; mem:ST4[%395]
438 // %R6<def> = LDR %SP, %reg0, 100, pred:0, pred:%CPSR; mem:LD4[FixedStack12]
439 // STR %R0, %R6<kill>, %reg0, 0, pred:14, pred:%reg0; mem:ST4[%396](align=8)
440 //
441 // The first R6 kill is not really a kill since it's killed by a predicated
442 // instruction which may not be executed. The second R6 def may or may not
443 // re-define R6 so it's not safe to change it since the last R6 use cannot be
444 // changed.
Evan Cheng7f8e5632011-12-07 07:15:52 +0000445 bool Special = MI->isCall() ||
446 MI->hasExtraSrcRegAllocReq() ||
Evan Chengf128bdc2010-06-16 07:35:02 +0000447 TII->isPredicated(MI);
448
David Goodwinde11f362009-10-26 19:32:42 +0000449 // Scan the register uses for this instruction and update
450 // live-ranges, groups and RegRefs.
451 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
452 MachineOperand &MO = MI->getOperand(i);
453 if (!MO.isReg() || !MO.isUse()) continue;
454 unsigned Reg = MO.getReg();
455 if (Reg == 0) continue;
Jim Grosbacheb431da2010-01-06 16:48:02 +0000456
457 DEBUG(dbgs() << " " << TRI->getName(Reg) << "=g" <<
458 State->GetGroup(Reg));
David Goodwinde11f362009-10-26 19:32:42 +0000459
460 // It wasn't previously live but now it is, this is a kill. Forget
461 // the previous live-range information and start a new live-range
462 // for the register.
David Goodwin9f1b2d42009-10-29 19:17:04 +0000463 HandleLastUse(Reg, Count, "(last-use)");
David Goodwinde11f362009-10-26 19:32:42 +0000464
Evan Chengf128bdc2010-06-16 07:35:02 +0000465 if (Special) {
David Greene75a2efb2009-12-24 00:14:25 +0000466 DEBUG(if (State->GetGroup(Reg) != 0) dbgs() << "->g0(alloc-req)");
David Goodwine056d102009-10-26 22:31:16 +0000467 State->UnionGroups(Reg, 0);
David Goodwinde11f362009-10-26 19:32:42 +0000468 }
469
470 // Note register reference...
Craig Topperc0196b12014-04-14 00:51:57 +0000471 const TargetRegisterClass *RC = nullptr;
David Goodwinde11f362009-10-26 19:32:42 +0000472 if (i < MI->getDesc().getNumOperands())
Jakob Stoklund Olesen3c52f022012-05-07 22:10:26 +0000473 RC = TII->getRegClass(MI->getDesc(), i, TRI, MF);
David Goodwine056d102009-10-26 22:31:16 +0000474 AggressiveAntiDepState::RegisterReference RR = { &MO, RC };
David Goodwinde11f362009-10-26 19:32:42 +0000475 RegRefs.insert(std::make_pair(Reg, RR));
476 }
Jim Grosbacheb431da2010-01-06 16:48:02 +0000477
David Greene75a2efb2009-12-24 00:14:25 +0000478 DEBUG(dbgs() << '\n');
David Goodwinde11f362009-10-26 19:32:42 +0000479
480 // Form a group of all defs and uses of a KILL instruction to ensure
481 // that all registers are renamed as a group.
Chris Lattnerb06015a2010-02-09 19:54:29 +0000482 if (MI->isKill()) {
David Greene75a2efb2009-12-24 00:14:25 +0000483 DEBUG(dbgs() << "\tKill Group:");
David Goodwinde11f362009-10-26 19:32:42 +0000484
485 unsigned FirstReg = 0;
486 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
487 MachineOperand &MO = MI->getOperand(i);
488 if (!MO.isReg()) continue;
489 unsigned Reg = MO.getReg();
490 if (Reg == 0) continue;
Jim Grosbacheb431da2010-01-06 16:48:02 +0000491
David Goodwinde11f362009-10-26 19:32:42 +0000492 if (FirstReg != 0) {
David Greene75a2efb2009-12-24 00:14:25 +0000493 DEBUG(dbgs() << "=" << TRI->getName(Reg));
David Goodwine056d102009-10-26 22:31:16 +0000494 State->UnionGroups(FirstReg, Reg);
David Goodwinde11f362009-10-26 19:32:42 +0000495 } else {
David Greene75a2efb2009-12-24 00:14:25 +0000496 DEBUG(dbgs() << " " << TRI->getName(Reg));
David Goodwinde11f362009-10-26 19:32:42 +0000497 FirstReg = Reg;
498 }
499 }
Jim Grosbacheb431da2010-01-06 16:48:02 +0000500
David Greene75a2efb2009-12-24 00:14:25 +0000501 DEBUG(dbgs() << "->g" << State->GetGroup(FirstReg) << '\n');
David Goodwinde11f362009-10-26 19:32:42 +0000502 }
503}
504
505BitVector AggressiveAntiDepBreaker::GetRenameRegisters(unsigned Reg) {
506 BitVector BV(TRI->getNumRegs(), false);
507 bool first = true;
508
509 // Check all references that need rewriting for Reg. For each, use
510 // the corresponding register class to narrow the set of registers
511 // that are appropriate for renaming.
Jim Grosbacheb431da2010-01-06 16:48:02 +0000512 std::pair<std::multimap<unsigned,
David Goodwine056d102009-10-26 22:31:16 +0000513 AggressiveAntiDepState::RegisterReference>::iterator,
514 std::multimap<unsigned,
515 AggressiveAntiDepState::RegisterReference>::iterator>
516 Range = State->GetRegRefs().equal_range(Reg);
Jim Grosbacheb431da2010-01-06 16:48:02 +0000517 for (std::multimap<unsigned,
518 AggressiveAntiDepState::RegisterReference>::iterator Q = Range.first,
519 QE = Range.second; Q != QE; ++Q) {
David Goodwinde11f362009-10-26 19:32:42 +0000520 const TargetRegisterClass *RC = Q->second.RC;
Craig Topperc0196b12014-04-14 00:51:57 +0000521 if (!RC) continue;
David Goodwinde11f362009-10-26 19:32:42 +0000522
523 BitVector RCBV = TRI->getAllocatableSet(MF, RC);
524 if (first) {
525 BV |= RCBV;
526 first = false;
527 } else {
528 BV &= RCBV;
529 }
530
Craig Toppercf0444b2014-11-17 05:50:14 +0000531 DEBUG(dbgs() << " " << TRI->getRegClassName(RC));
David Goodwinde11f362009-10-26 19:32:42 +0000532 }
Jim Grosbacheb431da2010-01-06 16:48:02 +0000533
David Goodwinde11f362009-10-26 19:32:42 +0000534 return BV;
Jim Grosbacheb431da2010-01-06 16:48:02 +0000535}
David Goodwinde11f362009-10-26 19:32:42 +0000536
537bool AggressiveAntiDepBreaker::FindSuitableFreeRegisters(
David Goodwin7d8878a2009-11-05 01:19:35 +0000538 unsigned AntiDepGroupIndex,
539 RenameOrderType& RenameOrder,
540 std::map<unsigned, unsigned> &RenameMap) {
Bill Wendling030b0282010-07-15 18:43:09 +0000541 std::vector<unsigned> &KillIndices = State->GetKillIndices();
542 std::vector<unsigned> &DefIndices = State->GetDefIndices();
Jim Grosbacheb431da2010-01-06 16:48:02 +0000543 std::multimap<unsigned, AggressiveAntiDepState::RegisterReference>&
David Goodwine056d102009-10-26 22:31:16 +0000544 RegRefs = State->GetRegRefs();
545
David Goodwinb9fe5d52009-11-13 19:52:48 +0000546 // Collect all referenced registers in the same group as
547 // AntiDepReg. These all need to be renamed together if we are to
548 // break the anti-dependence.
David Goodwinde11f362009-10-26 19:32:42 +0000549 std::vector<unsigned> Regs;
David Goodwinb9fe5d52009-11-13 19:52:48 +0000550 State->GetGroupRegs(AntiDepGroupIndex, Regs, &RegRefs);
David Goodwinde11f362009-10-26 19:32:42 +0000551 assert(Regs.size() > 0 && "Empty register group!");
552 if (Regs.size() == 0)
553 return false;
554
555 // Find the "superest" register in the group. At the same time,
556 // collect the BitVector of registers that can be used to rename
557 // each register.
Jim Grosbacheb431da2010-01-06 16:48:02 +0000558 DEBUG(dbgs() << "\tRename Candidates for Group g" << AntiDepGroupIndex
559 << ":\n");
David Goodwinde11f362009-10-26 19:32:42 +0000560 std::map<unsigned, BitVector> RenameRegisterMap;
561 unsigned SuperReg = 0;
562 for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
563 unsigned Reg = Regs[i];
564 if ((SuperReg == 0) || TRI->isSuperRegister(SuperReg, Reg))
565 SuperReg = Reg;
566
567 // If Reg has any references, then collect possible rename regs
568 if (RegRefs.count(Reg) > 0) {
David Greene75a2efb2009-12-24 00:14:25 +0000569 DEBUG(dbgs() << "\t\t" << TRI->getName(Reg) << ":");
Jim Grosbacheb431da2010-01-06 16:48:02 +0000570
David Goodwinde11f362009-10-26 19:32:42 +0000571 BitVector BV = GetRenameRegisters(Reg);
572 RenameRegisterMap.insert(std::pair<unsigned, BitVector>(Reg, BV));
573
David Greene75a2efb2009-12-24 00:14:25 +0000574 DEBUG(dbgs() << " ::");
David Goodwinde11f362009-10-26 19:32:42 +0000575 DEBUG(for (int r = BV.find_first(); r != -1; r = BV.find_next(r))
David Greene75a2efb2009-12-24 00:14:25 +0000576 dbgs() << " " << TRI->getName(r));
577 DEBUG(dbgs() << "\n");
David Goodwinde11f362009-10-26 19:32:42 +0000578 }
579 }
580
581 // All group registers should be a subreg of SuperReg.
582 for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
583 unsigned Reg = Regs[i];
584 if (Reg == SuperReg) continue;
585 bool IsSub = TRI->isSubRegister(SuperReg, Reg);
Will Schmidt44ff8f02014-07-31 19:50:53 +0000586 // FIXME: remove this once PR18663 has been properly fixed. For now,
587 // return a conservative answer:
588 // assert(IsSub && "Expecting group subregister");
David Goodwinde11f362009-10-26 19:32:42 +0000589 if (!IsSub)
590 return false;
591 }
592
David Goodwin5305dc02009-11-20 23:33:54 +0000593#ifndef NDEBUG
594 // If DebugDiv > 0 then only rename (renamecnt % DebugDiv) == DebugMod
595 if (DebugDiv > 0) {
596 static int renamecnt = 0;
597 if (renamecnt++ % DebugDiv != DebugMod)
598 return false;
Jim Grosbacheb431da2010-01-06 16:48:02 +0000599
David Greene75a2efb2009-12-24 00:14:25 +0000600 dbgs() << "*** Performing rename " << TRI->getName(SuperReg) <<
David Goodwin5305dc02009-11-20 23:33:54 +0000601 " for debug ***\n";
602 }
603#endif
604
David Goodwin7d8878a2009-11-05 01:19:35 +0000605 // Check each possible rename register for SuperReg in round-robin
606 // order. If that register is available, and the corresponding
607 // registers are available for the other group subregisters, then we
608 // can use those registers to rename.
Rafael Espindola871c7242010-07-12 02:55:34 +0000609
610 // FIXME: Using getMinimalPhysRegClass is very conservative. We should
611 // check every use of the register and find the largest register class
612 // that can be used in all of them.
Jim Grosbacheb431da2010-01-06 16:48:02 +0000613 const TargetRegisterClass *SuperRC =
Rafael Espindola871c7242010-07-12 02:55:34 +0000614 TRI->getMinimalPhysRegClass(SuperReg, MVT::Other);
Jim Grosbacheb431da2010-01-06 16:48:02 +0000615
Jakob Stoklund Olesenbdb55e02012-11-29 03:34:17 +0000616 ArrayRef<MCPhysReg> Order = RegClassInfo.getOrder(SuperRC);
Jakob Stoklund Olesen4f5f84c2011-06-16 21:56:21 +0000617 if (Order.empty()) {
David Greene75a2efb2009-12-24 00:14:25 +0000618 DEBUG(dbgs() << "\tEmpty Super Regclass!!\n");
David Goodwin7d8878a2009-11-05 01:19:35 +0000619 return false;
620 }
621
David Greene75a2efb2009-12-24 00:14:25 +0000622 DEBUG(dbgs() << "\tFind Registers:");
David Goodwindd1c6192009-11-19 23:12:37 +0000623
Benjamin Kramer2c99e412014-10-10 15:32:50 +0000624 RenameOrder.insert(RenameOrderType::value_type(SuperRC, Order.size()));
David Goodwin7d8878a2009-11-05 01:19:35 +0000625
Jakob Stoklund Olesen4f5f84c2011-06-16 21:56:21 +0000626 unsigned OrigR = RenameOrder[SuperRC];
627 unsigned EndR = ((OrigR == Order.size()) ? 0 : OrigR);
628 unsigned R = OrigR;
David Goodwin7d8878a2009-11-05 01:19:35 +0000629 do {
Jakob Stoklund Olesen4f5f84c2011-06-16 21:56:21 +0000630 if (R == 0) R = Order.size();
David Goodwin7d8878a2009-11-05 01:19:35 +0000631 --R;
Jakob Stoklund Olesen4f5f84c2011-06-16 21:56:21 +0000632 const unsigned NewSuperReg = Order[R];
Jim Grosbach944aece2010-09-02 17:12:55 +0000633 // Don't consider non-allocatable registers
Jakob Stoklund Olesenf67bf3e2012-10-15 22:41:03 +0000634 if (!MRI.isAllocatable(NewSuperReg)) continue;
David Goodwinde11f362009-10-26 19:32:42 +0000635 // Don't replace a register with itself.
David Goodwin5305dc02009-11-20 23:33:54 +0000636 if (NewSuperReg == SuperReg) continue;
Jim Grosbacheb431da2010-01-06 16:48:02 +0000637
David Greene75a2efb2009-12-24 00:14:25 +0000638 DEBUG(dbgs() << " [" << TRI->getName(NewSuperReg) << ':');
David Goodwin5305dc02009-11-20 23:33:54 +0000639 RenameMap.clear();
640
641 // For each referenced group register (which must be a SuperReg or
642 // a subregister of SuperReg), find the corresponding subregister
643 // of NewSuperReg and make sure it is free to be renamed.
644 for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
645 unsigned Reg = Regs[i];
646 unsigned NewReg = 0;
647 if (Reg == SuperReg) {
648 NewReg = NewSuperReg;
649 } else {
650 unsigned NewSubRegIdx = TRI->getSubRegIndex(SuperReg, Reg);
651 if (NewSubRegIdx != 0)
652 NewReg = TRI->getSubReg(NewSuperReg, NewSubRegIdx);
David Goodwinde11f362009-10-26 19:32:42 +0000653 }
David Goodwin5305dc02009-11-20 23:33:54 +0000654
David Greene75a2efb2009-12-24 00:14:25 +0000655 DEBUG(dbgs() << " " << TRI->getName(NewReg));
Jim Grosbacheb431da2010-01-06 16:48:02 +0000656
David Goodwin5305dc02009-11-20 23:33:54 +0000657 // Check if Reg can be renamed to NewReg.
658 BitVector BV = RenameRegisterMap[Reg];
659 if (!BV.test(NewReg)) {
David Greene75a2efb2009-12-24 00:14:25 +0000660 DEBUG(dbgs() << "(no rename)");
David Goodwin5305dc02009-11-20 23:33:54 +0000661 goto next_super_reg;
662 }
663
664 // If NewReg is dead and NewReg's most recent def is not before
665 // Regs's kill, it's safe to replace Reg with NewReg. We
666 // must also check all aliases of NewReg, because we can't define a
667 // register when any sub or super is already live.
668 if (State->IsLive(NewReg) || (KillIndices[Reg] > DefIndices[NewReg])) {
David Greene75a2efb2009-12-24 00:14:25 +0000669 DEBUG(dbgs() << "(live)");
David Goodwin5305dc02009-11-20 23:33:54 +0000670 goto next_super_reg;
671 } else {
672 bool found = false;
Jakob Stoklund Olesen54038d72012-06-01 23:28:30 +0000673 for (MCRegAliasIterator AI(NewReg, TRI, false); AI.isValid(); ++AI) {
674 unsigned AliasReg = *AI;
Jim Grosbacheb431da2010-01-06 16:48:02 +0000675 if (State->IsLive(AliasReg) ||
676 (KillIndices[Reg] > DefIndices[AliasReg])) {
David Greene75a2efb2009-12-24 00:14:25 +0000677 DEBUG(dbgs() << "(alias " << TRI->getName(AliasReg) << " live)");
David Goodwin5305dc02009-11-20 23:33:54 +0000678 found = true;
679 break;
680 }
681 }
682 if (found)
683 goto next_super_reg;
684 }
Jim Grosbacheb431da2010-01-06 16:48:02 +0000685
Hal Finkelc8cf2b82014-12-09 01:00:59 +0000686 // We cannot rename 'Reg' to 'NewReg' if one of the uses of 'Reg' also
687 // defines 'NewReg' via an early-clobber operand.
688 auto Range = RegRefs.equal_range(Reg);
689 for (auto Q = Range.first, QE = Range.second; Q != QE; ++Q) {
690 auto UseMI = Q->second.Operand->getParent();
691 int Idx = UseMI->findRegisterDefOperandIdx(NewReg, false, true, TRI);
692 if (Idx == -1)
693 continue;
694
695 if (UseMI->getOperand(Idx).isEarlyClobber()) {
696 DEBUG(dbgs() << "(ec)");
697 goto next_super_reg;
698 }
699 }
700
David Goodwin5305dc02009-11-20 23:33:54 +0000701 // Record that 'Reg' can be renamed to 'NewReg'.
702 RenameMap.insert(std::pair<unsigned, unsigned>(Reg, NewReg));
David Goodwinde11f362009-10-26 19:32:42 +0000703 }
Jim Grosbacheb431da2010-01-06 16:48:02 +0000704
David Goodwin5305dc02009-11-20 23:33:54 +0000705 // If we fall-out here, then every register in the group can be
706 // renamed, as recorded in RenameMap.
707 RenameOrder.erase(SuperRC);
708 RenameOrder.insert(RenameOrderType::value_type(SuperRC, R));
David Greene75a2efb2009-12-24 00:14:25 +0000709 DEBUG(dbgs() << "]\n");
David Goodwin5305dc02009-11-20 23:33:54 +0000710 return true;
711
712 next_super_reg:
David Greene75a2efb2009-12-24 00:14:25 +0000713 DEBUG(dbgs() << ']');
David Goodwin7d8878a2009-11-05 01:19:35 +0000714 } while (R != EndR);
David Goodwinde11f362009-10-26 19:32:42 +0000715
David Greene75a2efb2009-12-24 00:14:25 +0000716 DEBUG(dbgs() << '\n');
David Goodwinde11f362009-10-26 19:32:42 +0000717
718 // No registers are free and available!
719 return false;
720}
721
722/// BreakAntiDependencies - Identifiy anti-dependencies within the
723/// ScheduleDAG and break them by renaming registers.
724///
David Goodwine056d102009-10-26 22:31:16 +0000725unsigned AggressiveAntiDepBreaker::BreakAntiDependencies(
Dan Gohman35bc4d42010-04-19 23:11:58 +0000726 const std::vector<SUnit>& SUnits,
727 MachineBasicBlock::iterator Begin,
728 MachineBasicBlock::iterator End,
Devang Patelf02a3762011-06-02 21:26:52 +0000729 unsigned InsertPosIndex,
730 DbgValueVector &DbgValues) {
731
Bill Wendling030b0282010-07-15 18:43:09 +0000732 std::vector<unsigned> &KillIndices = State->GetKillIndices();
733 std::vector<unsigned> &DefIndices = State->GetDefIndices();
Jim Grosbacheb431da2010-01-06 16:48:02 +0000734 std::multimap<unsigned, AggressiveAntiDepState::RegisterReference>&
David Goodwine056d102009-10-26 22:31:16 +0000735 RegRefs = State->GetRegRefs();
736
David Goodwinde11f362009-10-26 19:32:42 +0000737 // The code below assumes that there is at least one instruction,
738 // so just duck out immediately if the block is empty.
David Goodwin8501dbbe2009-11-03 20:57:50 +0000739 if (SUnits.empty()) return 0;
Jim Grosbacheb431da2010-01-06 16:48:02 +0000740
David Goodwin7d8878a2009-11-05 01:19:35 +0000741 // For each regclass the next register to use for renaming.
742 RenameOrderType RenameOrder;
David Goodwinde11f362009-10-26 19:32:42 +0000743
744 // ...need a map from MI to SUnit.
Dan Gohman35bc4d42010-04-19 23:11:58 +0000745 std::map<MachineInstr *, const SUnit *> MISUnitMap;
David Goodwinde11f362009-10-26 19:32:42 +0000746 for (unsigned i = 0, e = SUnits.size(); i != e; ++i) {
Dan Gohman35bc4d42010-04-19 23:11:58 +0000747 const SUnit *SU = &SUnits[i];
748 MISUnitMap.insert(std::pair<MachineInstr *, const SUnit *>(SU->getInstr(),
749 SU));
David Goodwinde11f362009-10-26 19:32:42 +0000750 }
751
David Goodwinb9fe5d52009-11-13 19:52:48 +0000752 // Track progress along the critical path through the SUnit graph as
753 // we walk the instructions. This is needed for regclasses that only
754 // break critical-path anti-dependencies.
Craig Topperc0196b12014-04-14 00:51:57 +0000755 const SUnit *CriticalPathSU = nullptr;
756 MachineInstr *CriticalPathMI = nullptr;
David Goodwinb9fe5d52009-11-13 19:52:48 +0000757 if (CriticalPathSet.any()) {
758 for (unsigned i = 0, e = SUnits.size(); i != e; ++i) {
Dan Gohman35bc4d42010-04-19 23:11:58 +0000759 const SUnit *SU = &SUnits[i];
Jim Grosbacheb431da2010-01-06 16:48:02 +0000760 if (!CriticalPathSU ||
761 ((SU->getDepth() + SU->Latency) >
David Goodwinb9fe5d52009-11-13 19:52:48 +0000762 (CriticalPathSU->getDepth() + CriticalPathSU->Latency))) {
763 CriticalPathSU = SU;
764 }
765 }
Jim Grosbacheb431da2010-01-06 16:48:02 +0000766
David Goodwinb9fe5d52009-11-13 19:52:48 +0000767 CriticalPathMI = CriticalPathSU->getInstr();
768 }
769
Jim Grosbacheb431da2010-01-06 16:48:02 +0000770#ifndef NDEBUG
David Greene75a2efb2009-12-24 00:14:25 +0000771 DEBUG(dbgs() << "\n===== Aggressive anti-dependency breaking\n");
772 DEBUG(dbgs() << "Available regs:");
David Goodwin80a03cc2009-11-20 19:32:48 +0000773 for (unsigned Reg = 0; Reg < TRI->getNumRegs(); ++Reg) {
774 if (!State->IsLive(Reg))
David Greene75a2efb2009-12-24 00:14:25 +0000775 DEBUG(dbgs() << " " << TRI->getName(Reg));
David Goodwinde11f362009-10-26 19:32:42 +0000776 }
David Greene75a2efb2009-12-24 00:14:25 +0000777 DEBUG(dbgs() << '\n');
David Goodwinde11f362009-10-26 19:32:42 +0000778#endif
779
780 // Attempt to break anti-dependence edges. Walk the instructions
781 // from the bottom up, tracking information about liveness as we go
782 // to help determine which registers are available.
783 unsigned Broken = 0;
784 unsigned Count = InsertPosIndex - 1;
785 for (MachineBasicBlock::iterator I = End, E = Begin;
786 I != E; --Count) {
787 MachineInstr *MI = --I;
788
Hal Finkel8606e3c2012-01-16 22:53:41 +0000789 if (MI->isDebugValue())
790 continue;
791
David Greene75a2efb2009-12-24 00:14:25 +0000792 DEBUG(dbgs() << "Anti: ");
David Goodwinde11f362009-10-26 19:32:42 +0000793 DEBUG(MI->dump());
794
795 std::set<unsigned> PassthruRegs;
796 GetPassthruRegs(MI, PassthruRegs);
797
798 // Process the defs in MI...
799 PrescanInstruction(MI, Count, PassthruRegs);
Jim Grosbacheb431da2010-01-06 16:48:02 +0000800
David Goodwin80a03cc2009-11-20 19:32:48 +0000801 // The dependence edges that represent anti- and output-
David Goodwinb9fe5d52009-11-13 19:52:48 +0000802 // dependencies that are candidates for breaking.
Dan Gohman35bc4d42010-04-19 23:11:58 +0000803 std::vector<const SDep *> Edges;
804 const SUnit *PathSU = MISUnitMap[MI];
David Goodwin80a03cc2009-11-20 19:32:48 +0000805 AntiDepEdges(PathSU, Edges);
David Goodwinb9fe5d52009-11-13 19:52:48 +0000806
807 // If MI is not on the critical path, then we don't rename
808 // registers in the CriticalPathSet.
Craig Topperc0196b12014-04-14 00:51:57 +0000809 BitVector *ExcludeRegs = nullptr;
David Goodwinb9fe5d52009-11-13 19:52:48 +0000810 if (MI == CriticalPathMI) {
811 CriticalPathSU = CriticalPathStep(CriticalPathSU);
Craig Topperc0196b12014-04-14 00:51:57 +0000812 CriticalPathMI = (CriticalPathSU) ? CriticalPathSU->getInstr() : nullptr;
Hal Finkel6f1ff8e2013-09-12 04:22:31 +0000813 } else if (CriticalPathSet.any()) {
David Goodwinb9fe5d52009-11-13 19:52:48 +0000814 ExcludeRegs = &CriticalPathSet;
815 }
816
David Goodwinde11f362009-10-26 19:32:42 +0000817 // Ignore KILL instructions (they form a group in ScanInstruction
818 // but don't cause any anti-dependence breaking themselves)
Chris Lattnerb06015a2010-02-09 19:54:29 +0000819 if (!MI->isKill()) {
David Goodwinde11f362009-10-26 19:32:42 +0000820 // Attempt to break each anti-dependency...
821 for (unsigned i = 0, e = Edges.size(); i != e; ++i) {
Dan Gohman35bc4d42010-04-19 23:11:58 +0000822 const SDep *Edge = Edges[i];
David Goodwinde11f362009-10-26 19:32:42 +0000823 SUnit *NextSU = Edge->getSUnit();
Jim Grosbacheb431da2010-01-06 16:48:02 +0000824
David Goodwinda83f7d2009-11-12 19:08:21 +0000825 if ((Edge->getKind() != SDep::Anti) &&
826 (Edge->getKind() != SDep::Output)) continue;
Jim Grosbacheb431da2010-01-06 16:48:02 +0000827
David Goodwinde11f362009-10-26 19:32:42 +0000828 unsigned AntiDepReg = Edge->getReg();
David Greene75a2efb2009-12-24 00:14:25 +0000829 DEBUG(dbgs() << "\tAntidep reg: " << TRI->getName(AntiDepReg));
David Goodwinde11f362009-10-26 19:32:42 +0000830 assert(AntiDepReg != 0 && "Anti-dependence on reg0?");
Jim Grosbacheb431da2010-01-06 16:48:02 +0000831
Jakob Stoklund Olesenf67bf3e2012-10-15 22:41:03 +0000832 if (!MRI.isAllocatable(AntiDepReg)) {
David Goodwinde11f362009-10-26 19:32:42 +0000833 // Don't break anti-dependencies on non-allocatable registers.
David Greene75a2efb2009-12-24 00:14:25 +0000834 DEBUG(dbgs() << " (non-allocatable)\n");
David Goodwinde11f362009-10-26 19:32:42 +0000835 continue;
Craig Topperc0196b12014-04-14 00:51:57 +0000836 } else if (ExcludeRegs && ExcludeRegs->test(AntiDepReg)) {
David Goodwinb9fe5d52009-11-13 19:52:48 +0000837 // Don't break anti-dependencies for critical path registers
838 // if not on the critical path
David Greene75a2efb2009-12-24 00:14:25 +0000839 DEBUG(dbgs() << " (not critical-path)\n");
David Goodwinb9fe5d52009-11-13 19:52:48 +0000840 continue;
David Goodwinde11f362009-10-26 19:32:42 +0000841 } else if (PassthruRegs.count(AntiDepReg) != 0) {
842 // If the anti-dep register liveness "passes-thru", then
843 // don't try to change it. It will be changed along with
844 // the use if required to break an earlier antidep.
David Greene75a2efb2009-12-24 00:14:25 +0000845 DEBUG(dbgs() << " (passthru)\n");
David Goodwinde11f362009-10-26 19:32:42 +0000846 continue;
847 } else {
848 // No anti-dep breaking for implicit deps
849 MachineOperand *AntiDepOp = MI->findRegisterDefOperand(AntiDepReg);
Craig Topperc0196b12014-04-14 00:51:57 +0000850 assert(AntiDepOp && "Can't find index for defined register operand");
851 if (!AntiDepOp || AntiDepOp->isImplicit()) {
David Greene75a2efb2009-12-24 00:14:25 +0000852 DEBUG(dbgs() << " (implicit)\n");
David Goodwinde11f362009-10-26 19:32:42 +0000853 continue;
854 }
Jim Grosbacheb431da2010-01-06 16:48:02 +0000855
David Goodwinde11f362009-10-26 19:32:42 +0000856 // If the SUnit has other dependencies on the SUnit that
857 // it anti-depends on, don't bother breaking the
858 // anti-dependency since those edges would prevent such
859 // units from being scheduled past each other
860 // regardless.
David Goodwin80a03cc2009-11-20 19:32:48 +0000861 //
862 // Also, if there are dependencies on other SUnits with the
863 // same register as the anti-dependency, don't attempt to
864 // break it.
Dan Gohman35bc4d42010-04-19 23:11:58 +0000865 for (SUnit::const_pred_iterator P = PathSU->Preds.begin(),
David Goodwinde11f362009-10-26 19:32:42 +0000866 PE = PathSU->Preds.end(); P != PE; ++P) {
David Goodwin80a03cc2009-11-20 19:32:48 +0000867 if (P->getSUnit() == NextSU ?
868 (P->getKind() != SDep::Anti || P->getReg() != AntiDepReg) :
869 (P->getKind() == SDep::Data && P->getReg() == AntiDepReg)) {
870 AntiDepReg = 0;
871 break;
872 }
873 }
Dan Gohman35bc4d42010-04-19 23:11:58 +0000874 for (SUnit::const_pred_iterator P = PathSU->Preds.begin(),
David Goodwin80a03cc2009-11-20 19:32:48 +0000875 PE = PathSU->Preds.end(); P != PE; ++P) {
876 if ((P->getSUnit() == NextSU) && (P->getKind() != SDep::Anti) &&
877 (P->getKind() != SDep::Output)) {
David Greene75a2efb2009-12-24 00:14:25 +0000878 DEBUG(dbgs() << " (real dependency)\n");
David Goodwinde11f362009-10-26 19:32:42 +0000879 AntiDepReg = 0;
880 break;
Jim Grosbacheb431da2010-01-06 16:48:02 +0000881 } else if ((P->getSUnit() != NextSU) &&
882 (P->getKind() == SDep::Data) &&
David Goodwin80a03cc2009-11-20 19:32:48 +0000883 (P->getReg() == AntiDepReg)) {
David Greene75a2efb2009-12-24 00:14:25 +0000884 DEBUG(dbgs() << " (other dependency)\n");
David Goodwin80a03cc2009-11-20 19:32:48 +0000885 AntiDepReg = 0;
886 break;
David Goodwinde11f362009-10-26 19:32:42 +0000887 }
888 }
Jim Grosbacheb431da2010-01-06 16:48:02 +0000889
David Goodwinde11f362009-10-26 19:32:42 +0000890 if (AntiDepReg == 0) continue;
891 }
Jim Grosbacheb431da2010-01-06 16:48:02 +0000892
David Goodwinde11f362009-10-26 19:32:42 +0000893 assert(AntiDepReg != 0);
894 if (AntiDepReg == 0) continue;
Jim Grosbacheb431da2010-01-06 16:48:02 +0000895
David Goodwinde11f362009-10-26 19:32:42 +0000896 // Determine AntiDepReg's register group.
David Goodwine056d102009-10-26 22:31:16 +0000897 const unsigned GroupIndex = State->GetGroup(AntiDepReg);
David Goodwinde11f362009-10-26 19:32:42 +0000898 if (GroupIndex == 0) {
David Greene75a2efb2009-12-24 00:14:25 +0000899 DEBUG(dbgs() << " (zero group)\n");
David Goodwinde11f362009-10-26 19:32:42 +0000900 continue;
901 }
Jim Grosbacheb431da2010-01-06 16:48:02 +0000902
David Greene75a2efb2009-12-24 00:14:25 +0000903 DEBUG(dbgs() << '\n');
Jim Grosbacheb431da2010-01-06 16:48:02 +0000904
David Goodwinde11f362009-10-26 19:32:42 +0000905 // Look for a suitable register to use to break the anti-dependence.
906 std::map<unsigned, unsigned> RenameMap;
David Goodwin7d8878a2009-11-05 01:19:35 +0000907 if (FindSuitableFreeRegisters(GroupIndex, RenameOrder, RenameMap)) {
David Greene75a2efb2009-12-24 00:14:25 +0000908 DEBUG(dbgs() << "\tBreaking anti-dependence edge on "
David Goodwinde11f362009-10-26 19:32:42 +0000909 << TRI->getName(AntiDepReg) << ":");
Jim Grosbacheb431da2010-01-06 16:48:02 +0000910
David Goodwinde11f362009-10-26 19:32:42 +0000911 // Handle each group register...
912 for (std::map<unsigned, unsigned>::iterator
913 S = RenameMap.begin(), E = RenameMap.end(); S != E; ++S) {
914 unsigned CurrReg = S->first;
915 unsigned NewReg = S->second;
Jim Grosbacheb431da2010-01-06 16:48:02 +0000916
917 DEBUG(dbgs() << " " << TRI->getName(CurrReg) << "->" <<
918 TRI->getName(NewReg) << "(" <<
David Goodwinde11f362009-10-26 19:32:42 +0000919 RegRefs.count(CurrReg) << " refs)");
Jim Grosbacheb431da2010-01-06 16:48:02 +0000920
David Goodwinde11f362009-10-26 19:32:42 +0000921 // Update the references to the old register CurrReg to
922 // refer to the new register NewReg.
Jim Grosbacheb431da2010-01-06 16:48:02 +0000923 std::pair<std::multimap<unsigned,
924 AggressiveAntiDepState::RegisterReference>::iterator,
David Goodwine056d102009-10-26 22:31:16 +0000925 std::multimap<unsigned,
Jim Grosbacheb431da2010-01-06 16:48:02 +0000926 AggressiveAntiDepState::RegisterReference>::iterator>
David Goodwinde11f362009-10-26 19:32:42 +0000927 Range = RegRefs.equal_range(CurrReg);
Jim Grosbacheb431da2010-01-06 16:48:02 +0000928 for (std::multimap<unsigned,
929 AggressiveAntiDepState::RegisterReference>::iterator
David Goodwinde11f362009-10-26 19:32:42 +0000930 Q = Range.first, QE = Range.second; Q != QE; ++Q) {
931 Q->second.Operand->setReg(NewReg);
Jim Grosbach12ac8f02010-06-01 23:48:44 +0000932 // If the SU for the instruction being updated has debug
933 // information related to the anti-dependency register, make
934 // sure to update that as well.
935 const SUnit *SU = MISUnitMap[Q->second.Operand->getParent()];
Jim Grosbach84854832010-06-02 15:29:36 +0000936 if (!SU) continue;
Devang Patelf02a3762011-06-02 21:26:52 +0000937 for (DbgValueVector::iterator DVI = DbgValues.begin(),
938 DVE = DbgValues.end(); DVI != DVE; ++DVI)
939 if (DVI->second == Q->second.Operand->getParent())
940 UpdateDbgValue(DVI->first, AntiDepReg, NewReg);
David Goodwinde11f362009-10-26 19:32:42 +0000941 }
Jim Grosbacheb431da2010-01-06 16:48:02 +0000942
David Goodwinde11f362009-10-26 19:32:42 +0000943 // We just went back in time and modified history; the
944 // liveness information for CurrReg is now inconsistent. Set
945 // the state as if it were dead.
David Goodwine056d102009-10-26 22:31:16 +0000946 State->UnionGroups(NewReg, 0);
David Goodwinde11f362009-10-26 19:32:42 +0000947 RegRefs.erase(NewReg);
948 DefIndices[NewReg] = DefIndices[CurrReg];
949 KillIndices[NewReg] = KillIndices[CurrReg];
Jim Grosbacheb431da2010-01-06 16:48:02 +0000950
David Goodwine056d102009-10-26 22:31:16 +0000951 State->UnionGroups(CurrReg, 0);
David Goodwinde11f362009-10-26 19:32:42 +0000952 RegRefs.erase(CurrReg);
953 DefIndices[CurrReg] = KillIndices[CurrReg];
954 KillIndices[CurrReg] = ~0u;
955 assert(((KillIndices[CurrReg] == ~0u) !=
956 (DefIndices[CurrReg] == ~0u)) &&
957 "Kill and Def maps aren't consistent for AntiDepReg!");
958 }
Jim Grosbacheb431da2010-01-06 16:48:02 +0000959
David Goodwinde11f362009-10-26 19:32:42 +0000960 ++Broken;
David Greene75a2efb2009-12-24 00:14:25 +0000961 DEBUG(dbgs() << '\n');
David Goodwinde11f362009-10-26 19:32:42 +0000962 }
963 }
964 }
965
966 ScanInstruction(MI, Count);
967 }
Jim Grosbacheb431da2010-01-06 16:48:02 +0000968
David Goodwinde11f362009-10-26 19:32:42 +0000969 return Broken;
970}