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gerrit-public.fairphone.software / toolchain / llvm-project / eafe26d0824c5282f8ff832f38e07e8c1eb92cf0 / . / llvm / lib / Target / NVPTX / NVPTXISelLowering.cpp
blob: 09e5a613f2d5be05561b5afde52e65eadbb6dc84 [file] [log] [blame]
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]1//
2// The LLVM Compiler Infrastructure
3//
4// This file is distributed under the University of Illinois Open Source
5// License. See LICENSE.TXT for details.
6//
7//===----------------------------------------------------------------------===//
8//
9// This file defines the interfaces that NVPTX uses to lower LLVM code into a
10// selection DAG.
11//
12//===----------------------------------------------------------------------===//
13
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]14#include "NVPTXISelLowering.h"
Chandler Carruthed0881b2012-12-03 16:50:05 +0000[diff] [blame]15#include "NVPTX.h"
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]16#include "NVPTXTargetMachine.h"
17#include "NVPTXTargetObjectFile.h"
18#include "NVPTXUtilities.h"
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]19#include "llvm/CodeGen/Analysis.h"
20#include "llvm/CodeGen/MachineFrameInfo.h"
21#include "llvm/CodeGen/MachineFunction.h"
22#include "llvm/CodeGen/MachineInstrBuilder.h"
23#include "llvm/CodeGen/MachineRegisterInfo.h"
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]24#include "llvm/CodeGen/TargetLoweringObjectFileImpl.h"
Chandler Carruth219b89b2014-03-04 11:01:28 +0000[diff] [blame]25#include "llvm/IR/CallSite.h"
Chandler Carruth9fb823b2013-01-02 11:36:10 +0000[diff] [blame]26#include "llvm/IR/DerivedTypes.h"
27#include "llvm/IR/Function.h"
28#include "llvm/IR/GlobalValue.h"
29#include "llvm/IR/IntrinsicInst.h"
30#include "llvm/IR/Intrinsics.h"
31#include "llvm/IR/Module.h"
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]32#include "llvm/MC/MCSectionELF.h"
Chandler Carruthed0881b2012-12-03 16:50:05 +0000[diff] [blame]33#include "llvm/Support/CommandLine.h"
34#include "llvm/Support/Debug.h"
35#include "llvm/Support/ErrorHandling.h"
36#include "llvm/Support/raw_ostream.h"
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]37#include <sstream>
38
39#undef DEBUG_TYPE
40#define DEBUG_TYPE "nvptx-lower"
41
42using namespace llvm;
43
44static unsigned int uniqueCallSite = 0;
45
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]46static cl::opt<bool> sched4reg(
47 "nvptx-sched4reg",
48 cl::desc("NVPTX Specific: schedule for register pressue"), cl::init(false));
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]49
Justin Holewinskibe8dc642013-02-12 14:18:49 +0000[diff] [blame]50static bool IsPTXVectorType(MVT VT) {
51 switch (VT.SimpleTy) {
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]52 default:
53 return false;
Justin Holewinskif8f70912013-06-28 17:57:59 +0000[diff] [blame]54 case MVT::v2i1:
55 case MVT::v4i1:
Justin Holewinskibe8dc642013-02-12 14:18:49 +0000[diff] [blame]56 case MVT::v2i8:
57 case MVT::v4i8:
58 case MVT::v2i16:
59 case MVT::v4i16:
60 case MVT::v2i32:
61 case MVT::v4i32:
62 case MVT::v2i64:
63 case MVT::v2f32:
64 case MVT::v4f32:
65 case MVT::v2f64:
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]66 return true;
Justin Holewinskibe8dc642013-02-12 14:18:49 +0000[diff] [blame]67 }
68}
69
Justin Holewinskif8f70912013-06-28 17:57:59 +0000[diff] [blame]70/// ComputePTXValueVTs - For the given Type \p Ty, returns the set of primitive
71/// EVTs that compose it. Unlike ComputeValueVTs, this will break apart vectors
72/// into their primitive components.
73/// NOTE: This is a band-aid for code that expects ComputeValueVTs to return the
74/// same number of types as the Ins/Outs arrays in LowerFormalArguments,
75/// LowerCall, and LowerReturn.
76static void ComputePTXValueVTs(const TargetLowering &TLI, Type *Ty,
77 SmallVectorImpl<EVT> &ValueVTs,
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]78 SmallVectorImpl<uint64_t> *Offsets = nullptr,
Justin Holewinskif8f70912013-06-28 17:57:59 +0000[diff] [blame]79 uint64_t StartingOffset = 0) {
80 SmallVector<EVT, 16> TempVTs;
81 SmallVector<uint64_t, 16> TempOffsets;
82
83 ComputeValueVTs(TLI, Ty, TempVTs, &TempOffsets, StartingOffset);
84 for (unsigned i = 0, e = TempVTs.size(); i != e; ++i) {
85 EVT VT = TempVTs[i];
86 uint64_t Off = TempOffsets[i];
87 if (VT.isVector())
88 for (unsigned j = 0, je = VT.getVectorNumElements(); j != je; ++j) {
89 ValueVTs.push_back(VT.getVectorElementType());
90 if (Offsets)
91 Offsets->push_back(Off+j*VT.getVectorElementType().getStoreSize());
92 }
93 else {
94 ValueVTs.push_back(VT);
95 if (Offsets)
96 Offsets->push_back(Off);
97 }
98 }
99}
100
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]101// NVPTXTargetLowering Constructor.
102NVPTXTargetLowering::NVPTXTargetLowering(NVPTXTargetMachine &TM)
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]103 : TargetLowering(TM, new NVPTXTargetObjectFile()), nvTM(&TM),
104 nvptxSubtarget(TM.getSubtarget<NVPTXSubtarget>()) {
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]105
106 // always lower memset, memcpy, and memmove intrinsics to load/store
107 // instructions, rather
108 // then generating calls to memset, mempcy or memmove.
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]109 MaxStoresPerMemset = (unsigned) 0xFFFFFFFF;
110 MaxStoresPerMemcpy = (unsigned) 0xFFFFFFFF;
111 MaxStoresPerMemmove = (unsigned) 0xFFFFFFFF;
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]112
113 setBooleanContents(ZeroOrNegativeOneBooleanContent);
114
115 // Jump is Expensive. Don't create extra control flow for 'and', 'or'
116 // condition branches.
117 setJumpIsExpensive(true);
118
119 // By default, use the Source scheduling
120 if (sched4reg)
121 setSchedulingPreference(Sched::RegPressure);
122 else
123 setSchedulingPreference(Sched::Source);
124
125 addRegisterClass(MVT::i1, &NVPTX::Int1RegsRegClass);
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]126 addRegisterClass(MVT::i16, &NVPTX::Int16RegsRegClass);
127 addRegisterClass(MVT::i32, &NVPTX::Int32RegsRegClass);
128 addRegisterClass(MVT::i64, &NVPTX::Int64RegsRegClass);
129 addRegisterClass(MVT::f32, &NVPTX::Float32RegsRegClass);
130 addRegisterClass(MVT::f64, &NVPTX::Float64RegsRegClass);
131
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]132 // Operations not directly supported by NVPTX.
Tom Stellard3787b122014-06-10 16:01:29 +0000[diff] [blame]133 setOperationAction(ISD::SELECT_CC, MVT::f32, Expand);
134 setOperationAction(ISD::SELECT_CC, MVT::f64, Expand);
135 setOperationAction(ISD::SELECT_CC, MVT::i1, Expand);
136 setOperationAction(ISD::SELECT_CC, MVT::i8, Expand);
137 setOperationAction(ISD::SELECT_CC, MVT::i16, Expand);
138 setOperationAction(ISD::SELECT_CC, MVT::i32, Expand);
139 setOperationAction(ISD::SELECT_CC, MVT::i64, Expand);
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]140 setOperationAction(ISD::BR_CC, MVT::f32, Expand);
141 setOperationAction(ISD::BR_CC, MVT::f64, Expand);
142 setOperationAction(ISD::BR_CC, MVT::i1, Expand);
143 setOperationAction(ISD::BR_CC, MVT::i8, Expand);
144 setOperationAction(ISD::BR_CC, MVT::i16, Expand);
145 setOperationAction(ISD::BR_CC, MVT::i32, Expand);
146 setOperationAction(ISD::BR_CC, MVT::i64, Expand);
Justin Holewinski318c6252013-07-01 12:58:56 +0000[diff] [blame]147 // Some SIGN_EXTEND_INREG can be done using cvt instruction.
148 // For others we will expand to a SHL/SRA pair.
149 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i64, Legal);
150 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Legal);
151 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Legal);
152 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Legal);
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]153 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]154
155 if (nvptxSubtarget.hasROT64()) {
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]156 setOperationAction(ISD::ROTL, MVT::i64, Legal);
157 setOperationAction(ISD::ROTR, MVT::i64, Legal);
158 } else {
159 setOperationAction(ISD::ROTL, MVT::i64, Expand);
160 setOperationAction(ISD::ROTR, MVT::i64, Expand);
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]161 }
162 if (nvptxSubtarget.hasROT32()) {
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]163 setOperationAction(ISD::ROTL, MVT::i32, Legal);
164 setOperationAction(ISD::ROTR, MVT::i32, Legal);
165 } else {
166 setOperationAction(ISD::ROTL, MVT::i32, Expand);
167 setOperationAction(ISD::ROTR, MVT::i32, Expand);
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]168 }
169
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]170 setOperationAction(ISD::ROTL, MVT::i16, Expand);
171 setOperationAction(ISD::ROTR, MVT::i16, Expand);
172 setOperationAction(ISD::ROTL, MVT::i8, Expand);
173 setOperationAction(ISD::ROTR, MVT::i8, Expand);
174 setOperationAction(ISD::BSWAP, MVT::i16, Expand);
175 setOperationAction(ISD::BSWAP, MVT::i32, Expand);
176 setOperationAction(ISD::BSWAP, MVT::i64, Expand);
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]177
178 // Indirect branch is not supported.
179 // This also disables Jump Table creation.
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]180 setOperationAction(ISD::BR_JT, MVT::Other, Expand);
181 setOperationAction(ISD::BRIND, MVT::Other, Expand);
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]182
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]183 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
184 setOperationAction(ISD::GlobalAddress, MVT::i64, Custom);
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]185
186 // We want to legalize constant related memmove and memcopy
187 // intrinsics.
188 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::Other, Custom);
189
190 // Turn FP extload into load/fextend
191 setLoadExtAction(ISD::EXTLOAD, MVT::f32, Expand);
192 // Turn FP truncstore into trunc + store.
193 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
194
195 // PTX does not support load / store predicate registers
Justin Holewinskic6462aa2012-11-14 19:19:16 +0000[diff] [blame]196 setOperationAction(ISD::LOAD, MVT::i1, Custom);
197 setOperationAction(ISD::STORE, MVT::i1, Custom);
198
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]199 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
200 setLoadExtAction(ISD::ZEXTLOAD, MVT::i1, Promote);
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]201 setTruncStoreAction(MVT::i64, MVT::i1, Expand);
202 setTruncStoreAction(MVT::i32, MVT::i1, Expand);
203 setTruncStoreAction(MVT::i16, MVT::i1, Expand);
204 setTruncStoreAction(MVT::i8, MVT::i1, Expand);
205
206 // This is legal in NVPTX
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]207 setOperationAction(ISD::ConstantFP, MVT::f64, Legal);
208 setOperationAction(ISD::ConstantFP, MVT::f32, Legal);
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]209
210 // TRAP can be lowered to PTX trap
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]211 setOperationAction(ISD::TRAP, MVT::Other, Legal);
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]212
Justin Holewinski51cb1342013-07-01 12:59:04 +0000[diff] [blame]213 setOperationAction(ISD::ADDC, MVT::i64, Expand);
214 setOperationAction(ISD::ADDE, MVT::i64, Expand);
215
Justin Holewinskibe8dc642013-02-12 14:18:49 +0000[diff] [blame]216 // Register custom handling for vector loads/stores
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]217 for (int i = MVT::FIRST_VECTOR_VALUETYPE; i <= MVT::LAST_VECTOR_VALUETYPE;
218 ++i) {
219 MVT VT = (MVT::SimpleValueType) i;
Justin Holewinskibe8dc642013-02-12 14:18:49 +0000[diff] [blame]220 if (IsPTXVectorType(VT)) {
221 setOperationAction(ISD::LOAD, VT, Custom);
222 setOperationAction(ISD::STORE, VT, Custom);
223 setOperationAction(ISD::INTRINSIC_W_CHAIN, VT, Custom);
224 }
225 }
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]226
Justin Holewinskif8f70912013-06-28 17:57:59 +0000[diff] [blame]227 // Custom handling for i8 intrinsics
228 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::i8, Custom);
229
Justin Holewinskidc372df2013-06-28 17:58:07 +0000[diff] [blame]230 setOperationAction(ISD::CTLZ, MVT::i16, Legal);
231 setOperationAction(ISD::CTLZ, MVT::i32, Legal);
232 setOperationAction(ISD::CTLZ, MVT::i64, Legal);
233 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i16, Legal);
234 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32, Legal);
235 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Legal);
236 setOperationAction(ISD::CTTZ, MVT::i16, Expand);
237 setOperationAction(ISD::CTTZ, MVT::i32, Expand);
238 setOperationAction(ISD::CTTZ, MVT::i64, Expand);
239 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i16, Expand);
240 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32, Expand);
241 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i64, Expand);
242 setOperationAction(ISD::CTPOP, MVT::i16, Legal);
243 setOperationAction(ISD::CTPOP, MVT::i32, Legal);
244 setOperationAction(ISD::CTPOP, MVT::i64, Legal);
245
Justin Holewinskieafe26d2014-06-27 18:35:37 +0000[diff] [blame^]246 // We have some custom DAG combine patterns for these nodes
247 setTargetDAGCombine(ISD::ADD);
248 setTargetDAGCombine(ISD::AND);
249 setTargetDAGCombine(ISD::FADD);
250 setTargetDAGCombine(ISD::MUL);
251 setTargetDAGCombine(ISD::SHL);
252
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]253 // Now deduce the information based on the above mentioned
254 // actions
255 computeRegisterProperties();
256}
257
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]258const char *NVPTXTargetLowering::getTargetNodeName(unsigned Opcode) const {
259 switch (Opcode) {
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]260 default:
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]261 return nullptr;
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]262 case NVPTXISD::CALL:
263 return "NVPTXISD::CALL";
264 case NVPTXISD::RET_FLAG:
265 return "NVPTXISD::RET_FLAG";
266 case NVPTXISD::Wrapper:
267 return "NVPTXISD::Wrapper";
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]268 case NVPTXISD::DeclareParam:
269 return "NVPTXISD::DeclareParam";
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]270 case NVPTXISD::DeclareScalarParam:
271 return "NVPTXISD::DeclareScalarParam";
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]272 case NVPTXISD::DeclareRet:
273 return "NVPTXISD::DeclareRet";
274 case NVPTXISD::DeclareRetParam:
275 return "NVPTXISD::DeclareRetParam";
276 case NVPTXISD::PrintCall:
277 return "NVPTXISD::PrintCall";
278 case NVPTXISD::LoadParam:
279 return "NVPTXISD::LoadParam";
Justin Holewinskife44314f2013-06-28 17:57:51 +0000[diff] [blame]280 case NVPTXISD::LoadParamV2:
281 return "NVPTXISD::LoadParamV2";
282 case NVPTXISD::LoadParamV4:
283 return "NVPTXISD::LoadParamV4";
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]284 case NVPTXISD::StoreParam:
285 return "NVPTXISD::StoreParam";
Justin Holewinskife44314f2013-06-28 17:57:51 +0000[diff] [blame]286 case NVPTXISD::StoreParamV2:
287 return "NVPTXISD::StoreParamV2";
288 case NVPTXISD::StoreParamV4:
289 return "NVPTXISD::StoreParamV4";
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]290 case NVPTXISD::StoreParamS32:
291 return "NVPTXISD::StoreParamS32";
292 case NVPTXISD::StoreParamU32:
293 return "NVPTXISD::StoreParamU32";
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]294 case NVPTXISD::CallArgBegin:
295 return "NVPTXISD::CallArgBegin";
296 case NVPTXISD::CallArg:
297 return "NVPTXISD::CallArg";
298 case NVPTXISD::LastCallArg:
299 return "NVPTXISD::LastCallArg";
300 case NVPTXISD::CallArgEnd:
301 return "NVPTXISD::CallArgEnd";
302 case NVPTXISD::CallVoid:
303 return "NVPTXISD::CallVoid";
304 case NVPTXISD::CallVal:
305 return "NVPTXISD::CallVal";
306 case NVPTXISD::CallSymbol:
307 return "NVPTXISD::CallSymbol";
308 case NVPTXISD::Prototype:
309 return "NVPTXISD::Prototype";
310 case NVPTXISD::MoveParam:
311 return "NVPTXISD::MoveParam";
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]312 case NVPTXISD::StoreRetval:
313 return "NVPTXISD::StoreRetval";
Justin Holewinskife44314f2013-06-28 17:57:51 +0000[diff] [blame]314 case NVPTXISD::StoreRetvalV2:
315 return "NVPTXISD::StoreRetvalV2";
316 case NVPTXISD::StoreRetvalV4:
317 return "NVPTXISD::StoreRetvalV4";
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]318 case NVPTXISD::PseudoUseParam:
319 return "NVPTXISD::PseudoUseParam";
320 case NVPTXISD::RETURN:
321 return "NVPTXISD::RETURN";
322 case NVPTXISD::CallSeqBegin:
323 return "NVPTXISD::CallSeqBegin";
324 case NVPTXISD::CallSeqEnd:
325 return "NVPTXISD::CallSeqEnd";
Justin Holewinski3d49e5c2013-11-15 12:30:04 +0000[diff] [blame]326 case NVPTXISD::CallPrototype:
327 return "NVPTXISD::CallPrototype";
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]328 case NVPTXISD::LoadV2:
329 return "NVPTXISD::LoadV2";
330 case NVPTXISD::LoadV4:
331 return "NVPTXISD::LoadV4";
332 case NVPTXISD::LDGV2:
333 return "NVPTXISD::LDGV2";
334 case NVPTXISD::LDGV4:
335 return "NVPTXISD::LDGV4";
336 case NVPTXISD::LDUV2:
337 return "NVPTXISD::LDUV2";
338 case NVPTXISD::LDUV4:
339 return "NVPTXISD::LDUV4";
340 case NVPTXISD::StoreV2:
341 return "NVPTXISD::StoreV2";
342 case NVPTXISD::StoreV4:
343 return "NVPTXISD::StoreV4";
Justin Holewinskieafe26d2014-06-27 18:35:37 +0000[diff] [blame^]344 case NVPTXISD::FUN_SHFL_CLAMP:
345 return "NVPTXISD::FUN_SHFL_CLAMP";
346 case NVPTXISD::FUN_SHFR_CLAMP:
347 return "NVPTXISD::FUN_SHFR_CLAMP";
Justin Holewinski30d56a72014-04-09 15:39:15 +0000[diff] [blame]348 case NVPTXISD::Tex1DFloatI32: return "NVPTXISD::Tex1DFloatI32";
349 case NVPTXISD::Tex1DFloatFloat: return "NVPTXISD::Tex1DFloatFloat";
350 case NVPTXISD::Tex1DFloatFloatLevel:
351 return "NVPTXISD::Tex1DFloatFloatLevel";
352 case NVPTXISD::Tex1DFloatFloatGrad:
353 return "NVPTXISD::Tex1DFloatFloatGrad";
354 case NVPTXISD::Tex1DI32I32: return "NVPTXISD::Tex1DI32I32";
355 case NVPTXISD::Tex1DI32Float: return "NVPTXISD::Tex1DI32Float";
356 case NVPTXISD::Tex1DI32FloatLevel:
357 return "NVPTXISD::Tex1DI32FloatLevel";
358 case NVPTXISD::Tex1DI32FloatGrad:
359 return "NVPTXISD::Tex1DI32FloatGrad";
360 case NVPTXISD::Tex1DArrayFloatI32: return "NVPTXISD::Tex2DArrayFloatI32";
361 case NVPTXISD::Tex1DArrayFloatFloat: return "NVPTXISD::Tex2DArrayFloatFloat";
362 case NVPTXISD::Tex1DArrayFloatFloatLevel:
363 return "NVPTXISD::Tex2DArrayFloatFloatLevel";
364 case NVPTXISD::Tex1DArrayFloatFloatGrad:
365 return "NVPTXISD::Tex2DArrayFloatFloatGrad";
366 case NVPTXISD::Tex1DArrayI32I32: return "NVPTXISD::Tex2DArrayI32I32";
367 case NVPTXISD::Tex1DArrayI32Float: return "NVPTXISD::Tex2DArrayI32Float";
368 case NVPTXISD::Tex1DArrayI32FloatLevel:
369 return "NVPTXISD::Tex2DArrayI32FloatLevel";
370 case NVPTXISD::Tex1DArrayI32FloatGrad:
371 return "NVPTXISD::Tex2DArrayI32FloatGrad";
372 case NVPTXISD::Tex2DFloatI32: return "NVPTXISD::Tex2DFloatI32";
373 case NVPTXISD::Tex2DFloatFloat: return "NVPTXISD::Tex2DFloatFloat";
374 case NVPTXISD::Tex2DFloatFloatLevel:
375 return "NVPTXISD::Tex2DFloatFloatLevel";
376 case NVPTXISD::Tex2DFloatFloatGrad:
377 return "NVPTXISD::Tex2DFloatFloatGrad";
378 case NVPTXISD::Tex2DI32I32: return "NVPTXISD::Tex2DI32I32";
379 case NVPTXISD::Tex2DI32Float: return "NVPTXISD::Tex2DI32Float";
380 case NVPTXISD::Tex2DI32FloatLevel:
381 return "NVPTXISD::Tex2DI32FloatLevel";
382 case NVPTXISD::Tex2DI32FloatGrad:
383 return "NVPTXISD::Tex2DI32FloatGrad";
384 case NVPTXISD::Tex2DArrayFloatI32: return "NVPTXISD::Tex2DArrayFloatI32";
385 case NVPTXISD::Tex2DArrayFloatFloat: return "NVPTXISD::Tex2DArrayFloatFloat";
386 case NVPTXISD::Tex2DArrayFloatFloatLevel:
387 return "NVPTXISD::Tex2DArrayFloatFloatLevel";
388 case NVPTXISD::Tex2DArrayFloatFloatGrad:
389 return "NVPTXISD::Tex2DArrayFloatFloatGrad";
390 case NVPTXISD::Tex2DArrayI32I32: return "NVPTXISD::Tex2DArrayI32I32";
391 case NVPTXISD::Tex2DArrayI32Float: return "NVPTXISD::Tex2DArrayI32Float";
392 case NVPTXISD::Tex2DArrayI32FloatLevel:
393 return "NVPTXISD::Tex2DArrayI32FloatLevel";
394 case NVPTXISD::Tex2DArrayI32FloatGrad:
395 return "NVPTXISD::Tex2DArrayI32FloatGrad";
396 case NVPTXISD::Tex3DFloatI32: return "NVPTXISD::Tex3DFloatI32";
397 case NVPTXISD::Tex3DFloatFloat: return "NVPTXISD::Tex3DFloatFloat";
398 case NVPTXISD::Tex3DFloatFloatLevel:
399 return "NVPTXISD::Tex3DFloatFloatLevel";
400 case NVPTXISD::Tex3DFloatFloatGrad:
401 return "NVPTXISD::Tex3DFloatFloatGrad";
402 case NVPTXISD::Tex3DI32I32: return "NVPTXISD::Tex3DI32I32";
403 case NVPTXISD::Tex3DI32Float: return "NVPTXISD::Tex3DI32Float";
404 case NVPTXISD::Tex3DI32FloatLevel:
405 return "NVPTXISD::Tex3DI32FloatLevel";
406 case NVPTXISD::Tex3DI32FloatGrad:
407 return "NVPTXISD::Tex3DI32FloatGrad";
408
409 case NVPTXISD::Suld1DI8Trap: return "NVPTXISD::Suld1DI8Trap";
410 case NVPTXISD::Suld1DI16Trap: return "NVPTXISD::Suld1DI16Trap";
411 case NVPTXISD::Suld1DI32Trap: return "NVPTXISD::Suld1DI32Trap";
412 case NVPTXISD::Suld1DV2I8Trap: return "NVPTXISD::Suld1DV2I8Trap";
413 case NVPTXISD::Suld1DV2I16Trap: return "NVPTXISD::Suld1DV2I16Trap";
414 case NVPTXISD::Suld1DV2I32Trap: return "NVPTXISD::Suld1DV2I32Trap";
415 case NVPTXISD::Suld1DV4I8Trap: return "NVPTXISD::Suld1DV4I8Trap";
416 case NVPTXISD::Suld1DV4I16Trap: return "NVPTXISD::Suld1DV4I16Trap";
417 case NVPTXISD::Suld1DV4I32Trap: return "NVPTXISD::Suld1DV4I32Trap";
418
419 case NVPTXISD::Suld1DArrayI8Trap: return "NVPTXISD::Suld1DArrayI8Trap";
420 case NVPTXISD::Suld1DArrayI16Trap: return "NVPTXISD::Suld1DArrayI16Trap";
421 case NVPTXISD::Suld1DArrayI32Trap: return "NVPTXISD::Suld1DArrayI32Trap";
422 case NVPTXISD::Suld1DArrayV2I8Trap: return "NVPTXISD::Suld1DArrayV2I8Trap";
423 case NVPTXISD::Suld1DArrayV2I16Trap: return "NVPTXISD::Suld1DArrayV2I16Trap";
424 case NVPTXISD::Suld1DArrayV2I32Trap: return "NVPTXISD::Suld1DArrayV2I32Trap";
425 case NVPTXISD::Suld1DArrayV4I8Trap: return "NVPTXISD::Suld1DArrayV4I8Trap";
426 case NVPTXISD::Suld1DArrayV4I16Trap: return "NVPTXISD::Suld1DArrayV4I16Trap";
427 case NVPTXISD::Suld1DArrayV4I32Trap: return "NVPTXISD::Suld1DArrayV4I32Trap";
428
429 case NVPTXISD::Suld2DI8Trap: return "NVPTXISD::Suld2DI8Trap";
430 case NVPTXISD::Suld2DI16Trap: return "NVPTXISD::Suld2DI16Trap";
431 case NVPTXISD::Suld2DI32Trap: return "NVPTXISD::Suld2DI32Trap";
432 case NVPTXISD::Suld2DV2I8Trap: return "NVPTXISD::Suld2DV2I8Trap";
433 case NVPTXISD::Suld2DV2I16Trap: return "NVPTXISD::Suld2DV2I16Trap";
434 case NVPTXISD::Suld2DV2I32Trap: return "NVPTXISD::Suld2DV2I32Trap";
435 case NVPTXISD::Suld2DV4I8Trap: return "NVPTXISD::Suld2DV4I8Trap";
436 case NVPTXISD::Suld2DV4I16Trap: return "NVPTXISD::Suld2DV4I16Trap";
437 case NVPTXISD::Suld2DV4I32Trap: return "NVPTXISD::Suld2DV4I32Trap";
438
439 case NVPTXISD::Suld2DArrayI8Trap: return "NVPTXISD::Suld2DArrayI8Trap";
440 case NVPTXISD::Suld2DArrayI16Trap: return "NVPTXISD::Suld2DArrayI16Trap";
441 case NVPTXISD::Suld2DArrayI32Trap: return "NVPTXISD::Suld2DArrayI32Trap";
442 case NVPTXISD::Suld2DArrayV2I8Trap: return "NVPTXISD::Suld2DArrayV2I8Trap";
443 case NVPTXISD::Suld2DArrayV2I16Trap: return "NVPTXISD::Suld2DArrayV2I16Trap";
444 case NVPTXISD::Suld2DArrayV2I32Trap: return "NVPTXISD::Suld2DArrayV2I32Trap";
445 case NVPTXISD::Suld2DArrayV4I8Trap: return "NVPTXISD::Suld2DArrayV4I8Trap";
446 case NVPTXISD::Suld2DArrayV4I16Trap: return "NVPTXISD::Suld2DArrayV4I16Trap";
447 case NVPTXISD::Suld2DArrayV4I32Trap: return "NVPTXISD::Suld2DArrayV4I32Trap";
448
449 case NVPTXISD::Suld3DI8Trap: return "NVPTXISD::Suld3DI8Trap";
450 case NVPTXISD::Suld3DI16Trap: return "NVPTXISD::Suld3DI16Trap";
451 case NVPTXISD::Suld3DI32Trap: return "NVPTXISD::Suld3DI32Trap";
452 case NVPTXISD::Suld3DV2I8Trap: return "NVPTXISD::Suld3DV2I8Trap";
453 case NVPTXISD::Suld3DV2I16Trap: return "NVPTXISD::Suld3DV2I16Trap";
454 case NVPTXISD::Suld3DV2I32Trap: return "NVPTXISD::Suld3DV2I32Trap";
455 case NVPTXISD::Suld3DV4I8Trap: return "NVPTXISD::Suld3DV4I8Trap";
456 case NVPTXISD::Suld3DV4I16Trap: return "NVPTXISD::Suld3DV4I16Trap";
457 case NVPTXISD::Suld3DV4I32Trap: return "NVPTXISD::Suld3DV4I32Trap";
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]458 }
459}
460
Matt Arsenaultf751d622014-03-31 20:54:58 +0000[diff] [blame]461bool NVPTXTargetLowering::shouldSplitVectorType(EVT VT) const {
462 return VT.getScalarType() == MVT::i1;
Justin Holewinskibc451192012-11-29 14:26:24 +0000[diff] [blame]463}
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]464
465SDValue
466NVPTXTargetLowering::LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const {
Andrew Trickef9de2a2013-05-25 02:42:55 +0000[diff] [blame]467 SDLoc dl(Op);
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]468 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
469 Op = DAG.getTargetGlobalAddress(GV, dl, getPointerTy());
470 return DAG.getNode(NVPTXISD::Wrapper, dl, getPointerTy(), Op);
471}
472
Justin Holewinskif8f70912013-06-28 17:57:59 +0000[diff] [blame]473std::string
474NVPTXTargetLowering::getPrototype(Type *retTy, const ArgListTy &Args,
475 const SmallVectorImpl<ISD::OutputArg> &Outs,
476 unsigned retAlignment,
477 const ImmutableCallSite *CS) const {
478
479 bool isABI = (nvptxSubtarget.getSmVersion() >= 20);
480 assert(isABI && "Non-ABI compilation is not supported");
481 if (!isABI)
482 return "";
483
484 std::stringstream O;
485 O << "prototype_" << uniqueCallSite << " : .callprototype ";
486
487 if (retTy->getTypeID() == Type::VoidTyID) {
488 O << "()";
489 } else {
490 O << "(";
Rafael Espindola08013342013-12-07 19:34:20 +0000[diff] [blame]491 if (retTy->isFloatingPointTy() || retTy->isIntegerTy()) {
Justin Holewinskif8f70912013-06-28 17:57:59 +0000[diff] [blame]492 unsigned size = 0;
493 if (const IntegerType *ITy = dyn_cast<IntegerType>(retTy)) {
494 size = ITy->getBitWidth();
495 if (size < 32)
496 size = 32;
497 } else {
498 assert(retTy->isFloatingPointTy() &&
499 "Floating point type expected here");
500 size = retTy->getPrimitiveSizeInBits();
501 }
502
503 O << ".param .b" << size << " _";
504 } else if (isa<PointerType>(retTy)) {
505 O << ".param .b" << getPointerTy().getSizeInBits() << " _";
506 } else {
507 if ((retTy->getTypeID() == Type::StructTyID) || isa<VectorType>(retTy)) {
508 SmallVector<EVT, 16> vtparts;
509 ComputeValueVTs(*this, retTy, vtparts);
510 unsigned totalsz = 0;
511 for (unsigned i = 0, e = vtparts.size(); i != e; ++i) {
512 unsigned elems = 1;
513 EVT elemtype = vtparts[i];
514 if (vtparts[i].isVector()) {
515 elems = vtparts[i].getVectorNumElements();
516 elemtype = vtparts[i].getVectorElementType();
517 }
518 // TODO: no need to loop
519 for (unsigned j = 0, je = elems; j != je; ++j) {
520 unsigned sz = elemtype.getSizeInBits();
521 if (elemtype.isInteger() && (sz < 8))
522 sz = 8;
523 totalsz += sz / 8;
524 }
525 }
526 O << ".param .align " << retAlignment << " .b8 _[" << totalsz << "]";
527 } else {
528 assert(false && "Unknown return type");
529 }
530 }
531 O << ") ";
532 }
533 O << "_ (";
534
535 bool first = true;
536 MVT thePointerTy = getPointerTy();
537
538 unsigned OIdx = 0;
539 for (unsigned i = 0, e = Args.size(); i != e; ++i, ++OIdx) {
540 Type *Ty = Args[i].Ty;
541 if (!first) {
542 O << ", ";
543 }
544 first = false;
545
546 if (Outs[OIdx].Flags.isByVal() == false) {
547 if (Ty->isAggregateType() || Ty->isVectorTy()) {
548 unsigned align = 0;
549 const CallInst *CallI = cast<CallInst>(CS->getInstruction());
550 const DataLayout *TD = getDataLayout();
551 // +1 because index 0 is reserved for return type alignment
552 if (!llvm::getAlign(*CallI, i + 1, align))
553 align = TD->getABITypeAlignment(Ty);
554 unsigned sz = TD->getTypeAllocSize(Ty);
555 O << ".param .align " << align << " .b8 ";
556 O << "_";
557 O << "[" << sz << "]";
558 // update the index for Outs
559 SmallVector<EVT, 16> vtparts;
560 ComputeValueVTs(*this, Ty, vtparts);
561 if (unsigned len = vtparts.size())
562 OIdx += len - 1;
563 continue;
564 }
Justin Holewinskidff28d22013-07-01 12:59:01 +0000[diff] [blame]565 // i8 types in IR will be i16 types in SDAG
566 assert((getValueType(Ty) == Outs[OIdx].VT ||
567 (getValueType(Ty) == MVT::i8 && Outs[OIdx].VT == MVT::i16)) &&
Justin Holewinskif8f70912013-06-28 17:57:59 +0000[diff] [blame]568 "type mismatch between callee prototype and arguments");
569 // scalar type
570 unsigned sz = 0;
571 if (isa<IntegerType>(Ty)) {
572 sz = cast<IntegerType>(Ty)->getBitWidth();
573 if (sz < 32)
574 sz = 32;
575 } else if (isa<PointerType>(Ty))
576 sz = thePointerTy.getSizeInBits();
577 else
578 sz = Ty->getPrimitiveSizeInBits();
579 O << ".param .b" << sz << " ";
580 O << "_";
581 continue;
582 }
583 const PointerType *PTy = dyn_cast<PointerType>(Ty);
584 assert(PTy && "Param with byval attribute should be a pointer type");
585 Type *ETy = PTy->getElementType();
586
587 unsigned align = Outs[OIdx].Flags.getByValAlign();
588 unsigned sz = getDataLayout()->getTypeAllocSize(ETy);
589 O << ".param .align " << align << " .b8 ";
590 O << "_";
591 O << "[" << sz << "]";
592 }
593 O << ");";
594 return O.str();
595}
596
597unsigned
598NVPTXTargetLowering::getArgumentAlignment(SDValue Callee,
599 const ImmutableCallSite *CS,
600 Type *Ty,
601 unsigned Idx) const {
602 const DataLayout *TD = getDataLayout();
Justin Holewinski124e93d2013-11-11 19:28:19 +0000[diff] [blame]603 unsigned Align = 0;
604 const Value *DirectCallee = CS->getCalledFunction();
Justin Holewinskif8f70912013-06-28 17:57:59 +0000[diff] [blame]605
Justin Holewinski124e93d2013-11-11 19:28:19 +0000[diff] [blame]606 if (!DirectCallee) {
607 // We don't have a direct function symbol, but that may be because of
608 // constant cast instructions in the call.
609 const Instruction *CalleeI = CS->getInstruction();
610 assert(CalleeI && "Call target is not a function or derived value?");
611
612 // With bitcast'd call targets, the instruction will be the call
613 if (isa<CallInst>(CalleeI)) {
614 // Check if we have call alignment metadata
615 if (llvm::getAlign(*cast<CallInst>(CalleeI), Idx, Align))
616 return Align;
617
618 const Value *CalleeV = cast<CallInst>(CalleeI)->getCalledValue();
619 // Ignore any bitcast instructions
620 while(isa<ConstantExpr>(CalleeV)) {
621 const ConstantExpr *CE = cast<ConstantExpr>(CalleeV);
622 if (!CE->isCast())
623 break;
624 // Look through the bitcast
625 CalleeV = cast<ConstantExpr>(CalleeV)->getOperand(0);
626 }
627
628 // We have now looked past all of the bitcasts. Do we finally have a
629 // Function?
630 if (isa<Function>(CalleeV))
631 DirectCallee = CalleeV;
632 }
Justin Holewinskif8f70912013-06-28 17:57:59 +0000[diff] [blame]633 }
634
Justin Holewinski124e93d2013-11-11 19:28:19 +0000[diff] [blame]635 // Check for function alignment information if we found that the
636 // ultimate target is a Function
637 if (DirectCallee)
638 if (llvm::getAlign(*cast<Function>(DirectCallee), Idx, Align))
639 return Align;
640
641 // Call is indirect or alignment information is not available, fall back to
642 // the ABI type alignment
643 return TD->getABITypeAlignment(Ty);
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]644}
645
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]646SDValue NVPTXTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
647 SmallVectorImpl<SDValue> &InVals) const {
648 SelectionDAG &DAG = CLI.DAG;
Andrew Trickef9de2a2013-05-25 02:42:55 +0000[diff] [blame]649 SDLoc dl = CLI.DL;
Craig Topperb94011f2013-07-14 04:42:23 +0000[diff] [blame]650 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
651 SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;
652 SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins;
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]653 SDValue Chain = CLI.Chain;
654 SDValue Callee = CLI.Callee;
655 bool &isTailCall = CLI.IsTailCall;
Saleem Abdulrasool9f664c12014-05-17 21:50:01 +0000[diff] [blame]656 ArgListTy &Args = CLI.getArgs();
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]657 Type *retTy = CLI.RetTy;
658 ImmutableCallSite *CS = CLI.CS;
Justin Holewinskiaa583972012-05-25 16:35:28 +0000[diff] [blame]659
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]660 bool isABI = (nvptxSubtarget.getSmVersion() >= 20);
Justin Holewinskif8f70912013-06-28 17:57:59 +0000[diff] [blame]661 assert(isABI && "Non-ABI compilation is not supported");
662 if (!isABI)
663 return Chain;
664 const DataLayout *TD = getDataLayout();
665 MachineFunction &MF = DAG.getMachineFunction();
666 const Function *F = MF.getFunction();
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]667
668 SDValue tempChain = Chain;
Justin Holewinskif8f70912013-06-28 17:57:59 +0000[diff] [blame]669 Chain =
670 DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(uniqueCallSite, true),
671 dl);
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]672 SDValue InFlag = Chain.getValue(1);
673
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]674 unsigned paramCount = 0;
Justin Holewinskif8f70912013-06-28 17:57:59 +0000[diff] [blame]675 // Args.size() and Outs.size() need not match.
676 // Outs.size() will be larger
677 // * if there is an aggregate argument with multiple fields (each field
678 // showing up separately in Outs)
679 // * if there is a vector argument with more than typical vector-length
680 // elements (generally if more than 4) where each vector element is
681 // individually present in Outs.
682 // So a different index should be used for indexing into Outs/OutVals.
683 // See similar issue in LowerFormalArguments.
684 unsigned OIdx = 0;
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]685 // Declare the .params or .reg need to pass values
686 // to the function
Justin Holewinskif8f70912013-06-28 17:57:59 +0000[diff] [blame]687 for (unsigned i = 0, e = Args.size(); i != e; ++i, ++OIdx) {
688 EVT VT = Outs[OIdx].VT;
689 Type *Ty = Args[i].Ty;
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]690
Justin Holewinskif8f70912013-06-28 17:57:59 +0000[diff] [blame]691 if (Outs[OIdx].Flags.isByVal() == false) {
692 if (Ty->isAggregateType()) {
693 // aggregate
694 SmallVector<EVT, 16> vtparts;
695 ComputeValueVTs(*this, Ty, vtparts);
696
697 unsigned align = getArgumentAlignment(Callee, CS, Ty, paramCount + 1);
698 // declare .param .align <align> .b8 .param<n>[<size>];
699 unsigned sz = TD->getTypeAllocSize(Ty);
700 SDVTList DeclareParamVTs = DAG.getVTList(MVT::Other, MVT::Glue);
701 SDValue DeclareParamOps[] = { Chain, DAG.getConstant(align, MVT::i32),
702 DAG.getConstant(paramCount, MVT::i32),
703 DAG.getConstant(sz, MVT::i32), InFlag };
704 Chain = DAG.getNode(NVPTXISD::DeclareParam, dl, DeclareParamVTs,
Craig Topper48d114b2014-04-26 18:35:24 +0000[diff] [blame]705 DeclareParamOps);
Justin Holewinskif8f70912013-06-28 17:57:59 +0000[diff] [blame]706 InFlag = Chain.getValue(1);
707 unsigned curOffset = 0;
708 for (unsigned j = 0, je = vtparts.size(); j != je; ++j) {
709 unsigned elems = 1;
710 EVT elemtype = vtparts[j];
711 if (vtparts[j].isVector()) {
712 elems = vtparts[j].getVectorNumElements();
713 elemtype = vtparts[j].getVectorElementType();
714 }
715 for (unsigned k = 0, ke = elems; k != ke; ++k) {
716 unsigned sz = elemtype.getSizeInBits();
717 if (elemtype.isInteger() && (sz < 8))
718 sz = 8;
719 SDValue StVal = OutVals[OIdx];
720 if (elemtype.getSizeInBits() < 16) {
Justin Holewinskia2911282013-07-01 12:58:58 +0000[diff] [blame]721 StVal = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i16, StVal);
Justin Holewinskif8f70912013-06-28 17:57:59 +0000[diff] [blame]722 }
723 SDVTList CopyParamVTs = DAG.getVTList(MVT::Other, MVT::Glue);
724 SDValue CopyParamOps[] = { Chain,
725 DAG.getConstant(paramCount, MVT::i32),
726 DAG.getConstant(curOffset, MVT::i32),
727 StVal, InFlag };
728 Chain = DAG.getMemIntrinsicNode(NVPTXISD::StoreParam, dl,
Craig Topper206fcd42014-04-26 19:29:41 +0000[diff] [blame]729 CopyParamVTs, CopyParamOps,
Justin Holewinskif8f70912013-06-28 17:57:59 +0000[diff] [blame]730 elemtype, MachinePointerInfo());
731 InFlag = Chain.getValue(1);
732 curOffset += sz / 8;
733 ++OIdx;
734 }
735 }
736 if (vtparts.size() > 0)
737 --OIdx;
738 ++paramCount;
739 continue;
740 }
741 if (Ty->isVectorTy()) {
742 EVT ObjectVT = getValueType(Ty);
743 unsigned align = getArgumentAlignment(Callee, CS, Ty, paramCount + 1);
744 // declare .param .align <align> .b8 .param<n>[<size>];
745 unsigned sz = TD->getTypeAllocSize(Ty);
746 SDVTList DeclareParamVTs = DAG.getVTList(MVT::Other, MVT::Glue);
747 SDValue DeclareParamOps[] = { Chain, DAG.getConstant(align, MVT::i32),
748 DAG.getConstant(paramCount, MVT::i32),
749 DAG.getConstant(sz, MVT::i32), InFlag };
750 Chain = DAG.getNode(NVPTXISD::DeclareParam, dl, DeclareParamVTs,
Craig Topper48d114b2014-04-26 18:35:24 +0000[diff] [blame]751 DeclareParamOps);
Justin Holewinskif8f70912013-06-28 17:57:59 +0000[diff] [blame]752 InFlag = Chain.getValue(1);
753 unsigned NumElts = ObjectVT.getVectorNumElements();
754 EVT EltVT = ObjectVT.getVectorElementType();
755 EVT MemVT = EltVT;
756 bool NeedExtend = false;
757 if (EltVT.getSizeInBits() < 16) {
758 NeedExtend = true;
759 EltVT = MVT::i16;
760 }
761
762 // V1 store
763 if (NumElts == 1) {
764 SDValue Elt = OutVals[OIdx++];
765 if (NeedExtend)
766 Elt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, Elt);
767
768 SDVTList CopyParamVTs = DAG.getVTList(MVT::Other, MVT::Glue);
769 SDValue CopyParamOps[] = { Chain,
770 DAG.getConstant(paramCount, MVT::i32),
771 DAG.getConstant(0, MVT::i32), Elt,
772 InFlag };
773 Chain = DAG.getMemIntrinsicNode(NVPTXISD::StoreParam, dl,
Craig Topper206fcd42014-04-26 19:29:41 +0000[diff] [blame]774 CopyParamVTs, CopyParamOps,
Justin Holewinskif8f70912013-06-28 17:57:59 +0000[diff] [blame]775 MemVT, MachinePointerInfo());
776 InFlag = Chain.getValue(1);
777 } else if (NumElts == 2) {
778 SDValue Elt0 = OutVals[OIdx++];
779 SDValue Elt1 = OutVals[OIdx++];
780 if (NeedExtend) {
781 Elt0 = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, Elt0);
782 Elt1 = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, Elt1);
783 }
784
785 SDVTList CopyParamVTs = DAG.getVTList(MVT::Other, MVT::Glue);
786 SDValue CopyParamOps[] = { Chain,
787 DAG.getConstant(paramCount, MVT::i32),
788 DAG.getConstant(0, MVT::i32), Elt0, Elt1,
789 InFlag };
790 Chain = DAG.getMemIntrinsicNode(NVPTXISD::StoreParamV2, dl,
Craig Topper206fcd42014-04-26 19:29:41 +0000[diff] [blame]791 CopyParamVTs, CopyParamOps,
Justin Holewinskif8f70912013-06-28 17:57:59 +0000[diff] [blame]792 MemVT, MachinePointerInfo());
793 InFlag = Chain.getValue(1);
794 } else {
795 unsigned curOffset = 0;
796 // V4 stores
797 // We have at least 4 elements (<3 x Ty> expands to 4 elements) and
798 // the
799 // vector will be expanded to a power of 2 elements, so we know we can
800 // always round up to the next multiple of 4 when creating the vector
801 // stores.
802 // e.g. 4 elem => 1 st.v4
803 // 6 elem => 2 st.v4
804 // 8 elem => 2 st.v4
805 // 11 elem => 3 st.v4
806 unsigned VecSize = 4;
807 if (EltVT.getSizeInBits() == 64)
808 VecSize = 2;
809
810 // This is potentially only part of a vector, so assume all elements
811 // are packed together.
812 unsigned PerStoreOffset = MemVT.getStoreSizeInBits() / 8 * VecSize;
813
814 for (unsigned i = 0; i < NumElts; i += VecSize) {
815 // Get values
816 SDValue StoreVal;
817 SmallVector<SDValue, 8> Ops;
818 Ops.push_back(Chain);
819 Ops.push_back(DAG.getConstant(paramCount, MVT::i32));
820 Ops.push_back(DAG.getConstant(curOffset, MVT::i32));
821
822 unsigned Opc = NVPTXISD::StoreParamV2;
823
824 StoreVal = OutVals[OIdx++];
825 if (NeedExtend)
826 StoreVal = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, StoreVal);
827 Ops.push_back(StoreVal);
828
829 if (i + 1 < NumElts) {
830 StoreVal = OutVals[OIdx++];
831 if (NeedExtend)
832 StoreVal =
833 DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, StoreVal);
834 } else {
835 StoreVal = DAG.getUNDEF(EltVT);
836 }
837 Ops.push_back(StoreVal);
838
839 if (VecSize == 4) {
840 Opc = NVPTXISD::StoreParamV4;
841 if (i + 2 < NumElts) {
842 StoreVal = OutVals[OIdx++];
843 if (NeedExtend)
844 StoreVal =
845 DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, StoreVal);
846 } else {
847 StoreVal = DAG.getUNDEF(EltVT);
848 }
849 Ops.push_back(StoreVal);
850
851 if (i + 3 < NumElts) {
852 StoreVal = OutVals[OIdx++];
853 if (NeedExtend)
854 StoreVal =
855 DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, StoreVal);
856 } else {
857 StoreVal = DAG.getUNDEF(EltVT);
858 }
859 Ops.push_back(StoreVal);
860 }
861
Justin Holewinskidff28d22013-07-01 12:59:01 +0000[diff] [blame]862 Ops.push_back(InFlag);
863
Justin Holewinskif8f70912013-06-28 17:57:59 +0000[diff] [blame]864 SDVTList CopyParamVTs = DAG.getVTList(MVT::Other, MVT::Glue);
Craig Topper206fcd42014-04-26 19:29:41 +0000[diff] [blame]865 Chain = DAG.getMemIntrinsicNode(Opc, dl, CopyParamVTs, Ops,
866 MemVT, MachinePointerInfo());
Justin Holewinskif8f70912013-06-28 17:57:59 +0000[diff] [blame]867 InFlag = Chain.getValue(1);
868 curOffset += PerStoreOffset;
869 }
870 }
871 ++paramCount;
872 --OIdx;
873 continue;
874 }
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]875 // Plain scalar
876 // for ABI, declare .param .b<size> .param<n>;
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]877 unsigned sz = VT.getSizeInBits();
Justin Holewinskif8f70912013-06-28 17:57:59 +0000[diff] [blame]878 bool needExtend = false;
879 if (VT.isInteger()) {
880 if (sz < 16)
881 needExtend = true;
882 if (sz < 32)
883 sz = 32;
884 }
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]885 SDVTList DeclareParamVTs = DAG.getVTList(MVT::Other, MVT::Glue);
886 SDValue DeclareParamOps[] = { Chain,
887 DAG.getConstant(paramCount, MVT::i32),
888 DAG.getConstant(sz, MVT::i32),
Justin Holewinskif8f70912013-06-28 17:57:59 +0000[diff] [blame]889 DAG.getConstant(0, MVT::i32), InFlag };
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]890 Chain = DAG.getNode(NVPTXISD::DeclareScalarParam, dl, DeclareParamVTs,
Craig Topper48d114b2014-04-26 18:35:24 +0000[diff] [blame]891 DeclareParamOps);
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]892 InFlag = Chain.getValue(1);
Justin Holewinskif8f70912013-06-28 17:57:59 +0000[diff] [blame]893 SDValue OutV = OutVals[OIdx];
894 if (needExtend) {
895 // zext/sext i1 to i16
896 unsigned opc = ISD::ZERO_EXTEND;
897 if (Outs[OIdx].Flags.isSExt())
898 opc = ISD::SIGN_EXTEND;
899 OutV = DAG.getNode(opc, dl, MVT::i16, OutV);
900 }
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]901 SDVTList CopyParamVTs = DAG.getVTList(MVT::Other, MVT::Glue);
902 SDValue CopyParamOps[] = { Chain, DAG.getConstant(paramCount, MVT::i32),
Justin Holewinskif8f70912013-06-28 17:57:59 +0000[diff] [blame]903 DAG.getConstant(0, MVT::i32), OutV, InFlag };
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]904
905 unsigned opcode = NVPTXISD::StoreParam;
Justin Holewinskif8f70912013-06-28 17:57:59 +0000[diff] [blame]906 if (Outs[OIdx].Flags.isZExt())
907 opcode = NVPTXISD::StoreParamU32;
908 else if (Outs[OIdx].Flags.isSExt())
909 opcode = NVPTXISD::StoreParamS32;
Craig Topper206fcd42014-04-26 19:29:41 +0000[diff] [blame]910 Chain = DAG.getMemIntrinsicNode(opcode, dl, CopyParamVTs, CopyParamOps,
Justin Holewinskif8f70912013-06-28 17:57:59 +0000[diff] [blame]911 VT, MachinePointerInfo());
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]912
913 InFlag = Chain.getValue(1);
914 ++paramCount;
915 continue;
916 }
917 // struct or vector
918 SmallVector<EVT, 16> vtparts;
919 const PointerType *PTy = dyn_cast<PointerType>(Args[i].Ty);
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]920 assert(PTy && "Type of a byval parameter should be pointer");
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]921 ComputeValueVTs(*this, PTy->getElementType(), vtparts);
922
Justin Holewinskif8f70912013-06-28 17:57:59 +0000[diff] [blame]923 // declare .param .align <align> .b8 .param<n>[<size>];
924 unsigned sz = Outs[OIdx].Flags.getByValSize();
925 SDVTList DeclareParamVTs = DAG.getVTList(MVT::Other, MVT::Glue);
926 // The ByValAlign in the Outs[OIdx].Flags is alway set at this point,
927 // so we don't need to worry about natural alignment or not.
928 // See TargetLowering::LowerCallTo().
929 SDValue DeclareParamOps[] = {
930 Chain, DAG.getConstant(Outs[OIdx].Flags.getByValAlign(), MVT::i32),
931 DAG.getConstant(paramCount, MVT::i32), DAG.getConstant(sz, MVT::i32),
932 InFlag
933 };
934 Chain = DAG.getNode(NVPTXISD::DeclareParam, dl, DeclareParamVTs,
Craig Topper48d114b2014-04-26 18:35:24 +0000[diff] [blame]935 DeclareParamOps);
Justin Holewinskif8f70912013-06-28 17:57:59 +0000[diff] [blame]936 InFlag = Chain.getValue(1);
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]937 unsigned curOffset = 0;
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]938 for (unsigned j = 0, je = vtparts.size(); j != je; ++j) {
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]939 unsigned elems = 1;
940 EVT elemtype = vtparts[j];
941 if (vtparts[j].isVector()) {
942 elems = vtparts[j].getVectorNumElements();
943 elemtype = vtparts[j].getVectorElementType();
944 }
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]945 for (unsigned k = 0, ke = elems; k != ke; ++k) {
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]946 unsigned sz = elemtype.getSizeInBits();
Justin Holewinskif8f70912013-06-28 17:57:59 +0000[diff] [blame]947 if (elemtype.isInteger() && (sz < 8))
948 sz = 8;
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]949 SDValue srcAddr =
Justin Holewinskif8f70912013-06-28 17:57:59 +0000[diff] [blame]950 DAG.getNode(ISD::ADD, dl, getPointerTy(), OutVals[OIdx],
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]951 DAG.getConstant(curOffset, getPointerTy()));
Justin Holewinskif8f70912013-06-28 17:57:59 +0000[diff] [blame]952 SDValue theVal = DAG.getLoad(elemtype, dl, tempChain, srcAddr,
953 MachinePointerInfo(), false, false, false,
954 0);
955 if (elemtype.getSizeInBits() < 16) {
Justin Holewinskia2911282013-07-01 12:58:58 +0000[diff] [blame]956 theVal = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i16, theVal);
Justin Holewinskif8f70912013-06-28 17:57:59 +0000[diff] [blame]957 }
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]958 SDVTList CopyParamVTs = DAG.getVTList(MVT::Other, MVT::Glue);
959 SDValue CopyParamOps[] = { Chain, DAG.getConstant(paramCount, MVT::i32),
Justin Holewinskif8f70912013-06-28 17:57:59 +0000[diff] [blame]960 DAG.getConstant(curOffset, MVT::i32), theVal,
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]961 InFlag };
Justin Holewinskif8f70912013-06-28 17:57:59 +0000[diff] [blame]962 Chain = DAG.getMemIntrinsicNode(NVPTXISD::StoreParam, dl, CopyParamVTs,
Craig Topper206fcd42014-04-26 19:29:41 +0000[diff] [blame]963 CopyParamOps, elemtype,
Justin Holewinskif8f70912013-06-28 17:57:59 +0000[diff] [blame]964 MachinePointerInfo());
965
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]966 InFlag = Chain.getValue(1);
Justin Holewinskif8f70912013-06-28 17:57:59 +0000[diff] [blame]967 curOffset += sz / 8;
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]968 }
969 }
Justin Holewinskif8f70912013-06-28 17:57:59 +0000[diff] [blame]970 ++paramCount;
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]971 }
972
973 GlobalAddressSDNode *Func = dyn_cast<GlobalAddressSDNode>(Callee.getNode());
974 unsigned retAlignment = 0;
975
976 // Handle Result
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]977 if (Ins.size() > 0) {
978 SmallVector<EVT, 16> resvtparts;
979 ComputeValueVTs(*this, retTy, resvtparts);
980
Justin Holewinskif8f70912013-06-28 17:57:59 +0000[diff] [blame]981 // Declare
982 // .param .align 16 .b8 retval0[<size-in-bytes>], or
983 // .param .b<size-in-bits> retval0
984 unsigned resultsz = TD->getTypeAllocSizeInBits(retTy);
Rafael Espindola08013342013-12-07 19:34:20 +0000[diff] [blame]985 if (retTy->isSingleValueType()) {
Justin Holewinskif8f70912013-06-28 17:57:59 +0000[diff] [blame]986 // Scalar needs to be at least 32bit wide
987 if (resultsz < 32)
988 resultsz = 32;
989 SDVTList DeclareRetVTs = DAG.getVTList(MVT::Other, MVT::Glue);
990 SDValue DeclareRetOps[] = { Chain, DAG.getConstant(1, MVT::i32),
991 DAG.getConstant(resultsz, MVT::i32),
992 DAG.getConstant(0, MVT::i32), InFlag };
993 Chain = DAG.getNode(NVPTXISD::DeclareRet, dl, DeclareRetVTs,
Craig Topper48d114b2014-04-26 18:35:24 +0000[diff] [blame]994 DeclareRetOps);
Justin Holewinskif8f70912013-06-28 17:57:59 +0000[diff] [blame]995 InFlag = Chain.getValue(1);
996 } else {
997 retAlignment = getArgumentAlignment(Callee, CS, retTy, 0);
998 SDVTList DeclareRetVTs = DAG.getVTList(MVT::Other, MVT::Glue);
999 SDValue DeclareRetOps[] = { Chain,
1000 DAG.getConstant(retAlignment, MVT::i32),
1001 DAG.getConstant(resultsz / 8, MVT::i32),
1002 DAG.getConstant(0, MVT::i32), InFlag };
1003 Chain = DAG.getNode(NVPTXISD::DeclareRetParam, dl, DeclareRetVTs,
Craig Topper48d114b2014-04-26 18:35:24 +0000[diff] [blame]1004 DeclareRetOps);
Justin Holewinskif8f70912013-06-28 17:57:59 +0000[diff] [blame]1005 InFlag = Chain.getValue(1);
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]1006 }
1007 }
1008
1009 if (!Func) {
1010 // This is indirect function call case : PTX requires a prototype of the
1011 // form
1012 // proto_0 : .callprototype(.param .b32 _) _ (.param .b32 _);
1013 // to be emitted, and the label has to used as the last arg of call
1014 // instruction.
Justin Holewinski3d49e5c2013-11-15 12:30:04 +0000[diff] [blame]1015 // The prototype is embedded in a string and put as the operand for a
1016 // CallPrototype SDNode which will print out to the value of the string.
1017 SDVTList ProtoVTs = DAG.getVTList(MVT::Other, MVT::Glue);
1018 std::string Proto = getPrototype(retTy, Args, Outs, retAlignment, CS);
1019 const char *ProtoStr =
1020 nvTM->getManagedStrPool()->getManagedString(Proto.c_str())->c_str();
1021 SDValue ProtoOps[] = {
1022 Chain, DAG.getTargetExternalSymbol(ProtoStr, MVT::i32), InFlag,
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]1023 };
Craig Topper48d114b2014-04-26 18:35:24 +0000[diff] [blame]1024 Chain = DAG.getNode(NVPTXISD::CallPrototype, dl, ProtoVTs, ProtoOps);
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]1025 InFlag = Chain.getValue(1);
1026 }
1027 // Op to just print "call"
1028 SDVTList PrintCallVTs = DAG.getVTList(MVT::Other, MVT::Glue);
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]1029 SDValue PrintCallOps[] = {
Justin Holewinskif8f70912013-06-28 17:57:59 +0000[diff] [blame]1030 Chain, DAG.getConstant((Ins.size() == 0) ? 0 : 1, MVT::i32), InFlag
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]1031 };
1032 Chain = DAG.getNode(Func ? (NVPTXISD::PrintCallUni) : (NVPTXISD::PrintCall),
Craig Topper48d114b2014-04-26 18:35:24 +0000[diff] [blame]1033 dl, PrintCallVTs, PrintCallOps);
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]1034 InFlag = Chain.getValue(1);
1035
1036 // Ops to print out the function name
1037 SDVTList CallVoidVTs = DAG.getVTList(MVT::Other, MVT::Glue);
1038 SDValue CallVoidOps[] = { Chain, Callee, InFlag };
Craig Topper48d114b2014-04-26 18:35:24 +0000[diff] [blame]1039 Chain = DAG.getNode(NVPTXISD::CallVoid, dl, CallVoidVTs, CallVoidOps);
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]1040 InFlag = Chain.getValue(1);
1041
1042 // Ops to print out the param list
1043 SDVTList CallArgBeginVTs = DAG.getVTList(MVT::Other, MVT::Glue);
1044 SDValue CallArgBeginOps[] = { Chain, InFlag };
1045 Chain = DAG.getNode(NVPTXISD::CallArgBegin, dl, CallArgBeginVTs,
Craig Topper48d114b2014-04-26 18:35:24 +0000[diff] [blame]1046 CallArgBeginOps);
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]1047 InFlag = Chain.getValue(1);
1048
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]1049 for (unsigned i = 0, e = paramCount; i != e; ++i) {
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]1050 unsigned opcode;
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]1051 if (i == (e - 1))
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]1052 opcode = NVPTXISD::LastCallArg;
1053 else
1054 opcode = NVPTXISD::CallArg;
1055 SDVTList CallArgVTs = DAG.getVTList(MVT::Other, MVT::Glue);
1056 SDValue CallArgOps[] = { Chain, DAG.getConstant(1, MVT::i32),
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]1057 DAG.getConstant(i, MVT::i32), InFlag };
Craig Topper48d114b2014-04-26 18:35:24 +0000[diff] [blame]1058 Chain = DAG.getNode(opcode, dl, CallArgVTs, CallArgOps);
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]1059 InFlag = Chain.getValue(1);
1060 }
1061 SDVTList CallArgEndVTs = DAG.getVTList(MVT::Other, MVT::Glue);
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]1062 SDValue CallArgEndOps[] = { Chain, DAG.getConstant(Func ? 1 : 0, MVT::i32),
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]1063 InFlag };
Craig Topper48d114b2014-04-26 18:35:24 +0000[diff] [blame]1064 Chain = DAG.getNode(NVPTXISD::CallArgEnd, dl, CallArgEndVTs, CallArgEndOps);
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]1065 InFlag = Chain.getValue(1);
1066
1067 if (!Func) {
1068 SDVTList PrototypeVTs = DAG.getVTList(MVT::Other, MVT::Glue);
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]1069 SDValue PrototypeOps[] = { Chain, DAG.getConstant(uniqueCallSite, MVT::i32),
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]1070 InFlag };
Craig Topper48d114b2014-04-26 18:35:24 +0000[diff] [blame]1071 Chain = DAG.getNode(NVPTXISD::Prototype, dl, PrototypeVTs, PrototypeOps);
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]1072 InFlag = Chain.getValue(1);
1073 }
1074
1075 // Generate loads from param memory/moves from registers for result
1076 if (Ins.size() > 0) {
Justin Holewinskif8f70912013-06-28 17:57:59 +0000[diff] [blame]1077 unsigned resoffset = 0;
1078 if (retTy && retTy->isVectorTy()) {
1079 EVT ObjectVT = getValueType(retTy);
1080 unsigned NumElts = ObjectVT.getVectorNumElements();
1081 EVT EltVT = ObjectVT.getVectorElementType();
Benjamin Kramer3cc579a2013-06-29 22:51:12 +0000[diff] [blame]1082 assert(nvTM->getTargetLowering()->getNumRegisters(F->getContext(),
1083 ObjectVT) == NumElts &&
Justin Holewinskif8f70912013-06-28 17:57:59 +0000[diff] [blame]1084 "Vector was not scalarized");
1085 unsigned sz = EltVT.getSizeInBits();
1086 bool needTruncate = sz < 16 ? true : false;
1087
1088 if (NumElts == 1) {
1089 // Just a simple load
Craig Topper59f626d2014-04-26 19:29:47 +0000[diff] [blame]1090 SmallVector<EVT, 4> LoadRetVTs;
Justin Holewinskif8f70912013-06-28 17:57:59 +0000[diff] [blame]1091 if (needTruncate) {
1092 // If loading i1 result, generate
1093 // load i16
1094 // trunc i16 to i1
1095 LoadRetVTs.push_back(MVT::i16);
1096 } else
1097 LoadRetVTs.push_back(EltVT);
1098 LoadRetVTs.push_back(MVT::Other);
1099 LoadRetVTs.push_back(MVT::Glue);
Craig Topper59f626d2014-04-26 19:29:47 +0000[diff] [blame]1100 SmallVector<SDValue, 4> LoadRetOps;
Justin Holewinskif8f70912013-06-28 17:57:59 +0000[diff] [blame]1101 LoadRetOps.push_back(Chain);
1102 LoadRetOps.push_back(DAG.getConstant(1, MVT::i32));
1103 LoadRetOps.push_back(DAG.getConstant(0, MVT::i32));
1104 LoadRetOps.push_back(InFlag);
1105 SDValue retval = DAG.getMemIntrinsicNode(
1106 NVPTXISD::LoadParam, dl,
Craig Topper206fcd42014-04-26 19:29:41 +0000[diff] [blame]1107 DAG.getVTList(LoadRetVTs), LoadRetOps, EltVT, MachinePointerInfo());
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]1108 Chain = retval.getValue(1);
1109 InFlag = retval.getValue(2);
Justin Holewinskif8f70912013-06-28 17:57:59 +0000[diff] [blame]1110 SDValue Ret0 = retval;
1111 if (needTruncate)
1112 Ret0 = DAG.getNode(ISD::TRUNCATE, dl, EltVT, Ret0);
1113 InVals.push_back(Ret0);
1114 } else if (NumElts == 2) {
1115 // LoadV2
Craig Topper59f626d2014-04-26 19:29:47 +0000[diff] [blame]1116 SmallVector<EVT, 4> LoadRetVTs;
Justin Holewinskif8f70912013-06-28 17:57:59 +0000[diff] [blame]1117 if (needTruncate) {
1118 // If loading i1 result, generate
1119 // load i16
1120 // trunc i16 to i1
1121 LoadRetVTs.push_back(MVT::i16);
1122 LoadRetVTs.push_back(MVT::i16);
1123 } else {
1124 LoadRetVTs.push_back(EltVT);
1125 LoadRetVTs.push_back(EltVT);
1126 }
1127 LoadRetVTs.push_back(MVT::Other);
1128 LoadRetVTs.push_back(MVT::Glue);
Craig Topper59f626d2014-04-26 19:29:47 +0000[diff] [blame]1129 SmallVector<SDValue, 4> LoadRetOps;
Justin Holewinskif8f70912013-06-28 17:57:59 +0000[diff] [blame]1130 LoadRetOps.push_back(Chain);
1131 LoadRetOps.push_back(DAG.getConstant(1, MVT::i32));
1132 LoadRetOps.push_back(DAG.getConstant(0, MVT::i32));
1133 LoadRetOps.push_back(InFlag);
1134 SDValue retval = DAG.getMemIntrinsicNode(
1135 NVPTXISD::LoadParamV2, dl,
Craig Topper206fcd42014-04-26 19:29:41 +0000[diff] [blame]1136 DAG.getVTList(LoadRetVTs), LoadRetOps, EltVT, MachinePointerInfo());
Justin Holewinskif8f70912013-06-28 17:57:59 +0000[diff] [blame]1137 Chain = retval.getValue(2);
1138 InFlag = retval.getValue(3);
1139 SDValue Ret0 = retval.getValue(0);
1140 SDValue Ret1 = retval.getValue(1);
1141 if (needTruncate) {
1142 Ret0 = DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, Ret0);
1143 InVals.push_back(Ret0);
1144 Ret1 = DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, Ret1);
1145 InVals.push_back(Ret1);
1146 } else {
1147 InVals.push_back(Ret0);
1148 InVals.push_back(Ret1);
1149 }
1150 } else {
1151 // Split into N LoadV4
1152 unsigned Ofst = 0;
1153 unsigned VecSize = 4;
1154 unsigned Opc = NVPTXISD::LoadParamV4;
1155 if (EltVT.getSizeInBits() == 64) {
1156 VecSize = 2;
1157 Opc = NVPTXISD::LoadParamV2;
1158 }
1159 EVT VecVT = EVT::getVectorVT(F->getContext(), EltVT, VecSize);
1160 for (unsigned i = 0; i < NumElts; i += VecSize) {
1161 SmallVector<EVT, 8> LoadRetVTs;
1162 if (needTruncate) {
1163 // If loading i1 result, generate
1164 // load i16
1165 // trunc i16 to i1
1166 for (unsigned j = 0; j < VecSize; ++j)
1167 LoadRetVTs.push_back(MVT::i16);
1168 } else {
1169 for (unsigned j = 0; j < VecSize; ++j)
1170 LoadRetVTs.push_back(EltVT);
1171 }
1172 LoadRetVTs.push_back(MVT::Other);
1173 LoadRetVTs.push_back(MVT::Glue);
1174 SmallVector<SDValue, 4> LoadRetOps;
1175 LoadRetOps.push_back(Chain);
1176 LoadRetOps.push_back(DAG.getConstant(1, MVT::i32));
1177 LoadRetOps.push_back(DAG.getConstant(Ofst, MVT::i32));
1178 LoadRetOps.push_back(InFlag);
1179 SDValue retval = DAG.getMemIntrinsicNode(
Craig Topperabb4ac72014-04-16 06:10:51 +0000[diff] [blame]1180 Opc, dl, DAG.getVTList(LoadRetVTs),
Craig Topper206fcd42014-04-26 19:29:41 +0000[diff] [blame]1181 LoadRetOps, EltVT, MachinePointerInfo());
Justin Holewinskif8f70912013-06-28 17:57:59 +0000[diff] [blame]1182 if (VecSize == 2) {
1183 Chain = retval.getValue(2);
1184 InFlag = retval.getValue(3);
1185 } else {
1186 Chain = retval.getValue(4);
1187 InFlag = retval.getValue(5);
1188 }
1189
1190 for (unsigned j = 0; j < VecSize; ++j) {
1191 if (i + j >= NumElts)
1192 break;
1193 SDValue Elt = retval.getValue(j);
1194 if (needTruncate)
1195 Elt = DAG.getNode(ISD::TRUNCATE, dl, EltVT, Elt);
1196 InVals.push_back(Elt);
1197 }
1198 Ofst += TD->getTypeAllocSize(VecVT.getTypeForEVT(F->getContext()));
1199 }
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]1200 }
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]1201 } else {
Justin Holewinskif8f70912013-06-28 17:57:59 +0000[diff] [blame]1202 SmallVector<EVT, 16> VTs;
1203 ComputePTXValueVTs(*this, retTy, VTs);
1204 assert(VTs.size() == Ins.size() && "Bad value decomposition");
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]1205 for (unsigned i = 0, e = Ins.size(); i != e; ++i) {
Justin Holewinskif8f70912013-06-28 17:57:59 +0000[diff] [blame]1206 unsigned sz = VTs[i].getSizeInBits();
1207 bool needTruncate = sz < 8 ? true : false;
1208 if (VTs[i].isInteger() && (sz < 8))
1209 sz = 8;
1210
1211 SmallVector<EVT, 4> LoadRetVTs;
Justin Holewinskie04e4bd2013-06-28 17:58:10 +0000[diff] [blame]1212 EVT TheLoadType = VTs[i];
1213 if (retTy->isIntegerTy() &&
1214 TD->getTypeAllocSizeInBits(retTy) < 32) {
1215 // This is for integer types only, and specifically not for
1216 // aggregates.
1217 LoadRetVTs.push_back(MVT::i32);
1218 TheLoadType = MVT::i32;
1219 } else if (sz < 16) {
Justin Holewinskif8f70912013-06-28 17:57:59 +0000[diff] [blame]1220 // If loading i1/i8 result, generate
1221 // load i8 (-> i16)
1222 // trunc i16 to i1/i8
1223 LoadRetVTs.push_back(MVT::i16);
1224 } else
1225 LoadRetVTs.push_back(Ins[i].VT);
1226 LoadRetVTs.push_back(MVT::Other);
1227 LoadRetVTs.push_back(MVT::Glue);
1228
1229 SmallVector<SDValue, 4> LoadRetOps;
1230 LoadRetOps.push_back(Chain);
1231 LoadRetOps.push_back(DAG.getConstant(1, MVT::i32));
1232 LoadRetOps.push_back(DAG.getConstant(resoffset, MVT::i32));
1233 LoadRetOps.push_back(InFlag);
1234 SDValue retval = DAG.getMemIntrinsicNode(
1235 NVPTXISD::LoadParam, dl,
Craig Topper206fcd42014-04-26 19:29:41 +0000[diff] [blame]1236 DAG.getVTList(LoadRetVTs), LoadRetOps,
1237 TheLoadType, MachinePointerInfo());
Justin Holewinskif8f70912013-06-28 17:57:59 +0000[diff] [blame]1238 Chain = retval.getValue(1);
1239 InFlag = retval.getValue(2);
1240 SDValue Ret0 = retval.getValue(0);
1241 if (needTruncate)
1242 Ret0 = DAG.getNode(ISD::TRUNCATE, dl, Ins[i].VT, Ret0);
1243 InVals.push_back(Ret0);
1244 resoffset += sz / 8;
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]1245 }
1246 }
1247 }
Justin Holewinskif8f70912013-06-28 17:57:59 +0000[diff] [blame]1248
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]1249 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(uniqueCallSite, true),
1250 DAG.getIntPtrConstant(uniqueCallSite + 1, true),
Andrew Trickad6d08a2013-05-29 22:03:55 +0000[diff] [blame]1251 InFlag, dl);
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]1252 uniqueCallSite++;
1253
1254 // set isTailCall to false for now, until we figure out how to express
1255 // tail call optimization in PTX
1256 isTailCall = false;
1257 return Chain;
1258}
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]1259
1260// By default CONCAT_VECTORS is lowered by ExpandVectorBuildThroughStack()
1261// (see LegalizeDAG.cpp). This is slow and uses local memory.
1262// We use extract/insert/build vector just as what LegalizeOp() does in llvm 2.5
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]1263SDValue
1264NVPTXTargetLowering::LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) const {
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]1265 SDNode *Node = Op.getNode();
Andrew Trickef9de2a2013-05-25 02:42:55 +0000[diff] [blame]1266 SDLoc dl(Node);
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]1267 SmallVector<SDValue, 8> Ops;
1268 unsigned NumOperands = Node->getNumOperands();
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]1269 for (unsigned i = 0; i < NumOperands; ++i) {
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]1270 SDValue SubOp = Node->getOperand(i);
1271 EVT VVT = SubOp.getNode()->getValueType(0);
1272 EVT EltVT = VVT.getVectorElementType();
1273 unsigned NumSubElem = VVT.getVectorNumElements();
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]1274 for (unsigned j = 0; j < NumSubElem; ++j) {
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]1275 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, SubOp,
1276 DAG.getIntPtrConstant(j)));
1277 }
1278 }
Craig Topper48d114b2014-04-26 18:35:24 +0000[diff] [blame]1279 return DAG.getNode(ISD::BUILD_VECTOR, dl, Node->getValueType(0), Ops);
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]1280}
1281
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]1282SDValue
1283NVPTXTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]1284 switch (Op.getOpcode()) {
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]1285 case ISD::RETURNADDR:
1286 return SDValue();
1287 case ISD::FRAMEADDR:
1288 return SDValue();
1289 case ISD::GlobalAddress:
1290 return LowerGlobalAddress(Op, DAG);
1291 case ISD::INTRINSIC_W_CHAIN:
1292 return Op;
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]1293 case ISD::BUILD_VECTOR:
1294 case ISD::EXTRACT_SUBVECTOR:
1295 return Op;
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]1296 case ISD::CONCAT_VECTORS:
1297 return LowerCONCAT_VECTORS(Op, DAG);
1298 case ISD::STORE:
1299 return LowerSTORE(Op, DAG);
1300 case ISD::LOAD:
1301 return LowerLOAD(Op, DAG);
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]1302 default:
David Blaikie891d0a32012-05-04 22:34:16 +0000[diff] [blame]1303 llvm_unreachable("Custom lowering not defined for operation");
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]1304 }
1305}
1306
Justin Holewinskibe8dc642013-02-12 14:18:49 +0000[diff] [blame]1307SDValue NVPTXTargetLowering::LowerLOAD(SDValue Op, SelectionDAG &DAG) const {
1308 if (Op.getValueType() == MVT::i1)
1309 return LowerLOADi1(Op, DAG);
1310 else
1311 return SDValue();
1312}
1313
Justin Holewinskic6462aa2012-11-14 19:19:16 +0000[diff] [blame]1314// v = ld i1* addr
1315// =>
Justin Holewinskif8f70912013-06-28 17:57:59 +0000[diff] [blame]1316// v1 = ld i8* addr (-> i16)
1317// v = trunc i16 to i1
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]1318SDValue NVPTXTargetLowering::LowerLOADi1(SDValue Op, SelectionDAG &DAG) const {
Justin Holewinskic6462aa2012-11-14 19:19:16 +0000[diff] [blame]1319 SDNode *Node = Op.getNode();
1320 LoadSDNode *LD = cast<LoadSDNode>(Node);
Andrew Trickef9de2a2013-05-25 02:42:55 +0000[diff] [blame]1321 SDLoc dl(Node);
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]1322 assert(LD->getExtensionType() == ISD::NON_EXTLOAD);
NAKAMURA Takumi5bbe0e12012-11-14 23:46:15 +0000[diff] [blame]1323 assert(Node->getValueType(0) == MVT::i1 &&
1324 "Custom lowering for i1 load only");
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]1325 SDValue newLD =
Justin Holewinskif8f70912013-06-28 17:57:59 +0000[diff] [blame]1326 DAG.getLoad(MVT::i16, dl, LD->getChain(), LD->getBasePtr(),
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]1327 LD->getPointerInfo(), LD->isVolatile(), LD->isNonTemporal(),
1328 LD->isInvariant(), LD->getAlignment());
Justin Holewinskic6462aa2012-11-14 19:19:16 +0000[diff] [blame]1329 SDValue result = DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, newLD);
1330 // The legalizer (the caller) is expecting two values from the legalized
1331 // load, so we build a MergeValues node for it. See ExpandUnalignedLoad()
1332 // in LegalizeDAG.cpp which also uses MergeValues.
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]1333 SDValue Ops[] = { result, LD->getChain() };
Craig Topper64941d92014-04-27 19:20:57 +0000[diff] [blame]1334 return DAG.getMergeValues(Ops, dl);
Justin Holewinskic6462aa2012-11-14 19:19:16 +0000[diff] [blame]1335}
1336
Justin Holewinskibe8dc642013-02-12 14:18:49 +0000[diff] [blame]1337SDValue NVPTXTargetLowering::LowerSTORE(SDValue Op, SelectionDAG &DAG) const {
1338 EVT ValVT = Op.getOperand(1).getValueType();
1339 if (ValVT == MVT::i1)
1340 return LowerSTOREi1(Op, DAG);
1341 else if (ValVT.isVector())
1342 return LowerSTOREVector(Op, DAG);
1343 else
1344 return SDValue();
1345}
1346
1347SDValue
1348NVPTXTargetLowering::LowerSTOREVector(SDValue Op, SelectionDAG &DAG) const {
1349 SDNode *N = Op.getNode();
1350 SDValue Val = N->getOperand(1);
Andrew Trickef9de2a2013-05-25 02:42:55 +0000[diff] [blame]1351 SDLoc DL(N);
Justin Holewinskibe8dc642013-02-12 14:18:49 +0000[diff] [blame]1352 EVT ValVT = Val.getValueType();
1353
1354 if (ValVT.isVector()) {
1355 // We only handle "native" vector sizes for now, e.g. <4 x double> is not
1356 // legal. We can (and should) split that into 2 stores of <2 x double> here
1357 // but I'm leaving that as a TODO for now.
1358 if (!ValVT.isSimple())
1359 return SDValue();
1360 switch (ValVT.getSimpleVT().SimpleTy) {
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]1361 default:
1362 return SDValue();
Justin Holewinskibe8dc642013-02-12 14:18:49 +0000[diff] [blame]1363 case MVT::v2i8:
1364 case MVT::v2i16:
1365 case MVT::v2i32:
1366 case MVT::v2i64:
1367 case MVT::v2f32:
1368 case MVT::v2f64:
1369 case MVT::v4i8:
1370 case MVT::v4i16:
1371 case MVT::v4i32:
1372 case MVT::v4f32:
1373 // This is a "native" vector type
1374 break;
1375 }
1376
1377 unsigned Opcode = 0;
1378 EVT EltVT = ValVT.getVectorElementType();
1379 unsigned NumElts = ValVT.getVectorNumElements();
1380
1381 // Since StoreV2 is a target node, we cannot rely on DAG type legalization.
1382 // Therefore, we must ensure the type is legal. For i1 and i8, we set the
Alp Tokercb402912014-01-24 17:20:08 +0000[diff] [blame]1383 // stored type to i16 and propagate the "real" type as the memory type.
Justin Holewinskia2911282013-07-01 12:58:58 +0000[diff] [blame]1384 bool NeedExt = false;
Justin Holewinskibe8dc642013-02-12 14:18:49 +0000[diff] [blame]1385 if (EltVT.getSizeInBits() < 16)
Justin Holewinskia2911282013-07-01 12:58:58 +0000[diff] [blame]1386 NeedExt = true;
Justin Holewinskibe8dc642013-02-12 14:18:49 +0000[diff] [blame]1387
1388 switch (NumElts) {
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]1389 default:
1390 return SDValue();
Justin Holewinskibe8dc642013-02-12 14:18:49 +0000[diff] [blame]1391 case 2:
1392 Opcode = NVPTXISD::StoreV2;
1393 break;
1394 case 4: {
1395 Opcode = NVPTXISD::StoreV4;
1396 break;
1397 }
1398 }
1399
1400 SmallVector<SDValue, 8> Ops;
1401
1402 // First is the chain
1403 Ops.push_back(N->getOperand(0));
1404
1405 // Then the split values
1406 for (unsigned i = 0; i < NumElts; ++i) {
1407 SDValue ExtVal = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, EltVT, Val,
1408 DAG.getIntPtrConstant(i));
Justin Holewinskia2911282013-07-01 12:58:58 +0000[diff] [blame]1409 if (NeedExt)
1410 ExtVal = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i16, ExtVal);
Justin Holewinskibe8dc642013-02-12 14:18:49 +0000[diff] [blame]1411 Ops.push_back(ExtVal);
1412 }
1413
1414 // Then any remaining arguments
1415 for (unsigned i = 2, e = N->getNumOperands(); i != e; ++i) {
1416 Ops.push_back(N->getOperand(i));
1417 }
1418
1419 MemSDNode *MemSD = cast<MemSDNode>(N);
1420
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]1421 SDValue NewSt = DAG.getMemIntrinsicNode(
Craig Topper206fcd42014-04-26 19:29:41 +0000[diff] [blame]1422 Opcode, DL, DAG.getVTList(MVT::Other), Ops,
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]1423 MemSD->getMemoryVT(), MemSD->getMemOperand());
Justin Holewinskibe8dc642013-02-12 14:18:49 +0000[diff] [blame]1424
1425 //return DCI.CombineTo(N, NewSt, true);
1426 return NewSt;
1427 }
1428
1429 return SDValue();
1430}
1431
Justin Holewinskic6462aa2012-11-14 19:19:16 +0000[diff] [blame]1432// st i1 v, addr
1433// =>
Justin Holewinskif8f70912013-06-28 17:57:59 +0000[diff] [blame]1434// v1 = zxt v to i16
1435// st.u8 i16, addr
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]1436SDValue NVPTXTargetLowering::LowerSTOREi1(SDValue Op, SelectionDAG &DAG) const {
Justin Holewinskic6462aa2012-11-14 19:19:16 +0000[diff] [blame]1437 SDNode *Node = Op.getNode();
Andrew Trickef9de2a2013-05-25 02:42:55 +0000[diff] [blame]1438 SDLoc dl(Node);
Justin Holewinskic6462aa2012-11-14 19:19:16 +0000[diff] [blame]1439 StoreSDNode *ST = cast<StoreSDNode>(Node);
1440 SDValue Tmp1 = ST->getChain();
1441 SDValue Tmp2 = ST->getBasePtr();
1442 SDValue Tmp3 = ST->getValue();
NAKAMURA Takumi5bbe0e12012-11-14 23:46:15 +0000[diff] [blame]1443 assert(Tmp3.getValueType() == MVT::i1 && "Custom lowering for i1 store only");
Justin Holewinskic6462aa2012-11-14 19:19:16 +0000[diff] [blame]1444 unsigned Alignment = ST->getAlignment();
1445 bool isVolatile = ST->isVolatile();
1446 bool isNonTemporal = ST->isNonTemporal();
Justin Holewinskif8f70912013-06-28 17:57:59 +0000[diff] [blame]1447 Tmp3 = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, Tmp3);
1448 SDValue Result = DAG.getTruncStore(Tmp1, dl, Tmp3, Tmp2,
1449 ST->getPointerInfo(), MVT::i8, isNonTemporal,
1450 isVolatile, Alignment);
Justin Holewinskic6462aa2012-11-14 19:19:16 +0000[diff] [blame]1451 return Result;
1452}
1453
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]1454SDValue NVPTXTargetLowering::getExtSymb(SelectionDAG &DAG, const char *inname,
1455 int idx, EVT v) const {
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]1456 std::string *name = nvTM->getManagedStrPool()->getManagedString(inname);
1457 std::stringstream suffix;
1458 suffix << idx;
1459 *name += suffix.str();
1460 return DAG.getTargetExternalSymbol(name->c_str(), v);
1461}
1462
1463SDValue
1464NVPTXTargetLowering::getParamSymbol(SelectionDAG &DAG, int idx, EVT v) const {
Justin Holewinskia2a63d22013-08-06 14:13:27 +0000[diff] [blame]1465 std::string ParamSym;
1466 raw_string_ostream ParamStr(ParamSym);
1467
1468 ParamStr << DAG.getMachineFunction().getName() << "_param_" << idx;
1469 ParamStr.flush();
1470
1471 std::string *SavedStr =
1472 nvTM->getManagedStrPool()->getManagedString(ParamSym.c_str());
1473 return DAG.getTargetExternalSymbol(SavedStr->c_str(), v);
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]1474}
1475
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]1476SDValue NVPTXTargetLowering::getParamHelpSymbol(SelectionDAG &DAG, int idx) {
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]1477 return getExtSymb(DAG, ".HLPPARAM", idx);
1478}
1479
1480// Check to see if the kernel argument is image*_t or sampler_t
1481
1482bool llvm::isImageOrSamplerVal(const Value *arg, const Module *context) {
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]1483 static const char *const specialTypes[] = { "struct._image2d_t",
1484 "struct._image3d_t",
1485 "struct._sampler_t" };
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]1486
1487 const Type *Ty = arg->getType();
1488 const PointerType *PTy = dyn_cast<PointerType>(Ty);
1489
1490 if (!PTy)
1491 return false;
1492
1493 if (!context)
1494 return false;
1495
1496 const StructType *STy = dyn_cast<StructType>(PTy->getElementType());
Justin Holewinskifb711152012-12-05 20:50:28 +0000[diff] [blame]1497 const std::string TypeName = STy && !STy->isLiteral() ? STy->getName() : "";
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]1498
Craig Toppere4260f92012-05-24 04:22:05 +0000[diff] [blame]1499 for (int i = 0, e = array_lengthof(specialTypes); i != e; ++i)
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]1500 if (TypeName == specialTypes[i])
1501 return true;
1502
1503 return false;
1504}
1505
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]1506SDValue NVPTXTargetLowering::LowerFormalArguments(
1507 SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
Andrew Trickef9de2a2013-05-25 02:42:55 +0000[diff] [blame]1508 const SmallVectorImpl<ISD::InputArg> &Ins, SDLoc dl, SelectionDAG &DAG,
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]1509 SmallVectorImpl<SDValue> &InVals) const {
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]1510 MachineFunction &MF = DAG.getMachineFunction();
Micah Villmowcdfe20b2012-10-08 16:38:25 +0000[diff] [blame]1511 const DataLayout *TD = getDataLayout();
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]1512
1513 const Function *F = MF.getFunction();
Bill Wendlinge94d8432012-12-07 23:16:57 +0000[diff] [blame]1514 const AttributeSet &PAL = F->getAttributes();
Eric Christopher2ecb77e2014-06-27 03:45:49 +0000[diff] [blame]1515 const TargetLowering *TLI = DAG.getTarget().getTargetLowering();
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]1516
1517 SDValue Root = DAG.getRoot();
1518 std::vector<SDValue> OutChains;
1519
1520 bool isKernel = llvm::isKernelFunction(*F);
1521 bool isABI = (nvptxSubtarget.getSmVersion() >= 20);
Justin Holewinski44f5c602013-06-28 17:57:53 +0000[diff] [blame]1522 assert(isABI && "Non-ABI compilation is not supported");
1523 if (!isABI)
1524 return Chain;
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]1525
1526 std::vector<Type *> argTypes;
1527 std::vector<const Argument *> theArgs;
1528 for (Function::const_arg_iterator I = F->arg_begin(), E = F->arg_end();
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]1529 I != E; ++I) {
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]1530 theArgs.push_back(I);
1531 argTypes.push_back(I->getType());
1532 }
Justin Holewinski44f5c602013-06-28 17:57:53 +0000[diff] [blame]1533 // argTypes.size() (or theArgs.size()) and Ins.size() need not match.
1534 // Ins.size() will be larger
1535 // * if there is an aggregate argument with multiple fields (each field
1536 // showing up separately in Ins)
1537 // * if there is a vector argument with more than typical vector-length
1538 // elements (generally if more than 4) where each vector element is
1539 // individually present in Ins.
1540 // So a different index should be used for indexing into Ins.
1541 // See similar issue in LowerCall.
1542 unsigned InsIdx = 0;
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]1543
1544 int idx = 0;
Justin Holewinski44f5c602013-06-28 17:57:53 +0000[diff] [blame]1545 for (unsigned i = 0, e = theArgs.size(); i != e; ++i, ++idx, ++InsIdx) {
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]1546 Type *Ty = argTypes[i];
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]1547
1548 // If the kernel argument is image*_t or sampler_t, convert it to
1549 // a i32 constant holding the parameter position. This can later
1550 // matched in the AsmPrinter to output the correct mangled name.
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]1551 if (isImageOrSamplerVal(
1552 theArgs[i],
1553 (theArgs[i]->getParent() ? theArgs[i]->getParent()->getParent()
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]1554 : nullptr))) {
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]1555 assert(isKernel && "Only kernels can have image/sampler params");
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]1556 InVals.push_back(DAG.getConstant(i + 1, MVT::i32));
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]1557 continue;
1558 }
1559
1560 if (theArgs[i]->use_empty()) {
1561 // argument is dead
Justin Holewinski44f5c602013-06-28 17:57:53 +0000[diff] [blame]1562 if (Ty->isAggregateType()) {
1563 SmallVector<EVT, 16> vtparts;
1564
Justin Holewinskif8f70912013-06-28 17:57:59 +0000[diff] [blame]1565 ComputePTXValueVTs(*this, Ty, vtparts);
Justin Holewinski44f5c602013-06-28 17:57:53 +0000[diff] [blame]1566 assert(vtparts.size() > 0 && "empty aggregate type not expected");
1567 for (unsigned parti = 0, parte = vtparts.size(); parti != parte;
1568 ++parti) {
1569 EVT partVT = vtparts[parti];
1570 InVals.push_back(DAG.getNode(ISD::UNDEF, dl, partVT));
1571 ++InsIdx;
Justin Holewinskie9884092013-03-24 21:17:47 +0000[diff] [blame]1572 }
Justin Holewinski44f5c602013-06-28 17:57:53 +0000[diff] [blame]1573 if (vtparts.size() > 0)
1574 --InsIdx;
1575 continue;
Justin Holewinskie9884092013-03-24 21:17:47 +0000[diff] [blame]1576 }
Justin Holewinski44f5c602013-06-28 17:57:53 +0000[diff] [blame]1577 if (Ty->isVectorTy()) {
1578 EVT ObjectVT = getValueType(Ty);
1579 unsigned NumRegs = TLI->getNumRegisters(F->getContext(), ObjectVT);
1580 for (unsigned parti = 0; parti < NumRegs; ++parti) {
1581 InVals.push_back(DAG.getNode(ISD::UNDEF, dl, Ins[InsIdx].VT));
1582 ++InsIdx;
1583 }
1584 if (NumRegs > 0)
1585 --InsIdx;
1586 continue;
1587 }
1588 InVals.push_back(DAG.getNode(ISD::UNDEF, dl, Ins[InsIdx].VT));
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]1589 continue;
1590 }
1591
1592 // In the following cases, assign a node order of "idx+1"
Justin Holewinski44f5c602013-06-28 17:57:53 +0000[diff] [blame]1593 // to newly created nodes. The SDNodes for params have to
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]1594 // appear in the same order as their order of appearance
1595 // in the original function. "idx+1" holds that order.
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]1596 if (PAL.hasAttribute(i + 1, Attribute::ByVal) == false) {
Justin Holewinski44f5c602013-06-28 17:57:53 +0000[diff] [blame]1597 if (Ty->isAggregateType()) {
1598 SmallVector<EVT, 16> vtparts;
1599 SmallVector<uint64_t, 16> offsets;
1600
Justin Holewinskif8f70912013-06-28 17:57:59 +0000[diff] [blame]1601 // NOTE: Here, we lose the ability to issue vector loads for vectors
1602 // that are a part of a struct. This should be investigated in the
1603 // future.
1604 ComputePTXValueVTs(*this, Ty, vtparts, &offsets, 0);
Justin Holewinski44f5c602013-06-28 17:57:53 +0000[diff] [blame]1605 assert(vtparts.size() > 0 && "empty aggregate type not expected");
1606 bool aggregateIsPacked = false;
1607 if (StructType *STy = llvm::dyn_cast<StructType>(Ty))
1608 aggregateIsPacked = STy->isPacked();
1609
1610 SDValue Arg = getParamSymbol(DAG, idx, getPointerTy());
1611 for (unsigned parti = 0, parte = vtparts.size(); parti != parte;
1612 ++parti) {
1613 EVT partVT = vtparts[parti];
1614 Value *srcValue = Constant::getNullValue(
1615 PointerType::get(partVT.getTypeForEVT(F->getContext()),
1616 llvm::ADDRESS_SPACE_PARAM));
1617 SDValue srcAddr =
1618 DAG.getNode(ISD::ADD, dl, getPointerTy(), Arg,
1619 DAG.getConstant(offsets[parti], getPointerTy()));
1620 unsigned partAlign =
1621 aggregateIsPacked ? 1
1622 : TD->getABITypeAlignment(
1623 partVT.getTypeForEVT(F->getContext()));
Justin Holewinskia2911282013-07-01 12:58:58 +0000[diff] [blame]1624 SDValue p;
1625 if (Ins[InsIdx].VT.getSizeInBits() > partVT.getSizeInBits()) {
1626 ISD::LoadExtType ExtOp = Ins[InsIdx].Flags.isSExt() ?
1627 ISD::SEXTLOAD : ISD::ZEXTLOAD;
1628 p = DAG.getExtLoad(ExtOp, dl, Ins[InsIdx].VT, Root, srcAddr,
Justin Holewinskif8f70912013-06-28 17:57:59 +0000[diff] [blame]1629 MachinePointerInfo(srcValue), partVT, false,
1630 false, partAlign);
Justin Holewinskia2911282013-07-01 12:58:58 +0000[diff] [blame]1631 } else {
Justin Holewinskif8f70912013-06-28 17:57:59 +0000[diff] [blame]1632 p = DAG.getLoad(partVT, dl, Root, srcAddr,
1633 MachinePointerInfo(srcValue), false, false, false,
1634 partAlign);
Justin Holewinskia2911282013-07-01 12:58:58 +0000[diff] [blame]1635 }
Justin Holewinski44f5c602013-06-28 17:57:53 +0000[diff] [blame]1636 if (p.getNode())
1637 p.getNode()->setIROrder(idx + 1);
1638 InVals.push_back(p);
1639 ++InsIdx;
Justin Holewinskie9884092013-03-24 21:17:47 +0000[diff] [blame]1640 }
Justin Holewinski44f5c602013-06-28 17:57:53 +0000[diff] [blame]1641 if (vtparts.size() > 0)
1642 --InsIdx;
Justin Holewinskie9884092013-03-24 21:17:47 +0000[diff] [blame]1643 continue;
1644 }
Justin Holewinski44f5c602013-06-28 17:57:53 +0000[diff] [blame]1645 if (Ty->isVectorTy()) {
1646 EVT ObjectVT = getValueType(Ty);
Justin Holewinskiaaaf2892013-06-25 12:22:21 +0000[diff] [blame]1647 SDValue Arg = getParamSymbol(DAG, idx, getPointerTy());
Justin Holewinski44f5c602013-06-28 17:57:53 +0000[diff] [blame]1648 unsigned NumElts = ObjectVT.getVectorNumElements();
1649 assert(TLI->getNumRegisters(F->getContext(), ObjectVT) == NumElts &&
1650 "Vector was not scalarized");
1651 unsigned Ofst = 0;
1652 EVT EltVT = ObjectVT.getVectorElementType();
1653
1654 // V1 load
1655 // f32 = load ...
1656 if (NumElts == 1) {
1657 // We only have one element, so just directly load it
1658 Value *SrcValue = Constant::getNullValue(PointerType::get(
1659 EltVT.getTypeForEVT(F->getContext()), llvm::ADDRESS_SPACE_PARAM));
1660 SDValue SrcAddr = DAG.getNode(ISD::ADD, dl, getPointerTy(), Arg,
1661 DAG.getConstant(Ofst, getPointerTy()));
1662 SDValue P = DAG.getLoad(
1663 EltVT, dl, Root, SrcAddr, MachinePointerInfo(SrcValue), false,
1664 false, true,
1665 TD->getABITypeAlignment(EltVT.getTypeForEVT(F->getContext())));
1666 if (P.getNode())
1667 P.getNode()->setIROrder(idx + 1);
1668
Justin Holewinskif8f70912013-06-28 17:57:59 +0000[diff] [blame]1669 if (Ins[InsIdx].VT.getSizeInBits() > EltVT.getSizeInBits())
Justin Holewinskia2911282013-07-01 12:58:58 +0000[diff] [blame]1670 P = DAG.getNode(ISD::ANY_EXTEND, dl, Ins[InsIdx].VT, P);
Justin Holewinski44f5c602013-06-28 17:57:53 +0000[diff] [blame]1671 InVals.push_back(P);
1672 Ofst += TD->getTypeAllocSize(EltVT.getTypeForEVT(F->getContext()));
1673 ++InsIdx;
1674 } else if (NumElts == 2) {
1675 // V2 load
1676 // f32,f32 = load ...
1677 EVT VecVT = EVT::getVectorVT(F->getContext(), EltVT, 2);
1678 Value *SrcValue = Constant::getNullValue(PointerType::get(
1679 VecVT.getTypeForEVT(F->getContext()), llvm::ADDRESS_SPACE_PARAM));
1680 SDValue SrcAddr = DAG.getNode(ISD::ADD, dl, getPointerTy(), Arg,
1681 DAG.getConstant(Ofst, getPointerTy()));
1682 SDValue P = DAG.getLoad(
1683 VecVT, dl, Root, SrcAddr, MachinePointerInfo(SrcValue), false,
1684 false, true,
1685 TD->getABITypeAlignment(VecVT.getTypeForEVT(F->getContext())));
1686 if (P.getNode())
1687 P.getNode()->setIROrder(idx + 1);
1688
1689 SDValue Elt0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, P,
1690 DAG.getIntPtrConstant(0));
1691 SDValue Elt1 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, P,
1692 DAG.getIntPtrConstant(1));
Justin Holewinskif8f70912013-06-28 17:57:59 +0000[diff] [blame]1693
1694 if (Ins[InsIdx].VT.getSizeInBits() > EltVT.getSizeInBits()) {
Justin Holewinskia2911282013-07-01 12:58:58 +0000[diff] [blame]1695 Elt0 = DAG.getNode(ISD::ANY_EXTEND, dl, Ins[InsIdx].VT, Elt0);
1696 Elt1 = DAG.getNode(ISD::ANY_EXTEND, dl, Ins[InsIdx].VT, Elt1);
Justin Holewinskif8f70912013-06-28 17:57:59 +0000[diff] [blame]1697 }
1698
Justin Holewinski44f5c602013-06-28 17:57:53 +0000[diff] [blame]1699 InVals.push_back(Elt0);
1700 InVals.push_back(Elt1);
1701 Ofst += TD->getTypeAllocSize(VecVT.getTypeForEVT(F->getContext()));
1702 InsIdx += 2;
1703 } else {
1704 // V4 loads
1705 // We have at least 4 elements (<3 x Ty> expands to 4 elements) and
1706 // the
1707 // vector will be expanded to a power of 2 elements, so we know we can
1708 // always round up to the next multiple of 4 when creating the vector
1709 // loads.
1710 // e.g. 4 elem => 1 ld.v4
1711 // 6 elem => 2 ld.v4
1712 // 8 elem => 2 ld.v4
1713 // 11 elem => 3 ld.v4
1714 unsigned VecSize = 4;
1715 if (EltVT.getSizeInBits() == 64) {
1716 VecSize = 2;
1717 }
1718 EVT VecVT = EVT::getVectorVT(F->getContext(), EltVT, VecSize);
1719 for (unsigned i = 0; i < NumElts; i += VecSize) {
1720 Value *SrcValue = Constant::getNullValue(
1721 PointerType::get(VecVT.getTypeForEVT(F->getContext()),
1722 llvm::ADDRESS_SPACE_PARAM));
1723 SDValue SrcAddr =
1724 DAG.getNode(ISD::ADD, dl, getPointerTy(), Arg,
1725 DAG.getConstant(Ofst, getPointerTy()));
1726 SDValue P = DAG.getLoad(
1727 VecVT, dl, Root, SrcAddr, MachinePointerInfo(SrcValue), false,
1728 false, true,
1729 TD->getABITypeAlignment(VecVT.getTypeForEVT(F->getContext())));
1730 if (P.getNode())
1731 P.getNode()->setIROrder(idx + 1);
1732
1733 for (unsigned j = 0; j < VecSize; ++j) {
1734 if (i + j >= NumElts)
1735 break;
1736 SDValue Elt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, P,
1737 DAG.getIntPtrConstant(j));
Justin Holewinskif8f70912013-06-28 17:57:59 +0000[diff] [blame]1738 if (Ins[InsIdx].VT.getSizeInBits() > EltVT.getSizeInBits())
Justin Holewinskia2911282013-07-01 12:58:58 +0000[diff] [blame]1739 Elt = DAG.getNode(ISD::ANY_EXTEND, dl, Ins[InsIdx].VT, Elt);
Justin Holewinski44f5c602013-06-28 17:57:53 +0000[diff] [blame]1740 InVals.push_back(Elt);
1741 }
1742 Ofst += TD->getTypeAllocSize(VecVT.getTypeForEVT(F->getContext()));
Justin Holewinski44f5c602013-06-28 17:57:53 +0000[diff] [blame]1743 }
Justin Holewinski4f5bc9b2013-11-11 19:28:16 +0000[diff] [blame]1744 InsIdx += NumElts;
Justin Holewinski44f5c602013-06-28 17:57:53 +0000[diff] [blame]1745 }
1746
1747 if (NumElts > 0)
1748 --InsIdx;
1749 continue;
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]1750 }
Justin Holewinski44f5c602013-06-28 17:57:53 +0000[diff] [blame]1751 // A plain scalar.
1752 EVT ObjectVT = getValueType(Ty);
Justin Holewinski44f5c602013-06-28 17:57:53 +0000[diff] [blame]1753 // If ABI, load from the param symbol
1754 SDValue Arg = getParamSymbol(DAG, idx, getPointerTy());
1755 Value *srcValue = Constant::getNullValue(PointerType::get(
1756 ObjectVT.getTypeForEVT(F->getContext()), llvm::ADDRESS_SPACE_PARAM));
Justin Holewinskif8f70912013-06-28 17:57:59 +0000[diff] [blame]1757 SDValue p;
Justin Holewinskia2911282013-07-01 12:58:58 +0000[diff] [blame]1758 if (ObjectVT.getSizeInBits() < Ins[InsIdx].VT.getSizeInBits()) {
1759 ISD::LoadExtType ExtOp = Ins[InsIdx].Flags.isSExt() ?
1760 ISD::SEXTLOAD : ISD::ZEXTLOAD;
1761 p = DAG.getExtLoad(ExtOp, dl, Ins[InsIdx].VT, Root, Arg,
Justin Holewinskif8f70912013-06-28 17:57:59 +0000[diff] [blame]1762 MachinePointerInfo(srcValue), ObjectVT, false, false,
Justin Holewinskia2911282013-07-01 12:58:58 +0000[diff] [blame]1763 TD->getABITypeAlignment(ObjectVT.getTypeForEVT(F->getContext())));
1764 } else {
Justin Holewinskif8f70912013-06-28 17:57:59 +0000[diff] [blame]1765 p = DAG.getLoad(Ins[InsIdx].VT, dl, Root, Arg,
1766 MachinePointerInfo(srcValue), false, false, false,
Justin Holewinskia2911282013-07-01 12:58:58 +0000[diff] [blame]1767 TD->getABITypeAlignment(ObjectVT.getTypeForEVT(F->getContext())));
1768 }
Justin Holewinski44f5c602013-06-28 17:57:53 +0000[diff] [blame]1769 if (p.getNode())
1770 p.getNode()->setIROrder(idx + 1);
1771 InVals.push_back(p);
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]1772 continue;
1773 }
1774
1775 // Param has ByVal attribute
Justin Holewinski44f5c602013-06-28 17:57:53 +0000[diff] [blame]1776 // Return MoveParam(param symbol).
1777 // Ideally, the param symbol can be returned directly,
1778 // but when SDNode builder decides to use it in a CopyToReg(),
1779 // machine instruction fails because TargetExternalSymbol
1780 // (not lowered) is target dependent, and CopyToReg assumes
1781 // the source is lowered.
1782 EVT ObjectVT = getValueType(Ty);
1783 assert(ObjectVT == Ins[InsIdx].VT &&
1784 "Ins type did not match function type");
1785 SDValue Arg = getParamSymbol(DAG, idx, getPointerTy());
1786 SDValue p = DAG.getNode(NVPTXISD::MoveParam, dl, ObjectVT, Arg);
1787 if (p.getNode())
1788 p.getNode()->setIROrder(idx + 1);
1789 if (isKernel)
1790 InVals.push_back(p);
1791 else {
1792 SDValue p2 = DAG.getNode(
1793 ISD::INTRINSIC_WO_CHAIN, dl, ObjectVT,
1794 DAG.getConstant(Intrinsic::nvvm_ptr_local_to_gen, MVT::i32), p);
1795 InVals.push_back(p2);
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]1796 }
1797 }
1798
1799 // Clang will check explicit VarArg and issue error if any. However, Clang
1800 // will let code with
Justin Holewinski44f5c602013-06-28 17:57:53 +0000[diff] [blame]1801 // implicit var arg like f() pass. See bug 617733.
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]1802 // We treat this case as if the arg list is empty.
Justin Holewinski44f5c602013-06-28 17:57:53 +0000[diff] [blame]1803 // if (F.isVarArg()) {
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]1804 // assert(0 && "VarArg not supported yet!");
1805 //}
1806
1807 if (!OutChains.empty())
Craig Topper48d114b2014-04-26 18:35:24 +0000[diff] [blame]1808 DAG.setRoot(DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains));
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]1809
1810 return Chain;
1811}
1812
Justin Holewinski44f5c602013-06-28 17:57:53 +0000[diff] [blame]1813
Justin Holewinski120baee2013-06-28 17:57:55 +0000[diff] [blame]1814SDValue
1815NVPTXTargetLowering::LowerReturn(SDValue Chain, CallingConv::ID CallConv,
1816 bool isVarArg,
1817 const SmallVectorImpl<ISD::OutputArg> &Outs,
1818 const SmallVectorImpl<SDValue> &OutVals,
1819 SDLoc dl, SelectionDAG &DAG) const {
1820 MachineFunction &MF = DAG.getMachineFunction();
1821 const Function *F = MF.getFunction();
Justin Holewinskie04e4bd2013-06-28 17:58:10 +0000[diff] [blame]1822 Type *RetTy = F->getReturnType();
Justin Holewinski120baee2013-06-28 17:57:55 +0000[diff] [blame]1823 const DataLayout *TD = getDataLayout();
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]1824
1825 bool isABI = (nvptxSubtarget.getSmVersion() >= 20);
Justin Holewinski120baee2013-06-28 17:57:55 +0000[diff] [blame]1826 assert(isABI && "Non-ABI compilation is not supported");
1827 if (!isABI)
1828 return Chain;
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]1829
Justin Holewinskie04e4bd2013-06-28 17:58:10 +0000[diff] [blame]1830 if (VectorType *VTy = dyn_cast<VectorType>(RetTy)) {
Justin Holewinski120baee2013-06-28 17:57:55 +0000[diff] [blame]1831 // If we have a vector type, the OutVals array will be the scalarized
1832 // components and we have combine them into 1 or more vector stores.
1833 unsigned NumElts = VTy->getNumElements();
1834 assert(NumElts == Outs.size() && "Bad scalarization of return value");
1835
Justin Holewinskif8f70912013-06-28 17:57:59 +0000[diff] [blame]1836 // const_cast can be removed in later LLVM versions
Justin Holewinskie04e4bd2013-06-28 17:58:10 +0000[diff] [blame]1837 EVT EltVT = getValueType(RetTy).getVectorElementType();
Justin Holewinskif8f70912013-06-28 17:57:59 +0000[diff] [blame]1838 bool NeedExtend = false;
1839 if (EltVT.getSizeInBits() < 16)
1840 NeedExtend = true;
1841
Justin Holewinski120baee2013-06-28 17:57:55 +0000[diff] [blame]1842 // V1 store
1843 if (NumElts == 1) {
1844 SDValue StoreVal = OutVals[0];
1845 // We only have one element, so just directly store it
Justin Holewinskif8f70912013-06-28 17:57:59 +0000[diff] [blame]1846 if (NeedExtend)
1847 StoreVal = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, StoreVal);
1848 SDValue Ops[] = { Chain, DAG.getConstant(0, MVT::i32), StoreVal };
1849 Chain = DAG.getMemIntrinsicNode(NVPTXISD::StoreRetval, dl,
Craig Topper206fcd42014-04-26 19:29:41 +0000[diff] [blame]1850 DAG.getVTList(MVT::Other), Ops,
Justin Holewinskif8f70912013-06-28 17:57:59 +0000[diff] [blame]1851 EltVT, MachinePointerInfo());
1852
Justin Holewinski120baee2013-06-28 17:57:55 +0000[diff] [blame]1853 } else if (NumElts == 2) {
1854 // V2 store
1855 SDValue StoreVal0 = OutVals[0];
1856 SDValue StoreVal1 = OutVals[1];
1857
Justin Holewinskif8f70912013-06-28 17:57:59 +0000[diff] [blame]1858 if (NeedExtend) {
1859 StoreVal0 = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, StoreVal0);
1860 StoreVal1 = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, StoreVal1);
Justin Holewinski120baee2013-06-28 17:57:55 +0000[diff] [blame]1861 }
1862
Justin Holewinskif8f70912013-06-28 17:57:59 +0000[diff] [blame]1863 SDValue Ops[] = { Chain, DAG.getConstant(0, MVT::i32), StoreVal0,
1864 StoreVal1 };
1865 Chain = DAG.getMemIntrinsicNode(NVPTXISD::StoreRetvalV2, dl,
Craig Topper206fcd42014-04-26 19:29:41 +0000[diff] [blame]1866 DAG.getVTList(MVT::Other), Ops,
Justin Holewinskif8f70912013-06-28 17:57:59 +0000[diff] [blame]1867 EltVT, MachinePointerInfo());
Justin Holewinski120baee2013-06-28 17:57:55 +0000[diff] [blame]1868 } else {
1869 // V4 stores
1870 // We have at least 4 elements (<3 x Ty> expands to 4 elements) and the
1871 // vector will be expanded to a power of 2 elements, so we know we can
1872 // always round up to the next multiple of 4 when creating the vector
1873 // stores.
1874 // e.g. 4 elem => 1 st.v4
1875 // 6 elem => 2 st.v4
1876 // 8 elem => 2 st.v4
1877 // 11 elem => 3 st.v4
1878
1879 unsigned VecSize = 4;
1880 if (OutVals[0].getValueType().getSizeInBits() == 64)
1881 VecSize = 2;
1882
1883 unsigned Offset = 0;
1884
1885 EVT VecVT =
1886 EVT::getVectorVT(F->getContext(), OutVals[0].getValueType(), VecSize);
1887 unsigned PerStoreOffset =
1888 TD->getTypeAllocSize(VecVT.getTypeForEVT(F->getContext()));
1889
Justin Holewinski120baee2013-06-28 17:57:55 +0000[diff] [blame]1890 for (unsigned i = 0; i < NumElts; i += VecSize) {
1891 // Get values
1892 SDValue StoreVal;
1893 SmallVector<SDValue, 8> Ops;
1894 Ops.push_back(Chain);
1895 Ops.push_back(DAG.getConstant(Offset, MVT::i32));
1896 unsigned Opc = NVPTXISD::StoreRetvalV2;
Justin Holewinskif8f70912013-06-28 17:57:59 +0000[diff] [blame]1897 EVT ExtendedVT = (NeedExtend) ? MVT::i16 : OutVals[0].getValueType();
Justin Holewinski120baee2013-06-28 17:57:55 +0000[diff] [blame]1898
1899 StoreVal = OutVals[i];
Justin Holewinskif8f70912013-06-28 17:57:59 +0000[diff] [blame]1900 if (NeedExtend)
1901 StoreVal = DAG.getNode(ISD::ZERO_EXTEND, dl, ExtendedVT, StoreVal);
Justin Holewinski120baee2013-06-28 17:57:55 +0000[diff] [blame]1902 Ops.push_back(StoreVal);
1903
1904 if (i + 1 < NumElts) {
1905 StoreVal = OutVals[i + 1];
Justin Holewinskif8f70912013-06-28 17:57:59 +0000[diff] [blame]1906 if (NeedExtend)
1907 StoreVal = DAG.getNode(ISD::ZERO_EXTEND, dl, ExtendedVT, StoreVal);
Justin Holewinski120baee2013-06-28 17:57:55 +0000[diff] [blame]1908 } else {
1909 StoreVal = DAG.getUNDEF(ExtendedVT);
1910 }
1911 Ops.push_back(StoreVal);
1912
1913 if (VecSize == 4) {
1914 Opc = NVPTXISD::StoreRetvalV4;
1915 if (i + 2 < NumElts) {
1916 StoreVal = OutVals[i + 2];
Justin Holewinskif8f70912013-06-28 17:57:59 +0000[diff] [blame]1917 if (NeedExtend)
1918 StoreVal =
1919 DAG.getNode(ISD::ZERO_EXTEND, dl, ExtendedVT, StoreVal);
Justin Holewinski120baee2013-06-28 17:57:55 +0000[diff] [blame]1920 } else {
1921 StoreVal = DAG.getUNDEF(ExtendedVT);
1922 }
1923 Ops.push_back(StoreVal);
1924
1925 if (i + 3 < NumElts) {
1926 StoreVal = OutVals[i + 3];
Justin Holewinskif8f70912013-06-28 17:57:59 +0000[diff] [blame]1927 if (NeedExtend)
1928 StoreVal =
1929 DAG.getNode(ISD::ZERO_EXTEND, dl, ExtendedVT, StoreVal);
Justin Holewinski120baee2013-06-28 17:57:55 +0000[diff] [blame]1930 } else {
1931 StoreVal = DAG.getUNDEF(ExtendedVT);
1932 }
1933 Ops.push_back(StoreVal);
1934 }
1935
Justin Holewinskif8f70912013-06-28 17:57:59 +0000[diff] [blame]1936 // Chain = DAG.getNode(Opc, dl, MVT::Other, &Ops[0], Ops.size());
1937 Chain =
Craig Topper206fcd42014-04-26 19:29:41 +0000[diff] [blame]1938 DAG.getMemIntrinsicNode(Opc, dl, DAG.getVTList(MVT::Other), Ops,
1939 EltVT, MachinePointerInfo());
Justin Holewinski120baee2013-06-28 17:57:55 +0000[diff] [blame]1940 Offset += PerStoreOffset;
1941 }
1942 }
1943 } else {
Justin Holewinskif8f70912013-06-28 17:57:59 +0000[diff] [blame]1944 SmallVector<EVT, 16> ValVTs;
1945 // const_cast is necessary since we are still using an LLVM version from
1946 // before the type system re-write.
Justin Holewinskie04e4bd2013-06-28 17:58:10 +0000[diff] [blame]1947 ComputePTXValueVTs(*this, RetTy, ValVTs);
Justin Holewinskif8f70912013-06-28 17:57:59 +0000[diff] [blame]1948 assert(ValVTs.size() == OutVals.size() && "Bad return value decomposition");
1949
Justin Holewinskie04e4bd2013-06-28 17:58:10 +0000[diff] [blame]1950 unsigned SizeSoFar = 0;
Justin Holewinski120baee2013-06-28 17:57:55 +0000[diff] [blame]1951 for (unsigned i = 0, e = Outs.size(); i != e; ++i) {
1952 SDValue theVal = OutVals[i];
Justin Holewinskie04e4bd2013-06-28 17:58:10 +0000[diff] [blame]1953 EVT TheValType = theVal.getValueType();
Justin Holewinski120baee2013-06-28 17:57:55 +0000[diff] [blame]1954 unsigned numElems = 1;
Justin Holewinskie04e4bd2013-06-28 17:58:10 +0000[diff] [blame]1955 if (TheValType.isVector())
1956 numElems = TheValType.getVectorNumElements();
Justin Holewinski120baee2013-06-28 17:57:55 +0000[diff] [blame]1957 for (unsigned j = 0, je = numElems; j != je; ++j) {
Justin Holewinskie04e4bd2013-06-28 17:58:10 +0000[diff] [blame]1958 SDValue TmpVal = theVal;
1959 if (TheValType.isVector())
1960 TmpVal = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
1961 TheValType.getVectorElementType(), TmpVal,
Justin Holewinski120baee2013-06-28 17:57:55 +0000[diff] [blame]1962 DAG.getIntPtrConstant(j));
Justin Holewinskie04e4bd2013-06-28 17:58:10 +0000[diff] [blame]1963 EVT TheStoreType = ValVTs[i];
1964 if (RetTy->isIntegerTy() &&
1965 TD->getTypeAllocSizeInBits(RetTy) < 32) {
1966 // The following zero-extension is for integer types only, and
1967 // specifically not for aggregates.
1968 TmpVal = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, TmpVal);
1969 TheStoreType = MVT::i32;
1970 }
1971 else if (TmpVal.getValueType().getSizeInBits() < 16)
1972 TmpVal = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i16, TmpVal);
1973
1974 SDValue Ops[] = { Chain, DAG.getConstant(SizeSoFar, MVT::i32), TmpVal };
Justin Holewinskif8f70912013-06-28 17:57:59 +0000[diff] [blame]1975 Chain = DAG.getMemIntrinsicNode(NVPTXISD::StoreRetval, dl,
Craig Topper206fcd42014-04-26 19:29:41 +0000[diff] [blame]1976 DAG.getVTList(MVT::Other), Ops,
1977 TheStoreType,
Justin Holewinskie04e4bd2013-06-28 17:58:10 +0000[diff] [blame]1978 MachinePointerInfo());
1979 if(TheValType.isVector())
1980 SizeSoFar +=
1981 TheStoreType.getVectorElementType().getStoreSizeInBits() / 8;
Justin Holewinski120baee2013-06-28 17:57:55 +0000[diff] [blame]1982 else
Justin Holewinskie04e4bd2013-06-28 17:58:10 +0000[diff] [blame]1983 SizeSoFar += TheStoreType.getStoreSizeInBits()/8;
Justin Holewinski120baee2013-06-28 17:57:55 +0000[diff] [blame]1984 }
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]1985 }
1986 }
1987
1988 return DAG.getNode(NVPTXISD::RET_FLAG, dl, MVT::Other, Chain);
1989}
1990
Justin Holewinskif8f70912013-06-28 17:57:59 +0000[diff] [blame]1991
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]1992void NVPTXTargetLowering::LowerAsmOperandForConstraint(
1993 SDValue Op, std::string &Constraint, std::vector<SDValue> &Ops,
1994 SelectionDAG &DAG) const {
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]1995 if (Constraint.length() > 1)
1996 return;
1997 else
1998 TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
1999}
2000
2001// NVPTX suuport vector of legal types of any length in Intrinsics because the
2002// NVPTX specific type legalizer
2003// will legalize them to the PTX supported length.
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]2004bool NVPTXTargetLowering::isTypeSupportedInIntrinsic(MVT VT) const {
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]2005 if (isTypeLegal(VT))
2006 return true;
2007 if (VT.isVector()) {
2008 MVT eVT = VT.getVectorElementType();
2009 if (isTypeLegal(eVT))
2010 return true;
2011 }
2012 return false;
2013}
2014
Justin Holewinski30d56a72014-04-09 15:39:15 +0000[diff] [blame]2015static unsigned getOpcForTextureInstr(unsigned Intrinsic) {
2016 switch (Intrinsic) {
2017 default:
2018 return 0;
2019
2020 case Intrinsic::nvvm_tex_1d_v4f32_i32:
2021 return NVPTXISD::Tex1DFloatI32;
2022 case Intrinsic::nvvm_tex_1d_v4f32_f32:
2023 return NVPTXISD::Tex1DFloatFloat;
2024 case Intrinsic::nvvm_tex_1d_level_v4f32_f32:
2025 return NVPTXISD::Tex1DFloatFloatLevel;
2026 case Intrinsic::nvvm_tex_1d_grad_v4f32_f32:
2027 return NVPTXISD::Tex1DFloatFloatGrad;
2028 case Intrinsic::nvvm_tex_1d_v4i32_i32:
2029 return NVPTXISD::Tex1DI32I32;
2030 case Intrinsic::nvvm_tex_1d_v4i32_f32:
2031 return NVPTXISD::Tex1DI32Float;
2032 case Intrinsic::nvvm_tex_1d_level_v4i32_f32:
2033 return NVPTXISD::Tex1DI32FloatLevel;
2034 case Intrinsic::nvvm_tex_1d_grad_v4i32_f32:
2035 return NVPTXISD::Tex1DI32FloatGrad;
2036
2037 case Intrinsic::nvvm_tex_1d_array_v4f32_i32:
2038 return NVPTXISD::Tex1DArrayFloatI32;
2039 case Intrinsic::nvvm_tex_1d_array_v4f32_f32:
2040 return NVPTXISD::Tex1DArrayFloatFloat;
2041 case Intrinsic::nvvm_tex_1d_array_level_v4f32_f32:
2042 return NVPTXISD::Tex1DArrayFloatFloatLevel;
2043 case Intrinsic::nvvm_tex_1d_array_grad_v4f32_f32:
2044 return NVPTXISD::Tex1DArrayFloatFloatGrad;
2045 case Intrinsic::nvvm_tex_1d_array_v4i32_i32:
2046 return NVPTXISD::Tex1DArrayI32I32;
2047 case Intrinsic::nvvm_tex_1d_array_v4i32_f32:
2048 return NVPTXISD::Tex1DArrayI32Float;
2049 case Intrinsic::nvvm_tex_1d_array_level_v4i32_f32:
2050 return NVPTXISD::Tex1DArrayI32FloatLevel;
2051 case Intrinsic::nvvm_tex_1d_array_grad_v4i32_f32:
2052 return NVPTXISD::Tex1DArrayI32FloatGrad;
2053
2054 case Intrinsic::nvvm_tex_2d_v4f32_i32:
2055 return NVPTXISD::Tex2DFloatI32;
2056 case Intrinsic::nvvm_tex_2d_v4f32_f32:
2057 return NVPTXISD::Tex2DFloatFloat;
2058 case Intrinsic::nvvm_tex_2d_level_v4f32_f32:
2059 return NVPTXISD::Tex2DFloatFloatLevel;
2060 case Intrinsic::nvvm_tex_2d_grad_v4f32_f32:
2061 return NVPTXISD::Tex2DFloatFloatGrad;
2062 case Intrinsic::nvvm_tex_2d_v4i32_i32:
2063 return NVPTXISD::Tex2DI32I32;
2064 case Intrinsic::nvvm_tex_2d_v4i32_f32:
2065 return NVPTXISD::Tex2DI32Float;
2066 case Intrinsic::nvvm_tex_2d_level_v4i32_f32:
2067 return NVPTXISD::Tex2DI32FloatLevel;
2068 case Intrinsic::nvvm_tex_2d_grad_v4i32_f32:
2069 return NVPTXISD::Tex2DI32FloatGrad;
2070
2071 case Intrinsic::nvvm_tex_2d_array_v4f32_i32:
2072 return NVPTXISD::Tex2DArrayFloatI32;
2073 case Intrinsic::nvvm_tex_2d_array_v4f32_f32:
2074 return NVPTXISD::Tex2DArrayFloatFloat;
2075 case Intrinsic::nvvm_tex_2d_array_level_v4f32_f32:
2076 return NVPTXISD::Tex2DArrayFloatFloatLevel;
2077 case Intrinsic::nvvm_tex_2d_array_grad_v4f32_f32:
2078 return NVPTXISD::Tex2DArrayFloatFloatGrad;
2079 case Intrinsic::nvvm_tex_2d_array_v4i32_i32:
2080 return NVPTXISD::Tex2DArrayI32I32;
2081 case Intrinsic::nvvm_tex_2d_array_v4i32_f32:
2082 return NVPTXISD::Tex2DArrayI32Float;
2083 case Intrinsic::nvvm_tex_2d_array_level_v4i32_f32:
2084 return NVPTXISD::Tex2DArrayI32FloatLevel;
2085 case Intrinsic::nvvm_tex_2d_array_grad_v4i32_f32:
2086 return NVPTXISD::Tex2DArrayI32FloatGrad;
2087
2088 case Intrinsic::nvvm_tex_3d_v4f32_i32:
2089 return NVPTXISD::Tex3DFloatI32;
2090 case Intrinsic::nvvm_tex_3d_v4f32_f32:
2091 return NVPTXISD::Tex3DFloatFloat;
2092 case Intrinsic::nvvm_tex_3d_level_v4f32_f32:
2093 return NVPTXISD::Tex3DFloatFloatLevel;
2094 case Intrinsic::nvvm_tex_3d_grad_v4f32_f32:
2095 return NVPTXISD::Tex3DFloatFloatGrad;
2096 case Intrinsic::nvvm_tex_3d_v4i32_i32:
2097 return NVPTXISD::Tex3DI32I32;
2098 case Intrinsic::nvvm_tex_3d_v4i32_f32:
2099 return NVPTXISD::Tex3DI32Float;
2100 case Intrinsic::nvvm_tex_3d_level_v4i32_f32:
2101 return NVPTXISD::Tex3DI32FloatLevel;
2102 case Intrinsic::nvvm_tex_3d_grad_v4i32_f32:
2103 return NVPTXISD::Tex3DI32FloatGrad;
2104 }
2105}
2106
2107static unsigned getOpcForSurfaceInstr(unsigned Intrinsic) {
2108 switch (Intrinsic) {
2109 default:
2110 return 0;
2111 case Intrinsic::nvvm_suld_1d_i8_trap:
2112 return NVPTXISD::Suld1DI8Trap;
2113 case Intrinsic::nvvm_suld_1d_i16_trap:
2114 return NVPTXISD::Suld1DI16Trap;
2115 case Intrinsic::nvvm_suld_1d_i32_trap:
2116 return NVPTXISD::Suld1DI32Trap;
2117 case Intrinsic::nvvm_suld_1d_v2i8_trap:
2118 return NVPTXISD::Suld1DV2I8Trap;
2119 case Intrinsic::nvvm_suld_1d_v2i16_trap:
2120 return NVPTXISD::Suld1DV2I16Trap;
2121 case Intrinsic::nvvm_suld_1d_v2i32_trap:
2122 return NVPTXISD::Suld1DV2I32Trap;
2123 case Intrinsic::nvvm_suld_1d_v4i8_trap:
2124 return NVPTXISD::Suld1DV4I8Trap;
2125 case Intrinsic::nvvm_suld_1d_v4i16_trap:
2126 return NVPTXISD::Suld1DV4I16Trap;
2127 case Intrinsic::nvvm_suld_1d_v4i32_trap:
2128 return NVPTXISD::Suld1DV4I32Trap;
2129 case Intrinsic::nvvm_suld_1d_array_i8_trap:
2130 return NVPTXISD::Suld1DArrayI8Trap;
2131 case Intrinsic::nvvm_suld_1d_array_i16_trap:
2132 return NVPTXISD::Suld1DArrayI16Trap;
2133 case Intrinsic::nvvm_suld_1d_array_i32_trap:
2134 return NVPTXISD::Suld1DArrayI32Trap;
2135 case Intrinsic::nvvm_suld_1d_array_v2i8_trap:
2136 return NVPTXISD::Suld1DArrayV2I8Trap;
2137 case Intrinsic::nvvm_suld_1d_array_v2i16_trap:
2138 return NVPTXISD::Suld1DArrayV2I16Trap;
2139 case Intrinsic::nvvm_suld_1d_array_v2i32_trap:
2140 return NVPTXISD::Suld1DArrayV2I32Trap;
2141 case Intrinsic::nvvm_suld_1d_array_v4i8_trap:
2142 return NVPTXISD::Suld1DArrayV4I8Trap;
2143 case Intrinsic::nvvm_suld_1d_array_v4i16_trap:
2144 return NVPTXISD::Suld1DArrayV4I16Trap;
2145 case Intrinsic::nvvm_suld_1d_array_v4i32_trap:
2146 return NVPTXISD::Suld1DArrayV4I32Trap;
2147 case Intrinsic::nvvm_suld_2d_i8_trap:
2148 return NVPTXISD::Suld2DI8Trap;
2149 case Intrinsic::nvvm_suld_2d_i16_trap:
2150 return NVPTXISD::Suld2DI16Trap;
2151 case Intrinsic::nvvm_suld_2d_i32_trap:
2152 return NVPTXISD::Suld2DI32Trap;
2153 case Intrinsic::nvvm_suld_2d_v2i8_trap:
2154 return NVPTXISD::Suld2DV2I8Trap;
2155 case Intrinsic::nvvm_suld_2d_v2i16_trap:
2156 return NVPTXISD::Suld2DV2I16Trap;
2157 case Intrinsic::nvvm_suld_2d_v2i32_trap:
2158 return NVPTXISD::Suld2DV2I32Trap;
2159 case Intrinsic::nvvm_suld_2d_v4i8_trap:
2160 return NVPTXISD::Suld2DV4I8Trap;
2161 case Intrinsic::nvvm_suld_2d_v4i16_trap:
2162 return NVPTXISD::Suld2DV4I16Trap;
2163 case Intrinsic::nvvm_suld_2d_v4i32_trap:
2164 return NVPTXISD::Suld2DV4I32Trap;
2165 case Intrinsic::nvvm_suld_2d_array_i8_trap:
2166 return NVPTXISD::Suld2DArrayI8Trap;
2167 case Intrinsic::nvvm_suld_2d_array_i16_trap:
2168 return NVPTXISD::Suld2DArrayI16Trap;
2169 case Intrinsic::nvvm_suld_2d_array_i32_trap:
2170 return NVPTXISD::Suld2DArrayI32Trap;
2171 case Intrinsic::nvvm_suld_2d_array_v2i8_trap:
2172 return NVPTXISD::Suld2DArrayV2I8Trap;
2173 case Intrinsic::nvvm_suld_2d_array_v2i16_trap:
2174 return NVPTXISD::Suld2DArrayV2I16Trap;
2175 case Intrinsic::nvvm_suld_2d_array_v2i32_trap:
2176 return NVPTXISD::Suld2DArrayV2I32Trap;
2177 case Intrinsic::nvvm_suld_2d_array_v4i8_trap:
2178 return NVPTXISD::Suld2DArrayV4I8Trap;
2179 case Intrinsic::nvvm_suld_2d_array_v4i16_trap:
2180 return NVPTXISD::Suld2DArrayV4I16Trap;
2181 case Intrinsic::nvvm_suld_2d_array_v4i32_trap:
2182 return NVPTXISD::Suld2DArrayV4I32Trap;
2183 case Intrinsic::nvvm_suld_3d_i8_trap:
2184 return NVPTXISD::Suld3DI8Trap;
2185 case Intrinsic::nvvm_suld_3d_i16_trap:
2186 return NVPTXISD::Suld3DI16Trap;
2187 case Intrinsic::nvvm_suld_3d_i32_trap:
2188 return NVPTXISD::Suld3DI32Trap;
2189 case Intrinsic::nvvm_suld_3d_v2i8_trap:
2190 return NVPTXISD::Suld3DV2I8Trap;
2191 case Intrinsic::nvvm_suld_3d_v2i16_trap:
2192 return NVPTXISD::Suld3DV2I16Trap;
2193 case Intrinsic::nvvm_suld_3d_v2i32_trap:
2194 return NVPTXISD::Suld3DV2I32Trap;
2195 case Intrinsic::nvvm_suld_3d_v4i8_trap:
2196 return NVPTXISD::Suld3DV4I8Trap;
2197 case Intrinsic::nvvm_suld_3d_v4i16_trap:
2198 return NVPTXISD::Suld3DV4I16Trap;
2199 case Intrinsic::nvvm_suld_3d_v4i32_trap:
2200 return NVPTXISD::Suld3DV4I32Trap;
2201 }
2202}
2203
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]2204// llvm.ptx.memcpy.const and llvm.ptx.memmove.const need to be modeled as
2205// TgtMemIntrinsic
2206// because we need the information that is only available in the "Value" type
2207// of destination
2208// pointer. In particular, the address space information.
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]2209bool NVPTXTargetLowering::getTgtMemIntrinsic(
2210 IntrinsicInfo &Info, const CallInst &I, unsigned Intrinsic) const {
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]2211 switch (Intrinsic) {
2212 default:
2213 return false;
2214
2215 case Intrinsic::nvvm_atomic_load_add_f32:
2216 Info.opc = ISD::INTRINSIC_W_CHAIN;
2217 Info.memVT = MVT::f32;
2218 Info.ptrVal = I.getArgOperand(0);
2219 Info.offset = 0;
2220 Info.vol = 0;
2221 Info.readMem = true;
2222 Info.writeMem = true;
2223 Info.align = 0;
2224 return true;
2225
2226 case Intrinsic::nvvm_atomic_load_inc_32:
2227 case Intrinsic::nvvm_atomic_load_dec_32:
2228 Info.opc = ISD::INTRINSIC_W_CHAIN;
2229 Info.memVT = MVT::i32;
2230 Info.ptrVal = I.getArgOperand(0);
2231 Info.offset = 0;
2232 Info.vol = 0;
2233 Info.readMem = true;
2234 Info.writeMem = true;
2235 Info.align = 0;
2236 return true;
2237
2238 case Intrinsic::nvvm_ldu_global_i:
2239 case Intrinsic::nvvm_ldu_global_f:
2240 case Intrinsic::nvvm_ldu_global_p:
2241
2242 Info.opc = ISD::INTRINSIC_W_CHAIN;
2243 if (Intrinsic == Intrinsic::nvvm_ldu_global_i)
Justin Holewinskif8f70912013-06-28 17:57:59 +0000[diff] [blame]2244 Info.memVT = getValueType(I.getType());
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]2245 else if (Intrinsic == Intrinsic::nvvm_ldu_global_p)
Justin Holewinskif8f70912013-06-28 17:57:59 +0000[diff] [blame]2246 Info.memVT = getValueType(I.getType());
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]2247 else
2248 Info.memVT = MVT::f32;
2249 Info.ptrVal = I.getArgOperand(0);
2250 Info.offset = 0;
2251 Info.vol = 0;
2252 Info.readMem = true;
2253 Info.writeMem = false;
2254 Info.align = 0;
2255 return true;
2256
Justin Holewinski30d56a72014-04-09 15:39:15 +0000[diff] [blame]2257 case Intrinsic::nvvm_tex_1d_v4f32_i32:
2258 case Intrinsic::nvvm_tex_1d_v4f32_f32:
2259 case Intrinsic::nvvm_tex_1d_level_v4f32_f32:
2260 case Intrinsic::nvvm_tex_1d_grad_v4f32_f32:
2261 case Intrinsic::nvvm_tex_1d_array_v4f32_i32:
2262 case Intrinsic::nvvm_tex_1d_array_v4f32_f32:
2263 case Intrinsic::nvvm_tex_1d_array_level_v4f32_f32:
2264 case Intrinsic::nvvm_tex_1d_array_grad_v4f32_f32:
2265 case Intrinsic::nvvm_tex_2d_v4f32_i32:
2266 case Intrinsic::nvvm_tex_2d_v4f32_f32:
2267 case Intrinsic::nvvm_tex_2d_level_v4f32_f32:
2268 case Intrinsic::nvvm_tex_2d_grad_v4f32_f32:
2269 case Intrinsic::nvvm_tex_2d_array_v4f32_i32:
2270 case Intrinsic::nvvm_tex_2d_array_v4f32_f32:
2271 case Intrinsic::nvvm_tex_2d_array_level_v4f32_f32:
2272 case Intrinsic::nvvm_tex_2d_array_grad_v4f32_f32:
2273 case Intrinsic::nvvm_tex_3d_v4f32_i32:
2274 case Intrinsic::nvvm_tex_3d_v4f32_f32:
2275 case Intrinsic::nvvm_tex_3d_level_v4f32_f32:
2276 case Intrinsic::nvvm_tex_3d_grad_v4f32_f32: {
2277 Info.opc = getOpcForTextureInstr(Intrinsic);
2278 Info.memVT = MVT::f32;
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]2279 Info.ptrVal = nullptr;
Justin Holewinski30d56a72014-04-09 15:39:15 +0000[diff] [blame]2280 Info.offset = 0;
2281 Info.vol = 0;
2282 Info.readMem = true;
2283 Info.writeMem = false;
2284 Info.align = 16;
2285 return true;
2286 }
2287 case Intrinsic::nvvm_tex_1d_v4i32_i32:
2288 case Intrinsic::nvvm_tex_1d_v4i32_f32:
2289 case Intrinsic::nvvm_tex_1d_level_v4i32_f32:
2290 case Intrinsic::nvvm_tex_1d_grad_v4i32_f32:
2291 case Intrinsic::nvvm_tex_1d_array_v4i32_i32:
2292 case Intrinsic::nvvm_tex_1d_array_v4i32_f32:
2293 case Intrinsic::nvvm_tex_1d_array_level_v4i32_f32:
2294 case Intrinsic::nvvm_tex_1d_array_grad_v4i32_f32:
2295 case Intrinsic::nvvm_tex_2d_v4i32_i32:
2296 case Intrinsic::nvvm_tex_2d_v4i32_f32:
2297 case Intrinsic::nvvm_tex_2d_level_v4i32_f32:
2298 case Intrinsic::nvvm_tex_2d_grad_v4i32_f32:
2299 case Intrinsic::nvvm_tex_2d_array_v4i32_i32:
2300 case Intrinsic::nvvm_tex_2d_array_v4i32_f32:
2301 case Intrinsic::nvvm_tex_2d_array_level_v4i32_f32:
2302 case Intrinsic::nvvm_tex_2d_array_grad_v4i32_f32:
2303 case Intrinsic::nvvm_tex_3d_v4i32_i32:
2304 case Intrinsic::nvvm_tex_3d_v4i32_f32:
2305 case Intrinsic::nvvm_tex_3d_level_v4i32_f32:
2306 case Intrinsic::nvvm_tex_3d_grad_v4i32_f32: {
2307 Info.opc = getOpcForTextureInstr(Intrinsic);
2308 Info.memVT = MVT::i32;
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]2309 Info.ptrVal = nullptr;
Justin Holewinski30d56a72014-04-09 15:39:15 +0000[diff] [blame]2310 Info.offset = 0;
2311 Info.vol = 0;
2312 Info.readMem = true;
2313 Info.writeMem = false;
2314 Info.align = 16;
2315 return true;
2316 }
2317 case Intrinsic::nvvm_suld_1d_i8_trap:
2318 case Intrinsic::nvvm_suld_1d_v2i8_trap:
2319 case Intrinsic::nvvm_suld_1d_v4i8_trap:
2320 case Intrinsic::nvvm_suld_1d_array_i8_trap:
2321 case Intrinsic::nvvm_suld_1d_array_v2i8_trap:
2322 case Intrinsic::nvvm_suld_1d_array_v4i8_trap:
2323 case Intrinsic::nvvm_suld_2d_i8_trap:
2324 case Intrinsic::nvvm_suld_2d_v2i8_trap:
2325 case Intrinsic::nvvm_suld_2d_v4i8_trap:
2326 case Intrinsic::nvvm_suld_2d_array_i8_trap:
2327 case Intrinsic::nvvm_suld_2d_array_v2i8_trap:
2328 case Intrinsic::nvvm_suld_2d_array_v4i8_trap:
2329 case Intrinsic::nvvm_suld_3d_i8_trap:
2330 case Intrinsic::nvvm_suld_3d_v2i8_trap:
2331 case Intrinsic::nvvm_suld_3d_v4i8_trap: {
2332 Info.opc = getOpcForSurfaceInstr(Intrinsic);
2333 Info.memVT = MVT::i8;
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]2334 Info.ptrVal = nullptr;
Justin Holewinski30d56a72014-04-09 15:39:15 +0000[diff] [blame]2335 Info.offset = 0;
2336 Info.vol = 0;
2337 Info.readMem = true;
2338 Info.writeMem = false;
2339 Info.align = 16;
2340 return true;
2341 }
2342 case Intrinsic::nvvm_suld_1d_i16_trap:
2343 case Intrinsic::nvvm_suld_1d_v2i16_trap:
2344 case Intrinsic::nvvm_suld_1d_v4i16_trap:
2345 case Intrinsic::nvvm_suld_1d_array_i16_trap:
2346 case Intrinsic::nvvm_suld_1d_array_v2i16_trap:
2347 case Intrinsic::nvvm_suld_1d_array_v4i16_trap:
2348 case Intrinsic::nvvm_suld_2d_i16_trap:
2349 case Intrinsic::nvvm_suld_2d_v2i16_trap:
2350 case Intrinsic::nvvm_suld_2d_v4i16_trap:
2351 case Intrinsic::nvvm_suld_2d_array_i16_trap:
2352 case Intrinsic::nvvm_suld_2d_array_v2i16_trap:
2353 case Intrinsic::nvvm_suld_2d_array_v4i16_trap:
2354 case Intrinsic::nvvm_suld_3d_i16_trap:
2355 case Intrinsic::nvvm_suld_3d_v2i16_trap:
2356 case Intrinsic::nvvm_suld_3d_v4i16_trap: {
2357 Info.opc = getOpcForSurfaceInstr(Intrinsic);
2358 Info.memVT = MVT::i16;
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]2359 Info.ptrVal = nullptr;
Justin Holewinski30d56a72014-04-09 15:39:15 +0000[diff] [blame]2360 Info.offset = 0;
2361 Info.vol = 0;
2362 Info.readMem = true;
2363 Info.writeMem = false;
2364 Info.align = 16;
2365 return true;
2366 }
2367 case Intrinsic::nvvm_suld_1d_i32_trap:
2368 case Intrinsic::nvvm_suld_1d_v2i32_trap:
2369 case Intrinsic::nvvm_suld_1d_v4i32_trap:
2370 case Intrinsic::nvvm_suld_1d_array_i32_trap:
2371 case Intrinsic::nvvm_suld_1d_array_v2i32_trap:
2372 case Intrinsic::nvvm_suld_1d_array_v4i32_trap:
2373 case Intrinsic::nvvm_suld_2d_i32_trap:
2374 case Intrinsic::nvvm_suld_2d_v2i32_trap:
2375 case Intrinsic::nvvm_suld_2d_v4i32_trap:
2376 case Intrinsic::nvvm_suld_2d_array_i32_trap:
2377 case Intrinsic::nvvm_suld_2d_array_v2i32_trap:
2378 case Intrinsic::nvvm_suld_2d_array_v4i32_trap:
2379 case Intrinsic::nvvm_suld_3d_i32_trap:
2380 case Intrinsic::nvvm_suld_3d_v2i32_trap:
2381 case Intrinsic::nvvm_suld_3d_v4i32_trap: {
2382 Info.opc = getOpcForSurfaceInstr(Intrinsic);
2383 Info.memVT = MVT::i32;
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]2384 Info.ptrVal = nullptr;
Justin Holewinski30d56a72014-04-09 15:39:15 +0000[diff] [blame]2385 Info.offset = 0;
2386 Info.vol = 0;
2387 Info.readMem = true;
2388 Info.writeMem = false;
2389 Info.align = 16;
2390 return true;
2391 }
2392
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]2393 }
2394 return false;
2395}
2396
2397/// isLegalAddressingMode - Return true if the addressing mode represented
2398/// by AM is legal for this target, for a load/store of the specified type.
2399/// Used to guide target specific optimizations, like loop strength reduction
2400/// (LoopStrengthReduce.cpp) and memory optimization for address mode
2401/// (CodeGenPrepare.cpp)
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]2402bool NVPTXTargetLowering::isLegalAddressingMode(const AddrMode &AM,
2403 Type *Ty) const {
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]2404
2405 // AddrMode - This represents an addressing mode of:
2406 // BaseGV + BaseOffs + BaseReg + Scale*ScaleReg
2407 //
2408 // The legal address modes are
2409 // - [avar]
2410 // - [areg]
2411 // - [areg+immoff]
2412 // - [immAddr]
2413
2414 if (AM.BaseGV) {
2415 if (AM.BaseOffs || AM.HasBaseReg || AM.Scale)
2416 return false;
2417 return true;
2418 }
2419
2420 switch (AM.Scale) {
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]2421 case 0: // "r", "r+i" or "i" is allowed
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]2422 break;
2423 case 1:
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]2424 if (AM.HasBaseReg) // "r+r+i" or "r+r" is not allowed.
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]2425 return false;
2426 // Otherwise we have r+i.
2427 break;
2428 default:
2429 // No scale > 1 is allowed
2430 return false;
2431 }
2432 return true;
2433}
2434
2435//===----------------------------------------------------------------------===//
2436// NVPTX Inline Assembly Support
2437//===----------------------------------------------------------------------===//
2438
2439/// getConstraintType - Given a constraint letter, return the type of
2440/// constraint it is for this target.
2441NVPTXTargetLowering::ConstraintType
2442NVPTXTargetLowering::getConstraintType(const std::string &Constraint) const {
2443 if (Constraint.size() == 1) {
2444 switch (Constraint[0]) {
2445 default:
2446 break;
2447 case 'r':
2448 case 'h':
2449 case 'c':
2450 case 'l':
2451 case 'f':
2452 case 'd':
2453 case '0':
2454 case 'N':
2455 return C_RegisterClass;
2456 }
2457 }
2458 return TargetLowering::getConstraintType(Constraint);
2459}
2460
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]2461std::pair<unsigned, const TargetRegisterClass *>
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]2462NVPTXTargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
Chad Rosier295bd432013-06-22 18:37:38 +0000[diff] [blame]2463 MVT VT) const {
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]2464 if (Constraint.size() == 1) {
2465 switch (Constraint[0]) {
2466 case 'c':
Justin Holewinskif8f70912013-06-28 17:57:59 +0000[diff] [blame]2467 return std::make_pair(0U, &NVPTX::Int16RegsRegClass);
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]2468 case 'h':
2469 return std::make_pair(0U, &NVPTX::Int16RegsRegClass);
2470 case 'r':
2471 return std::make_pair(0U, &NVPTX::Int32RegsRegClass);
2472 case 'l':
2473 case 'N':
2474 return std::make_pair(0U, &NVPTX::Int64RegsRegClass);
2475 case 'f':
2476 return std::make_pair(0U, &NVPTX::Float32RegsRegClass);
2477 case 'd':
2478 return std::make_pair(0U, &NVPTX::Float64RegsRegClass);
2479 }
2480 }
2481 return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
2482}
2483
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]2484/// getFunctionAlignment - Return the Log2 alignment of this function.
2485unsigned NVPTXTargetLowering::getFunctionAlignment(const Function *) const {
2486 return 4;
2487}
Justin Holewinskibe8dc642013-02-12 14:18:49 +0000[diff] [blame]2488
Justin Holewinskieafe26d2014-06-27 18:35:37 +0000[diff] [blame^]2489//===----------------------------------------------------------------------===//
2490// NVPTX DAG Combining
2491//===----------------------------------------------------------------------===//
2492
2493extern unsigned FMAContractLevel;
2494
2495/// PerformADDCombineWithOperands - Try DAG combinations for an ADD with
2496/// operands N0 and N1. This is a helper for PerformADDCombine that is
2497/// called with the default operands, and if that fails, with commuted
2498/// operands.
2499static SDValue PerformADDCombineWithOperands(SDNode *N, SDValue N0, SDValue N1,
2500 TargetLowering::DAGCombinerInfo &DCI,
2501 const NVPTXSubtarget &Subtarget,
2502 CodeGenOpt::Level OptLevel) {
2503 SelectionDAG &DAG = DCI.DAG;
2504 // Skip non-integer, non-scalar case
2505 EVT VT=N0.getValueType();
2506 if (VT.isVector())
2507 return SDValue();
2508
2509 // fold (add (mul a, b), c) -> (mad a, b, c)
2510 //
2511 if (N0.getOpcode() == ISD::MUL) {
2512 assert (VT.isInteger());
2513 // For integer:
2514 // Since integer multiply-add costs the same as integer multiply
2515 // but is more costly than integer add, do the fusion only when
2516 // the mul is only used in the add.
2517 if (OptLevel==CodeGenOpt::None || VT != MVT::i32 ||
2518 !N0.getNode()->hasOneUse())
2519 return SDValue();
2520
2521 // Do the folding
2522 return DAG.getNode(NVPTXISD::IMAD, SDLoc(N), VT,
2523 N0.getOperand(0), N0.getOperand(1), N1);
2524 }
2525 else if (N0.getOpcode() == ISD::FMUL) {
2526 if (VT == MVT::f32 || VT == MVT::f64) {
2527 if (FMAContractLevel == 0)
2528 return SDValue();
2529
2530 // For floating point:
2531 // Do the fusion only when the mul has less than 5 uses and all
2532 // are add.
2533 // The heuristic is that if a use is not an add, then that use
2534 // cannot be fused into fma, therefore mul is still needed anyway.
2535 // If there are more than 4 uses, even if they are all add, fusing
2536 // them will increase register pressue.
2537 //
2538 int numUses = 0;
2539 int nonAddCount = 0;
2540 for (SDNode::use_iterator UI = N0.getNode()->use_begin(),
2541 UE = N0.getNode()->use_end();
2542 UI != UE; ++UI) {
2543 numUses++;
2544 SDNode *User = *UI;
2545 if (User->getOpcode() != ISD::FADD)
2546 ++nonAddCount;
2547 }
2548 if (numUses >= 5)
2549 return SDValue();
2550 if (nonAddCount) {
2551 int orderNo = N->getIROrder();
2552 int orderNo2 = N0.getNode()->getIROrder();
2553 // simple heuristics here for considering potential register
2554 // pressure, the logics here is that the differnce are used
2555 // to measure the distance between def and use, the longer distance
2556 // more likely cause register pressure.
2557 if (orderNo - orderNo2 < 500)
2558 return SDValue();
2559
2560 // Now, check if at least one of the FMUL's operands is live beyond the node N,
2561 // which guarantees that the FMA will not increase register pressure at node N.
2562 bool opIsLive = false;
2563 const SDNode *left = N0.getOperand(0).getNode();
2564 const SDNode *right = N0.getOperand(1).getNode();
2565
2566 if (dyn_cast<ConstantSDNode>(left) || dyn_cast<ConstantSDNode>(right))
2567 opIsLive = true;
2568
2569 if (!opIsLive)
2570 for (SDNode::use_iterator UI = left->use_begin(), UE = left->use_end(); UI != UE; ++UI) {
2571 SDNode *User = *UI;
2572 int orderNo3 = User->getIROrder();
2573 if (orderNo3 > orderNo) {
2574 opIsLive = true;
2575 break;
2576 }
2577 }
2578
2579 if (!opIsLive)
2580 for (SDNode::use_iterator UI = right->use_begin(), UE = right->use_end(); UI != UE; ++UI) {
2581 SDNode *User = *UI;
2582 int orderNo3 = User->getIROrder();
2583 if (orderNo3 > orderNo) {
2584 opIsLive = true;
2585 break;
2586 }
2587 }
2588
2589 if (!opIsLive)
2590 return SDValue();
2591 }
2592
2593 return DAG.getNode(ISD::FMA, SDLoc(N), VT,
2594 N0.getOperand(0), N0.getOperand(1), N1);
2595 }
2596 }
2597
2598 return SDValue();
2599}
2600
2601/// PerformADDCombine - Target-specific dag combine xforms for ISD::ADD.
2602///
2603static SDValue PerformADDCombine(SDNode *N,
2604 TargetLowering::DAGCombinerInfo &DCI,
2605 const NVPTXSubtarget &Subtarget,
2606 CodeGenOpt::Level OptLevel) {
2607 SDValue N0 = N->getOperand(0);
2608 SDValue N1 = N->getOperand(1);
2609
2610 // First try with the default operand order.
2611 SDValue Result = PerformADDCombineWithOperands(N, N0, N1, DCI, Subtarget,
2612 OptLevel);
2613 if (Result.getNode())
2614 return Result;
2615
2616 // If that didn't work, try again with the operands commuted.
2617 return PerformADDCombineWithOperands(N, N1, N0, DCI, Subtarget, OptLevel);
2618}
2619
2620static SDValue PerformANDCombine(SDNode *N,
2621 TargetLowering::DAGCombinerInfo &DCI) {
2622 // The type legalizer turns a vector load of i8 values into a zextload to i16
2623 // registers, optionally ANY_EXTENDs it (if target type is integer),
2624 // and ANDs off the high 8 bits. Since we turn this load into a
2625 // target-specific DAG node, the DAG combiner fails to eliminate these AND
2626 // nodes. Do that here.
2627 SDValue Val = N->getOperand(0);
2628 SDValue Mask = N->getOperand(1);
2629
2630 if (isa<ConstantSDNode>(Val)) {
2631 std::swap(Val, Mask);
2632 }
2633
2634 SDValue AExt;
2635 // Generally, we will see zextload -> IMOV16rr -> ANY_EXTEND -> and
2636 if (Val.getOpcode() == ISD::ANY_EXTEND) {
2637 AExt = Val;
2638 Val = Val->getOperand(0);
2639 }
2640
2641 if (Val->isMachineOpcode() && Val->getMachineOpcode() == NVPTX::IMOV16rr) {
2642 Val = Val->getOperand(0);
2643 }
2644
2645 if (Val->getOpcode() == NVPTXISD::LoadV2 ||
2646 Val->getOpcode() == NVPTXISD::LoadV4) {
2647 ConstantSDNode *MaskCnst = dyn_cast<ConstantSDNode>(Mask);
2648 if (!MaskCnst) {
2649 // Not an AND with a constant
2650 return SDValue();
2651 }
2652
2653 uint64_t MaskVal = MaskCnst->getZExtValue();
2654 if (MaskVal != 0xff) {
2655 // Not an AND that chops off top 8 bits
2656 return SDValue();
2657 }
2658
2659 MemSDNode *Mem = dyn_cast<MemSDNode>(Val);
2660 if (!Mem) {
2661 // Not a MemSDNode?!?
2662 return SDValue();
2663 }
2664
2665 EVT MemVT = Mem->getMemoryVT();
2666 if (MemVT != MVT::v2i8 && MemVT != MVT::v4i8) {
2667 // We only handle the i8 case
2668 return SDValue();
2669 }
2670
2671 unsigned ExtType =
2672 cast<ConstantSDNode>(Val->getOperand(Val->getNumOperands()-1))->
2673 getZExtValue();
2674 if (ExtType == ISD::SEXTLOAD) {
2675 // If for some reason the load is a sextload, the and is needed to zero
2676 // out the high 8 bits
2677 return SDValue();
2678 }
2679
2680 bool AddTo = false;
2681 if (AExt.getNode() != 0) {
2682 // Re-insert the ext as a zext.
2683 Val = DCI.DAG.getNode(ISD::ZERO_EXTEND, SDLoc(N),
2684 AExt.getValueType(), Val);
2685 AddTo = true;
2686 }
2687
2688 // If we get here, the AND is unnecessary. Just replace it with the load
2689 DCI.CombineTo(N, Val, AddTo);
2690 }
2691
2692 return SDValue();
2693}
2694
2695enum OperandSignedness {
2696 Signed = 0,
2697 Unsigned,
2698 Unknown
2699};
2700
2701/// IsMulWideOperandDemotable - Checks if the provided DAG node is an operand
2702/// that can be demoted to \p OptSize bits without loss of information. The
2703/// signedness of the operand, if determinable, is placed in \p S.
2704static bool IsMulWideOperandDemotable(SDValue Op,
2705 unsigned OptSize,
2706 OperandSignedness &S) {
2707 S = Unknown;
2708
2709 if (Op.getOpcode() == ISD::SIGN_EXTEND ||
2710 Op.getOpcode() == ISD::SIGN_EXTEND_INREG) {
2711 EVT OrigVT = Op.getOperand(0).getValueType();
2712 if (OrigVT.getSizeInBits() == OptSize) {
2713 S = Signed;
2714 return true;
2715 }
2716 } else if (Op.getOpcode() == ISD::ZERO_EXTEND) {
2717 EVT OrigVT = Op.getOperand(0).getValueType();
2718 if (OrigVT.getSizeInBits() == OptSize) {
2719 S = Unsigned;
2720 return true;
2721 }
2722 }
2723
2724 return false;
2725}
2726
2727/// AreMulWideOperandsDemotable - Checks if the given LHS and RHS operands can
2728/// be demoted to \p OptSize bits without loss of information. If the operands
2729/// contain a constant, it should appear as the RHS operand. The signedness of
2730/// the operands is placed in \p IsSigned.
2731static bool AreMulWideOperandsDemotable(SDValue LHS, SDValue RHS,
2732 unsigned OptSize,
2733 bool &IsSigned) {
2734
2735 OperandSignedness LHSSign;
2736
2737 // The LHS operand must be a demotable op
2738 if (!IsMulWideOperandDemotable(LHS, OptSize, LHSSign))
2739 return false;
2740
2741 // We should have been able to determine the signedness from the LHS
2742 if (LHSSign == Unknown)
2743 return false;
2744
2745 IsSigned = (LHSSign == Signed);
2746
2747 // The RHS can be a demotable op or a constant
2748 if (ConstantSDNode *CI = dyn_cast<ConstantSDNode>(RHS)) {
2749 APInt Val = CI->getAPIntValue();
2750 if (LHSSign == Unsigned) {
2751 if (Val.isIntN(OptSize)) {
2752 return true;
2753 }
2754 return false;
2755 } else {
2756 if (Val.isSignedIntN(OptSize)) {
2757 return true;
2758 }
2759 return false;
2760 }
2761 } else {
2762 OperandSignedness RHSSign;
2763 if (!IsMulWideOperandDemotable(RHS, OptSize, RHSSign))
2764 return false;
2765
2766 if (LHSSign != RHSSign)
2767 return false;
2768
2769 return true;
2770 }
2771}
2772
2773/// TryMULWIDECombine - Attempt to replace a multiply of M bits with a multiply
2774/// of M/2 bits that produces an M-bit result (i.e. mul.wide). This transform
2775/// works on both multiply DAG nodes and SHL DAG nodes with a constant shift
2776/// amount.
2777static SDValue TryMULWIDECombine(SDNode *N,
2778 TargetLowering::DAGCombinerInfo &DCI) {
2779 EVT MulType = N->getValueType(0);
2780 if (MulType != MVT::i32 && MulType != MVT::i64) {
2781 return SDValue();
2782 }
2783
2784 unsigned OptSize = MulType.getSizeInBits() >> 1;
2785 SDValue LHS = N->getOperand(0);
2786 SDValue RHS = N->getOperand(1);
2787
2788 // Canonicalize the multiply so the constant (if any) is on the right
2789 if (N->getOpcode() == ISD::MUL) {
2790 if (isa<ConstantSDNode>(LHS)) {
2791 std::swap(LHS, RHS);
2792 }
2793 }
2794
2795 // If we have a SHL, determine the actual multiply amount
2796 if (N->getOpcode() == ISD::SHL) {
2797 ConstantSDNode *ShlRHS = dyn_cast<ConstantSDNode>(RHS);
2798 if (!ShlRHS) {
2799 return SDValue();
2800 }
2801
2802 APInt ShiftAmt = ShlRHS->getAPIntValue();
2803 unsigned BitWidth = MulType.getSizeInBits();
2804 if (ShiftAmt.sge(0) && ShiftAmt.slt(BitWidth)) {
2805 APInt MulVal = APInt(BitWidth, 1) << ShiftAmt;
2806 RHS = DCI.DAG.getConstant(MulVal, MulType);
2807 } else {
2808 return SDValue();
2809 }
2810 }
2811
2812 bool Signed;
2813 // Verify that our operands are demotable
2814 if (!AreMulWideOperandsDemotable(LHS, RHS, OptSize, Signed)) {
2815 return SDValue();
2816 }
2817
2818 EVT DemotedVT;
2819 if (MulType == MVT::i32) {
2820 DemotedVT = MVT::i16;
2821 } else {
2822 DemotedVT = MVT::i32;
2823 }
2824
2825 // Truncate the operands to the correct size. Note that these are just for
2826 // type consistency and will (likely) be eliminated in later phases.
2827 SDValue TruncLHS =
2828 DCI.DAG.getNode(ISD::TRUNCATE, SDLoc(N), DemotedVT, LHS);
2829 SDValue TruncRHS =
2830 DCI.DAG.getNode(ISD::TRUNCATE, SDLoc(N), DemotedVT, RHS);
2831
2832 unsigned Opc;
2833 if (Signed) {
2834 Opc = NVPTXISD::MUL_WIDE_SIGNED;
2835 } else {
2836 Opc = NVPTXISD::MUL_WIDE_UNSIGNED;
2837 }
2838
2839 return DCI.DAG.getNode(Opc, SDLoc(N), MulType, TruncLHS, TruncRHS);
2840}
2841
2842/// PerformMULCombine - Runs PTX-specific DAG combine patterns on MUL nodes.
2843static SDValue PerformMULCombine(SDNode *N,
2844 TargetLowering::DAGCombinerInfo &DCI,
2845 CodeGenOpt::Level OptLevel) {
2846 if (OptLevel > 0) {
2847 // Try mul.wide combining at OptLevel > 0
2848 SDValue Ret = TryMULWIDECombine(N, DCI);
2849 if (Ret.getNode())
2850 return Ret;
2851 }
2852
2853 return SDValue();
2854}
2855
2856/// PerformSHLCombine - Runs PTX-specific DAG combine patterns on SHL nodes.
2857static SDValue PerformSHLCombine(SDNode *N,
2858 TargetLowering::DAGCombinerInfo &DCI,
2859 CodeGenOpt::Level OptLevel) {
2860 if (OptLevel > 0) {
2861 // Try mul.wide combining at OptLevel > 0
2862 SDValue Ret = TryMULWIDECombine(N, DCI);
2863 if (Ret.getNode())
2864 return Ret;
2865 }
2866
2867 return SDValue();
2868}
2869
2870SDValue NVPTXTargetLowering::PerformDAGCombine(SDNode *N,
2871 DAGCombinerInfo &DCI) const {
2872 // FIXME: Get this from the DAG somehow
2873 CodeGenOpt::Level OptLevel = CodeGenOpt::Aggressive;
2874 switch (N->getOpcode()) {
2875 default: break;
2876 case ISD::ADD:
2877 case ISD::FADD:
2878 return PerformADDCombine(N, DCI, nvptxSubtarget, OptLevel);
2879 case ISD::MUL:
2880 return PerformMULCombine(N, DCI, OptLevel);
2881 case ISD::SHL:
2882 return PerformSHLCombine(N, DCI, OptLevel);
2883 case ISD::AND:
2884 return PerformANDCombine(N, DCI);
2885 }
2886 return SDValue();
2887}
2888
Justin Holewinskibe8dc642013-02-12 14:18:49 +0000[diff] [blame]2889/// ReplaceVectorLoad - Convert vector loads into multi-output scalar loads.
2890static void ReplaceLoadVector(SDNode *N, SelectionDAG &DAG,
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]2891 SmallVectorImpl<SDValue> &Results) {
Justin Holewinskibe8dc642013-02-12 14:18:49 +0000[diff] [blame]2892 EVT ResVT = N->getValueType(0);
Andrew Trickef9de2a2013-05-25 02:42:55 +0000[diff] [blame]2893 SDLoc DL(N);
Justin Holewinskibe8dc642013-02-12 14:18:49 +0000[diff] [blame]2894
2895 assert(ResVT.isVector() && "Vector load must have vector type");
2896
2897 // We only handle "native" vector sizes for now, e.g. <4 x double> is not
2898 // legal. We can (and should) split that into 2 loads of <2 x double> here
2899 // but I'm leaving that as a TODO for now.
2900 assert(ResVT.isSimple() && "Can only handle simple types");
2901 switch (ResVT.getSimpleVT().SimpleTy) {
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]2902 default:
2903 return;
Justin Holewinskibe8dc642013-02-12 14:18:49 +0000[diff] [blame]2904 case MVT::v2i8:
2905 case MVT::v2i16:
2906 case MVT::v2i32:
2907 case MVT::v2i64:
2908 case MVT::v2f32:
2909 case MVT::v2f64:
2910 case MVT::v4i8:
2911 case MVT::v4i16:
2912 case MVT::v4i32:
2913 case MVT::v4f32:
2914 // This is a "native" vector type
2915 break;
2916 }
2917
2918 EVT EltVT = ResVT.getVectorElementType();
2919 unsigned NumElts = ResVT.getVectorNumElements();
2920
2921 // Since LoadV2 is a target node, we cannot rely on DAG type legalization.
2922 // Therefore, we must ensure the type is legal. For i1 and i8, we set the
Alp Tokercb402912014-01-24 17:20:08 +0000[diff] [blame]2923 // loaded type to i16 and propagate the "real" type as the memory type.
Justin Holewinskibe8dc642013-02-12 14:18:49 +0000[diff] [blame]2924 bool NeedTrunc = false;
2925 if (EltVT.getSizeInBits() < 16) {
2926 EltVT = MVT::i16;
2927 NeedTrunc = true;
2928 }
2929
2930 unsigned Opcode = 0;
2931 SDVTList LdResVTs;
2932
2933 switch (NumElts) {
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]2934 default:
2935 return;
Justin Holewinskibe8dc642013-02-12 14:18:49 +0000[diff] [blame]2936 case 2:
2937 Opcode = NVPTXISD::LoadV2;
2938 LdResVTs = DAG.getVTList(EltVT, EltVT, MVT::Other);
2939 break;
2940 case 4: {
2941 Opcode = NVPTXISD::LoadV4;
2942 EVT ListVTs[] = { EltVT, EltVT, EltVT, EltVT, MVT::Other };
Craig Topperabb4ac72014-04-16 06:10:51 +0000[diff] [blame]2943 LdResVTs = DAG.getVTList(ListVTs);
Justin Holewinskibe8dc642013-02-12 14:18:49 +0000[diff] [blame]2944 break;
2945 }
2946 }
2947
2948 SmallVector<SDValue, 8> OtherOps;
2949
2950 // Copy regular operands
2951 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
2952 OtherOps.push_back(N->getOperand(i));
2953
2954 LoadSDNode *LD = cast<LoadSDNode>(N);
2955
2956 // The select routine does not have access to the LoadSDNode instance, so
2957 // pass along the extension information
2958 OtherOps.push_back(DAG.getIntPtrConstant(LD->getExtensionType()));
2959
Craig Topper206fcd42014-04-26 19:29:41 +0000[diff] [blame]2960 SDValue NewLD = DAG.getMemIntrinsicNode(Opcode, DL, LdResVTs, OtherOps,
2961 LD->getMemoryVT(),
Justin Holewinskibe8dc642013-02-12 14:18:49 +0000[diff] [blame]2962 LD->getMemOperand());
2963
2964 SmallVector<SDValue, 4> ScalarRes;
2965
2966 for (unsigned i = 0; i < NumElts; ++i) {
2967 SDValue Res = NewLD.getValue(i);
2968 if (NeedTrunc)
2969 Res = DAG.getNode(ISD::TRUNCATE, DL, ResVT.getVectorElementType(), Res);
2970 ScalarRes.push_back(Res);
2971 }
2972
2973 SDValue LoadChain = NewLD.getValue(NumElts);
2974
Craig Topper48d114b2014-04-26 18:35:24 +0000[diff] [blame]2975 SDValue BuildVec = DAG.getNode(ISD::BUILD_VECTOR, DL, ResVT, ScalarRes);
Justin Holewinskibe8dc642013-02-12 14:18:49 +0000[diff] [blame]2976
2977 Results.push_back(BuildVec);
2978 Results.push_back(LoadChain);
2979}
2980
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]2981static void ReplaceINTRINSIC_W_CHAIN(SDNode *N, SelectionDAG &DAG,
Justin Holewinskibe8dc642013-02-12 14:18:49 +0000[diff] [blame]2982 SmallVectorImpl<SDValue> &Results) {
2983 SDValue Chain = N->getOperand(0);
2984 SDValue Intrin = N->getOperand(1);
Andrew Trickef9de2a2013-05-25 02:42:55 +0000[diff] [blame]2985 SDLoc DL(N);
Justin Holewinskibe8dc642013-02-12 14:18:49 +0000[diff] [blame]2986
2987 // Get the intrinsic ID
2988 unsigned IntrinNo = cast<ConstantSDNode>(Intrin.getNode())->getZExtValue();
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]2989 switch (IntrinNo) {
2990 default:
2991 return;
Justin Holewinskibe8dc642013-02-12 14:18:49 +0000[diff] [blame]2992 case Intrinsic::nvvm_ldg_global_i:
2993 case Intrinsic::nvvm_ldg_global_f:
2994 case Intrinsic::nvvm_ldg_global_p:
2995 case Intrinsic::nvvm_ldu_global_i:
2996 case Intrinsic::nvvm_ldu_global_f:
2997 case Intrinsic::nvvm_ldu_global_p: {
2998 EVT ResVT = N->getValueType(0);
2999
3000 if (ResVT.isVector()) {
3001 // Vector LDG/LDU
3002
3003 unsigned NumElts = ResVT.getVectorNumElements();
3004 EVT EltVT = ResVT.getVectorElementType();
3005
Justin Holewinskif8f70912013-06-28 17:57:59 +0000[diff] [blame]3006 // Since LDU/LDG are target nodes, we cannot rely on DAG type
3007 // legalization.
Justin Holewinskibe8dc642013-02-12 14:18:49 +0000[diff] [blame]3008 // Therefore, we must ensure the type is legal. For i1 and i8, we set the
Alp Tokercb402912014-01-24 17:20:08 +0000[diff] [blame]3009 // loaded type to i16 and propagate the "real" type as the memory type.
Justin Holewinskibe8dc642013-02-12 14:18:49 +0000[diff] [blame]3010 bool NeedTrunc = false;
3011 if (EltVT.getSizeInBits() < 16) {
3012 EltVT = MVT::i16;
3013 NeedTrunc = true;
3014 }
3015
3016 unsigned Opcode = 0;
3017 SDVTList LdResVTs;
3018
3019 switch (NumElts) {
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]3020 default:
3021 return;
Justin Holewinskibe8dc642013-02-12 14:18:49 +0000[diff] [blame]3022 case 2:
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]3023 switch (IntrinNo) {
3024 default:
3025 return;
Justin Holewinskibe8dc642013-02-12 14:18:49 +0000[diff] [blame]3026 case Intrinsic::nvvm_ldg_global_i:
3027 case Intrinsic::nvvm_ldg_global_f:
3028 case Intrinsic::nvvm_ldg_global_p:
3029 Opcode = NVPTXISD::LDGV2;
3030 break;
3031 case Intrinsic::nvvm_ldu_global_i:
3032 case Intrinsic::nvvm_ldu_global_f:
3033 case Intrinsic::nvvm_ldu_global_p:
3034 Opcode = NVPTXISD::LDUV2;
3035 break;
3036 }
3037 LdResVTs = DAG.getVTList(EltVT, EltVT, MVT::Other);
3038 break;
3039 case 4: {
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]3040 switch (IntrinNo) {
3041 default:
3042 return;
Justin Holewinskibe8dc642013-02-12 14:18:49 +0000[diff] [blame]3043 case Intrinsic::nvvm_ldg_global_i:
3044 case Intrinsic::nvvm_ldg_global_f:
3045 case Intrinsic::nvvm_ldg_global_p:
3046 Opcode = NVPTXISD::LDGV4;
3047 break;
3048 case Intrinsic::nvvm_ldu_global_i:
3049 case Intrinsic::nvvm_ldu_global_f:
3050 case Intrinsic::nvvm_ldu_global_p:
3051 Opcode = NVPTXISD::LDUV4;
3052 break;
3053 }
3054 EVT ListVTs[] = { EltVT, EltVT, EltVT, EltVT, MVT::Other };
Craig Topperabb4ac72014-04-16 06:10:51 +0000[diff] [blame]3055 LdResVTs = DAG.getVTList(ListVTs);
Justin Holewinskibe8dc642013-02-12 14:18:49 +0000[diff] [blame]3056 break;
3057 }
3058 }
3059
3060 SmallVector<SDValue, 8> OtherOps;
3061
3062 // Copy regular operands
3063
3064 OtherOps.push_back(Chain); // Chain
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]3065 // Skip operand 1 (intrinsic ID)
Justin Holewinskif8f70912013-06-28 17:57:59 +0000[diff] [blame]3066 // Others
Justin Holewinskibe8dc642013-02-12 14:18:49 +0000[diff] [blame]3067 for (unsigned i = 2, e = N->getNumOperands(); i != e; ++i)
3068 OtherOps.push_back(N->getOperand(i));
3069
3070 MemIntrinsicSDNode *MemSD = cast<MemIntrinsicSDNode>(N);
3071
Craig Topper206fcd42014-04-26 19:29:41 +0000[diff] [blame]3072 SDValue NewLD = DAG.getMemIntrinsicNode(Opcode, DL, LdResVTs, OtherOps,
3073 MemSD->getMemoryVT(),
3074 MemSD->getMemOperand());
Justin Holewinskibe8dc642013-02-12 14:18:49 +0000[diff] [blame]3075
3076 SmallVector<SDValue, 4> ScalarRes;
3077
3078 for (unsigned i = 0; i < NumElts; ++i) {
3079 SDValue Res = NewLD.getValue(i);
3080 if (NeedTrunc)
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]3081 Res =
3082 DAG.getNode(ISD::TRUNCATE, DL, ResVT.getVectorElementType(), Res);
Justin Holewinskibe8dc642013-02-12 14:18:49 +0000[diff] [blame]3083 ScalarRes.push_back(Res);
3084 }
3085
3086 SDValue LoadChain = NewLD.getValue(NumElts);
3087
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]3088 SDValue BuildVec =
Craig Topper48d114b2014-04-26 18:35:24 +0000[diff] [blame]3089 DAG.getNode(ISD::BUILD_VECTOR, DL, ResVT, ScalarRes);
Justin Holewinskibe8dc642013-02-12 14:18:49 +0000[diff] [blame]3090
3091 Results.push_back(BuildVec);
3092 Results.push_back(LoadChain);
3093 } else {
3094 // i8 LDG/LDU
3095 assert(ResVT.isSimple() && ResVT.getSimpleVT().SimpleTy == MVT::i8 &&
3096 "Custom handling of non-i8 ldu/ldg?");
3097
3098 // Just copy all operands as-is
3099 SmallVector<SDValue, 4> Ops;
3100 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
3101 Ops.push_back(N->getOperand(i));
3102
3103 // Force output to i16
3104 SDVTList LdResVTs = DAG.getVTList(MVT::i16, MVT::Other);
3105
3106 MemIntrinsicSDNode *MemSD = cast<MemIntrinsicSDNode>(N);
3107
3108 // We make sure the memory type is i8, which will be used during isel
3109 // to select the proper instruction.
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]3110 SDValue NewLD =
Craig Topper206fcd42014-04-26 19:29:41 +0000[diff] [blame]3111 DAG.getMemIntrinsicNode(ISD::INTRINSIC_W_CHAIN, DL, LdResVTs, Ops,
3112 MVT::i8, MemSD->getMemOperand());
Justin Holewinskibe8dc642013-02-12 14:18:49 +0000[diff] [blame]3113
Justin Holewinskie8c93e32013-07-01 12:58:48 +0000[diff] [blame]3114 Results.push_back(DAG.getNode(ISD::TRUNCATE, DL, MVT::i8,
3115 NewLD.getValue(0)));
Justin Holewinskibe8dc642013-02-12 14:18:49 +0000[diff] [blame]3116 Results.push_back(NewLD.getValue(1));
3117 }
3118 }
3119 }
3120}
3121
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]3122void NVPTXTargetLowering::ReplaceNodeResults(
3123 SDNode *N, SmallVectorImpl<SDValue> &Results, SelectionDAG &DAG) const {
Justin Holewinskibe8dc642013-02-12 14:18:49 +0000[diff] [blame]3124 switch (N->getOpcode()) {
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]3125 default:
3126 report_fatal_error("Unhandled custom legalization");
Justin Holewinskibe8dc642013-02-12 14:18:49 +0000[diff] [blame]3127 case ISD::LOAD:
3128 ReplaceLoadVector(N, DAG, Results);
3129 return;
3130 case ISD::INTRINSIC_W_CHAIN:
3131 ReplaceINTRINSIC_W_CHAIN(N, DAG, Results);
3132 return;
3133 }
3134}
Juergen Ributzkad12ccbd2013-11-19 00:57:56 +0000[diff] [blame]3135
3136// Pin NVPTXSection's and NVPTXTargetObjectFile's vtables to this file.
3137void NVPTXSection::anchor() {}
3138
3139NVPTXTargetObjectFile::~NVPTXTargetObjectFile() {
3140 delete TextSection;
3141 delete DataSection;
3142 delete BSSSection;
3143 delete ReadOnlySection;
3144
3145 delete StaticCtorSection;
3146 delete StaticDtorSection;
3147 delete LSDASection;
3148 delete EHFrameSection;
3149 delete DwarfAbbrevSection;
3150 delete DwarfInfoSection;
3151 delete DwarfLineSection;
3152 delete DwarfFrameSection;
3153 delete DwarfPubTypesSection;
3154 delete DwarfDebugInlineSection;
3155 delete DwarfStrSection;
3156 delete DwarfLocSection;
3157 delete DwarfARangesSection;
3158 delete DwarfRangesSection;
3159 delete DwarfMacroInfoSection;
3160}