Tom Stellard | 7d41161 | 2013-02-05 17:09:13 +0000 | [diff] [blame] | 1 | ; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s |
| 2 | |
| 3 | ; These tests make sure the compiler is optimizing branches using predicates |
| 4 | ; when it is legal to do so. |
| 5 | |
| 6 | ; CHECK: @simple_if |
| 7 | ; CHECK: PRED_SET{{[EGN][ET]*}}_INT Pred, |
| 8 | ; CHECK: LSHL T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}, 1, 0(0.000000e+00) Pred_sel |
| 9 | define void @simple_if(i32 addrspace(1)* %out, i32 %in) { |
| 10 | entry: |
| 11 | %0 = icmp sgt i32 %in, 0 |
| 12 | br i1 %0, label %IF, label %ENDIF |
| 13 | |
| 14 | IF: |
| 15 | %1 = shl i32 %in, 1 |
| 16 | br label %ENDIF |
| 17 | |
| 18 | ENDIF: |
| 19 | %2 = phi i32 [ %in, %entry ], [ %1, %IF ] |
| 20 | store i32 %2, i32 addrspace(1)* %out |
| 21 | ret void |
| 22 | } |
| 23 | |
| 24 | ; CHECK: @simple_if_else |
| 25 | ; CHECK: PRED_SET{{[EGN][ET]*}}_INT Pred, |
| 26 | ; CHECK: LSH{{[LR] T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}, 1, 0(0.000000e+00) Pred_sel |
| 27 | ; CHECK: LSH{{[LR] T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}, 1, 0(0.000000e+00) Pred_sel |
| 28 | define void @simple_if_else(i32 addrspace(1)* %out, i32 %in) { |
| 29 | entry: |
| 30 | %0 = icmp sgt i32 %in, 0 |
| 31 | br i1 %0, label %IF, label %ELSE |
| 32 | |
| 33 | IF: |
| 34 | %1 = shl i32 %in, 1 |
| 35 | br label %ENDIF |
| 36 | |
| 37 | ELSE: |
| 38 | %2 = lshr i32 %in, 1 |
| 39 | br label %ENDIF |
| 40 | |
| 41 | ENDIF: |
| 42 | %3 = phi i32 [ %1, %IF ], [ %2, %ELSE ] |
| 43 | store i32 %3, i32 addrspace(1)* %out |
| 44 | ret void |
| 45 | } |
| 46 | |
| 47 | ; CHECK: @nested_if |
Vincent Lejeune | bfaa63a6 | 2013-04-01 21:48:05 +0000 | [diff] [blame] | 48 | ; CHECK: ALU_PUSH_BEFORE |
Vincent Lejeune | bfaa63a6 | 2013-04-01 21:48:05 +0000 | [diff] [blame] | 49 | ; CHECK: JUMP |
Vincent Lejeune | 3abdbf1 | 2013-04-30 00:14:38 +0000 | [diff] [blame^] | 50 | ; CHECK: POP |
| 51 | ; CHECK: PRED_SET{{[EGN][ET]*}}_INT Exec |
Tom Stellard | 7d41161 | 2013-02-05 17:09:13 +0000 | [diff] [blame] | 52 | ; CHECK: PRED_SET{{[EGN][ET]*}}_INT Pred, |
| 53 | ; CHECK: LSHL T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}, 1, 0(0.000000e+00) Pred_sel |
Tom Stellard | 7d41161 | 2013-02-05 17:09:13 +0000 | [diff] [blame] | 54 | define void @nested_if(i32 addrspace(1)* %out, i32 %in) { |
| 55 | entry: |
| 56 | %0 = icmp sgt i32 %in, 0 |
| 57 | br i1 %0, label %IF0, label %ENDIF |
| 58 | |
| 59 | IF0: |
| 60 | %1 = add i32 %in, 10 |
| 61 | %2 = icmp sgt i32 %1, 0 |
| 62 | br i1 %2, label %IF1, label %ENDIF |
| 63 | |
| 64 | IF1: |
| 65 | %3 = shl i32 %1, 1 |
| 66 | br label %ENDIF |
| 67 | |
| 68 | ENDIF: |
| 69 | %4 = phi i32 [%in, %entry], [%1, %IF0], [%3, %IF1] |
| 70 | store i32 %4, i32 addrspace(1)* %out |
| 71 | ret void |
| 72 | } |
| 73 | |
| 74 | ; CHECK: @nested_if_else |
Vincent Lejeune | bfaa63a6 | 2013-04-01 21:48:05 +0000 | [diff] [blame] | 75 | ; CHECK: ALU_PUSH_BEFORE |
Vincent Lejeune | bfaa63a6 | 2013-04-01 21:48:05 +0000 | [diff] [blame] | 76 | ; CHECK: JUMP |
Vincent Lejeune | 3abdbf1 | 2013-04-30 00:14:38 +0000 | [diff] [blame^] | 77 | ; CHECK: POP |
| 78 | ; CHECK: PRED_SET{{[EGN][ET]*}}_INT Exec |
Tom Stellard | 7d41161 | 2013-02-05 17:09:13 +0000 | [diff] [blame] | 79 | ; CHECK: PRED_SET{{[EGN][ET]*}}_INT Pred, |
| 80 | ; CHECK: LSH{{[LR] T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}, 1, 0(0.000000e+00) Pred_sel |
| 81 | ; CHECK: LSH{{[LR] T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}, 1, 0(0.000000e+00) Pred_sel |
Tom Stellard | 7d41161 | 2013-02-05 17:09:13 +0000 | [diff] [blame] | 82 | define void @nested_if_else(i32 addrspace(1)* %out, i32 %in) { |
| 83 | entry: |
| 84 | %0 = icmp sgt i32 %in, 0 |
| 85 | br i1 %0, label %IF0, label %ENDIF |
| 86 | |
| 87 | IF0: |
| 88 | %1 = add i32 %in, 10 |
| 89 | %2 = icmp sgt i32 %1, 0 |
| 90 | br i1 %2, label %IF1, label %ELSE1 |
| 91 | |
| 92 | IF1: |
| 93 | %3 = shl i32 %1, 1 |
| 94 | br label %ENDIF |
| 95 | |
| 96 | ELSE1: |
| 97 | %4 = lshr i32 %in, 1 |
| 98 | br label %ENDIF |
| 99 | |
| 100 | ENDIF: |
| 101 | %5 = phi i32 [%in, %entry], [%3, %IF1], [%4, %ELSE1] |
| 102 | store i32 %5, i32 addrspace(1)* %out |
| 103 | ret void |
| 104 | } |