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gerrit-public.fairphone.software / toolchain / llvm-project / 413577a8790407d75ba834fa5668c2632fe1851e / . / llvm / lib / Support / X86TargetParser.cpp
blob: 99836b8460def2d33e810ef9d013b9d4429e066e [file] [log] [blame]
Craig Topperd5c28c42020-06-09 12:18:08 -0700[diff] [blame]1//===-- X86TargetParser - Parser for X86 features ---------------*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file implements a target parser to recognise X86 hardware features.
10//
11//===----------------------------------------------------------------------===//
12
13#include "llvm/Support/X86TargetParser.h"
14#include "llvm/ADT/StringSwitch.h"
15#include "llvm/ADT/Triple.h"
16
17using namespace llvm;
Craig Topper8dc92142020-06-24 10:36:02 -0700[diff] [blame]18using namespace llvm::X86;
Craig Topperd5c28c42020-06-09 12:18:08 -0700[diff] [blame]19
Craig Topper8dc92142020-06-24 10:36:02 -0700[diff] [blame]20namespace {
21
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]22/// Container class for CPU features.
23/// This is a constexpr reimplementation of a subset of std::bitset. It would be
24/// nice to use std::bitset directly, but it doesn't support constant
25/// initialization.
26class FeatureBitset {
27 static constexpr unsigned NUM_FEATURE_WORDS =
28 (X86::CPU_FEATURE_MAX + 31) / 32;
29
30 // This cannot be a std::array, operator[] is not constexpr until C++17.
31 uint32_t Bits[NUM_FEATURE_WORDS] = {};
32
33public:
34 constexpr FeatureBitset() = default;
35 constexpr FeatureBitset(std::initializer_list<unsigned> Init) {
36 for (auto I : Init)
37 set(I);
38 }
39
Fangrui Song0c7af8c2020-08-04 17:50:06 -0700[diff] [blame]40 bool any() const {
41 return llvm::any_of(Bits, [](uint64_t V) { return V != 0; });
42 }
43
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]44 constexpr FeatureBitset &set(unsigned I) {
Craig Topperf40b1132020-07-09 14:52:16 -0700[diff] [blame]45 // GCC <6.2 crashes if this is written in a single statement.
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]46 uint32_t NewBits = Bits[I / 32] | (uint32_t(1) << (I % 32));
47 Bits[I / 32] = NewBits;
48 return *this;
49 }
50
51 constexpr bool operator[](unsigned I) const {
52 uint32_t Mask = uint32_t(1) << (I % 32);
53 return (Bits[I / 32] & Mask) != 0;
54 }
55
Craig Topperf40b1132020-07-09 14:52:16 -0700[diff] [blame]56 constexpr FeatureBitset &operator&=(const FeatureBitset &RHS) {
57 for (unsigned I = 0, E = array_lengthof(Bits); I != E; ++I) {
58 // GCC <6.2 crashes if this is written in a single statement.
59 uint32_t NewBits = Bits[I] & RHS.Bits[I];
60 Bits[I] = NewBits;
61 }
62 return *this;
63 }
64
Craig Topper16f3d692020-07-06 22:47:54 -0700[diff] [blame]65 constexpr FeatureBitset &operator|=(const FeatureBitset &RHS) {
66 for (unsigned I = 0, E = array_lengthof(Bits); I != E; ++I) {
Craig Topperf40b1132020-07-09 14:52:16 -0700[diff] [blame]67 // GCC <6.2 crashes if this is written in a single statement.
Craig Topper16f3d692020-07-06 22:47:54 -0700[diff] [blame]68 uint32_t NewBits = Bits[I] | RHS.Bits[I];
69 Bits[I] = NewBits;
70 }
71 return *this;
72 }
73
Craig Topperf40b1132020-07-09 14:52:16 -0700[diff] [blame]74 // gcc 5.3 miscompiles this if we try to write this using operator&=.
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]75 constexpr FeatureBitset operator&(const FeatureBitset &RHS) const {
Hans Wennborg9ecda9a2020-07-09 17:47:35 +0200[diff] [blame]76 FeatureBitset Result;
77 for (unsigned I = 0, E = array_lengthof(Bits); I != E; ++I)
78 Result.Bits[I] = Bits[I] & RHS.Bits[I];
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]79 return Result;
80 }
81
Craig Topperf40b1132020-07-09 14:52:16 -0700[diff] [blame]82 // gcc 5.3 miscompiles this if we try to write this using operator&=.
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]83 constexpr FeatureBitset operator|(const FeatureBitset &RHS) const {
Hans Wennborg9ecda9a2020-07-09 17:47:35 +0200[diff] [blame]84 FeatureBitset Result;
85 for (unsigned I = 0, E = array_lengthof(Bits); I != E; ++I)
86 Result.Bits[I] = Bits[I] | RHS.Bits[I];
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]87 return Result;
88 }
89
90 constexpr FeatureBitset operator~() const {
91 FeatureBitset Result;
92 for (unsigned I = 0, E = array_lengthof(Bits); I != E; ++I)
93 Result.Bits[I] = ~Bits[I];
94 return Result;
95 }
Fangrui Song0c7af8c2020-08-04 17:50:06 -0700[diff] [blame]96
97 constexpr bool operator!=(const FeatureBitset &RHS) const {
98 for (unsigned I = 0, E = array_lengthof(Bits); I != E; ++I)
99 if (Bits[I] != RHS.Bits[I])
100 return true;
101 return false;
102 }
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]103};
104
Craig Topper8dc92142020-06-24 10:36:02 -0700[diff] [blame]105struct ProcInfo {
106 StringLiteral Name;
107 X86::CPUKind Kind;
108 unsigned KeyFeature;
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]109 FeatureBitset Features;
Craig Topper8dc92142020-06-24 10:36:02 -0700[diff] [blame]110};
111
Craig Topper16f3d692020-07-06 22:47:54 -0700[diff] [blame]112struct FeatureInfo {
113 StringLiteral Name;
114 FeatureBitset ImpliedFeatures;
115};
116
Craig Topper8dc92142020-06-24 10:36:02 -0700[diff] [blame]117} // end anonymous namespace
118
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]119#define X86_FEATURE(ENUM, STRING) \
120 static constexpr FeatureBitset Feature##ENUM = {X86::FEATURE_##ENUM};
121#include "llvm/Support/X86TargetParser.def"
122
123// Pentium with MMX.
124static constexpr FeatureBitset FeaturesPentiumMMX =
125 FeatureX87 | FeatureCMPXCHG8B | FeatureMMX;
126
127// Pentium 2 and 3.
128static constexpr FeatureBitset FeaturesPentium2 =
129 FeatureX87 | FeatureCMPXCHG8B | FeatureMMX | FeatureFXSR;
130static constexpr FeatureBitset FeaturesPentium3 = FeaturesPentium2 | FeatureSSE;
131
132// Pentium 4 CPUs
133static constexpr FeatureBitset FeaturesPentium4 =
134 FeaturesPentium3 | FeatureSSE2;
135static constexpr FeatureBitset FeaturesPrescott =
136 FeaturesPentium4 | FeatureSSE3;
137static constexpr FeatureBitset FeaturesNocona =
Craig Topperf40b1132020-07-09 14:52:16 -0700[diff] [blame]138 FeaturesPrescott | Feature64BIT | FeatureCMPXCHG16B;
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]139
140// Basic 64-bit capable CPU.
Craig Topperf40b1132020-07-09 14:52:16 -0700[diff] [blame]141static constexpr FeatureBitset FeaturesX86_64 = FeaturesPentium4 | Feature64BIT;
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]142
143// Intel Core CPUs
144static constexpr FeatureBitset FeaturesCore2 =
145 FeaturesNocona | FeatureSAHF | FeatureSSSE3;
146static constexpr FeatureBitset FeaturesPenryn = FeaturesCore2 | FeatureSSE4_1;
147static constexpr FeatureBitset FeaturesNehalem =
148 FeaturesPenryn | FeaturePOPCNT | FeatureSSE4_2;
149static constexpr FeatureBitset FeaturesWestmere =
150 FeaturesNehalem | FeaturePCLMUL;
151static constexpr FeatureBitset FeaturesSandyBridge =
152 FeaturesWestmere | FeatureAVX | FeatureXSAVE | FeatureXSAVEOPT;
153static constexpr FeatureBitset FeaturesIvyBridge =
154 FeaturesSandyBridge | FeatureF16C | FeatureFSGSBASE | FeatureRDRND;
155static constexpr FeatureBitset FeaturesHaswell =
156 FeaturesIvyBridge | FeatureAVX2 | FeatureBMI | FeatureBMI2 | FeatureFMA |
157 FeatureINVPCID | FeatureLZCNT | FeatureMOVBE;
158static constexpr FeatureBitset FeaturesBroadwell =
159 FeaturesHaswell | FeatureADX | FeaturePRFCHW | FeatureRDSEED;
160
161// Intel Knights Landing and Knights Mill
162// Knights Landing has feature parity with Broadwell.
163static constexpr FeatureBitset FeaturesKNL =
164 FeaturesBroadwell | FeatureAES | FeatureAVX512F | FeatureAVX512CD |
165 FeatureAVX512ER | FeatureAVX512PF | FeaturePREFETCHWT1;
166static constexpr FeatureBitset FeaturesKNM =
167 FeaturesKNL | FeatureAVX512VPOPCNTDQ;
168
169// Intel Skylake processors.
170static constexpr FeatureBitset FeaturesSkylakeClient =
171 FeaturesBroadwell | FeatureAES | FeatureCLFLUSHOPT | FeatureXSAVEC |
172 FeatureXSAVES | FeatureSGX;
173// SkylakeServer inherits all SkylakeClient features except SGX.
174// FIXME: That doesn't match gcc.
175static constexpr FeatureBitset FeaturesSkylakeServer =
176 (FeaturesSkylakeClient & ~FeatureSGX) | FeatureAVX512F | FeatureAVX512CD |
177 FeatureAVX512DQ | FeatureAVX512BW | FeatureAVX512VL | FeatureCLWB |
178 FeaturePKU;
179static constexpr FeatureBitset FeaturesCascadeLake =
180 FeaturesSkylakeServer | FeatureAVX512VNNI;
181static constexpr FeatureBitset FeaturesCooperLake =
182 FeaturesCascadeLake | FeatureAVX512BF16;
183
184// Intel 10nm processors.
185static constexpr FeatureBitset FeaturesCannonlake =
186 FeaturesSkylakeClient | FeatureAVX512F | FeatureAVX512CD | FeatureAVX512DQ |
187 FeatureAVX512BW | FeatureAVX512VL | FeatureAVX512IFMA | FeatureAVX512VBMI |
188 FeaturePKU | FeatureSHA;
189static constexpr FeatureBitset FeaturesICLClient =
190 FeaturesCannonlake | FeatureAVX512BITALG | FeatureAVX512VBMI2 |
191 FeatureAVX512VNNI | FeatureAVX512VPOPCNTDQ | FeatureCLWB | FeatureGFNI |
192 FeatureRDPID | FeatureVAES | FeatureVPCLMULQDQ;
193static constexpr FeatureBitset FeaturesICLServer =
194 FeaturesICLClient | FeaturePCONFIG | FeatureWBNOINVD;
195static constexpr FeatureBitset FeaturesTigerlake =
196 FeaturesICLClient | FeatureAVX512VP2INTERSECT | FeatureMOVDIR64B |
Xiang1 Zhang413577a2020-09-30 18:01:15 +0800[diff] [blame^]197 FeatureMOVDIRI | FeatureSHSTK | FeatureKL | FeatureWIDEKL;
Freddy Yee02d0812020-08-25 12:27:02 +0800[diff] [blame]198static constexpr FeatureBitset FeaturesSapphireRapids =
199 FeaturesICLServer | FeatureAMX_TILE | FeatureAMX_INT8 | FeatureAMX_BF16 |
200 FeatureAVX512BF16 | FeatureAVX512VP2INTERSECT | FeatureCLDEMOTE | FeatureENQCMD |
201 FeatureMOVDIR64B | FeatureMOVDIRI | FeaturePTWRITE | FeatureSERIALIZE |
202 FeatureSHSTK | FeatureTSXLDTRK | FeatureWAITPKG;
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]203
204// Intel Atom processors.
205// Bonnell has feature parity with Core2 and adds MOVBE.
206static constexpr FeatureBitset FeaturesBonnell = FeaturesCore2 | FeatureMOVBE;
207// Silvermont has parity with Westmere and Bonnell plus PRFCHW and RDRND.
208static constexpr FeatureBitset FeaturesSilvermont =
209 FeaturesBonnell | FeaturesWestmere | FeaturePRFCHW | FeatureRDRND;
210static constexpr FeatureBitset FeaturesGoldmont =
211 FeaturesSilvermont | FeatureAES | FeatureCLFLUSHOPT | FeatureFSGSBASE |
212 FeatureRDSEED | FeatureSHA | FeatureXSAVE | FeatureXSAVEC |
213 FeatureXSAVEOPT | FeatureXSAVES;
214static constexpr FeatureBitset FeaturesGoldmontPlus =
215 FeaturesGoldmont | FeaturePTWRITE | FeatureRDPID | FeatureSGX;
216static constexpr FeatureBitset FeaturesTremont =
217 FeaturesGoldmontPlus | FeatureCLWB | FeatureGFNI;
218
219// Geode Processor.
220static constexpr FeatureBitset FeaturesGeode =
221 FeatureX87 | FeatureCMPXCHG8B | FeatureMMX | Feature3DNOW | Feature3DNOWA;
222
223// K6 processor.
224static constexpr FeatureBitset FeaturesK6 =
225 FeatureX87 | FeatureCMPXCHG8B | FeatureMMX;
226
227// K7 and K8 architecture processors.
228static constexpr FeatureBitset FeaturesAthlon =
229 FeatureX87 | FeatureCMPXCHG8B | FeatureMMX | Feature3DNOW | Feature3DNOWA;
230static constexpr FeatureBitset FeaturesAthlonXP =
231 FeaturesAthlon | FeatureFXSR | FeatureSSE;
232static constexpr FeatureBitset FeaturesK8 =
Craig Topperf40b1132020-07-09 14:52:16 -0700[diff] [blame]233 FeaturesAthlonXP | FeatureSSE2 | Feature64BIT;
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]234static constexpr FeatureBitset FeaturesK8SSE3 = FeaturesK8 | FeatureSSE3;
235static constexpr FeatureBitset FeaturesAMDFAM10 =
236 FeaturesK8SSE3 | FeatureCMPXCHG16B | FeatureLZCNT | FeaturePOPCNT |
Craig Topper7fb3a842020-07-06 22:11:17 -0700[diff] [blame]237 FeaturePRFCHW | FeatureSAHF | FeatureSSE4_A;
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]238
239// Bobcat architecture processors.
240static constexpr FeatureBitset FeaturesBTVER1 =
Craig Topperf40b1132020-07-09 14:52:16 -0700[diff] [blame]241 FeatureX87 | FeatureCMPXCHG8B | FeatureCMPXCHG16B | Feature64BIT |
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]242 FeatureFXSR | FeatureLZCNT | FeatureMMX | FeaturePOPCNT | FeaturePRFCHW |
Craig Topper7fb3a842020-07-06 22:11:17 -0700[diff] [blame]243 FeatureSSE | FeatureSSE2 | FeatureSSE3 | FeatureSSSE3 | FeatureSSE4_A |
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]244 FeatureSAHF;
245static constexpr FeatureBitset FeaturesBTVER2 =
246 FeaturesBTVER1 | FeatureAES | FeatureAVX | FeatureBMI | FeatureF16C |
247 FeatureMOVBE | FeaturePCLMUL | FeatureXSAVE | FeatureXSAVEOPT;
248
249// AMD Bulldozer architecture processors.
250static constexpr FeatureBitset FeaturesBDVER1 =
251 FeatureX87 | FeatureAES | FeatureAVX | FeatureCMPXCHG8B |
Craig Topperf40b1132020-07-09 14:52:16 -0700[diff] [blame]252 FeatureCMPXCHG16B | Feature64BIT | FeatureFMA4 | FeatureFXSR | FeatureLWP |
Douglas Yung56fc6b92020-06-30 18:10:09 -0700[diff] [blame]253 FeatureLZCNT | FeatureMMX | FeaturePCLMUL | FeaturePOPCNT | FeaturePRFCHW |
254 FeatureSAHF | FeatureSSE | FeatureSSE2 | FeatureSSE3 | FeatureSSSE3 |
Craig Topper7fb3a842020-07-06 22:11:17 -0700[diff] [blame]255 FeatureSSE4_1 | FeatureSSE4_2 | FeatureSSE4_A | FeatureXOP | FeatureXSAVE;
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]256static constexpr FeatureBitset FeaturesBDVER2 =
257 FeaturesBDVER1 | FeatureBMI | FeatureFMA | FeatureF16C | FeatureTBM;
258static constexpr FeatureBitset FeaturesBDVER3 =
259 FeaturesBDVER2 | FeatureFSGSBASE | FeatureXSAVEOPT;
260static constexpr FeatureBitset FeaturesBDVER4 =
261 FeaturesBDVER3 | FeatureAVX2 | FeatureBMI2 | FeatureMOVBE | FeatureMWAITX |
262 FeatureRDRND;
263
264// AMD Zen architecture processors.
265static constexpr FeatureBitset FeaturesZNVER1 =
266 FeatureX87 | FeatureADX | FeatureAES | FeatureAVX | FeatureAVX2 |
267 FeatureBMI | FeatureBMI2 | FeatureCLFLUSHOPT | FeatureCLZERO |
Craig Topperf40b1132020-07-09 14:52:16 -0700[diff] [blame]268 FeatureCMPXCHG8B | FeatureCMPXCHG16B | Feature64BIT | FeatureF16C |
Douglas Yung56fc6b92020-06-30 18:10:09 -0700[diff] [blame]269 FeatureFMA | FeatureFSGSBASE | FeatureFXSR | FeatureLZCNT | FeatureMMX |
270 FeatureMOVBE | FeatureMWAITX | FeaturePCLMUL | FeaturePOPCNT |
271 FeaturePRFCHW | FeatureRDRND | FeatureRDSEED | FeatureSAHF | FeatureSHA |
272 FeatureSSE | FeatureSSE2 | FeatureSSE3 | FeatureSSSE3 | FeatureSSE4_1 |
Craig Topper7fb3a842020-07-06 22:11:17 -0700[diff] [blame]273 FeatureSSE4_2 | FeatureSSE4_A | FeatureXSAVE | FeatureXSAVEC |
Douglas Yung56fc6b92020-06-30 18:10:09 -0700[diff] [blame]274 FeatureXSAVEOPT | FeatureXSAVES;
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]275static constexpr FeatureBitset FeaturesZNVER2 =
276 FeaturesZNVER1 | FeatureCLWB | FeatureRDPID | FeatureWBNOINVD;
Craig Topper8dc92142020-06-24 10:36:02 -0700[diff] [blame]277
278static constexpr ProcInfo Processors[] = {
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]279 // Empty processor. Include X87 and CMPXCHG8 for backwards compatibility.
280 { {""}, CK_None, ~0U, FeatureX87 | FeatureCMPXCHG8B },
Craig Topper8dc92142020-06-24 10:36:02 -0700[diff] [blame]281 // i386-generation processors.
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]282 { {"i386"}, CK_i386, ~0U, FeatureX87 },
Craig Topper8dc92142020-06-24 10:36:02 -0700[diff] [blame]283 // i486-generation processors.
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]284 { {"i486"}, CK_i486, ~0U, FeatureX87 },
285 { {"winchip-c6"}, CK_WinChipC6, ~0U, FeaturesPentiumMMX },
286 { {"winchip2"}, CK_WinChip2, ~0U, FeaturesPentiumMMX | Feature3DNOW },
287 { {"c3"}, CK_C3, ~0U, FeaturesPentiumMMX | Feature3DNOW },
Craig Topper8dc92142020-06-24 10:36:02 -0700[diff] [blame]288 // i586-generation processors, P5 microarchitecture based.
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]289 { {"i586"}, CK_i586, ~0U, FeatureX87 | FeatureCMPXCHG8B },
290 { {"pentium"}, CK_Pentium, ~0U, FeatureX87 | FeatureCMPXCHG8B },
291 { {"pentium-mmx"}, CK_PentiumMMX, ~0U, FeaturesPentiumMMX },
Craig Topper8dc92142020-06-24 10:36:02 -0700[diff] [blame]292 // i686-generation processors, P6 / Pentium M microarchitecture based.
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]293 { {"pentiumpro"}, CK_PentiumPro, ~0U, FeatureX87 | FeatureCMPXCHG8B },
294 { {"i686"}, CK_i686, ~0U, FeatureX87 | FeatureCMPXCHG8B },
295 { {"pentium2"}, CK_Pentium2, ~0U, FeaturesPentium2 },
296 { {"pentium3"}, CK_Pentium3, ~0U, FeaturesPentium3 },
297 { {"pentium3m"}, CK_Pentium3, ~0U, FeaturesPentium3 },
298 { {"pentium-m"}, CK_PentiumM, ~0U, FeaturesPentium4 },
299 { {"c3-2"}, CK_C3_2, ~0U, FeaturesPentium3 },
300 { {"yonah"}, CK_Yonah, ~0U, FeaturesPrescott },
Craig Topper8dc92142020-06-24 10:36:02 -0700[diff] [blame]301 // Netburst microarchitecture based processors.
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]302 { {"pentium4"}, CK_Pentium4, ~0U, FeaturesPentium4 },
303 { {"pentium4m"}, CK_Pentium4, ~0U, FeaturesPentium4 },
304 { {"prescott"}, CK_Prescott, ~0U, FeaturesPrescott },
305 { {"nocona"}, CK_Nocona, ~0U, FeaturesNocona },
Craig Topper8dc92142020-06-24 10:36:02 -0700[diff] [blame]306 // Core microarchitecture based processors.
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]307 { {"core2"}, CK_Core2, ~0U, FeaturesCore2 },
308 { {"penryn"}, CK_Penryn, ~0U, FeaturesPenryn },
Craig Topper8dc92142020-06-24 10:36:02 -0700[diff] [blame]309 // Atom processors
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]310 { {"bonnell"}, CK_Bonnell, FEATURE_SSSE3, FeaturesBonnell },
311 { {"atom"}, CK_Bonnell, FEATURE_SSSE3, FeaturesBonnell },
312 { {"silvermont"}, CK_Silvermont, FEATURE_SSE4_2, FeaturesSilvermont },
313 { {"slm"}, CK_Silvermont, FEATURE_SSE4_2, FeaturesSilvermont },
314 { {"goldmont"}, CK_Goldmont, FEATURE_SSE4_2, FeaturesGoldmont },
315 { {"goldmont-plus"}, CK_GoldmontPlus, FEATURE_SSE4_2, FeaturesGoldmontPlus },
316 { {"tremont"}, CK_Tremont, FEATURE_SSE4_2, FeaturesTremont },
Craig Topper8dc92142020-06-24 10:36:02 -0700[diff] [blame]317 // Nehalem microarchitecture based processors.
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]318 { {"nehalem"}, CK_Nehalem, FEATURE_SSE4_2, FeaturesNehalem },
319 { {"corei7"}, CK_Nehalem, FEATURE_SSE4_2, FeaturesNehalem },
Craig Topper8dc92142020-06-24 10:36:02 -0700[diff] [blame]320 // Westmere microarchitecture based processors.
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]321 { {"westmere"}, CK_Westmere, FEATURE_PCLMUL, FeaturesWestmere },
Craig Topper8dc92142020-06-24 10:36:02 -0700[diff] [blame]322 // Sandy Bridge microarchitecture based processors.
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]323 { {"sandybridge"}, CK_SandyBridge, FEATURE_AVX, FeaturesSandyBridge },
324 { {"corei7-avx"}, CK_SandyBridge, FEATURE_AVX, FeaturesSandyBridge },
Craig Topper8dc92142020-06-24 10:36:02 -0700[diff] [blame]325 // Ivy Bridge microarchitecture based processors.
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]326 { {"ivybridge"}, CK_IvyBridge, FEATURE_AVX, FeaturesIvyBridge },
327 { {"core-avx-i"}, CK_IvyBridge, FEATURE_AVX, FeaturesIvyBridge },
Craig Topper8dc92142020-06-24 10:36:02 -0700[diff] [blame]328 // Haswell microarchitecture based processors.
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]329 { {"haswell"}, CK_Haswell, FEATURE_AVX2, FeaturesHaswell },
330 { {"core-avx2"}, CK_Haswell, FEATURE_AVX2, FeaturesHaswell },
Craig Topper8dc92142020-06-24 10:36:02 -0700[diff] [blame]331 // Broadwell microarchitecture based processors.
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]332 { {"broadwell"}, CK_Broadwell, FEATURE_AVX2, FeaturesBroadwell },
Craig Topper8dc92142020-06-24 10:36:02 -0700[diff] [blame]333 // Skylake client microarchitecture based processors.
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]334 { {"skylake"}, CK_SkylakeClient, FEATURE_AVX2, FeaturesSkylakeClient },
Craig Topper8dc92142020-06-24 10:36:02 -0700[diff] [blame]335 // Skylake server microarchitecture based processors.
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]336 { {"skylake-avx512"}, CK_SkylakeServer, FEATURE_AVX512F, FeaturesSkylakeServer },
337 { {"skx"}, CK_SkylakeServer, FEATURE_AVX512F, FeaturesSkylakeServer },
Craig Topper8dc92142020-06-24 10:36:02 -0700[diff] [blame]338 // Cascadelake Server microarchitecture based processors.
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]339 { {"cascadelake"}, CK_Cascadelake, FEATURE_AVX512VNNI, FeaturesCascadeLake },
Craig Topper8dc92142020-06-24 10:36:02 -0700[diff] [blame]340 // Cooperlake Server microarchitecture based processors.
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]341 { {"cooperlake"}, CK_Cooperlake, FEATURE_AVX512BF16, FeaturesCooperLake },
Craig Topper8dc92142020-06-24 10:36:02 -0700[diff] [blame]342 // Cannonlake client microarchitecture based processors.
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]343 { {"cannonlake"}, CK_Cannonlake, FEATURE_AVX512VBMI, FeaturesCannonlake },
Craig Topper8dc92142020-06-24 10:36:02 -0700[diff] [blame]344 // Icelake client microarchitecture based processors.
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]345 { {"icelake-client"}, CK_IcelakeClient, FEATURE_AVX512VBMI2, FeaturesICLClient },
Craig Topper8dc92142020-06-24 10:36:02 -0700[diff] [blame]346 // Icelake server microarchitecture based processors.
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]347 { {"icelake-server"}, CK_IcelakeServer, FEATURE_AVX512VBMI2, FeaturesICLServer },
Craig Topper8dc92142020-06-24 10:36:02 -0700[diff] [blame]348 // Tigerlake microarchitecture based processors.
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]349 { {"tigerlake"}, CK_Tigerlake, FEATURE_AVX512VP2INTERSECT, FeaturesTigerlake },
Freddy Yee02d0812020-08-25 12:27:02 +0800[diff] [blame]350 // Sapphire Rapids microarchitecture based processors.
351 { {"sapphirerapids"}, CK_SapphireRapids, FEATURE_AVX512VP2INTERSECT, FeaturesSapphireRapids },
Craig Topper8dc92142020-06-24 10:36:02 -0700[diff] [blame]352 // Knights Landing processor.
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]353 { {"knl"}, CK_KNL, FEATURE_AVX512F, FeaturesKNL },
Craig Topper8dc92142020-06-24 10:36:02 -0700[diff] [blame]354 // Knights Mill processor.
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]355 { {"knm"}, CK_KNM, FEATURE_AVX5124FMAPS, FeaturesKNM },
Craig Topper8dc92142020-06-24 10:36:02 -0700[diff] [blame]356 // Lakemont microarchitecture based processors.
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]357 { {"lakemont"}, CK_Lakemont, ~0U, FeatureCMPXCHG8B },
Craig Topper8dc92142020-06-24 10:36:02 -0700[diff] [blame]358 // K6 architecture processors.
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]359 { {"k6"}, CK_K6, ~0U, FeaturesK6 },
360 { {"k6-2"}, CK_K6_2, ~0U, FeaturesK6 | Feature3DNOW },
361 { {"k6-3"}, CK_K6_3, ~0U, FeaturesK6 | Feature3DNOW },
Craig Topper8dc92142020-06-24 10:36:02 -0700[diff] [blame]362 // K7 architecture processors.
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]363 { {"athlon"}, CK_Athlon, ~0U, FeaturesAthlon },
364 { {"athlon-tbird"}, CK_Athlon, ~0U, FeaturesAthlon },
365 { {"athlon-xp"}, CK_AthlonXP, ~0U, FeaturesAthlonXP },
366 { {"athlon-mp"}, CK_AthlonXP, ~0U, FeaturesAthlonXP },
367 { {"athlon-4"}, CK_AthlonXP, ~0U, FeaturesAthlonXP },
Craig Topper8dc92142020-06-24 10:36:02 -0700[diff] [blame]368 // K8 architecture processors.
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]369 { {"k8"}, CK_K8, ~0U, FeaturesK8 },
370 { {"athlon64"}, CK_K8, ~0U, FeaturesK8 },
371 { {"athlon-fx"}, CK_K8, ~0U, FeaturesK8 },
372 { {"opteron"}, CK_K8, ~0U, FeaturesK8 },
373 { {"k8-sse3"}, CK_K8SSE3, ~0U, FeaturesK8SSE3 },
374 { {"athlon64-sse3"}, CK_K8SSE3, ~0U, FeaturesK8SSE3 },
375 { {"opteron-sse3"}, CK_K8SSE3, ~0U, FeaturesK8SSE3 },
376 { {"amdfam10"}, CK_AMDFAM10, FEATURE_SSE4_A, FeaturesAMDFAM10 },
377 { {"barcelona"}, CK_AMDFAM10, FEATURE_SSE4_A, FeaturesAMDFAM10 },
Craig Topper8dc92142020-06-24 10:36:02 -0700[diff] [blame]378 // Bobcat architecture processors.
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]379 { {"btver1"}, CK_BTVER1, FEATURE_SSE4_A, FeaturesBTVER1 },
380 { {"btver2"}, CK_BTVER2, FEATURE_BMI, FeaturesBTVER2 },
Craig Topper8dc92142020-06-24 10:36:02 -0700[diff] [blame]381 // Bulldozer architecture processors.
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]382 { {"bdver1"}, CK_BDVER1, FEATURE_XOP, FeaturesBDVER1 },
383 { {"bdver2"}, CK_BDVER2, FEATURE_FMA, FeaturesBDVER2 },
384 { {"bdver3"}, CK_BDVER3, FEATURE_FMA, FeaturesBDVER3 },
385 { {"bdver4"}, CK_BDVER4, FEATURE_AVX2, FeaturesBDVER4 },
Craig Topper8dc92142020-06-24 10:36:02 -0700[diff] [blame]386 // Zen architecture processors.
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]387 { {"znver1"}, CK_ZNVER1, FEATURE_AVX2, FeaturesZNVER1 },
388 { {"znver2"}, CK_ZNVER2, FEATURE_AVX2, FeaturesZNVER2 },
Craig Topper8dc92142020-06-24 10:36:02 -0700[diff] [blame]389 // Generic 64-bit processor.
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]390 { {"x86-64"}, CK_x86_64, ~0U, FeaturesX86_64 },
Craig Topper8dc92142020-06-24 10:36:02 -0700[diff] [blame]391 // Geode processors.
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]392 { {"geode"}, CK_Geode, ~0U, FeaturesGeode },
Craig Topper8dc92142020-06-24 10:36:02 -0700[diff] [blame]393};
Craig Topperd5c28c42020-06-09 12:18:08 -0700[diff] [blame]394
395X86::CPUKind llvm::X86::parseArchX86(StringRef CPU, bool Only64Bit) {
Craig Topper8dc92142020-06-24 10:36:02 -0700[diff] [blame]396 for (const auto &P : Processors)
Craig Topperf40b1132020-07-09 14:52:16 -0700[diff] [blame]397 if (P.Name == CPU && (P.Features[FEATURE_64BIT] || !Only64Bit))
Craig Topper8dc92142020-06-24 10:36:02 -0700[diff] [blame]398 return P.Kind;
Craig Topperd5c28c42020-06-09 12:18:08 -0700[diff] [blame]399
Craig Topper8dc92142020-06-24 10:36:02 -0700[diff] [blame]400 return CK_None;
Craig Topperd5c28c42020-06-09 12:18:08 -0700[diff] [blame]401}
402
403void llvm::X86::fillValidCPUArchList(SmallVectorImpl<StringRef> &Values,
404 bool Only64Bit) {
Craig Topper8dc92142020-06-24 10:36:02 -0700[diff] [blame]405 for (const auto &P : Processors)
Craig Topperf40b1132020-07-09 14:52:16 -0700[diff] [blame]406 if (!P.Name.empty() && (P.Features[FEATURE_64BIT] || !Only64Bit))
Craig Topper8dc92142020-06-24 10:36:02 -0700[diff] [blame]407 Values.emplace_back(P.Name);
408}
409
410ProcessorFeatures llvm::X86::getKeyFeature(X86::CPUKind Kind) {
411 // FIXME: Can we avoid a linear search here? The table might be sorted by
412 // CPUKind so we could binary search?
413 for (const auto &P : Processors) {
414 if (P.Kind == Kind) {
415 assert(P.KeyFeature != ~0U && "Processor does not have a key feature.");
416 return static_cast<ProcessorFeatures>(P.KeyFeature);
417 }
418 }
419
420 llvm_unreachable("Unable to find CPU kind!");
Craig Topperd5c28c42020-06-09 12:18:08 -0700[diff] [blame]421}
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]422
Craig Topper16f3d692020-07-06 22:47:54 -0700[diff] [blame]423// Features with no dependencies.
Craig Topper44ea81a2020-07-07 00:27:50 -0700[diff] [blame]424static constexpr FeatureBitset ImpliedFeatures64BIT = {};
Craig Topper16f3d692020-07-06 22:47:54 -0700[diff] [blame]425static constexpr FeatureBitset ImpliedFeaturesADX = {};
426static constexpr FeatureBitset ImpliedFeaturesBMI = {};
427static constexpr FeatureBitset ImpliedFeaturesBMI2 = {};
428static constexpr FeatureBitset ImpliedFeaturesCLDEMOTE = {};
429static constexpr FeatureBitset ImpliedFeaturesCLFLUSHOPT = {};
430static constexpr FeatureBitset ImpliedFeaturesCLWB = {};
431static constexpr FeatureBitset ImpliedFeaturesCLZERO = {};
432static constexpr FeatureBitset ImpliedFeaturesCMOV = {};
433static constexpr FeatureBitset ImpliedFeaturesCMPXCHG16B = {};
434static constexpr FeatureBitset ImpliedFeaturesCMPXCHG8B = {};
Craig Topper16f3d692020-07-06 22:47:54 -0700[diff] [blame]435static constexpr FeatureBitset ImpliedFeaturesENQCMD = {};
436static constexpr FeatureBitset ImpliedFeaturesFSGSBASE = {};
437static constexpr FeatureBitset ImpliedFeaturesFXSR = {};
438static constexpr FeatureBitset ImpliedFeaturesINVPCID = {};
439static constexpr FeatureBitset ImpliedFeaturesLWP = {};
440static constexpr FeatureBitset ImpliedFeaturesLZCNT = {};
441static constexpr FeatureBitset ImpliedFeaturesMWAITX = {};
442static constexpr FeatureBitset ImpliedFeaturesMOVBE = {};
443static constexpr FeatureBitset ImpliedFeaturesMOVDIR64B = {};
444static constexpr FeatureBitset ImpliedFeaturesMOVDIRI = {};
445static constexpr FeatureBitset ImpliedFeaturesPCONFIG = {};
446static constexpr FeatureBitset ImpliedFeaturesPOPCNT = {};
447static constexpr FeatureBitset ImpliedFeaturesPKU = {};
448static constexpr FeatureBitset ImpliedFeaturesPREFETCHWT1 = {};
449static constexpr FeatureBitset ImpliedFeaturesPRFCHW = {};
450static constexpr FeatureBitset ImpliedFeaturesPTWRITE = {};
451static constexpr FeatureBitset ImpliedFeaturesRDPID = {};
452static constexpr FeatureBitset ImpliedFeaturesRDRND = {};
453static constexpr FeatureBitset ImpliedFeaturesRDSEED = {};
454static constexpr FeatureBitset ImpliedFeaturesRTM = {};
455static constexpr FeatureBitset ImpliedFeaturesSAHF = {};
456static constexpr FeatureBitset ImpliedFeaturesSERIALIZE = {};
457static constexpr FeatureBitset ImpliedFeaturesSGX = {};
458static constexpr FeatureBitset ImpliedFeaturesSHSTK = {};
459static constexpr FeatureBitset ImpliedFeaturesTBM = {};
460static constexpr FeatureBitset ImpliedFeaturesTSXLDTRK = {};
461static constexpr FeatureBitset ImpliedFeaturesWAITPKG = {};
462static constexpr FeatureBitset ImpliedFeaturesWBNOINVD = {};
463static constexpr FeatureBitset ImpliedFeaturesVZEROUPPER = {};
464static constexpr FeatureBitset ImpliedFeaturesX87 = {};
465static constexpr FeatureBitset ImpliedFeaturesXSAVE = {};
466
467// Not really CPU features, but need to be in the table because clang uses
468// target features to communicate them to the backend.
Craig Topper44ea81a2020-07-07 00:27:50 -0700[diff] [blame]469static constexpr FeatureBitset ImpliedFeaturesRETPOLINE_EXTERNAL_THUNK = {};
Craig Topper16f3d692020-07-06 22:47:54 -0700[diff] [blame]470static constexpr FeatureBitset ImpliedFeaturesRETPOLINE_INDIRECT_BRANCHES = {};
471static constexpr FeatureBitset ImpliedFeaturesRETPOLINE_INDIRECT_CALLS = {};
472static constexpr FeatureBitset ImpliedFeaturesLVI_CFI = {};
473static constexpr FeatureBitset ImpliedFeaturesLVI_LOAD_HARDENING = {};
474
475// XSAVE features are dependent on basic XSAVE.
476static constexpr FeatureBitset ImpliedFeaturesXSAVEC = FeatureXSAVE;
477static constexpr FeatureBitset ImpliedFeaturesXSAVEOPT = FeatureXSAVE;
478static constexpr FeatureBitset ImpliedFeaturesXSAVES = FeatureXSAVE;
479
480// MMX->3DNOW->3DNOWA chain.
481static constexpr FeatureBitset ImpliedFeaturesMMX = {};
482static constexpr FeatureBitset ImpliedFeatures3DNOW = FeatureMMX;
483static constexpr FeatureBitset ImpliedFeatures3DNOWA = Feature3DNOW;
484
485// SSE/AVX/AVX512F chain.
486static constexpr FeatureBitset ImpliedFeaturesSSE = {};
487static constexpr FeatureBitset ImpliedFeaturesSSE2 = FeatureSSE;
488static constexpr FeatureBitset ImpliedFeaturesSSE3 = FeatureSSE2;
489static constexpr FeatureBitset ImpliedFeaturesSSSE3 = FeatureSSE3;
490static constexpr FeatureBitset ImpliedFeaturesSSE4_1 = FeatureSSSE3;
491static constexpr FeatureBitset ImpliedFeaturesSSE4_2 = FeatureSSE4_1;
492static constexpr FeatureBitset ImpliedFeaturesAVX = FeatureSSE4_2;
493static constexpr FeatureBitset ImpliedFeaturesAVX2 = FeatureAVX;
494static constexpr FeatureBitset ImpliedFeaturesAVX512F =
495 FeatureAVX2 | FeatureF16C | FeatureFMA;
496
497// Vector extensions that build on SSE or AVX.
498static constexpr FeatureBitset ImpliedFeaturesAES = FeatureSSE2;
499static constexpr FeatureBitset ImpliedFeaturesF16C = FeatureAVX;
500static constexpr FeatureBitset ImpliedFeaturesFMA = FeatureAVX;
501static constexpr FeatureBitset ImpliedFeaturesGFNI = FeatureSSE2;
502static constexpr FeatureBitset ImpliedFeaturesPCLMUL = FeatureSSE2;
503static constexpr FeatureBitset ImpliedFeaturesSHA = FeatureSSE2;
504static constexpr FeatureBitset ImpliedFeaturesVAES = FeatureAES | FeatureAVX;
505static constexpr FeatureBitset ImpliedFeaturesVPCLMULQDQ =
506 FeatureAVX | FeaturePCLMUL;
507
508// AVX512 features.
509static constexpr FeatureBitset ImpliedFeaturesAVX512CD = FeatureAVX512F;
510static constexpr FeatureBitset ImpliedFeaturesAVX512BW = FeatureAVX512F;
511static constexpr FeatureBitset ImpliedFeaturesAVX512DQ = FeatureAVX512F;
512static constexpr FeatureBitset ImpliedFeaturesAVX512ER = FeatureAVX512F;
513static constexpr FeatureBitset ImpliedFeaturesAVX512PF = FeatureAVX512F;
514static constexpr FeatureBitset ImpliedFeaturesAVX512VL = FeatureAVX512F;
515
516static constexpr FeatureBitset ImpliedFeaturesAVX512BF16 = FeatureAVX512BW;
517static constexpr FeatureBitset ImpliedFeaturesAVX512BITALG = FeatureAVX512BW;
518static constexpr FeatureBitset ImpliedFeaturesAVX512IFMA = FeatureAVX512F;
519static constexpr FeatureBitset ImpliedFeaturesAVX512VNNI = FeatureAVX512F;
520static constexpr FeatureBitset ImpliedFeaturesAVX512VPOPCNTDQ = FeatureAVX512F;
521static constexpr FeatureBitset ImpliedFeaturesAVX512VBMI = FeatureAVX512BW;
522static constexpr FeatureBitset ImpliedFeaturesAVX512VBMI2 = FeatureAVX512BW;
523static constexpr FeatureBitset ImpliedFeaturesAVX512VP2INTERSECT =
524 FeatureAVX512F;
525
526// FIXME: These two aren't really implemented and just exist in the feature
527// list for __builtin_cpu_supports. So omit their dependencies.
528static constexpr FeatureBitset ImpliedFeaturesAVX5124FMAPS = {};
529static constexpr FeatureBitset ImpliedFeaturesAVX5124VNNIW = {};
530
531// SSE4_A->FMA4->XOP chain.
Craig Toppere6bb4c8e2020-09-08 10:49:32 -0700[diff] [blame]532static constexpr FeatureBitset ImpliedFeaturesSSE4_A = FeatureSSE3;
Craig Topper16f3d692020-07-06 22:47:54 -0700[diff] [blame]533static constexpr FeatureBitset ImpliedFeaturesFMA4 = FeatureAVX | FeatureSSE4_A;
534static constexpr FeatureBitset ImpliedFeaturesXOP = FeatureFMA4;
535
536// AMX Features
537static constexpr FeatureBitset ImpliedFeaturesAMX_TILE = {};
538static constexpr FeatureBitset ImpliedFeaturesAMX_BF16 = FeatureAMX_TILE;
539static constexpr FeatureBitset ImpliedFeaturesAMX_INT8 = FeatureAMX_TILE;
540
Xiang1 Zhang413577a2020-09-30 18:01:15 +0800[diff] [blame^]541// Key Locker Features
542static constexpr FeatureBitset ImpliedFeaturesKL = FeatureSSE2;
543static constexpr FeatureBitset ImpliedFeaturesWIDEKL = FeatureKL;
544
Craig Topper16f3d692020-07-06 22:47:54 -0700[diff] [blame]545static constexpr FeatureInfo FeatureInfos[X86::CPU_FEATURE_MAX] = {
546#define X86_FEATURE(ENUM, STR) {{STR}, ImpliedFeatures##ENUM},
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]547#include "llvm/Support/X86TargetParser.def"
548};
549
550void llvm::X86::getFeaturesForCPU(StringRef CPU,
Craig Topper16f3d692020-07-06 22:47:54 -0700[diff] [blame]551 SmallVectorImpl<StringRef> &EnabledFeatures) {
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]552 auto I = llvm::find_if(Processors,
553 [&](const ProcInfo &P) { return P.Name == CPU; });
554 assert(I != std::end(Processors) && "Processor not found!");
555
Craig Topperf40b1132020-07-09 14:52:16 -0700[diff] [blame]556 FeatureBitset Bits = I->Features;
557
558 // Remove the 64-bit feature which we only use to validate if a CPU can
559 // be used with 64-bit mode.
560 Bits &= ~Feature64BIT;
561
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]562 // Add the string version of all set bits.
Craig Topper504a1972020-08-06 00:13:40 -0700[diff] [blame]563 for (unsigned i = 0; i != CPU_FEATURE_MAX; ++i)
564 if (Bits[i] && !FeatureInfos[i].Name.empty())
565 EnabledFeatures.push_back(FeatureInfos[i].Name);
Craig Topper16f3d692020-07-06 22:47:54 -0700[diff] [blame]566}
567
568// For each feature that is (transitively) implied by this feature, set it.
569static void getImpliedEnabledFeatures(FeatureBitset &Bits,
570 const FeatureBitset &Implies) {
Fangrui Song0c7af8c2020-08-04 17:50:06 -0700[diff] [blame]571 // Fast path: Implies is often empty.
572 if (!Implies.any())
573 return;
574 FeatureBitset Prev;
Craig Topper16f3d692020-07-06 22:47:54 -0700[diff] [blame]575 Bits |= Implies;
Fangrui Song0c7af8c2020-08-04 17:50:06 -0700[diff] [blame]576 do {
577 Prev = Bits;
578 for (unsigned i = CPU_FEATURE_MAX; i;)
579 if (Bits[--i])
580 Bits |= FeatureInfos[i].ImpliedFeatures;
581 } while (Prev != Bits);
Craig Topper16f3d692020-07-06 22:47:54 -0700[diff] [blame]582}
583
584/// Create bit vector of features that are implied disabled if the feature
585/// passed in Value is disabled.
586static void getImpliedDisabledFeatures(FeatureBitset &Bits, unsigned Value) {
587 // Check all features looking for any dependent on this feature. If we find
588 // one, mark it and recursively find any feature that depend on it.
Fangrui Song0c7af8c2020-08-04 17:50:06 -0700[diff] [blame]589 FeatureBitset Prev;
590 Bits.set(Value);
591 do {
592 Prev = Bits;
593 for (unsigned i = 0; i != CPU_FEATURE_MAX; ++i)
594 if ((FeatureInfos[i].ImpliedFeatures & Bits).any())
595 Bits.set(i);
596 } while (Prev != Bits);
Craig Topper16f3d692020-07-06 22:47:54 -0700[diff] [blame]597}
598
Craig Topper504a1972020-08-06 00:13:40 -0700[diff] [blame]599void llvm::X86::updateImpliedFeatures(
Craig Topper16f3d692020-07-06 22:47:54 -0700[diff] [blame]600 StringRef Feature, bool Enabled,
Craig Topper504a1972020-08-06 00:13:40 -0700[diff] [blame]601 StringMap<bool> &Features) {
Craig Topper16f3d692020-07-06 22:47:54 -0700[diff] [blame]602 auto I = llvm::find_if(
603 FeatureInfos, [&](const FeatureInfo &FI) { return FI.Name == Feature; });
604 if (I == std::end(FeatureInfos)) {
Craig Topper44ea81a2020-07-07 00:27:50 -0700[diff] [blame]605 // FIXME: This shouldn't happen, but may not have all features in the table
606 // yet.
Craig Topper16f3d692020-07-06 22:47:54 -0700[diff] [blame]607 return;
608 }
609
610 FeatureBitset ImpliedBits;
611 if (Enabled)
612 getImpliedEnabledFeatures(ImpliedBits, I->ImpliedFeatures);
613 else
614 getImpliedDisabledFeatures(ImpliedBits,
615 std::distance(std::begin(FeatureInfos), I));
616
Craig Topper504a1972020-08-06 00:13:40 -0700[diff] [blame]617 // Update the map entry for all implied features.
618 for (unsigned i = 0; i != CPU_FEATURE_MAX; ++i)
619 if (ImpliedBits[i] && !FeatureInfos[i].Name.empty())
620 Features[FeatureInfos[i].Name] = Enabled;
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]621}