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gerrit-public.fairphone.software / toolchain / llvm-project / aadbabc070427fd3eaa85bb406d3d1db4ea2bac7 / . / llvm / lib / Target / Hexagon / HexagonPatternsHVX.td
blob: 6217df504f1966282cdb6a52bf31519ae044cbe1 [file] [log] [blame]
Krzysztof Parzyszek8abaf892018-02-06 20:22:20 +0000[diff] [blame]1def SDTVecLeaf:
2 SDTypeProfile<1, 0, [SDTCisVec<0>]>;
3def SDTVecBinOp:
4 SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVec<1>, SDTCisSameAs<1,2>]>;
5
6def SDTHexagonVEXTRACTW: SDTypeProfile<1, 2,
7 [SDTCisVT<0, i32>, SDTCisVec<1>, SDTCisVT<2, i32>]>;
8def HexagonVEXTRACTW : SDNode<"HexagonISD::VEXTRACTW", SDTHexagonVEXTRACTW>;
9
10def SDTHexagonVINSERTW0: SDTypeProfile<1, 2,
11 [SDTCisVec<0>, SDTCisSameAs<0, 1>, SDTCisVT<2, i32>]>;
12def HexagonVINSERTW0 : SDNode<"HexagonISD::VINSERTW0", SDTHexagonVINSERTW0>;
13
14def HwLen2: SDNodeXForm<imm, [{
15 const auto &ST = static_cast<const HexagonSubtarget&>(CurDAG->getSubtarget());
16 return CurDAG->getTargetConstant(ST.getVectorLength()/2, SDLoc(N), MVT::i32);
17}]>;
18
19def Q2V: OutPatFrag<(ops node:$Qs), (V6_vandqrt $Qs, (A2_tfrsi -1))>;
20
21def Combinev: OutPatFrag<(ops node:$Vs, node:$Vt),
22 (REG_SEQUENCE HvxWR, $Vs, vsub_hi, $Vt, vsub_lo)>;
23
24def Combineq: OutPatFrag<(ops node:$Qs, node:$Qt),
25 (V6_vandvrt
26 (V6_vor
27 (V6_vror (V6_vpackeb (V6_vd0), (Q2V $Qs)),
28 (A2_tfrsi (HwLen2 (i32 0)))), // Half the vector length
29 (V6_vpackeb (V6_vd0), (Q2V $Qt))),
30 (A2_tfrsi -1))>;
31
32def LoVec: OutPatFrag<(ops node:$Vs), (EXTRACT_SUBREG $Vs, vsub_lo)>;
33def HiVec: OutPatFrag<(ops node:$Vs), (EXTRACT_SUBREG $Vs, vsub_hi)>;
34
Krzysztof Parzyszekad83ce42018-02-14 20:46:06 +0000[diff] [blame]35def HexagonVZERO: SDNode<"HexagonISD::VZERO", SDTVecLeaf>;
36def HexagonQCAT: SDNode<"HexagonISD::QCAT", SDTVecBinOp>;
37def HexagonQTRUE: SDNode<"HexagonISD::QTRUE", SDTVecLeaf>;
38def HexagonQFALSE: SDNode<"HexagonISD::QFALSE", SDTVecLeaf>;
Krzysztof Parzyszekad83ce42018-02-14 20:46:06 +0000[diff] [blame]39
Krzysztof Parzyszek8abaf892018-02-06 20:22:20 +0000[diff] [blame]40def vzero: PatFrag<(ops), (HexagonVZERO)>;
41def qtrue: PatFrag<(ops), (HexagonQTRUE)>;
42def qfalse: PatFrag<(ops), (HexagonQFALSE)>;
43def qcat: PatFrag<(ops node:$Qs, node:$Qt),
44 (HexagonQCAT node:$Qs, node:$Qt)>;
45
46def qnot: PatFrag<(ops node:$Qs), (xor node:$Qs, qtrue)>;
47
48def VSxtb: OutPatFrag<(ops node:$Vs), (V6_vunpackb $Vs)>;
49def VSxth: OutPatFrag<(ops node:$Vs), (V6_vunpackh $Vs)>;
50def VZxtb: OutPatFrag<(ops node:$Vs), (V6_vunpackub $Vs)>;
51def VZxth: OutPatFrag<(ops node:$Vs), (V6_vunpackuh $Vs)>;
52
53def SplatB: SDNodeXForm<imm, [{
54 uint32_t V = N->getZExtValue();
55 assert(isUInt<8>(V));
56 uint32_t S = V << 24 | V << 16 | V << 8 | V;
57 return CurDAG->getTargetConstant(S, SDLoc(N), MVT::i32);
58}]>;
59
60def SplatH: SDNodeXForm<imm, [{
61 uint32_t V = N->getZExtValue();
62 assert(isUInt<16>(V));
63 return CurDAG->getTargetConstant(V << 16 | V, SDLoc(N), MVT::i32);
64}]>;
65
Krzysztof Parzyszekad83ce42018-02-14 20:46:06 +0000[diff] [blame]66def IsVecOff : PatLeaf<(i32 imm), [{
67 int32_t V = N->getSExtValue();
68 int32_t VecSize = HRI->getSpillSize(Hexagon::HvxVRRegClass);
69 assert(isPowerOf2_32(VecSize));
70 if ((uint32_t(V) & (uint32_t(VecSize)-1)) != 0)
71 return false;
72 int32_t L = Log2_32(VecSize);
73 return isInt<4>(V >> L);
74}]>;
75
76
77def alignedload: PatFrag<(ops node:$a), (load $a), [{
78 return isAlignedMemNode(dyn_cast<MemSDNode>(N));
79}]>;
80
81def unalignedload: PatFrag<(ops node:$a), (load $a), [{
82 return !isAlignedMemNode(dyn_cast<MemSDNode>(N));
83}]>;
84
85def alignedstore: PatFrag<(ops node:$v, node:$a), (store $v, $a), [{
86 return isAlignedMemNode(dyn_cast<MemSDNode>(N));
87}]>;
88
89def unalignedstore: PatFrag<(ops node:$v, node:$a), (store $v, $a), [{
90 return !isAlignedMemNode(dyn_cast<MemSDNode>(N));
91}]>;
92
Krzysztof Parzyszek8abaf892018-02-06 20:22:20 +0000[diff] [blame]93
94// HVX loads
95
Krzysztof Parzyszekad83ce42018-02-14 20:46:06 +0000[diff] [blame]96multiclass HvxLd_pat<InstHexagon MI, PatFrag Load, ValueType ResType,
Krzysztof Parzyszek8abaf892018-02-06 20:22:20 +0000[diff] [blame]97 PatFrag ImmPred> {
Krzysztof Parzyszekad83ce42018-02-14 20:46:06 +0000[diff] [blame]98 def: Pat<(ResType (Load I32:$Rt)),
99 (MI I32:$Rt, 0)>;
100 def: Pat<(ResType (Load (add I32:$Rt, ImmPred:$s))),
101 (MI I32:$Rt, imm:$s)>;
Krzysztof Parzyszek8abaf892018-02-06 20:22:20 +0000[diff] [blame]102 // The HVX selection code for shuffles can generate vector constants.
103 // Calling "Select" on the resulting loads from CP fails without these
104 // patterns.
Krzysztof Parzyszekad83ce42018-02-14 20:46:06 +0000[diff] [blame]105 def: Pat<(ResType (Load (HexagonCP tconstpool:$A))),
106 (MI (A2_tfrsi imm:$A), 0)>;
107 def: Pat<(ResType (Load (HexagonAtPcrel tconstpool:$A))),
Krzysztof Parzyszek8abaf892018-02-06 20:22:20 +0000[diff] [blame]108 (MI (C4_addipc imm:$A), 0)>;
109}
110
Krzysztof Parzyszekad83ce42018-02-14 20:46:06 +0000[diff] [blame]111multiclass HvxLda_pat<InstHexagon MI, PatFrag Load, ValueType ResType,
112 PatFrag ImmPred> {
113 let AddedComplexity = 50 in {
114 def: Pat<(ResType (Load (valignaddr I32:$Rt))),
115 (MI I32:$Rt, 0)>;
116 def: Pat<(ResType (Load (add (valignaddr I32:$Rt), ImmPred:$Off))),
117 (MI I32:$Rt, imm:$Off)>;
Krzysztof Parzyszek8abaf892018-02-06 20:22:20 +0000[diff] [blame]118 }
Krzysztof Parzyszekad83ce42018-02-14 20:46:06 +0000[diff] [blame]119 defm: HvxLd_pat<MI, Load, ResType, ImmPred>;
Krzysztof Parzyszek8abaf892018-02-06 20:22:20 +0000[diff] [blame]120}
121
Krzysztof Parzyszekad83ce42018-02-14 20:46:06 +0000[diff] [blame]122let Predicates = [UseHVX] in {
123 defm: HvxLda_pat<V6_vL32b_nt_ai, alignednontemporalload, VecI8, IsVecOff>;
124 defm: HvxLda_pat<V6_vL32b_nt_ai, alignednontemporalload, VecI16, IsVecOff>;
125 defm: HvxLda_pat<V6_vL32b_nt_ai, alignednontemporalload, VecI32, IsVecOff>;
126
127 defm: HvxLda_pat<V6_vL32b_ai, alignedload, VecI8, IsVecOff>;
128 defm: HvxLda_pat<V6_vL32b_ai, alignedload, VecI16, IsVecOff>;
129 defm: HvxLda_pat<V6_vL32b_ai, alignedload, VecI32, IsVecOff>;
130
131 defm: HvxLd_pat<V6_vL32Ub_ai, unalignedload, VecI8, IsVecOff>;
132 defm: HvxLd_pat<V6_vL32Ub_ai, unalignedload, VecI16, IsVecOff>;
133 defm: HvxLd_pat<V6_vL32Ub_ai, unalignedload, VecI32, IsVecOff>;
134}
Krzysztof Parzyszek8abaf892018-02-06 20:22:20 +0000[diff] [blame]135
136// HVX stores
137
138multiclass HvxSt_pat<InstHexagon MI, PatFrag Store, PatFrag ImmPred,
139 PatFrag Value> {
140 def: Pat<(Store Value:$Vs, I32:$Rt),
141 (MI I32:$Rt, 0, Value:$Vs)>;
142 def: Pat<(Store Value:$Vs, (add I32:$Rt, ImmPred:$s)),
143 (MI I32:$Rt, imm:$s, Value:$Vs)>;
144}
145
146let Predicates = [UseHVX] in {
Krzysztof Parzyszekad83ce42018-02-14 20:46:06 +0000[diff] [blame]147 defm: HvxSt_pat<V6_vS32b_nt_ai, alignednontemporalstore, IsVecOff, HVI8>;
148 defm: HvxSt_pat<V6_vS32b_nt_ai, alignednontemporalstore, IsVecOff, HVI16>;
149 defm: HvxSt_pat<V6_vS32b_nt_ai, alignednontemporalstore, IsVecOff, HVI32>;
Krzysztof Parzyszek8abaf892018-02-06 20:22:20 +0000[diff] [blame]150
Krzysztof Parzyszekad83ce42018-02-14 20:46:06 +0000[diff] [blame]151 defm: HvxSt_pat<V6_vS32b_ai, alignedstore, IsVecOff, HVI8>;
152 defm: HvxSt_pat<V6_vS32b_ai, alignedstore, IsVecOff, HVI16>;
153 defm: HvxSt_pat<V6_vS32b_ai, alignedstore, IsVecOff, HVI32>;
154
155 defm: HvxSt_pat<V6_vS32Ub_ai, unalignedstore, IsVecOff, HVI8>;
156 defm: HvxSt_pat<V6_vS32Ub_ai, unalignedstore, IsVecOff, HVI16>;
157 defm: HvxSt_pat<V6_vS32Ub_ai, unalignedstore, IsVecOff, HVI32>;
Krzysztof Parzyszek8abaf892018-02-06 20:22:20 +0000[diff] [blame]158}
159
160
161let Predicates = [UseHVX] in {
162 def: Pat<(VecI8 vzero), (V6_vd0)>;
163 def: Pat<(VecI16 vzero), (V6_vd0)>;
164 def: Pat<(VecI32 vzero), (V6_vd0)>;
165 // Use V6_vsubw_dv instead.
166 def: Pat<(VecPI8 vzero), (Combinev (V6_vd0), (V6_vd0))>;
167 def: Pat<(VecPI16 vzero), (Combinev (V6_vd0), (V6_vd0))>;
168 def: Pat<(VecPI32 vzero), (Combinev (V6_vd0), (V6_vd0))>;
169
170 def: Pat<(VecPI8 (concat_vectors HVI8:$Vs, HVI8:$Vt)),
171 (Combinev HvxVR:$Vt, HvxVR:$Vs)>;
172 def: Pat<(VecPI16 (concat_vectors HVI16:$Vs, HVI16:$Vt)),
173 (Combinev HvxVR:$Vt, HvxVR:$Vs)>;
174 def: Pat<(VecPI32 (concat_vectors HVI32:$Vs, HVI32:$Vt)),
175 (Combinev HvxVR:$Vt, HvxVR:$Vs)>;
176
177 def: Pat<(VecQ8 (qcat HQ16:$Qs, HQ16:$Qt)), (Combineq $Qs, $Qt)>;
178 def: Pat<(VecQ16 (qcat HQ32:$Qs, HQ32:$Qt)), (Combineq $Qs, $Qt)>;
179
180 def: Pat<(HexagonVEXTRACTW HVI8:$Vu, I32:$Rs),
181 (V6_extractw HvxVR:$Vu, I32:$Rs)>;
182 def: Pat<(HexagonVEXTRACTW HVI16:$Vu, I32:$Rs),
183 (V6_extractw HvxVR:$Vu, I32:$Rs)>;
184 def: Pat<(HexagonVEXTRACTW HVI32:$Vu, I32:$Rs),
185 (V6_extractw HvxVR:$Vu, I32:$Rs)>;
186
187 def: Pat<(HexagonVINSERTW0 HVI8:$Vu, I32:$Rt),
188 (V6_vinsertwr HvxVR:$Vu, I32:$Rt)>;
189 def: Pat<(HexagonVINSERTW0 HVI16:$Vu, I32:$Rt),
190 (V6_vinsertwr HvxVR:$Vu, I32:$Rt)>;
191 def: Pat<(HexagonVINSERTW0 HVI32:$Vu, I32:$Rt),
192 (V6_vinsertwr HvxVR:$Vu, I32:$Rt)>;
193
194 let AddedComplexity = 10 in {
195 def: Pat<(VecI8 (HexagonVSPLAT u8_0ImmPred:$V)),
196 (V6_lvsplatw (ToI32 (SplatB $V)))>;
197 def: Pat<(VecI16 (HexagonVSPLAT u16_0ImmPred:$V)),
198 (V6_lvsplatw (ToI32 (SplatH $V)))>;
199 def: Pat<(VecI32 (HexagonVSPLAT anyimm:$V)),
200 (V6_lvsplatw (ToI32 $V))>;
201 def: Pat<(VecPI8 (HexagonVSPLAT u8_0ImmPred:$V)),
202 (Combinev (V6_lvsplatw (ToI32 (SplatB $V))),
203 (V6_lvsplatw (ToI32 (SplatB $V))))>;
204 def: Pat<(VecPI16 (HexagonVSPLAT u16_0ImmPred:$V)),
205 (Combinev (V6_lvsplatw (ToI32 (SplatH $V))),
206 (V6_lvsplatw (ToI32 (SplatH $V))))>;
207 def: Pat<(VecPI32 (HexagonVSPLAT anyimm:$V)),
208 (Combinev (V6_lvsplatw (ToI32 $V)), (V6_lvsplatw (ToI32 $V)))>;
209 }
210 def: Pat<(VecI8 (HexagonVSPLAT I32:$Rs)),
211 (V6_lvsplatw (S2_vsplatrb I32:$Rs))>;
212 def: Pat<(VecI16 (HexagonVSPLAT I32:$Rs)),
213 (V6_lvsplatw (A2_combine_ll I32:$Rs, I32:$Rs))>;
214 def: Pat<(VecI32 (HexagonVSPLAT I32:$Rs)),
215 (V6_lvsplatw I32:$Rs)>;
216 def: Pat<(VecPI8 (HexagonVSPLAT I32:$Rs)),
217 (Combinev (V6_lvsplatw (S2_vsplatrb I32:$Rs)),
218 (V6_lvsplatw (S2_vsplatrb I32:$Rs)))>;
219 def: Pat<(VecPI16 (HexagonVSPLAT I32:$Rs)),
220 (Combinev (V6_lvsplatw (A2_combine_ll I32:$Rs, I32:$Rs)),
221 (V6_lvsplatw (A2_combine_ll I32:$Rs, I32:$Rs)))>;
222 def: Pat<(VecPI32 (HexagonVSPLAT I32:$Rs)),
223 (Combinev (V6_lvsplatw I32:$Rs), (V6_lvsplatw I32:$Rs))>;
224
225 def: Pat<(add HVI8:$Vs, HVI8:$Vt), (V6_vaddb HvxVR:$Vs, HvxVR:$Vt)>;
226 def: Pat<(add HVI16:$Vs, HVI16:$Vt), (V6_vaddh HvxVR:$Vs, HvxVR:$Vt)>;
227 def: Pat<(add HVI32:$Vs, HVI32:$Vt), (V6_vaddw HvxVR:$Vs, HvxVR:$Vt)>;
228 def: Pat<(add HWI8:$Vs, HWI8:$Vt), (V6_vaddb_dv HvxWR:$Vs, HvxWR:$Vt)>;
229 def: Pat<(add HWI16:$Vs, HWI16:$Vt), (V6_vaddh_dv HvxWR:$Vs, HvxWR:$Vt)>;
230 def: Pat<(add HWI32:$Vs, HWI32:$Vt), (V6_vaddw_dv HvxWR:$Vs, HvxWR:$Vt)>;
231
232 def: Pat<(sub HVI8:$Vs, HVI8:$Vt), (V6_vsubb HvxVR:$Vs, HvxVR:$Vt)>;
233 def: Pat<(sub HVI16:$Vs, HVI16:$Vt), (V6_vsubh HvxVR:$Vs, HvxVR:$Vt)>;
234 def: Pat<(sub HVI32:$Vs, HVI32:$Vt), (V6_vsubw HvxVR:$Vs, HvxVR:$Vt)>;
235 def: Pat<(sub HWI8:$Vs, HWI8:$Vt), (V6_vsubb_dv HvxWR:$Vs, HvxWR:$Vt)>;
236 def: Pat<(sub HWI16:$Vs, HWI16:$Vt), (V6_vsubh_dv HvxWR:$Vs, HvxWR:$Vt)>;
237 def: Pat<(sub HWI32:$Vs, HWI32:$Vt), (V6_vsubw_dv HvxWR:$Vs, HvxWR:$Vt)>;
238
239 def: Pat<(and HVI8:$Vs, HVI8:$Vt), (V6_vand HvxVR:$Vs, HvxVR:$Vt)>;
240 def: Pat<(or HVI8:$Vs, HVI8:$Vt), (V6_vor HvxVR:$Vs, HvxVR:$Vt)>;
241 def: Pat<(xor HVI8:$Vs, HVI8:$Vt), (V6_vxor HvxVR:$Vs, HvxVR:$Vt)>;
242
243 def: Pat<(vselect HQ8:$Qu, HVI8:$Vs, HVI8:$Vt),
244 (V6_vmux HvxQR:$Qu, HvxVR:$Vs, HvxVR:$Vt)>;
245 def: Pat<(vselect HQ16:$Qu, HVI16:$Vs, HVI16:$Vt),
246 (V6_vmux HvxQR:$Qu, HvxVR:$Vs, HvxVR:$Vt)>;
247 def: Pat<(vselect HQ32:$Qu, HVI32:$Vs, HVI32:$Vt),
248 (V6_vmux HvxQR:$Qu, HvxVR:$Vs, HvxVR:$Vt)>;
249
250 def: Pat<(vselect (qnot HQ8:$Qu), HVI8:$Vs, HVI8:$Vt),
251 (V6_vmux HvxQR:$Qu, HvxVR:$Vt, HvxVR:$Vs)>;
252 def: Pat<(vselect (qnot HQ16:$Qu), HVI16:$Vs, HVI16:$Vt),
253 (V6_vmux HvxQR:$Qu, HvxVR:$Vt, HvxVR:$Vs)>;
254 def: Pat<(vselect (qnot HQ32:$Qu), HVI32:$Vs, HVI32:$Vt),
255 (V6_vmux HvxQR:$Qu, HvxVR:$Vt, HvxVR:$Vs)>;
256
257 def: Pat<(VecPI16 (sext HVI8:$Vs)), (VSxtb $Vs)>;
258 def: Pat<(VecPI32 (sext HVI16:$Vs)), (VSxth $Vs)>;
259 def: Pat<(VecPI16 (zext HVI8:$Vs)), (VZxtb $Vs)>;
260 def: Pat<(VecPI32 (zext HVI16:$Vs)), (VZxth $Vs)>;
261
262 def: Pat<(VecI16 (sext_invec HVI8:$Vs)), (LoVec (VSxtb $Vs))>;
263 def: Pat<(VecI32 (sext_invec HVI16:$Vs)), (LoVec (VSxth $Vs))>;
264 def: Pat<(VecI32 (sext_invec HVI8:$Vs)),
265 (LoVec (VSxth (LoVec (VSxtb $Vs))))>;
266 def: Pat<(VecPI16 (sext_invec HWI8:$Vss)), (VSxtb (LoVec $Vss))>;
267 def: Pat<(VecPI32 (sext_invec HWI16:$Vss)), (VSxth (LoVec $Vss))>;
268 def: Pat<(VecPI32 (sext_invec HWI8:$Vss)),
269 (VSxth (LoVec (VSxtb (LoVec $Vss))))>;
270
271 def: Pat<(VecI16 (zext_invec HVI8:$Vs)), (LoVec (VZxtb $Vs))>;
272 def: Pat<(VecI32 (zext_invec HVI16:$Vs)), (LoVec (VZxth $Vs))>;
273 def: Pat<(VecI32 (zext_invec HVI8:$Vs)),
274 (LoVec (VZxth (LoVec (VZxtb $Vs))))>;
275 def: Pat<(VecPI16 (zext_invec HWI8:$Vss)), (VZxtb (LoVec $Vss))>;
276 def: Pat<(VecPI32 (zext_invec HWI16:$Vss)), (VZxth (LoVec $Vss))>;
277 def: Pat<(VecPI32 (zext_invec HWI8:$Vss)),
278 (VZxth (LoVec (VZxtb (LoVec $Vss))))>;
279
280 // The "source" types are not legal, and there are no parameterized
281 // definitions for them, but they are length-specific.
282 let Predicates = [UseHVX,UseHVX64B] in {
283 def: Pat<(VecI16 (sext_inreg HVI16:$Vs, v32i8)),
284 (V6_vasrh (V6_vaslh HVI16:$Vs, (A2_tfrsi 8)), (A2_tfrsi 8))>;
285 def: Pat<(VecI32 (sext_inreg HVI32:$Vs, v16i8)),
286 (V6_vasrw (V6_vaslw HVI32:$Vs, (A2_tfrsi 24)), (A2_tfrsi 24))>;
287 def: Pat<(VecI32 (sext_inreg HVI32:$Vs, v16i16)),
288 (V6_vasrw (V6_vaslw HVI32:$Vs, (A2_tfrsi 16)), (A2_tfrsi 16))>;
289 }
290 let Predicates = [UseHVX,UseHVX128B] in {
291 def: Pat<(VecI16 (sext_inreg HVI16:$Vs, v64i8)),
292 (V6_vasrh (V6_vaslh HVI16:$Vs, (A2_tfrsi 8)), (A2_tfrsi 8))>;
293 def: Pat<(VecI32 (sext_inreg HVI32:$Vs, v32i8)),
294 (V6_vasrw (V6_vaslw HVI32:$Vs, (A2_tfrsi 24)), (A2_tfrsi 24))>;
295 def: Pat<(VecI32 (sext_inreg HVI32:$Vs, v32i16)),
296 (V6_vasrw (V6_vaslw HVI32:$Vs, (A2_tfrsi 16)), (A2_tfrsi 16))>;
297 }
298
299 def: Pat<(HexagonVASL HVI8:$Vs, I32:$Rt),
300 (V6_vpackeb (V6_vaslh (HiVec (VZxtb HvxVR:$Vs)), I32:$Rt),
301 (V6_vaslh (LoVec (VZxtb HvxVR:$Vs)), I32:$Rt))>;
302 def: Pat<(HexagonVASR HVI8:$Vs, I32:$Rt),
303 (V6_vpackeb (V6_vasrh (HiVec (VSxtb HvxVR:$Vs)), I32:$Rt),
304 (V6_vasrh (LoVec (VSxtb HvxVR:$Vs)), I32:$Rt))>;
305 def: Pat<(HexagonVLSR HVI8:$Vs, I32:$Rt),
306 (V6_vpackeb (V6_vlsrh (HiVec (VZxtb HvxVR:$Vs)), I32:$Rt),
307 (V6_vlsrh (LoVec (VZxtb HvxVR:$Vs)), I32:$Rt))>;
308
309 def: Pat<(HexagonVASL HVI16:$Vs, I32:$Rt), (V6_vaslh HvxVR:$Vs, I32:$Rt)>;
310 def: Pat<(HexagonVASL HVI32:$Vs, I32:$Rt), (V6_vaslw HvxVR:$Vs, I32:$Rt)>;
311 def: Pat<(HexagonVASR HVI16:$Vs, I32:$Rt), (V6_vasrh HvxVR:$Vs, I32:$Rt)>;
312 def: Pat<(HexagonVASR HVI32:$Vs, I32:$Rt), (V6_vasrw HvxVR:$Vs, I32:$Rt)>;
313 def: Pat<(HexagonVLSR HVI16:$Vs, I32:$Rt), (V6_vlsrh HvxVR:$Vs, I32:$Rt)>;
314 def: Pat<(HexagonVLSR HVI32:$Vs, I32:$Rt), (V6_vlsrw HvxVR:$Vs, I32:$Rt)>;
315
316 def: Pat<(shl HVI16:$Vs, HVI16:$Vt), (V6_vaslhv HvxVR:$Vs, HvxVR:$Vt)>;
317 def: Pat<(shl HVI32:$Vs, HVI32:$Vt), (V6_vaslwv HvxVR:$Vs, HvxVR:$Vt)>;
318 def: Pat<(sra HVI16:$Vs, HVI16:$Vt), (V6_vasrhv HvxVR:$Vs, HvxVR:$Vt)>;
319 def: Pat<(sra HVI32:$Vs, HVI32:$Vt), (V6_vasrwv HvxVR:$Vs, HvxVR:$Vt)>;
320 def: Pat<(srl HVI16:$Vs, HVI16:$Vt), (V6_vlsrhv HvxVR:$Vs, HvxVR:$Vt)>;
321 def: Pat<(srl HVI32:$Vs, HVI32:$Vt), (V6_vlsrwv HvxVR:$Vs, HvxVR:$Vt)>;
322
Krzysztof Parzyszek9b48e8d2018-02-09 19:10:46 +0000[diff] [blame]323 def: Pat<(VecQ8 (qtrue)), (PS_qtrue)>;
324 def: Pat<(VecQ16 (qtrue)), (PS_qtrue)>;
325 def: Pat<(VecQ32 (qtrue)), (PS_qtrue)>;
326 def: Pat<(VecQ8 (qfalse)), (PS_qfalse)>;
327 def: Pat<(VecQ16 (qfalse)), (PS_qfalse)>;
328 def: Pat<(VecQ32 (qfalse)), (PS_qfalse)>;
329
Krzysztof Parzyszek8abaf892018-02-06 20:22:20 +0000[diff] [blame]330 def: Pat<(vnot HQ8:$Qs), (V6_pred_not HvxQR:$Qs)>;
331 def: Pat<(vnot HQ16:$Qs), (V6_pred_not HvxQR:$Qs)>;
332 def: Pat<(vnot HQ32:$Qs), (V6_pred_not HvxQR:$Qs)>;
333 def: Pat<(qnot HQ8:$Qs), (V6_pred_not HvxQR:$Qs)>;
334 def: Pat<(qnot HQ16:$Qs), (V6_pred_not HvxQR:$Qs)>;
335 def: Pat<(qnot HQ32:$Qs), (V6_pred_not HvxQR:$Qs)>;
336
337 def: Pat<(VecQ8 (seteq HVI8:$Vs, HVI8:$Vt)),
338 (V6_veqb HvxVR:$Vs, HvxVR:$Vt)>;
339 def: Pat<(VecQ8 (setgt HVI8:$Vs, HVI8:$Vt)),
340 (V6_vgtb HvxVR:$Vs, HvxVR:$Vt)>;
341 def: Pat<(VecQ8 (setugt HVI8:$Vs, HVI8:$Vt)),
342 (V6_vgtub HvxVR:$Vs, HvxVR:$Vt)>;
343 def: Pat<(VecQ16 (seteq HVI16:$Vs, HVI16:$Vt)),
344 (V6_veqh HvxVR:$Vs, HvxVR:$Vt)>;
345 def: Pat<(VecQ16 (setgt HVI16:$Vs, HVI16:$Vt)),
346 (V6_vgth HvxVR:$Vs, HvxVR:$Vt)>;
347 def: Pat<(VecQ16 (setugt HVI16:$Vs, HVI16:$Vt)),
348 (V6_vgtuh HvxVR:$Vs, HvxVR:$Vt)>;
349 def: Pat<(VecQ32 (seteq HVI32:$Vs, HVI32:$Vt)),
350 (V6_veqw HvxVR:$Vs, HvxVR:$Vt)>;
351 def: Pat<(VecQ32 (setgt HVI32:$Vs, HVI32:$Vt)),
352 (V6_vgtw HvxVR:$Vs, HvxVR:$Vt)>;
353 def: Pat<(VecQ32 (setugt HVI32:$Vs, HVI32:$Vt)),
354 (V6_vgtuw HvxVR:$Vs, HvxVR:$Vt)>;
355
356 def: Pat<(VecI8 (trunc HWI16:$Vss)),
357 (V6_vpackeb (HiVec $Vss), (LoVec $Vss))>;
358 def: Pat<(VecI16 (trunc HWI32:$Vss)),
359 (V6_vpackeh (HiVec $Vss), (LoVec $Vss))>;
Krzysztof Parzyszekd92c37e2018-04-19 14:46:44 +0000[diff] [blame]360
361 def: Pat<(VecI16 (bswap HVI16:$Vs)),
362 (V6_vdelta HvxVR:$Vs, (V6_lvsplatw (A2_tfrsi 0x01010101)))>;
363 def: Pat<(VecI32 (bswap HVI32:$Vs)),
364 (V6_vdelta HvxVR:$Vs, (V6_lvsplatw (A2_tfrsi 0x03030303)))>;
Krzysztof Parzyszek8abaf892018-02-06 20:22:20 +0000[diff] [blame]365}
366
367class HvxSel_pat<InstHexagon MI, PatFrag RegPred>
368 : Pat<(select I1:$Pu, RegPred:$Vs, RegPred:$Vt),
369 (MI I1:$Pu, RegPred:$Vs, RegPred:$Vt)>;
370
371let Predicates = [HasV60T,UseHVX] in {
372 def: HvxSel_pat<PS_vselect, HVI8>;
373 def: HvxSel_pat<PS_vselect, HVI16>;
374 def: HvxSel_pat<PS_vselect, HVI32>;
375 def: HvxSel_pat<PS_wselect, HWI8>;
376 def: HvxSel_pat<PS_wselect, HWI16>;
377 def: HvxSel_pat<PS_wselect, HWI32>;
378}
379