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gerrit-public.fairphone.software / toolchain / llvm-project / ad83ce4cb45771aecd4ed916abe368787da55b72 / . / llvm / lib / Target / Hexagon / HexagonPatternsHVX.td
blob: a3dc8d3dabc5ddc7d6023a99d2501bb0a98a0a58 [file] [log] [blame]
Krzysztof Parzyszek8abaf892018-02-06 20:22:20 +0000[diff] [blame]1def SDTVecLeaf:
2 SDTypeProfile<1, 0, [SDTCisVec<0>]>;
3def SDTVecBinOp:
4 SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVec<1>, SDTCisSameAs<1,2>]>;
5
6def SDTHexagonVEXTRACTW: SDTypeProfile<1, 2,
7 [SDTCisVT<0, i32>, SDTCisVec<1>, SDTCisVT<2, i32>]>;
8def HexagonVEXTRACTW : SDNode<"HexagonISD::VEXTRACTW", SDTHexagonVEXTRACTW>;
9
10def SDTHexagonVINSERTW0: SDTypeProfile<1, 2,
11 [SDTCisVec<0>, SDTCisSameAs<0, 1>, SDTCisVT<2, i32>]>;
12def HexagonVINSERTW0 : SDNode<"HexagonISD::VINSERTW0", SDTHexagonVINSERTW0>;
13
14def HwLen2: SDNodeXForm<imm, [{
15 const auto &ST = static_cast<const HexagonSubtarget&>(CurDAG->getSubtarget());
16 return CurDAG->getTargetConstant(ST.getVectorLength()/2, SDLoc(N), MVT::i32);
17}]>;
18
Krzysztof Parzyszekad83ce42018-02-14 20:46:06 +0000[diff] [blame^]19def NHwLen: SDNodeXForm<imm, [{
20 const auto &ST = static_cast<const HexagonSubtarget&>(CurDAG->getSubtarget());
21 return CurDAG->getTargetConstant(-int(ST.getVectorLength()), SDLoc(N),
22 MVT::i32);
23}]>;
24
Krzysztof Parzyszek8abaf892018-02-06 20:22:20 +0000[diff] [blame]25def Q2V: OutPatFrag<(ops node:$Qs), (V6_vandqrt $Qs, (A2_tfrsi -1))>;
26
27def Combinev: OutPatFrag<(ops node:$Vs, node:$Vt),
28 (REG_SEQUENCE HvxWR, $Vs, vsub_hi, $Vt, vsub_lo)>;
29
30def Combineq: OutPatFrag<(ops node:$Qs, node:$Qt),
31 (V6_vandvrt
32 (V6_vor
33 (V6_vror (V6_vpackeb (V6_vd0), (Q2V $Qs)),
34 (A2_tfrsi (HwLen2 (i32 0)))), // Half the vector length
35 (V6_vpackeb (V6_vd0), (Q2V $Qt))),
36 (A2_tfrsi -1))>;
37
38def LoVec: OutPatFrag<(ops node:$Vs), (EXTRACT_SUBREG $Vs, vsub_lo)>;
39def HiVec: OutPatFrag<(ops node:$Vs), (EXTRACT_SUBREG $Vs, vsub_hi)>;
40
Krzysztof Parzyszekad83ce42018-02-14 20:46:06 +0000[diff] [blame^]41def HexagonVZERO: SDNode<"HexagonISD::VZERO", SDTVecLeaf>;
42def HexagonQCAT: SDNode<"HexagonISD::QCAT", SDTVecBinOp>;
43def HexagonQTRUE: SDNode<"HexagonISD::QTRUE", SDTVecLeaf>;
44def HexagonQFALSE: SDNode<"HexagonISD::QFALSE", SDTVecLeaf>;
45def HexagonVALIGNADDR: SDNode<"HexagonISD::VALIGNADDR", SDTIntUnaryOp>;
46
Krzysztof Parzyszek8abaf892018-02-06 20:22:20 +0000[diff] [blame]47def vzero: PatFrag<(ops), (HexagonVZERO)>;
48def qtrue: PatFrag<(ops), (HexagonQTRUE)>;
49def qfalse: PatFrag<(ops), (HexagonQFALSE)>;
50def qcat: PatFrag<(ops node:$Qs, node:$Qt),
51 (HexagonQCAT node:$Qs, node:$Qt)>;
52
53def qnot: PatFrag<(ops node:$Qs), (xor node:$Qs, qtrue)>;
Krzysztof Parzyszekad83ce42018-02-14 20:46:06 +0000[diff] [blame^]54def valignaddr: PatFrag<(ops node:$Addr), (HexagonVALIGNADDR node:$Addr)>;
Krzysztof Parzyszek8abaf892018-02-06 20:22:20 +0000[diff] [blame]55
56def VSxtb: OutPatFrag<(ops node:$Vs), (V6_vunpackb $Vs)>;
57def VSxth: OutPatFrag<(ops node:$Vs), (V6_vunpackh $Vs)>;
58def VZxtb: OutPatFrag<(ops node:$Vs), (V6_vunpackub $Vs)>;
59def VZxth: OutPatFrag<(ops node:$Vs), (V6_vunpackuh $Vs)>;
60
61def SplatB: SDNodeXForm<imm, [{
62 uint32_t V = N->getZExtValue();
63 assert(isUInt<8>(V));
64 uint32_t S = V << 24 | V << 16 | V << 8 | V;
65 return CurDAG->getTargetConstant(S, SDLoc(N), MVT::i32);
66}]>;
67
68def SplatH: SDNodeXForm<imm, [{
69 uint32_t V = N->getZExtValue();
70 assert(isUInt<16>(V));
71 return CurDAG->getTargetConstant(V << 16 | V, SDLoc(N), MVT::i32);
72}]>;
73
Krzysztof Parzyszekad83ce42018-02-14 20:46:06 +0000[diff] [blame^]74def IsVecOff : PatLeaf<(i32 imm), [{
75 int32_t V = N->getSExtValue();
76 int32_t VecSize = HRI->getSpillSize(Hexagon::HvxVRRegClass);
77 assert(isPowerOf2_32(VecSize));
78 if ((uint32_t(V) & (uint32_t(VecSize)-1)) != 0)
79 return false;
80 int32_t L = Log2_32(VecSize);
81 return isInt<4>(V >> L);
82}]>;
83
84
85def alignedload: PatFrag<(ops node:$a), (load $a), [{
86 return isAlignedMemNode(dyn_cast<MemSDNode>(N));
87}]>;
88
89def unalignedload: PatFrag<(ops node:$a), (load $a), [{
90 return !isAlignedMemNode(dyn_cast<MemSDNode>(N));
91}]>;
92
93def alignedstore: PatFrag<(ops node:$v, node:$a), (store $v, $a), [{
94 return isAlignedMemNode(dyn_cast<MemSDNode>(N));
95}]>;
96
97def unalignedstore: PatFrag<(ops node:$v, node:$a), (store $v, $a), [{
98 return !isAlignedMemNode(dyn_cast<MemSDNode>(N));
99}]>;
100
Krzysztof Parzyszek8abaf892018-02-06 20:22:20 +0000[diff] [blame]101
102// HVX loads
103
Krzysztof Parzyszekad83ce42018-02-14 20:46:06 +0000[diff] [blame^]104multiclass HvxLd_pat<InstHexagon MI, PatFrag Load, ValueType ResType,
Krzysztof Parzyszek8abaf892018-02-06 20:22:20 +0000[diff] [blame]105 PatFrag ImmPred> {
Krzysztof Parzyszekad83ce42018-02-14 20:46:06 +0000[diff] [blame^]106 def: Pat<(ResType (Load I32:$Rt)),
107 (MI I32:$Rt, 0)>;
108 def: Pat<(ResType (Load (add I32:$Rt, ImmPred:$s))),
109 (MI I32:$Rt, imm:$s)>;
Krzysztof Parzyszek8abaf892018-02-06 20:22:20 +0000[diff] [blame]110 // The HVX selection code for shuffles can generate vector constants.
111 // Calling "Select" on the resulting loads from CP fails without these
112 // patterns.
Krzysztof Parzyszekad83ce42018-02-14 20:46:06 +0000[diff] [blame^]113 def: Pat<(ResType (Load (HexagonCP tconstpool:$A))),
114 (MI (A2_tfrsi imm:$A), 0)>;
115 def: Pat<(ResType (Load (HexagonAtPcrel tconstpool:$A))),
Krzysztof Parzyszek8abaf892018-02-06 20:22:20 +0000[diff] [blame]116 (MI (C4_addipc imm:$A), 0)>;
117}
118
Krzysztof Parzyszekad83ce42018-02-14 20:46:06 +0000[diff] [blame^]119multiclass HvxLda_pat<InstHexagon MI, PatFrag Load, ValueType ResType,
120 PatFrag ImmPred> {
121 let AddedComplexity = 50 in {
122 def: Pat<(ResType (Load (valignaddr I32:$Rt))),
123 (MI I32:$Rt, 0)>;
124 def: Pat<(ResType (Load (add (valignaddr I32:$Rt), ImmPred:$Off))),
125 (MI I32:$Rt, imm:$Off)>;
Krzysztof Parzyszek8abaf892018-02-06 20:22:20 +0000[diff] [blame]126 }
Krzysztof Parzyszekad83ce42018-02-14 20:46:06 +0000[diff] [blame^]127 defm: HvxLd_pat<MI, Load, ResType, ImmPred>;
Krzysztof Parzyszek8abaf892018-02-06 20:22:20 +0000[diff] [blame]128}
129
Krzysztof Parzyszekad83ce42018-02-14 20:46:06 +0000[diff] [blame^]130let Predicates = [UseHVX] in {
131 defm: HvxLda_pat<V6_vL32b_nt_ai, alignednontemporalload, VecI8, IsVecOff>;
132 defm: HvxLda_pat<V6_vL32b_nt_ai, alignednontemporalload, VecI16, IsVecOff>;
133 defm: HvxLda_pat<V6_vL32b_nt_ai, alignednontemporalload, VecI32, IsVecOff>;
134
135 defm: HvxLda_pat<V6_vL32b_ai, alignedload, VecI8, IsVecOff>;
136 defm: HvxLda_pat<V6_vL32b_ai, alignedload, VecI16, IsVecOff>;
137 defm: HvxLda_pat<V6_vL32b_ai, alignedload, VecI32, IsVecOff>;
138
139 defm: HvxLd_pat<V6_vL32Ub_ai, unalignedload, VecI8, IsVecOff>;
140 defm: HvxLd_pat<V6_vL32Ub_ai, unalignedload, VecI16, IsVecOff>;
141 defm: HvxLd_pat<V6_vL32Ub_ai, unalignedload, VecI32, IsVecOff>;
142}
Krzysztof Parzyszek8abaf892018-02-06 20:22:20 +0000[diff] [blame]143
144// HVX stores
145
146multiclass HvxSt_pat<InstHexagon MI, PatFrag Store, PatFrag ImmPred,
147 PatFrag Value> {
148 def: Pat<(Store Value:$Vs, I32:$Rt),
149 (MI I32:$Rt, 0, Value:$Vs)>;
150 def: Pat<(Store Value:$Vs, (add I32:$Rt, ImmPred:$s)),
151 (MI I32:$Rt, imm:$s, Value:$Vs)>;
152}
153
154let Predicates = [UseHVX] in {
Krzysztof Parzyszekad83ce42018-02-14 20:46:06 +0000[diff] [blame^]155 defm: HvxSt_pat<V6_vS32b_nt_ai, alignednontemporalstore, IsVecOff, HVI8>;
156 defm: HvxSt_pat<V6_vS32b_nt_ai, alignednontemporalstore, IsVecOff, HVI16>;
157 defm: HvxSt_pat<V6_vS32b_nt_ai, alignednontemporalstore, IsVecOff, HVI32>;
Krzysztof Parzyszek8abaf892018-02-06 20:22:20 +0000[diff] [blame]158
Krzysztof Parzyszekad83ce42018-02-14 20:46:06 +0000[diff] [blame^]159 defm: HvxSt_pat<V6_vS32b_ai, alignedstore, IsVecOff, HVI8>;
160 defm: HvxSt_pat<V6_vS32b_ai, alignedstore, IsVecOff, HVI16>;
161 defm: HvxSt_pat<V6_vS32b_ai, alignedstore, IsVecOff, HVI32>;
162
163 defm: HvxSt_pat<V6_vS32Ub_ai, unalignedstore, IsVecOff, HVI8>;
164 defm: HvxSt_pat<V6_vS32Ub_ai, unalignedstore, IsVecOff, HVI16>;
165 defm: HvxSt_pat<V6_vS32Ub_ai, unalignedstore, IsVecOff, HVI32>;
Krzysztof Parzyszek8abaf892018-02-06 20:22:20 +0000[diff] [blame]166}
167
168
169let Predicates = [UseHVX] in {
170 def: Pat<(VecI8 vzero), (V6_vd0)>;
171 def: Pat<(VecI16 vzero), (V6_vd0)>;
172 def: Pat<(VecI32 vzero), (V6_vd0)>;
173 // Use V6_vsubw_dv instead.
174 def: Pat<(VecPI8 vzero), (Combinev (V6_vd0), (V6_vd0))>;
175 def: Pat<(VecPI16 vzero), (Combinev (V6_vd0), (V6_vd0))>;
176 def: Pat<(VecPI32 vzero), (Combinev (V6_vd0), (V6_vd0))>;
177
Krzysztof Parzyszekad83ce42018-02-14 20:46:06 +0000[diff] [blame^]178 def: Pat<(valignaddr I32:$Rs), (A2_andir I32:$Rs, (NHwLen (i32 0)))>;
179
Krzysztof Parzyszek8abaf892018-02-06 20:22:20 +0000[diff] [blame]180 def: Pat<(VecPI8 (concat_vectors HVI8:$Vs, HVI8:$Vt)),
181 (Combinev HvxVR:$Vt, HvxVR:$Vs)>;
182 def: Pat<(VecPI16 (concat_vectors HVI16:$Vs, HVI16:$Vt)),
183 (Combinev HvxVR:$Vt, HvxVR:$Vs)>;
184 def: Pat<(VecPI32 (concat_vectors HVI32:$Vs, HVI32:$Vt)),
185 (Combinev HvxVR:$Vt, HvxVR:$Vs)>;
186
187 def: Pat<(VecQ8 (qcat HQ16:$Qs, HQ16:$Qt)), (Combineq $Qs, $Qt)>;
188 def: Pat<(VecQ16 (qcat HQ32:$Qs, HQ32:$Qt)), (Combineq $Qs, $Qt)>;
189
190 def: Pat<(HexagonVEXTRACTW HVI8:$Vu, I32:$Rs),
191 (V6_extractw HvxVR:$Vu, I32:$Rs)>;
192 def: Pat<(HexagonVEXTRACTW HVI16:$Vu, I32:$Rs),
193 (V6_extractw HvxVR:$Vu, I32:$Rs)>;
194 def: Pat<(HexagonVEXTRACTW HVI32:$Vu, I32:$Rs),
195 (V6_extractw HvxVR:$Vu, I32:$Rs)>;
196
197 def: Pat<(HexagonVINSERTW0 HVI8:$Vu, I32:$Rt),
198 (V6_vinsertwr HvxVR:$Vu, I32:$Rt)>;
199 def: Pat<(HexagonVINSERTW0 HVI16:$Vu, I32:$Rt),
200 (V6_vinsertwr HvxVR:$Vu, I32:$Rt)>;
201 def: Pat<(HexagonVINSERTW0 HVI32:$Vu, I32:$Rt),
202 (V6_vinsertwr HvxVR:$Vu, I32:$Rt)>;
203
204 let AddedComplexity = 10 in {
205 def: Pat<(VecI8 (HexagonVSPLAT u8_0ImmPred:$V)),
206 (V6_lvsplatw (ToI32 (SplatB $V)))>;
207 def: Pat<(VecI16 (HexagonVSPLAT u16_0ImmPred:$V)),
208 (V6_lvsplatw (ToI32 (SplatH $V)))>;
209 def: Pat<(VecI32 (HexagonVSPLAT anyimm:$V)),
210 (V6_lvsplatw (ToI32 $V))>;
211 def: Pat<(VecPI8 (HexagonVSPLAT u8_0ImmPred:$V)),
212 (Combinev (V6_lvsplatw (ToI32 (SplatB $V))),
213 (V6_lvsplatw (ToI32 (SplatB $V))))>;
214 def: Pat<(VecPI16 (HexagonVSPLAT u16_0ImmPred:$V)),
215 (Combinev (V6_lvsplatw (ToI32 (SplatH $V))),
216 (V6_lvsplatw (ToI32 (SplatH $V))))>;
217 def: Pat<(VecPI32 (HexagonVSPLAT anyimm:$V)),
218 (Combinev (V6_lvsplatw (ToI32 $V)), (V6_lvsplatw (ToI32 $V)))>;
219 }
220 def: Pat<(VecI8 (HexagonVSPLAT I32:$Rs)),
221 (V6_lvsplatw (S2_vsplatrb I32:$Rs))>;
222 def: Pat<(VecI16 (HexagonVSPLAT I32:$Rs)),
223 (V6_lvsplatw (A2_combine_ll I32:$Rs, I32:$Rs))>;
224 def: Pat<(VecI32 (HexagonVSPLAT I32:$Rs)),
225 (V6_lvsplatw I32:$Rs)>;
226 def: Pat<(VecPI8 (HexagonVSPLAT I32:$Rs)),
227 (Combinev (V6_lvsplatw (S2_vsplatrb I32:$Rs)),
228 (V6_lvsplatw (S2_vsplatrb I32:$Rs)))>;
229 def: Pat<(VecPI16 (HexagonVSPLAT I32:$Rs)),
230 (Combinev (V6_lvsplatw (A2_combine_ll I32:$Rs, I32:$Rs)),
231 (V6_lvsplatw (A2_combine_ll I32:$Rs, I32:$Rs)))>;
232 def: Pat<(VecPI32 (HexagonVSPLAT I32:$Rs)),
233 (Combinev (V6_lvsplatw I32:$Rs), (V6_lvsplatw I32:$Rs))>;
234
235 def: Pat<(add HVI8:$Vs, HVI8:$Vt), (V6_vaddb HvxVR:$Vs, HvxVR:$Vt)>;
236 def: Pat<(add HVI16:$Vs, HVI16:$Vt), (V6_vaddh HvxVR:$Vs, HvxVR:$Vt)>;
237 def: Pat<(add HVI32:$Vs, HVI32:$Vt), (V6_vaddw HvxVR:$Vs, HvxVR:$Vt)>;
238 def: Pat<(add HWI8:$Vs, HWI8:$Vt), (V6_vaddb_dv HvxWR:$Vs, HvxWR:$Vt)>;
239 def: Pat<(add HWI16:$Vs, HWI16:$Vt), (V6_vaddh_dv HvxWR:$Vs, HvxWR:$Vt)>;
240 def: Pat<(add HWI32:$Vs, HWI32:$Vt), (V6_vaddw_dv HvxWR:$Vs, HvxWR:$Vt)>;
241
242 def: Pat<(sub HVI8:$Vs, HVI8:$Vt), (V6_vsubb HvxVR:$Vs, HvxVR:$Vt)>;
243 def: Pat<(sub HVI16:$Vs, HVI16:$Vt), (V6_vsubh HvxVR:$Vs, HvxVR:$Vt)>;
244 def: Pat<(sub HVI32:$Vs, HVI32:$Vt), (V6_vsubw HvxVR:$Vs, HvxVR:$Vt)>;
245 def: Pat<(sub HWI8:$Vs, HWI8:$Vt), (V6_vsubb_dv HvxWR:$Vs, HvxWR:$Vt)>;
246 def: Pat<(sub HWI16:$Vs, HWI16:$Vt), (V6_vsubh_dv HvxWR:$Vs, HvxWR:$Vt)>;
247 def: Pat<(sub HWI32:$Vs, HWI32:$Vt), (V6_vsubw_dv HvxWR:$Vs, HvxWR:$Vt)>;
248
249 def: Pat<(and HVI8:$Vs, HVI8:$Vt), (V6_vand HvxVR:$Vs, HvxVR:$Vt)>;
250 def: Pat<(or HVI8:$Vs, HVI8:$Vt), (V6_vor HvxVR:$Vs, HvxVR:$Vt)>;
251 def: Pat<(xor HVI8:$Vs, HVI8:$Vt), (V6_vxor HvxVR:$Vs, HvxVR:$Vt)>;
252
253 def: Pat<(vselect HQ8:$Qu, HVI8:$Vs, HVI8:$Vt),
254 (V6_vmux HvxQR:$Qu, HvxVR:$Vs, HvxVR:$Vt)>;
255 def: Pat<(vselect HQ16:$Qu, HVI16:$Vs, HVI16:$Vt),
256 (V6_vmux HvxQR:$Qu, HvxVR:$Vs, HvxVR:$Vt)>;
257 def: Pat<(vselect HQ32:$Qu, HVI32:$Vs, HVI32:$Vt),
258 (V6_vmux HvxQR:$Qu, HvxVR:$Vs, HvxVR:$Vt)>;
259
260 def: Pat<(vselect (qnot HQ8:$Qu), HVI8:$Vs, HVI8:$Vt),
261 (V6_vmux HvxQR:$Qu, HvxVR:$Vt, HvxVR:$Vs)>;
262 def: Pat<(vselect (qnot HQ16:$Qu), HVI16:$Vs, HVI16:$Vt),
263 (V6_vmux HvxQR:$Qu, HvxVR:$Vt, HvxVR:$Vs)>;
264 def: Pat<(vselect (qnot HQ32:$Qu), HVI32:$Vs, HVI32:$Vt),
265 (V6_vmux HvxQR:$Qu, HvxVR:$Vt, HvxVR:$Vs)>;
266
267 def: Pat<(VecPI16 (sext HVI8:$Vs)), (VSxtb $Vs)>;
268 def: Pat<(VecPI32 (sext HVI16:$Vs)), (VSxth $Vs)>;
269 def: Pat<(VecPI16 (zext HVI8:$Vs)), (VZxtb $Vs)>;
270 def: Pat<(VecPI32 (zext HVI16:$Vs)), (VZxth $Vs)>;
271
272 def: Pat<(VecI16 (sext_invec HVI8:$Vs)), (LoVec (VSxtb $Vs))>;
273 def: Pat<(VecI32 (sext_invec HVI16:$Vs)), (LoVec (VSxth $Vs))>;
274 def: Pat<(VecI32 (sext_invec HVI8:$Vs)),
275 (LoVec (VSxth (LoVec (VSxtb $Vs))))>;
276 def: Pat<(VecPI16 (sext_invec HWI8:$Vss)), (VSxtb (LoVec $Vss))>;
277 def: Pat<(VecPI32 (sext_invec HWI16:$Vss)), (VSxth (LoVec $Vss))>;
278 def: Pat<(VecPI32 (sext_invec HWI8:$Vss)),
279 (VSxth (LoVec (VSxtb (LoVec $Vss))))>;
280
281 def: Pat<(VecI16 (zext_invec HVI8:$Vs)), (LoVec (VZxtb $Vs))>;
282 def: Pat<(VecI32 (zext_invec HVI16:$Vs)), (LoVec (VZxth $Vs))>;
283 def: Pat<(VecI32 (zext_invec HVI8:$Vs)),
284 (LoVec (VZxth (LoVec (VZxtb $Vs))))>;
285 def: Pat<(VecPI16 (zext_invec HWI8:$Vss)), (VZxtb (LoVec $Vss))>;
286 def: Pat<(VecPI32 (zext_invec HWI16:$Vss)), (VZxth (LoVec $Vss))>;
287 def: Pat<(VecPI32 (zext_invec HWI8:$Vss)),
288 (VZxth (LoVec (VZxtb (LoVec $Vss))))>;
289
290 // The "source" types are not legal, and there are no parameterized
291 // definitions for them, but they are length-specific.
292 let Predicates = [UseHVX,UseHVX64B] in {
293 def: Pat<(VecI16 (sext_inreg HVI16:$Vs, v32i8)),
294 (V6_vasrh (V6_vaslh HVI16:$Vs, (A2_tfrsi 8)), (A2_tfrsi 8))>;
295 def: Pat<(VecI32 (sext_inreg HVI32:$Vs, v16i8)),
296 (V6_vasrw (V6_vaslw HVI32:$Vs, (A2_tfrsi 24)), (A2_tfrsi 24))>;
297 def: Pat<(VecI32 (sext_inreg HVI32:$Vs, v16i16)),
298 (V6_vasrw (V6_vaslw HVI32:$Vs, (A2_tfrsi 16)), (A2_tfrsi 16))>;
299 }
300 let Predicates = [UseHVX,UseHVX128B] in {
301 def: Pat<(VecI16 (sext_inreg HVI16:$Vs, v64i8)),
302 (V6_vasrh (V6_vaslh HVI16:$Vs, (A2_tfrsi 8)), (A2_tfrsi 8))>;
303 def: Pat<(VecI32 (sext_inreg HVI32:$Vs, v32i8)),
304 (V6_vasrw (V6_vaslw HVI32:$Vs, (A2_tfrsi 24)), (A2_tfrsi 24))>;
305 def: Pat<(VecI32 (sext_inreg HVI32:$Vs, v32i16)),
306 (V6_vasrw (V6_vaslw HVI32:$Vs, (A2_tfrsi 16)), (A2_tfrsi 16))>;
307 }
308
309 def: Pat<(HexagonVASL HVI8:$Vs, I32:$Rt),
310 (V6_vpackeb (V6_vaslh (HiVec (VZxtb HvxVR:$Vs)), I32:$Rt),
311 (V6_vaslh (LoVec (VZxtb HvxVR:$Vs)), I32:$Rt))>;
312 def: Pat<(HexagonVASR HVI8:$Vs, I32:$Rt),
313 (V6_vpackeb (V6_vasrh (HiVec (VSxtb HvxVR:$Vs)), I32:$Rt),
314 (V6_vasrh (LoVec (VSxtb HvxVR:$Vs)), I32:$Rt))>;
315 def: Pat<(HexagonVLSR HVI8:$Vs, I32:$Rt),
316 (V6_vpackeb (V6_vlsrh (HiVec (VZxtb HvxVR:$Vs)), I32:$Rt),
317 (V6_vlsrh (LoVec (VZxtb HvxVR:$Vs)), I32:$Rt))>;
318
319 def: Pat<(HexagonVASL HVI16:$Vs, I32:$Rt), (V6_vaslh HvxVR:$Vs, I32:$Rt)>;
320 def: Pat<(HexagonVASL HVI32:$Vs, I32:$Rt), (V6_vaslw HvxVR:$Vs, I32:$Rt)>;
321 def: Pat<(HexagonVASR HVI16:$Vs, I32:$Rt), (V6_vasrh HvxVR:$Vs, I32:$Rt)>;
322 def: Pat<(HexagonVASR HVI32:$Vs, I32:$Rt), (V6_vasrw HvxVR:$Vs, I32:$Rt)>;
323 def: Pat<(HexagonVLSR HVI16:$Vs, I32:$Rt), (V6_vlsrh HvxVR:$Vs, I32:$Rt)>;
324 def: Pat<(HexagonVLSR HVI32:$Vs, I32:$Rt), (V6_vlsrw HvxVR:$Vs, I32:$Rt)>;
325
326 def: Pat<(shl HVI16:$Vs, HVI16:$Vt), (V6_vaslhv HvxVR:$Vs, HvxVR:$Vt)>;
327 def: Pat<(shl HVI32:$Vs, HVI32:$Vt), (V6_vaslwv HvxVR:$Vs, HvxVR:$Vt)>;
328 def: Pat<(sra HVI16:$Vs, HVI16:$Vt), (V6_vasrhv HvxVR:$Vs, HvxVR:$Vt)>;
329 def: Pat<(sra HVI32:$Vs, HVI32:$Vt), (V6_vasrwv HvxVR:$Vs, HvxVR:$Vt)>;
330 def: Pat<(srl HVI16:$Vs, HVI16:$Vt), (V6_vlsrhv HvxVR:$Vs, HvxVR:$Vt)>;
331 def: Pat<(srl HVI32:$Vs, HVI32:$Vt), (V6_vlsrwv HvxVR:$Vs, HvxVR:$Vt)>;
332
Krzysztof Parzyszek9b48e8d2018-02-09 19:10:46 +0000[diff] [blame]333 def: Pat<(VecQ8 (qtrue)), (PS_qtrue)>;
334 def: Pat<(VecQ16 (qtrue)), (PS_qtrue)>;
335 def: Pat<(VecQ32 (qtrue)), (PS_qtrue)>;
336 def: Pat<(VecQ8 (qfalse)), (PS_qfalse)>;
337 def: Pat<(VecQ16 (qfalse)), (PS_qfalse)>;
338 def: Pat<(VecQ32 (qfalse)), (PS_qfalse)>;
339
Krzysztof Parzyszek8abaf892018-02-06 20:22:20 +0000[diff] [blame]340 def: Pat<(vnot HQ8:$Qs), (V6_pred_not HvxQR:$Qs)>;
341 def: Pat<(vnot HQ16:$Qs), (V6_pred_not HvxQR:$Qs)>;
342 def: Pat<(vnot HQ32:$Qs), (V6_pred_not HvxQR:$Qs)>;
343 def: Pat<(qnot HQ8:$Qs), (V6_pred_not HvxQR:$Qs)>;
344 def: Pat<(qnot HQ16:$Qs), (V6_pred_not HvxQR:$Qs)>;
345 def: Pat<(qnot HQ32:$Qs), (V6_pred_not HvxQR:$Qs)>;
346
347 def: Pat<(VecQ8 (seteq HVI8:$Vs, HVI8:$Vt)),
348 (V6_veqb HvxVR:$Vs, HvxVR:$Vt)>;
349 def: Pat<(VecQ8 (setgt HVI8:$Vs, HVI8:$Vt)),
350 (V6_vgtb HvxVR:$Vs, HvxVR:$Vt)>;
351 def: Pat<(VecQ8 (setugt HVI8:$Vs, HVI8:$Vt)),
352 (V6_vgtub HvxVR:$Vs, HvxVR:$Vt)>;
353 def: Pat<(VecQ16 (seteq HVI16:$Vs, HVI16:$Vt)),
354 (V6_veqh HvxVR:$Vs, HvxVR:$Vt)>;
355 def: Pat<(VecQ16 (setgt HVI16:$Vs, HVI16:$Vt)),
356 (V6_vgth HvxVR:$Vs, HvxVR:$Vt)>;
357 def: Pat<(VecQ16 (setugt HVI16:$Vs, HVI16:$Vt)),
358 (V6_vgtuh HvxVR:$Vs, HvxVR:$Vt)>;
359 def: Pat<(VecQ32 (seteq HVI32:$Vs, HVI32:$Vt)),
360 (V6_veqw HvxVR:$Vs, HvxVR:$Vt)>;
361 def: Pat<(VecQ32 (setgt HVI32:$Vs, HVI32:$Vt)),
362 (V6_vgtw HvxVR:$Vs, HvxVR:$Vt)>;
363 def: Pat<(VecQ32 (setugt HVI32:$Vs, HVI32:$Vt)),
364 (V6_vgtuw HvxVR:$Vs, HvxVR:$Vt)>;
365
366 def: Pat<(VecI8 (trunc HWI16:$Vss)),
367 (V6_vpackeb (HiVec $Vss), (LoVec $Vss))>;
368 def: Pat<(VecI16 (trunc HWI32:$Vss)),
369 (V6_vpackeh (HiVec $Vss), (LoVec $Vss))>;
370}
371
372class HvxSel_pat<InstHexagon MI, PatFrag RegPred>
373 : Pat<(select I1:$Pu, RegPred:$Vs, RegPred:$Vt),
374 (MI I1:$Pu, RegPred:$Vs, RegPred:$Vt)>;
375
376let Predicates = [HasV60T,UseHVX] in {
377 def: HvxSel_pat<PS_vselect, HVI8>;
378 def: HvxSel_pat<PS_vselect, HVI16>;
379 def: HvxSel_pat<PS_vselect, HVI32>;
380 def: HvxSel_pat<PS_wselect, HWI8>;
381 def: HvxSel_pat<PS_wselect, HWI16>;
382 def: HvxSel_pat<PS_wselect, HWI32>;
383}
384