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gerrit-public.fairphone.software / toolchain / llvm-project / 458a669f49e30a30b0fbfcc34fc4e556befbb73b / . / llvm / test / Transforms / InstCombine / icmp-shr.ll
blob: 7562f24a35d847c0e075a4b8e33f53b773da7be1 [file] [log] [blame]
Suyog Sarda3a8c2c12014-07-22 19:19:36 +0000[diff] [blame]1; RUN: opt < %s -instcombine -S | FileCheck %s
2
3target datalayout = "e-p:64:64:64-p1:16:16:16-p2:32:32:32-p3:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64"
4
5; CHECK-LABEL: @exact_lshr_eq_both_zero
6; CHECK-NEXT: ret i1 true
7define i1 @exact_lshr_eq_both_zero(i8 %a) {
8 %shr = lshr exact i8 0, %a
9 %cmp = icmp eq i8 %shr, 0
10 ret i1 %cmp
11}
12
13; CHECK-LABEL: @exact_ashr_eq_both_zero
14; CHECK-NEXT: ret i1 true
15define i1 @exact_ashr_eq_both_zero(i8 %a) {
16 %shr = ashr exact i8 0, %a
17 %cmp = icmp eq i8 %shr, 0
18 ret i1 %cmp
19}
20
21; CHECK-LABEL: @nonexact_lshr_eq_both_zero
22; CHECK-NEXT: ret i1 true
23define i1 @nonexact_lshr_eq_both_zero(i8 %a) {
24 %shr = lshr i8 0, %a
25 %cmp = icmp eq i8 %shr, 0
26 ret i1 %cmp
27}
28
29; CHECK-LABEL: @nonexact_ashr_eq_both_zero
30; CHECK-NEXT: ret i1 true
31define i1 @nonexact_ashr_eq_both_zero(i8 %a) {
32 %shr = ashr i8 0, %a
33 %cmp = icmp eq i8 %shr, 0
34 ret i1 %cmp
35}
36
37; CHECK-LABEL: @exact_lshr_ne_both_zero
38; CHECK-NEXT: ret i1 false
39define i1 @exact_lshr_ne_both_zero(i8 %a) {
40 %shr = lshr exact i8 0, %a
41 %cmp = icmp ne i8 %shr, 0
42 ret i1 %cmp
43}
44
45; CHECK-LABEL: @exact_ashr_ne_both_zero
46; CHECK-NEXT: ret i1 false
47define i1 @exact_ashr_ne_both_zero(i8 %a) {
48 %shr = ashr exact i8 0, %a
49 %cmp = icmp ne i8 %shr, 0
50 ret i1 %cmp
51}
52
53; CHECK-LABEL: @nonexact_lshr_ne_both_zero
54; CHECK-NEXT: ret i1 false
55define i1 @nonexact_lshr_ne_both_zero(i8 %a) {
56 %shr = lshr i8 0, %a
57 %cmp = icmp ne i8 %shr, 0
58 ret i1 %cmp
59}
60
61; CHECK-LABEL: @nonexact_ashr_ne_both_zero
62; CHECK-NEXT: ret i1 false
63define i1 @nonexact_ashr_ne_both_zero(i8 %a) {
64 %shr = ashr i8 0, %a
65 %cmp = icmp ne i8 %shr, 0
66 ret i1 %cmp
67}
68
69; CHECK-LABEL: @exact_lshr_eq_last_zero
70; CHECK-NEXT: ret i1 false
71define i1 @exact_lshr_eq_last_zero(i8 %a) {
72 %shr = lshr exact i8 128, %a
73 %cmp = icmp eq i8 %shr, 0
74 ret i1 %cmp
75}
76
77; CHECK-LABEL: @exact_ashr_eq_last_zero
78; CHECK-NEXT: ret i1 false
79define i1 @exact_ashr_eq_last_zero(i8 %a) {
80 %shr = ashr exact i8 -128, %a
81 %cmp = icmp eq i8 %shr, 0
82 ret i1 %cmp
83}
84
85; CHECK-LABEL: @exact_lshr_ne_last_zero
86; CHECK-NEXT: ret i1 true
87define i1 @exact_lshr_ne_last_zero(i8 %a) {
88 %shr = lshr exact i8 128, %a
89 %cmp = icmp ne i8 %shr, 0
90 ret i1 %cmp
91}
92
93; CHECK-LABEL: @exact_ashr_ne_last_zero
94; CHECK-NEXT: ret i1 true
95define i1 @exact_ashr_ne_last_zero(i8 %a) {
96 %shr = ashr exact i8 -128, %a
97 %cmp = icmp ne i8 %shr, 0
98 ret i1 %cmp
99}
100
101; CHECK-LABEL: @nonexact_lshr_eq_last_zero
102; CHECK-NEXT: ret i1 false
103define i1 @nonexact_lshr_eq_last_zero(i8 %a) {
104 %shr = lshr i8 128, %a
105 %cmp = icmp eq i8 %shr, 0
106 ret i1 %cmp
107}
108
109; CHECK-LABEL: @nonexact_ashr_eq_last_zero
110; CHECK-NEXT: ret i1 false
111define i1 @nonexact_ashr_eq_last_zero(i8 %a) {
112 %shr = ashr i8 -128, %a
113 %cmp = icmp eq i8 %shr, 0
114 ret i1 %cmp
115}
116
117; CHECK-LABEL: @nonexact_lshr_ne_last_zero
118; CHECK-NEXT: ret i1 true
119define i1 @nonexact_lshr_ne_last_zero(i8 %a) {
120 %shr = lshr i8 128, %a
121 %cmp = icmp ne i8 %shr, 0
122 ret i1 %cmp
123}
124
125; CHECK-LABEL: @nonexact_ashr_ne_last_zero
126; CHECK-NEXT: ret i1 true
127define i1 @nonexact_ashr_ne_last_zero(i8 %a) {
128 %shr = ashr i8 -128, %a
129 %cmp = icmp ne i8 %shr, 0
130 ret i1 %cmp
131}
132
133; CHECK-LABEL: @lshr_eq_msb_low_last_zero
134; CHECK-NEXT: icmp ugt i8 %a, 6
135define i1 @lshr_eq_msb_low_last_zero(i8 %a) {
136 %shr = lshr i8 127, %a
137 %cmp = icmp eq i8 %shr, 0
138 ret i1 %cmp
139}
140
141; CHECK-LABEL: @ashr_eq_msb_low_second_zero
142; CHECK-NEXT: icmp ugt i8 %a, 6
143define i1 @ashr_eq_msb_low_second_zero(i8 %a) {
144 %shr = ashr i8 127, %a
145 %cmp = icmp eq i8 %shr, 0
146 ret i1 %cmp
147}
148
149; CHECK-LABEL: @lshr_ne_msb_low_last_zero
150; CHECK-NEXT: icmp ult i8 %a, 7
151define i1 @lshr_ne_msb_low_last_zero(i8 %a) {
152 %shr = lshr i8 127, %a
153 %cmp = icmp ne i8 %shr, 0
154 ret i1 %cmp
155}
156
157; CHECK-LABEL: @ashr_ne_msb_low_second_zero
158; CHECK-NEXT: icmp ult i8 %a, 7
159define i1 @ashr_ne_msb_low_second_zero(i8 %a) {
160 %shr = ashr i8 127, %a
161 %cmp = icmp ne i8 %shr, 0
162 ret i1 %cmp
163}
164
165; CHECK-LABEL: @lshr_eq_first_zero
166; CHECK-NEXT: ret i1 false
167define i1 @lshr_eq_first_zero(i8 %a) {
168 %shr = lshr i8 0, %a
169 %cmp = icmp eq i8 %shr, 2
170 ret i1 %cmp
171}
172
173; CHECK-LABEL: @ashr_eq_first_zero
174; CHECK-NEXT: ret i1 false
175define i1 @ashr_eq_first_zero(i8 %a) {
176 %shr = ashr i8 0, %a
177 %cmp = icmp eq i8 %shr, 2
178 ret i1 %cmp
179}
180
181; CHECK-LABEL: @lshr_ne_first_zero
182; CHECK-NEXT: ret i1 true
183define i1 @lshr_ne_first_zero(i8 %a) {
184 %shr = lshr i8 0, %a
185 %cmp = icmp ne i8 %shr, 2
186 ret i1 %cmp
187}
188
189; CHECK-LABEL: @ashr_ne_first_zero
190; CHECK-NEXT: ret i1 true
191define i1 @ashr_ne_first_zero(i8 %a) {
192 %shr = ashr i8 0, %a
193 %cmp = icmp ne i8 %shr, 2
194 ret i1 %cmp
195}
196
197; CHECK-LABEL: @ashr_eq_both_minus1
198; CHECK-NEXT: ret i1 true
199define i1 @ashr_eq_both_minus1(i8 %a) {
200 %shr = ashr i8 -1, %a
201 %cmp = icmp eq i8 %shr, -1
202 ret i1 %cmp
203}
204
205; CHECK-LABEL: @ashr_ne_both_minus1
206; CHECK-NEXT: ret i1 false
207define i1 @ashr_ne_both_minus1(i8 %a) {
208 %shr = ashr i8 -1, %a
209 %cmp = icmp ne i8 %shr, -1
210 ret i1 %cmp
211}
212
213; CHECK-LABEL: @exact_ashr_eq_both_minus1
214; CHECK-NEXT: ret i1 true
215define i1 @exact_ashr_eq_both_minus1(i8 %a) {
216 %shr = ashr exact i8 -1, %a
217 %cmp = icmp eq i8 %shr, -1
218 ret i1 %cmp
219}
220
221; CHECK-LABEL: @exact_ashr_ne_both_minus1
222; CHECK-NEXT: ret i1 false
223define i1 @exact_ashr_ne_both_minus1(i8 %a) {
224 %shr = ashr exact i8 -1, %a
225 %cmp = icmp ne i8 %shr, -1
226 ret i1 %cmp
227}
228
229; CHECK-LABEL: @ashr_eq_both_equal
230; CHECK-NEXT: icmp eq i8 %a, 0
231define i1 @ashr_eq_both_equal(i8 %a) {
232 %shr = ashr i8 128, %a
233 %cmp = icmp eq i8 %shr, 128
234 ret i1 %cmp
235}
236
237; CHECK-LABEL: @ashr_ne_both_equal
238; CHECK-NEXT: icmp ne i8 %a, 0
239define i1 @ashr_ne_both_equal(i8 %a) {
240 %shr = ashr i8 128, %a
241 %cmp = icmp ne i8 %shr, 128
242 ret i1 %cmp
243}
244
245; CHECK-LABEL: @lshr_eq_both_equal
246; CHECK-NEXT: icmp eq i8 %a, 0
247define i1 @lshr_eq_both_equal(i8 %a) {
248 %shr = lshr i8 127, %a
249 %cmp = icmp eq i8 %shr, 127
250 ret i1 %cmp
251}
252
253; CHECK-LABEL: @lshr_ne_both_equal
254; CHECK-NEXT: icmp ne i8 %a, 0
255define i1 @lshr_ne_both_equal(i8 %a) {
256 %shr = lshr i8 127, %a
257 %cmp = icmp ne i8 %shr, 127
258 ret i1 %cmp
259}
260
261; CHECK-LABEL: @exact_ashr_eq_both_equal
262; CHECK-NEXT: icmp eq i8 %a, 0
263define i1 @exact_ashr_eq_both_equal(i8 %a) {
264 %shr = ashr exact i8 128, %a
265 %cmp = icmp eq i8 %shr, 128
266 ret i1 %cmp
267}
268
269; CHECK-LABEL: @exact_ashr_ne_both_equal
270; CHECK-NEXT: icmp ne i8 %a, 0
271define i1 @exact_ashr_ne_both_equal(i8 %a) {
272 %shr = ashr exact i8 128, %a
273 %cmp = icmp ne i8 %shr, 128
274 ret i1 %cmp
275}
276
277; CHECK-LABEL: @exact_lshr_eq_both_equal
278; CHECK-NEXT: icmp eq i8 %a, 0
279define i1 @exact_lshr_eq_both_equal(i8 %a) {
280 %shr = lshr exact i8 126, %a
281 %cmp = icmp eq i8 %shr, 126
282 ret i1 %cmp
283}
284
285; CHECK-LABEL: @exact_lshr_ne_both_equal
286; CHECK-NEXT: icmp ne i8 %a, 0
287define i1 @exact_lshr_ne_both_equal(i8 %a) {
288 %shr = lshr exact i8 126, %a
289 %cmp = icmp ne i8 %shr, 126
290 ret i1 %cmp
291}
292
293; CHECK-LABEL: @exact_ashr_eq_opposite_msb
294; CHECK-NEXT: ret i1 false
295define i1 @exact_ashr_eq_opposite_msb(i8 %a) {
296 %shr = ashr exact i8 -128, %a
297 %cmp = icmp eq i8 %shr, 1
298 ret i1 %cmp
299}
300
301; CHECK-LABEL: @ashr_eq_opposite_msb
302; CHECK-NEXT: ret i1 false
303define i1 @ashr_eq_opposite_msb(i8 %a) {
304 %shr = ashr i8 -128, %a
305 %cmp = icmp eq i8 %shr, 1
306 ret i1 %cmp
307}
308
309; CHECK-LABEL: @exact_lshr_eq_opposite_msb
310; CHECK-NEXT: icmp eq i8 %a, 7
311define i1 @exact_lshr_eq_opposite_msb(i8 %a) {
312 %shr = lshr exact i8 -128, %a
313 %cmp = icmp eq i8 %shr, 1
314 ret i1 %cmp
315}
316
317; CHECK-LABEL: @lshr_eq_opposite_msb
318; CHECK-NEXT: icmp eq i8 %a, 7
319define i1 @lshr_eq_opposite_msb(i8 %a) {
320 %shr = lshr i8 -128, %a
321 %cmp = icmp eq i8 %shr, 1
322 ret i1 %cmp
323}
324
325; CHECK-LABEL: @exact_ashr_ne_opposite_msb
326; CHECK-NEXT: ret i1 true
327define i1 @exact_ashr_ne_opposite_msb(i8 %a) {
328 %shr = ashr exact i8 -128, %a
329 %cmp = icmp ne i8 %shr, 1
330 ret i1 %cmp
331}
332
333; CHECK-LABEL: @ashr_ne_opposite_msb
334; CHECK-NEXT: ret i1 true
335define i1 @ashr_ne_opposite_msb(i8 %a) {
336 %shr = ashr i8 -128, %a
337 %cmp = icmp ne i8 %shr, 1
338 ret i1 %cmp
339}
340
341; CHECK-LABEL: @exact_lshr_ne_opposite_msb
342; CHECK-NEXT: icmp ne i8 %a, 7
343define i1 @exact_lshr_ne_opposite_msb(i8 %a) {
344 %shr = lshr exact i8 -128, %a
345 %cmp = icmp ne i8 %shr, 1
346 ret i1 %cmp
347}
348
349; CHECK-LABEL: @lshr_ne_opposite_msb
350; CHECK-NEXT: icmp ne i8 %a, 7
351define i1 @lshr_ne_opposite_msb(i8 %a) {
352 %shr = lshr i8 -128, %a
353 %cmp = icmp ne i8 %shr, 1
354 ret i1 %cmp
355}
356
357; CHECK-LABEL: @exact_ashr_eq_shift_gt
358; CHECK-NEXT : ret i1 false
359define i1 @exact_ashr_eq_shift_gt(i8 %a) {
360 %shr = ashr exact i8 -2, %a
361 %cmp = icmp eq i8 %shr, -8
362 ret i1 %cmp
363}
364
365; CHECK-LABEL: @exact_ashr_ne_shift_gt
366; CHECK-NEXT : ret i1 true
367define i1 @exact_ashr_ne_shift_gt(i8 %a) {
368 %shr = ashr exact i8 -2, %a
369 %cmp = icmp ne i8 %shr, -8
370 ret i1 %cmp
371}
372
373; CHECK-LABEL: @nonexact_ashr_eq_shift_gt
374; CHECK-NEXT : ret i1 false
375define i1 @nonexact_ashr_eq_shift_gt(i8 %a) {
376 %shr = ashr i8 -2, %a
377 %cmp = icmp eq i8 %shr, -8
378 ret i1 %cmp
379}
380
381; CHECK-LABEL: @nonexact_ashr_ne_shift_gt
382; CHECK-NEXT : ret i1 true
383define i1 @nonexact_ashr_ne_shift_gt(i8 %a) {
384 %shr = ashr i8 -2, %a
385 %cmp = icmp ne i8 %shr, -8
386 ret i1 %cmp
387}
388
389; CHECK-LABEL: @exact_lshr_eq_shift_gt
390; CHECK-NEXT: ret i1 false
391define i1 @exact_lshr_eq_shift_gt(i8 %a) {
392 %shr = lshr exact i8 2, %a
393 %cmp = icmp eq i8 %shr, 8
394 ret i1 %cmp
395}
396
397; CHECK-LABEL: @exact_lshr_ne_shift_gt
398; CHECK-NEXT: ret i1 true
399define i1 @exact_lshr_ne_shift_gt(i8 %a) {
400 %shr = lshr exact i8 2, %a
401 %cmp = icmp ne i8 %shr, 8
402 ret i1 %cmp
403}
404
405; CHECK-LABEL: @nonexact_lshr_eq_shift_gt
406; CHECK-NEXT : ret i1 false
407define i1 @nonexact_lshr_eq_shift_gt(i8 %a) {
408 %shr = lshr i8 2, %a
409 %cmp = icmp eq i8 %shr, 8
410 ret i1 %cmp
411}
412
413; CHECK-LABEL: @nonexact_lshr_ne_shift_gt
414; CHECK-NEXT : ret i1 true
415define i1 @nonexact_lshr_ne_shift_gt(i8 %a) {
416 %shr = ashr i8 2, %a
417 %cmp = icmp ne i8 %shr, 8
418 ret i1 %cmp
419}
420
Suyog Sarda3a8c2c12014-07-22 19:19:36 +0000[diff] [blame]421; CHECK-LABEL: @exact_ashr_eq
422; CHECK-NEXT: icmp eq i8 %a, 7
423define i1 @exact_ashr_eq(i8 %a) {
424 %shr = ashr exact i8 -128, %a
425 %cmp = icmp eq i8 %shr, -1
426 ret i1 %cmp
427}
428
429; CHECK-LABEL: @exact_ashr_ne
430; CHECK-NEXT: icmp ne i8 %a, 7
431define i1 @exact_ashr_ne(i8 %a) {
432 %shr = ashr exact i8 -128, %a
433 %cmp = icmp ne i8 %shr, -1
434 ret i1 %cmp
435}
436
437; CHECK-LABEL: @exact_lshr_eq
438; CHECK-NEXT: icmp eq i8 %a, 2
439define i1 @exact_lshr_eq(i8 %a) {
440 %shr = lshr exact i8 4, %a
441 %cmp = icmp eq i8 %shr, 1
442 ret i1 %cmp
443}
444
445; CHECK-LABEL: @exact_lshr_ne
446; CHECK-NEXT: icmp ne i8 %a, 2
447define i1 @exact_lshr_ne(i8 %a) {
448 %shr = lshr exact i8 4, %a
449 %cmp = icmp ne i8 %shr, 1
450 ret i1 %cmp
451}
452
453; CHECK-LABEL: @nonexact_ashr_eq
454; CHECK-NEXT: icmp eq i8 %a, 7
455define i1 @nonexact_ashr_eq(i8 %a) {
456 %shr = ashr i8 -128, %a
457 %cmp = icmp eq i8 %shr, -1
458 ret i1 %cmp
459}
460
461; CHECK-LABEL: @nonexact_ashr_ne
462; CHECK-NEXT: icmp ne i8 %a, 7
463define i1 @nonexact_ashr_ne(i8 %a) {
464 %shr = ashr i8 -128, %a
465 %cmp = icmp ne i8 %shr, -1
466 ret i1 %cmp
467}
468
469; CHECK-LABEL: @nonexact_lshr_eq
470; CHECK-NEXT: icmp eq i8 %a, 2
471define i1 @nonexact_lshr_eq(i8 %a) {
472 %shr = lshr i8 4, %a
473 %cmp = icmp eq i8 %shr, 1
474 ret i1 %cmp
475}
476
477; CHECK-LABEL: @nonexact_lshr_ne
478; CHECK-NEXT: icmp ne i8 %a, 2
479define i1 @nonexact_lshr_ne(i8 %a) {
480 %shr = lshr i8 4, %a
481 %cmp = icmp ne i8 %shr, 1
482 ret i1 %cmp
483}
484
485; CHECK-LABEL: @exact_lshr_eq_exactdiv
486; CHECK-NEXT: icmp eq i8 %a, 4
487define i1 @exact_lshr_eq_exactdiv(i8 %a) {
488 %shr = lshr exact i8 80, %a
489 %cmp = icmp eq i8 %shr, 5
490 ret i1 %cmp
491}
492
493; CHECK-LABEL: @exact_lshr_ne_exactdiv
494; CHECK-NEXT: icmp ne i8 %a, 4
495define i1 @exact_lshr_ne_exactdiv(i8 %a) {
496 %shr = lshr exact i8 80, %a
497 %cmp = icmp ne i8 %shr, 5
498 ret i1 %cmp
499}
500
501; CHECK-LABEL: @nonexact_lshr_eq_exactdiv
502; CHECK-NEXT: icmp eq i8 %a, 4
503define i1 @nonexact_lshr_eq_exactdiv(i8 %a) {
504 %shr = lshr i8 80, %a
505 %cmp = icmp eq i8 %shr, 5
506 ret i1 %cmp
507}
508
509; CHECK-LABEL: @nonexact_lshr_ne_exactdiv
510; CHECK-NEXT: icmp ne i8 %a, 4
511define i1 @nonexact_lshr_ne_exactdiv(i8 %a) {
512 %shr = lshr i8 80, %a
513 %cmp = icmp ne i8 %shr, 5
514 ret i1 %cmp
515}
516
517; CHECK-LABEL: @exact_ashr_eq_exactdiv
518; CHECK-NEXT: icmp eq i8 %a, 4
519define i1 @exact_ashr_eq_exactdiv(i8 %a) {
520 %shr = ashr exact i8 -80, %a
521 %cmp = icmp eq i8 %shr, -5
522 ret i1 %cmp
523}
524
525; CHECK-LABEL: @exact_ashr_ne_exactdiv
526; CHECK-NEXT: icmp ne i8 %a, 4
527define i1 @exact_ashr_ne_exactdiv(i8 %a) {
528 %shr = ashr exact i8 -80, %a
529 %cmp = icmp ne i8 %shr, -5
530 ret i1 %cmp
531}
532
533; CHECK-LABEL: @nonexact_ashr_eq_exactdiv
534; CHECK-NEXT: icmp eq i8 %a, 4
535define i1 @nonexact_ashr_eq_exactdiv(i8 %a) {
536 %shr = ashr i8 -80, %a
537 %cmp = icmp eq i8 %shr, -5
538 ret i1 %cmp
539}
540
541; CHECK-LABEL: @nonexact_ashr_ne_exactdiv
542; CHECK-NEXT: icmp ne i8 %a, 4
543define i1 @nonexact_ashr_ne_exactdiv(i8 %a) {
544 %shr = ashr i8 -80, %a
545 %cmp = icmp ne i8 %shr, -5
546 ret i1 %cmp
547}
548
549; CHECK-LABEL: @exact_lshr_eq_noexactdiv
550; CHECK-NEXT: ret i1 false
551define i1 @exact_lshr_eq_noexactdiv(i8 %a) {
552 %shr = lshr exact i8 80, %a
553 %cmp = icmp eq i8 %shr, 31
554 ret i1 %cmp
555}
556
557; CHECK-LABEL: @exact_lshr_ne_noexactdiv
558; CHECK-NEXT: ret i1 true
559define i1 @exact_lshr_ne_noexactdiv(i8 %a) {
560 %shr = lshr exact i8 80, %a
561 %cmp = icmp ne i8 %shr, 31
562 ret i1 %cmp
563}
564
565; CHECK-LABEL: @nonexact_lshr_eq_noexactdiv
566; CHECK-NEXT: ret i1 false
567define i1 @nonexact_lshr_eq_noexactdiv(i8 %a) {
568 %shr = lshr i8 80, %a
569 %cmp = icmp eq i8 %shr, 31
570 ret i1 %cmp
571}
572
573; CHECK-LABEL: @nonexact_lshr_ne_noexactdiv
574; CHECK-NEXT: ret i1 true
575define i1 @nonexact_lshr_ne_noexactdiv(i8 %a) {
576 %shr = lshr i8 80, %a
577 %cmp = icmp ne i8 %shr, 31
578 ret i1 %cmp
579}
580
581; CHECK-LABEL: @exact_ashr_eq_noexactdiv
582; CHECK-NEXT: ret i1 false
583define i1 @exact_ashr_eq_noexactdiv(i8 %a) {
584 %shr = ashr exact i8 -80, %a
585 %cmp = icmp eq i8 %shr, -31
586 ret i1 %cmp
587}
588
589; CHECK-LABEL: @exact_ashr_ne_noexactdiv
590; CHECK-NEXT: ret i1 true
591define i1 @exact_ashr_ne_noexactdiv(i8 %a) {
592 %shr = ashr exact i8 -80, %a
593 %cmp = icmp ne i8 %shr, -31
594 ret i1 %cmp
595}
596
597; CHECK-LABEL: @nonexact_ashr_eq_noexactdiv
598; CHECK-NEXT: ret i1 false
599define i1 @nonexact_ashr_eq_noexactdiv(i8 %a) {
600 %shr = ashr i8 -80, %a
601 %cmp = icmp eq i8 %shr, -31
602 ret i1 %cmp
603}
604
605; CHECK-LABEL: @nonexact_ashr_ne_noexactdiv
606; CHECK-NEXT: ret i1 true
607define i1 @nonexact_ashr_ne_noexactdiv(i8 %a) {
608 %shr = ashr i8 -80, %a
609 %cmp = icmp ne i8 %shr, -31
610 ret i1 %cmp
611}
612
613; CHECK-LABEL: @exact_lshr_eq_noexactlog
614; CHECK-NEXT: ret i1 false
615define i1 @exact_lshr_eq_noexactlog(i8 %a) {
616 %shr = lshr exact i8 90, %a
617 %cmp = icmp eq i8 %shr, 30
618 ret i1 %cmp
619}
620
621; CHECK-LABEL: @exact_lshr_ne_noexactlog
622; CHECK-NEXT: ret i1 true
623define i1 @exact_lshr_ne_noexactlog(i8 %a) {
624 %shr = lshr exact i8 90, %a
625 %cmp = icmp ne i8 %shr, 30
626 ret i1 %cmp
627}
628
629; CHECK-LABEL: @nonexact_lshr_eq_noexactlog
630; CHECK-NEXT: ret i1 false
631define i1 @nonexact_lshr_eq_noexactlog(i8 %a) {
632 %shr = lshr i8 90, %a
633 %cmp = icmp eq i8 %shr, 30
634 ret i1 %cmp
635}
636
637; CHECK-LABEL: @nonexact_lshr_ne_noexactlog
638; CHECK-NEXT: ret i1 true
639define i1 @nonexact_lshr_ne_noexactlog(i8 %a) {
640 %shr = lshr i8 90, %a
641 %cmp = icmp ne i8 %shr, 30
642 ret i1 %cmp
643}
644
645; CHECK-LABEL: @exact_ashr_eq_noexactlog
646; CHECK-NEXT: ret i1 false
647define i1 @exact_ashr_eq_noexactlog(i8 %a) {
648 %shr = ashr exact i8 -90, %a
649 %cmp = icmp eq i8 %shr, -30
650 ret i1 %cmp
651}
652
653; CHECK-LABEL: @exact_ashr_ne_noexactlog
654; CHECK-NEXT: ret i1 true
655define i1 @exact_ashr_ne_noexactlog(i8 %a) {
656 %shr = ashr exact i8 -90, %a
657 %cmp = icmp ne i8 %shr, -30
658 ret i1 %cmp
659}
660
661; CHECK-LABEL: @nonexact_ashr_eq_noexactlog
662; CHECK-NEXT: ret i1 false
663define i1 @nonexact_ashr_eq_noexactlog(i8 %a) {
664 %shr = ashr i8 -90, %a
665 %cmp = icmp eq i8 %shr, -30
666 ret i1 %cmp
667}
668
669; CHECK-LABEL: @nonexact_ashr_ne_noexactlog
670; CHECK-NEXT: ret i1 true
671define i1 @nonexact_ashr_ne_noexactlog(i8 %a) {
672 %shr = ashr i8 -90, %a
673 %cmp = icmp ne i8 %shr, -30
674 ret i1 %cmp
675}
Andrea Di Biagio5b92b492014-09-17 11:32:31 +0000[diff] [blame]676
677; Don't try to fold the entire body of function @PR20945 into a
678; single `ret i1 true` statement.
679; If %B is equal to 1, then this function would return false.
680; As a consequence, the instruction combiner is not allowed to fold %cmp
681; to 'true'. Instead, it should replace %cmp with a simpler comparison
682; between %B and 1.
683
684; CHECK-LABEL: @PR20945(
685; CHECK: icmp ne i32 %B, 1
686define i1 @PR20945(i32 %B) {
687 %shr = ashr i32 -9, %B
688 %cmp = icmp ne i32 %shr, -5
689 ret i1 %cmp
690}
Andrea Di Biagio458a6692014-10-09 12:41:49 +0000[diff] [blame^]691
692; CHECK-LABEL: @PR21222
693; CHECK: icmp eq i32 %B, 6
694define i1 @PR21222(i32 %B) {
695 %shr = ashr i32 -93, %B
696 %cmp = icmp eq i32 %shr, -2
697 ret i1 %cmp
698}