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gerrit-public.fairphone.software / toolchain / llvm-project / 46402a42111b48a625cef2ea440f14387821982b / . / llvm / lib / Target / PowerPC / PPCSchedule440.td
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Jia Liub22310f2012-02-18 12:03:15 +0000[diff] [blame]1//===-- PPCSchedule440.td - PPC 440 Scheduling Definitions -*- tablegen -*-===//
2//
Hal Finkelad677b62011-10-17 04:03:55 +0000[diff] [blame]3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
Jia Liub22310f2012-02-18 12:03:15 +0000[diff] [blame]7//
Hal Finkelad677b62011-10-17 04:03:55 +0000[diff] [blame]8//===----------------------------------------------------------------------===//
9
10// Primary reference:
Hal Finkelafa70aa2011-10-17 18:10:08 +0000[diff] [blame]11// PowerPC 440x6 Embedded Processor Core User's Manual.
Hal Finkelad677b62011-10-17 04:03:55 +0000[diff] [blame]12// IBM (as updated in) 2010.
13
14// The basic PPC 440 does not include a floating-point unit; the pipeline
15// timings here are constructed to match the FP2 unit shipped with the
16// PPC-440- and PPC-450-based Blue Gene (L and P) supercomputers.
17// References:
18// S. Chatterjee, et al. Design and exploitation of a high-performance
19// SIMD floating-point unit for Blue Gene/L.
20// IBM J. Res. & Dev. 49 (2/3) March/May 2005.
21// also:
22// Carlos Sosa and Brant Knudson. IBM System Blue Gene Solution:
23// Blue Gene/P Application Development.
24// IBM (as updated in) 2009.
25
26//===----------------------------------------------------------------------===//
27// Functional units on the PowerPC 440/450 chip sets
28//
Hal Finkel92720ab2013-11-28 06:05:59 +0000[diff] [blame]29def P440_DISS1 : FuncUnit; // Issue unit 1
30def P440_DISS2 : FuncUnit; // Issue unit 2
31def P440_LRACC : FuncUnit; // Register access and dispatch for
32 // the simple integer (J-pipe) and
33 // load/store (L-pipe) pipelines
34def P440_IRACC : FuncUnit; // Register access and dispatch for
35 // the complex integer (I-pipe) pipeline
36def P440_FRACC : FuncUnit; // Register access and dispatch for
37 // the floating-point execution (F-pipe) pipeline
38def P440_IEXE1 : FuncUnit; // Execution stage 1 for the I pipeline
39def P440_IEXE2 : FuncUnit; // Execution stage 2 for the I pipeline
40def P440_IWB : FuncUnit; // Write-back unit for the I pipeline
41def P440_JEXE1 : FuncUnit; // Execution stage 1 for the J pipeline
42def P440_JEXE2 : FuncUnit; // Execution stage 2 for the J pipeline
43def P440_JWB : FuncUnit; // Write-back unit for the J pipeline
44def P440_AGEN : FuncUnit; // Address generation for the L pipeline
45def P440_CRD : FuncUnit; // D-cache access for the L pipeline
46def P440_LWB : FuncUnit; // Write-back unit for the L pipeline
47def P440_FEXE1 : FuncUnit; // Execution stage 1 for the F pipeline
48def P440_FEXE2 : FuncUnit; // Execution stage 2 for the F pipeline
49def P440_FEXE3 : FuncUnit; // Execution stage 3 for the F pipeline
50def P440_FEXE4 : FuncUnit; // Execution stage 4 for the F pipeline
51def P440_FEXE5 : FuncUnit; // Execution stage 5 for the F pipeline
52def P440_FEXE6 : FuncUnit; // Execution stage 6 for the F pipeline
53def P440_FWB : FuncUnit; // Write-back unit for the F pipeline
Hal Finkelad677b62011-10-17 04:03:55 +0000[diff] [blame]54
Hal Finkel92720ab2013-11-28 06:05:59 +0000[diff] [blame]55def P440_LWARX_Hold : FuncUnit; // This is a pseudo-unit which is used
56 // to make sure that no lwarx/stwcx.
57 // instructions are issued while another
58 // lwarx/stwcx. is in the L pipe.
Hal Finkelad677b62011-10-17 04:03:55 +0000[diff] [blame]59
Hal Finkel92720ab2013-11-28 06:05:59 +0000[diff] [blame]60def P440_GPR_Bypass : Bypass; // The bypass for general-purpose regs.
61def P440_FPR_Bypass : Bypass; // The bypass for floating-point regs.
Hal Finkelad677b62011-10-17 04:03:55 +0000[diff] [blame]62
63// Notes:
64// Instructions are held in the FRACC, LRACC and IRACC pipeline
65// stages until their source operands become ready. Exceptions:
66// - Store instructions will hold in the AGEN stage
67// - The integer multiply-accumulate instruction will hold in
68// the IEXE1 stage
69//
70// For most I-pipe operations, the result is available at the end of
71// the IEXE1 stage. Operations such as multiply and divide must
72// continue to execute in IEXE2 and IWB. Divide resides in IWB for
73// 33 cycles (multiply also calculates its result in IWB). For all
74// J-pipe instructions, the result is available
75// at the end of the JEXE1 stage. Loads have a 3-cycle latency
76// (data is not available until after the LWB stage).
77//
78// The L1 cache hit latency is four cycles for floating point loads
79// and three cycles for integer loads.
80//
81// The stwcx. instruction requires both the LRACC and the IRACC
82// dispatch stages. It must be issued from DISS0.
83//
84// All lwarx/stwcx. instructions hold in LRACC if another
85// uncommitted lwarx/stwcx. is in AGEN, CRD, or LWB.
86//
87// msync (a.k.a. sync) and mbar will hold in LWB until all load/store
88// resources are empty. AGEN and CRD are held empty until the msync/mbar
89// commits.
90//
91// Most floating-point instructions, computational and move,
92// have a 5-cycle latency. Divide takes longer (30 cycles). Instructions that
93// update the CR take 2 cycles. Stores take 3 cycles and, as mentioned above,
94// loads take 4 cycles (for L1 hit).
95
96//
97// This file defines the itinerary class data for the PPC 440 processor.
98//
99//===----------------------------------------------------------------------===//
100
101
102def PPC440Itineraries : ProcessorItineraries<
Hal Finkeldd063692013-11-29 05:58:38 +0000[diff] [blame]103 [P440_DISS1, P440_DISS2, P440_FRACC, P440_IRACC, P440_IEXE1, P440_IEXE2,
104 P440_IWB, P440_LRACC, P440_JEXE1, P440_JEXE2, P440_JWB, P440_AGEN, P440_CRD,
105 P440_LWB, P440_FEXE1, P440_FEXE2, P440_FEXE3, P440_FEXE4, P440_FEXE5,
106 P440_FEXE6, P440_FWB, P440_LWARX_Hold],
Hal Finkel92720ab2013-11-28 06:05:59 +0000[diff] [blame]107 [P440_GPR_Bypass, P440_FPR_Bypass], [
Hal Finkeldd063692013-11-29 05:58:38 +0000[diff] [blame]108 InstrItinData<IIC_IntSimple, [InstrStage<1, [P440_DISS1, P440_DISS2]>,
Hal Finkel92720ab2013-11-28 06:05:59 +0000[diff] [blame]109 InstrStage<1, [P440_IRACC, P440_LRACC]>,
110 InstrStage<1, [P440_IEXE1, P440_JEXE1]>,
111 InstrStage<1, [P440_IEXE2, P440_JEXE2]>,
112 InstrStage<1, [P440_IWB, P440_JWB]>],
Hal Finkela10bd1d2013-11-29 05:59:00 +0000[diff] [blame]113 [2, 0, 0],
Hal Finkel92720ab2013-11-28 06:05:59 +0000[diff] [blame]114 [P440_GPR_Bypass,
115 P440_GPR_Bypass, P440_GPR_Bypass]>,
Hal Finkeldd063692013-11-29 05:58:38 +0000[diff] [blame]116 InstrItinData<IIC_IntGeneral, [InstrStage<1, [P440_DISS1, P440_DISS2]>,
Hal Finkel92720ab2013-11-28 06:05:59 +0000[diff] [blame]117 InstrStage<1, [P440_IRACC, P440_LRACC]>,
118 InstrStage<1, [P440_IEXE1, P440_JEXE1]>,
119 InstrStage<1, [P440_IEXE2, P440_JEXE2]>,
120 InstrStage<1, [P440_IWB, P440_JWB]>],
Hal Finkela10bd1d2013-11-29 05:59:00 +0000[diff] [blame]121 [2, 0, 0],
Hal Finkel92720ab2013-11-28 06:05:59 +0000[diff] [blame]122 [P440_GPR_Bypass,
123 P440_GPR_Bypass, P440_GPR_Bypass]>,
Hal Finkeldd063692013-11-29 05:58:38 +0000[diff] [blame]124 InstrItinData<IIC_IntCompare, [InstrStage<1, [P440_DISS1, P440_DISS2]>,
Hal Finkel92720ab2013-11-28 06:05:59 +0000[diff] [blame]125 InstrStage<1, [P440_IRACC, P440_LRACC]>,
126 InstrStage<1, [P440_IEXE1, P440_JEXE1]>,
127 InstrStage<1, [P440_IEXE2, P440_JEXE2]>,
128 InstrStage<1, [P440_IWB, P440_JWB]>],
Hal Finkela10bd1d2013-11-29 05:59:00 +0000[diff] [blame]129 [2, 0, 0],
Hal Finkel92720ab2013-11-28 06:05:59 +0000[diff] [blame]130 [NoBypass, P440_GPR_Bypass, P440_GPR_Bypass]>,
Hal Finkeldd063692013-11-29 05:58:38 +0000[diff] [blame]131 InstrItinData<IIC_IntDivW, [InstrStage<1, [P440_DISS1, P440_DISS2]>,
Hal Finkel92720ab2013-11-28 06:05:59 +0000[diff] [blame]132 InstrStage<1, [P440_IRACC]>,
133 InstrStage<1, [P440_IEXE1]>,
134 InstrStage<1, [P440_IEXE2]>,
135 InstrStage<33, [P440_IWB]>],
Hal Finkela10bd1d2013-11-29 05:59:00 +0000[diff] [blame]136 [36, 0, 0],
Hal Finkel92720ab2013-11-28 06:05:59 +0000[diff] [blame]137 [NoBypass, P440_GPR_Bypass, P440_GPR_Bypass]>,
Hal Finkeldd063692013-11-29 05:58:38 +0000[diff] [blame]138 InstrItinData<IIC_IntMFFS, [InstrStage<1, [P440_DISS1, P440_DISS2]>,
Hal Finkel92720ab2013-11-28 06:05:59 +0000[diff] [blame]139 InstrStage<1, [P440_IRACC]>,
140 InstrStage<1, [P440_IEXE1]>,
141 InstrStage<1, [P440_IEXE2]>,
142 InstrStage<1, [P440_IWB]>],
Hal Finkela10bd1d2013-11-29 05:59:00 +0000[diff] [blame]143 [3, 0, 0],
Hal Finkel92720ab2013-11-28 06:05:59 +0000[diff] [blame]144 [P440_GPR_Bypass,
145 P440_GPR_Bypass, P440_GPR_Bypass]>,
Hal Finkeldd063692013-11-29 05:58:38 +0000[diff] [blame]146 InstrItinData<IIC_IntMTFSB0, [InstrStage<1, [P440_DISS1, P440_DISS2]>,
Hal Finkel92720ab2013-11-28 06:05:59 +0000[diff] [blame]147 InstrStage<1, [P440_IRACC]>,
148 InstrStage<1, [P440_IEXE1]>,
149 InstrStage<1, [P440_IEXE2]>,
150 InstrStage<1, [P440_IWB]>],
Hal Finkela10bd1d2013-11-29 05:59:00 +0000[diff] [blame]151 [3, 0, 0],
Hal Finkel92720ab2013-11-28 06:05:59 +0000[diff] [blame]152 [P440_GPR_Bypass,
153 P440_GPR_Bypass, P440_GPR_Bypass]>,
Hal Finkeldd063692013-11-29 05:58:38 +0000[diff] [blame]154 InstrItinData<IIC_IntMulHW, [InstrStage<1, [P440_DISS1, P440_DISS2]>,
Hal Finkel92720ab2013-11-28 06:05:59 +0000[diff] [blame]155 InstrStage<1, [P440_IRACC]>,
156 InstrStage<1, [P440_IEXE1]>,
157 InstrStage<1, [P440_IEXE2]>,
158 InstrStage<1, [P440_IWB]>],
Hal Finkela10bd1d2013-11-29 05:59:00 +0000[diff] [blame]159 [4, 0, 0],
Hal Finkel92720ab2013-11-28 06:05:59 +0000[diff] [blame]160 [NoBypass, P440_GPR_Bypass, P440_GPR_Bypass]>,
Hal Finkeldd063692013-11-29 05:58:38 +0000[diff] [blame]161 InstrItinData<IIC_IntMulHWU, [InstrStage<1, [P440_DISS1, P440_DISS2]>,
Hal Finkel92720ab2013-11-28 06:05:59 +0000[diff] [blame]162 InstrStage<1, [P440_IRACC]>,
163 InstrStage<1, [P440_IEXE1]>,
164 InstrStage<1, [P440_IEXE2]>,
165 InstrStage<1, [P440_IWB]>],
Hal Finkela10bd1d2013-11-29 05:59:00 +0000[diff] [blame]166 [4, 0, 0],
Hal Finkel92720ab2013-11-28 06:05:59 +0000[diff] [blame]167 [NoBypass, P440_GPR_Bypass, P440_GPR_Bypass]>,
Hal Finkeldd063692013-11-29 05:58:38 +0000[diff] [blame]168 InstrItinData<IIC_IntMulLI, [InstrStage<1, [P440_DISS1, P440_DISS2]>,
Hal Finkel92720ab2013-11-28 06:05:59 +0000[diff] [blame]169 InstrStage<1, [P440_IRACC]>,
170 InstrStage<1, [P440_IEXE1]>,
171 InstrStage<1, [P440_IEXE2]>,
172 InstrStage<1, [P440_IWB]>],
Hal Finkela10bd1d2013-11-29 05:59:00 +0000[diff] [blame]173 [4, 0, 0],
Hal Finkel92720ab2013-11-28 06:05:59 +0000[diff] [blame]174 [NoBypass, P440_GPR_Bypass, P440_GPR_Bypass]>,
Hal Finkeldd063692013-11-29 05:58:38 +0000[diff] [blame]175 InstrItinData<IIC_IntRotate, [InstrStage<1, [P440_DISS1, P440_DISS2]>,
Hal Finkel92720ab2013-11-28 06:05:59 +0000[diff] [blame]176 InstrStage<1, [P440_IRACC, P440_LRACC]>,
177 InstrStage<1, [P440_IEXE1, P440_JEXE1]>,
178 InstrStage<1, [P440_IEXE2, P440_JEXE2]>,
179 InstrStage<1, [P440_IWB, P440_JWB]>],
Hal Finkela10bd1d2013-11-29 05:59:00 +0000[diff] [blame]180 [2, 0, 0],
Hal Finkel92720ab2013-11-28 06:05:59 +0000[diff] [blame]181 [P440_GPR_Bypass,
182 P440_GPR_Bypass, P440_GPR_Bypass]>,
Hal Finkeldd063692013-11-29 05:58:38 +0000[diff] [blame]183 InstrItinData<IIC_IntShift, [InstrStage<1, [P440_DISS1, P440_DISS2]>,
Hal Finkel92720ab2013-11-28 06:05:59 +0000[diff] [blame]184 InstrStage<1, [P440_IRACC, P440_LRACC]>,
185 InstrStage<1, [P440_IEXE1, P440_JEXE1]>,
186 InstrStage<1, [P440_IEXE2, P440_JEXE2]>,
187 InstrStage<1, [P440_IWB, P440_JWB]>],
Hal Finkela10bd1d2013-11-29 05:59:00 +0000[diff] [blame]188 [2, 0, 0],
Hal Finkel92720ab2013-11-28 06:05:59 +0000[diff] [blame]189 [P440_GPR_Bypass,
190 P440_GPR_Bypass, P440_GPR_Bypass]>,
Hal Finkeldd063692013-11-29 05:58:38 +0000[diff] [blame]191 InstrItinData<IIC_IntTrapW, [InstrStage<1, [P440_DISS1, P440_DISS2]>,
Hal Finkel92720ab2013-11-28 06:05:59 +0000[diff] [blame]192 InstrStage<1, [P440_IRACC]>,
193 InstrStage<1, [P440_IEXE1]>,
194 InstrStage<1, [P440_IEXE2]>,
195 InstrStage<1, [P440_IWB]>],
Hal Finkela10bd1d2013-11-29 05:59:00 +0000[diff] [blame]196 [2, 0],
Hal Finkel92720ab2013-11-28 06:05:59 +0000[diff] [blame]197 [P440_GPR_Bypass, P440_GPR_Bypass]>,
Hal Finkeldd063692013-11-29 05:58:38 +0000[diff] [blame]198 InstrItinData<IIC_BrB, [InstrStage<1, [P440_DISS1, P440_DISS2]>,
Hal Finkel92720ab2013-11-28 06:05:59 +0000[diff] [blame]199 InstrStage<1, [P440_IRACC]>,
200 InstrStage<1, [P440_IEXE1]>,
201 InstrStage<1, [P440_IEXE2]>,
202 InstrStage<1, [P440_IWB]>],
Hal Finkela10bd1d2013-11-29 05:59:00 +0000[diff] [blame]203 [4, 0],
Hal Finkel92720ab2013-11-28 06:05:59 +0000[diff] [blame]204 [NoBypass, P440_GPR_Bypass]>,
Hal Finkeldd063692013-11-29 05:58:38 +0000[diff] [blame]205 InstrItinData<IIC_BrCR, [InstrStage<1, [P440_DISS1, P440_DISS2]>,
Hal Finkel92720ab2013-11-28 06:05:59 +0000[diff] [blame]206 InstrStage<1, [P440_IRACC]>,
207 InstrStage<1, [P440_IEXE1]>,
208 InstrStage<1, [P440_IEXE2]>,
209 InstrStage<1, [P440_IWB]>],
Hal Finkela10bd1d2013-11-29 05:59:00 +0000[diff] [blame]210 [4, 0, 0],
Hal Finkel92720ab2013-11-28 06:05:59 +0000[diff] [blame]211 [NoBypass, P440_GPR_Bypass, P440_GPR_Bypass]>,
Hal Finkeldd063692013-11-29 05:58:38 +0000[diff] [blame]212 InstrItinData<IIC_BrMCR, [InstrStage<1, [P440_DISS1, P440_DISS2]>,
Hal Finkel92720ab2013-11-28 06:05:59 +0000[diff] [blame]213 InstrStage<1, [P440_IRACC]>,
214 InstrStage<1, [P440_IEXE1]>,
215 InstrStage<1, [P440_IEXE2]>,
216 InstrStage<1, [P440_IWB]>],
Hal Finkela10bd1d2013-11-29 05:59:00 +0000[diff] [blame]217 [4, 0, 0],
Hal Finkel92720ab2013-11-28 06:05:59 +0000[diff] [blame]218 [NoBypass, P440_GPR_Bypass, P440_GPR_Bypass]>,
Hal Finkeldd063692013-11-29 05:58:38 +0000[diff] [blame]219 InstrItinData<IIC_BrMCRX, [InstrStage<1, [P440_DISS1, P440_DISS2]>,
Hal Finkel92720ab2013-11-28 06:05:59 +0000[diff] [blame]220 InstrStage<1, [P440_IRACC]>,
221 InstrStage<1, [P440_IEXE1]>,
222 InstrStage<1, [P440_IEXE2]>,
223 InstrStage<1, [P440_IWB]>],
Hal Finkela10bd1d2013-11-29 05:59:00 +0000[diff] [blame]224 [4, 0, 0],
Hal Finkel92720ab2013-11-28 06:05:59 +0000[diff] [blame]225 [NoBypass, P440_GPR_Bypass, P440_GPR_Bypass]>,
Hal Finkeldd063692013-11-29 05:58:38 +0000[diff] [blame]226 InstrItinData<IIC_LdStDCBA, [InstrStage<1, [P440_DISS1, P440_DISS2]>,
Hal Finkel92720ab2013-11-28 06:05:59 +0000[diff] [blame]227 InstrStage<1, [P440_LRACC]>,
228 InstrStage<1, [P440_AGEN]>,
229 InstrStage<1, [P440_CRD]>,
230 InstrStage<1, [P440_LWB]>],
Hal Finkel4035e8d2013-11-29 06:19:43 +0000[diff] [blame]231 [1, 1],
Hal Finkel92720ab2013-11-28 06:05:59 +0000[diff] [blame]232 [NoBypass, P440_GPR_Bypass]>,
Hal Finkeldd063692013-11-29 05:58:38 +0000[diff] [blame]233 InstrItinData<IIC_LdStDCBF, [InstrStage<1, [P440_DISS1, P440_DISS2]>,
Hal Finkel92720ab2013-11-28 06:05:59 +0000[diff] [blame]234 InstrStage<1, [P440_LRACC]>,
235 InstrStage<1, [P440_AGEN]>,
236 InstrStage<1, [P440_CRD]>,
237 InstrStage<1, [P440_LWB]>],
Hal Finkel4035e8d2013-11-29 06:19:43 +0000[diff] [blame]238 [1, 1],
Hal Finkel92720ab2013-11-28 06:05:59 +0000[diff] [blame]239 [NoBypass, P440_GPR_Bypass]>,
Hal Finkeldd063692013-11-29 05:58:38 +0000[diff] [blame]240 InstrItinData<IIC_LdStDCBI, [InstrStage<1, [P440_DISS1, P440_DISS2]>,
Hal Finkel92720ab2013-11-28 06:05:59 +0000[diff] [blame]241 InstrStage<1, [P440_LRACC]>,
242 InstrStage<1, [P440_AGEN]>,
243 InstrStage<1, [P440_CRD]>,
244 InstrStage<1, [P440_LWB]>],
Hal Finkel4035e8d2013-11-29 06:19:43 +0000[diff] [blame]245 [1, 1],
Hal Finkel92720ab2013-11-28 06:05:59 +0000[diff] [blame]246 [NoBypass, P440_GPR_Bypass]>,
Hal Finkeldd063692013-11-29 05:58:38 +0000[diff] [blame]247 InstrItinData<IIC_LdStLoad, [InstrStage<1, [P440_DISS1, P440_DISS2]>,
Hal Finkel92720ab2013-11-28 06:05:59 +0000[diff] [blame]248 InstrStage<1, [P440_LRACC]>,
249 InstrStage<1, [P440_AGEN]>,
250 InstrStage<1, [P440_CRD]>,
251 InstrStage<2, [P440_LWB]>],
Hal Finkel4035e8d2013-11-29 06:19:43 +0000[diff] [blame]252 [5, 1, 1],
Hal Finkel92720ab2013-11-28 06:05:59 +0000[diff] [blame]253 [P440_GPR_Bypass, P440_GPR_Bypass]>,
Hal Finkeldd063692013-11-29 05:58:38 +0000[diff] [blame]254 InstrItinData<IIC_LdStLoadUpd,[InstrStage<1, [P440_DISS1, P440_DISS2]>,
Hal Finkel92720ab2013-11-28 06:05:59 +0000[diff] [blame]255 InstrStage<1, [P440_LRACC]>,
256 InstrStage<1, [P440_AGEN]>,
257 InstrStage<1, [P440_CRD]>,
258 InstrStage<2, [P440_LWB]>],
Hal Finkel4035e8d2013-11-29 06:19:43 +0000[diff] [blame]259 [5, 2, 1, 1],
Hal Finkel92720ab2013-11-28 06:05:59 +0000[diff] [blame]260 [P440_GPR_Bypass, P440_GPR_Bypass]>,
Hal Finkel46402a42013-11-30 20:41:13 +0000[diff] [blame^]261 InstrItinData<IIC_LdStLoadUpdX,[InstrStage<1, [P440_DISS1, P440_DISS2]>,
262 InstrStage<1, [P440_LRACC]>,
263 InstrStage<1, [P440_AGEN]>,
264 InstrStage<1, [P440_CRD]>,
265 InstrStage<2, [P440_LWB]>],
266 [5, 2, 1, 1],
267 [P440_GPR_Bypass, P440_GPR_Bypass]>,
Hal Finkeldd063692013-11-29 05:58:38 +0000[diff] [blame]268 InstrItinData<IIC_LdStStore, [InstrStage<1, [P440_DISS1, P440_DISS2]>,
Hal Finkel92720ab2013-11-28 06:05:59 +0000[diff] [blame]269 InstrStage<1, [P440_LRACC]>,
270 InstrStage<1, [P440_AGEN]>,
271 InstrStage<1, [P440_CRD]>,
272 InstrStage<2, [P440_LWB]>],
Hal Finkel4035e8d2013-11-29 06:19:43 +0000[diff] [blame]273 [1, 1, 1],
Hal Finkel92720ab2013-11-28 06:05:59 +0000[diff] [blame]274 [NoBypass, P440_GPR_Bypass]>,
Hal Finkeldd063692013-11-29 05:58:38 +0000[diff] [blame]275 InstrItinData<IIC_LdStStoreUpd,[InstrStage<1, [P440_DISS1, P440_DISS2]>,
Hal Finkel92720ab2013-11-28 06:05:59 +0000[diff] [blame]276 InstrStage<1, [P440_LRACC]>,
277 InstrStage<1, [P440_AGEN]>,
278 InstrStage<1, [P440_CRD]>,
279 InstrStage<2, [P440_LWB]>],
Hal Finkel4035e8d2013-11-29 06:19:43 +0000[diff] [blame]280 [2, 1, 1, 1],
Hal Finkel92720ab2013-11-28 06:05:59 +0000[diff] [blame]281 [NoBypass, P440_GPR_Bypass]>,
Hal Finkeldd063692013-11-29 05:58:38 +0000[diff] [blame]282 InstrItinData<IIC_LdStICBI, [InstrStage<1, [P440_DISS1, P440_DISS2]>,
Hal Finkel92720ab2013-11-28 06:05:59 +0000[diff] [blame]283 InstrStage<1, [P440_LRACC]>,
284 InstrStage<1, [P440_AGEN]>,
285 InstrStage<1, [P440_CRD]>,
286 InstrStage<1, [P440_LWB]>],
Hal Finkel4035e8d2013-11-29 06:19:43 +0000[diff] [blame]287 [4, 1, 1],
Hal Finkel92720ab2013-11-28 06:05:59 +0000[diff] [blame]288 [NoBypass, P440_GPR_Bypass]>,
Hal Finkeldd063692013-11-29 05:58:38 +0000[diff] [blame]289 InstrItinData<IIC_LdStSTFD, [InstrStage<1, [P440_DISS1, P440_DISS2]>,
Hal Finkel92720ab2013-11-28 06:05:59 +0000[diff] [blame]290 InstrStage<1, [P440_LRACC]>,
291 InstrStage<1, [P440_AGEN]>,
292 InstrStage<1, [P440_CRD]>,
293 InstrStage<1, [P440_LWB]>],
Hal Finkel4035e8d2013-11-29 06:19:43 +0000[diff] [blame]294 [1, 1, 1],
Hal Finkel92720ab2013-11-28 06:05:59 +0000[diff] [blame]295 [NoBypass, P440_GPR_Bypass, P440_GPR_Bypass]>,
Hal Finkeldd063692013-11-29 05:58:38 +0000[diff] [blame]296 InstrItinData<IIC_LdStSTFDU, [InstrStage<1, [P440_DISS1, P440_DISS2]>,
Hal Finkel92720ab2013-11-28 06:05:59 +0000[diff] [blame]297 InstrStage<1, [P440_LRACC]>,
298 InstrStage<1, [P440_AGEN]>,
299 InstrStage<1, [P440_CRD]>,
300 InstrStage<1, [P440_LWB]>],
Hal Finkel4035e8d2013-11-29 06:19:43 +0000[diff] [blame]301 [2, 1, 1, 1],
Hal Finkel92720ab2013-11-28 06:05:59 +0000[diff] [blame]302 [NoBypass, P440_GPR_Bypass, P440_GPR_Bypass]>,
Hal Finkeldd063692013-11-29 05:58:38 +0000[diff] [blame]303 InstrItinData<IIC_LdStLFD, [InstrStage<1, [P440_DISS1, P440_DISS2]>,
Hal Finkel92720ab2013-11-28 06:05:59 +0000[diff] [blame]304 InstrStage<1, [P440_LRACC]>,
305 InstrStage<1, [P440_AGEN]>,
306 InstrStage<1, [P440_CRD]>,
307 InstrStage<2, [P440_LWB]>],
Hal Finkela10bd1d2013-11-29 05:59:00 +0000[diff] [blame]308 [5, 1, 1],
Hal Finkel92720ab2013-11-28 06:05:59 +0000[diff] [blame]309 [NoBypass, P440_GPR_Bypass, P440_GPR_Bypass]>,
Hal Finkeldd063692013-11-29 05:58:38 +0000[diff] [blame]310 InstrItinData<IIC_LdStLFDU, [InstrStage<1, [P440_DISS1, P440_DISS2]>,
Hal Finkel92720ab2013-11-28 06:05:59 +0000[diff] [blame]311 InstrStage<1, [P440_LRACC]>,
312 InstrStage<1, [P440_AGEN]>,
313 InstrStage<1, [P440_CRD]>,
314 InstrStage<1, [P440_LWB]>],
Hal Finkel4035e8d2013-11-29 06:19:43 +0000[diff] [blame]315 [5, 2, 1, 1],
Hal Finkel92720ab2013-11-28 06:05:59 +0000[diff] [blame]316 [NoBypass, P440_GPR_Bypass, P440_GPR_Bypass]>,
Hal Finkel46402a42013-11-30 20:41:13 +0000[diff] [blame^]317 InstrItinData<IIC_LdStLFDUX, [InstrStage<1, [P440_DISS1, P440_DISS2]>,
318 InstrStage<1, [P440_LRACC]>,
319 InstrStage<1, [P440_AGEN]>,
320 InstrStage<1, [P440_CRD]>,
321 InstrStage<1, [P440_LWB]>],
322 [5, 2, 1, 1],
323 [NoBypass, P440_GPR_Bypass, P440_GPR_Bypass]>,
Hal Finkeldd063692013-11-29 05:58:38 +0000[diff] [blame]324 InstrItinData<IIC_LdStLHA, [InstrStage<1, [P440_DISS1, P440_DISS2]>,
Hal Finkel92720ab2013-11-28 06:05:59 +0000[diff] [blame]325 InstrStage<1, [P440_LRACC]>,
326 InstrStage<1, [P440_AGEN]>,
327 InstrStage<1, [P440_CRD]>,
328 InstrStage<1, [P440_LWB]>],
Hal Finkel4035e8d2013-11-29 06:19:43 +0000[diff] [blame]329 [4, 1, 1],
Hal Finkel92720ab2013-11-28 06:05:59 +0000[diff] [blame]330 [NoBypass, P440_GPR_Bypass]>,
Hal Finkeldd063692013-11-29 05:58:38 +0000[diff] [blame]331 InstrItinData<IIC_LdStLHAU, [InstrStage<1, [P440_DISS1, P440_DISS2]>,
Hal Finkel92720ab2013-11-28 06:05:59 +0000[diff] [blame]332 InstrStage<1, [P440_LRACC]>,
333 InstrStage<1, [P440_AGEN]>,
334 InstrStage<1, [P440_CRD]>,
335 InstrStage<1, [P440_LWB]>],
Hal Finkel4035e8d2013-11-29 06:19:43 +0000[diff] [blame]336 [4, 1, 1],
Hal Finkel92720ab2013-11-28 06:05:59 +0000[diff] [blame]337 [NoBypass, P440_GPR_Bypass]>,
Hal Finkel46402a42013-11-30 20:41:13 +0000[diff] [blame^]338 InstrItinData<IIC_LdStLHAUX, [InstrStage<1, [P440_DISS1, P440_DISS2]>,
339 InstrStage<1, [P440_LRACC]>,
340 InstrStage<1, [P440_AGEN]>,
341 InstrStage<1, [P440_CRD]>,
342 InstrStage<1, [P440_LWB]>],
343 [4, 1, 1],
344 [NoBypass, P440_GPR_Bypass]>,
Hal Finkeldd063692013-11-29 05:58:38 +0000[diff] [blame]345 InstrItinData<IIC_LdStLMW, [InstrStage<1, [P440_DISS1, P440_DISS2]>,
Hal Finkel92720ab2013-11-28 06:05:59 +0000[diff] [blame]346 InstrStage<1, [P440_LRACC]>,
347 InstrStage<1, [P440_AGEN]>,
348 InstrStage<1, [P440_CRD]>,
349 InstrStage<1, [P440_LWB]>],
Hal Finkel4035e8d2013-11-29 06:19:43 +0000[diff] [blame]350 [4, 1, 1],
Hal Finkel92720ab2013-11-28 06:05:59 +0000[diff] [blame]351 [NoBypass, P440_GPR_Bypass]>,
Hal Finkeldd063692013-11-29 05:58:38 +0000[diff] [blame]352 InstrItinData<IIC_LdStLWARX, [InstrStage<1, [P440_DISS1]>,
Hal Finkel92720ab2013-11-28 06:05:59 +0000[diff] [blame]353 InstrStage<1, [P440_IRACC], 0>,
354 InstrStage<4, [P440_LWARX_Hold], 0>,
355 InstrStage<1, [P440_LRACC]>,
356 InstrStage<1, [P440_AGEN]>,
357 InstrStage<1, [P440_CRD]>,
358 InstrStage<1, [P440_LWB]>],
Hal Finkel4035e8d2013-11-29 06:19:43 +0000[diff] [blame]359 [4, 1, 1],
Hal Finkel92720ab2013-11-28 06:05:59 +0000[diff] [blame]360 [NoBypass, P440_GPR_Bypass]>,
Hal Finkeldd063692013-11-29 05:58:38 +0000[diff] [blame]361 InstrItinData<IIC_LdStSTD, [InstrStage<1, [P440_DISS1, P440_DISS2]>,
Hal Finkel92720ab2013-11-28 06:05:59 +0000[diff] [blame]362 InstrStage<1, [P440_LRACC]>,
363 InstrStage<1, [P440_AGEN]>,
364 InstrStage<1, [P440_CRD]>,
365 InstrStage<2, [P440_LWB]>],
Hal Finkel4035e8d2013-11-29 06:19:43 +0000[diff] [blame]366 [4, 1, 1],
Hal Finkel92720ab2013-11-28 06:05:59 +0000[diff] [blame]367 [NoBypass, P440_GPR_Bypass]>,
Hal Finkeldd063692013-11-29 05:58:38 +0000[diff] [blame]368 InstrItinData<IIC_LdStSTDU, [InstrStage<1, [P440_DISS1, P440_DISS2]>,
Hal Finkel92720ab2013-11-28 06:05:59 +0000[diff] [blame]369 InstrStage<1, [P440_LRACC]>,
370 InstrStage<1, [P440_AGEN]>,
371 InstrStage<1, [P440_CRD]>,
372 InstrStage<2, [P440_LWB]>],
Hal Finkel4035e8d2013-11-29 06:19:43 +0000[diff] [blame]373 [2, 1, 1, 1],
Hal Finkel92720ab2013-11-28 06:05:59 +0000[diff] [blame]374 [NoBypass, P440_GPR_Bypass]>,
Hal Finkel46402a42013-11-30 20:41:13 +0000[diff] [blame^]375 InstrItinData<IIC_LdStSTDUX, [InstrStage<1, [P440_DISS1, P440_DISS2]>,
376 InstrStage<1, [P440_LRACC]>,
377 InstrStage<1, [P440_AGEN]>,
378 InstrStage<1, [P440_CRD]>,
379 InstrStage<2, [P440_LWB]>],
380 [2, 1, 1, 1],
381 [NoBypass, P440_GPR_Bypass]>,
Hal Finkeldd063692013-11-29 05:58:38 +0000[diff] [blame]382 InstrItinData<IIC_LdStSTDCX, [InstrStage<1, [P440_DISS1]>,
Hal Finkel92720ab2013-11-28 06:05:59 +0000[diff] [blame]383 InstrStage<1, [P440_IRACC], 0>,
384 InstrStage<4, [P440_LWARX_Hold], 0>,
385 InstrStage<1, [P440_LRACC]>,
386 InstrStage<1, [P440_AGEN]>,
387 InstrStage<1, [P440_CRD]>,
388 InstrStage<1, [P440_LWB]>],
Hal Finkel4035e8d2013-11-29 06:19:43 +0000[diff] [blame]389 [4, 1, 1],
Hal Finkel92720ab2013-11-28 06:05:59 +0000[diff] [blame]390 [NoBypass, P440_GPR_Bypass]>,
Hal Finkeldd063692013-11-29 05:58:38 +0000[diff] [blame]391 InstrItinData<IIC_LdStSTWCX, [InstrStage<1, [P440_DISS1]>,
Hal Finkel92720ab2013-11-28 06:05:59 +0000[diff] [blame]392 InstrStage<1, [P440_IRACC], 0>,
393 InstrStage<4, [P440_LWARX_Hold], 0>,
394 InstrStage<1, [P440_LRACC]>,
395 InstrStage<1, [P440_AGEN]>,
396 InstrStage<1, [P440_CRD]>,
397 InstrStage<1, [P440_LWB]>],
Hal Finkel4035e8d2013-11-29 06:19:43 +0000[diff] [blame]398 [4, 1, 1],
Hal Finkel92720ab2013-11-28 06:05:59 +0000[diff] [blame]399 [NoBypass, P440_GPR_Bypass]>,
Hal Finkeldd063692013-11-29 05:58:38 +0000[diff] [blame]400 InstrItinData<IIC_LdStSync, [InstrStage<1, [P440_DISS1, P440_DISS2]>,
Hal Finkel92720ab2013-11-28 06:05:59 +0000[diff] [blame]401 InstrStage<1, [P440_LRACC]>,
402 InstrStage<3, [P440_AGEN], 1>,
403 InstrStage<2, [P440_CRD], 1>,
404 InstrStage<1, [P440_LWB]>]>,
Hal Finkeldd063692013-11-29 05:58:38 +0000[diff] [blame]405 InstrItinData<IIC_SprISYNC, [InstrStage<1, [P440_DISS1, P440_DISS2]>,
Hal Finkel92720ab2013-11-28 06:05:59 +0000[diff] [blame]406 InstrStage<1, [P440_FRACC], 0>,
407 InstrStage<1, [P440_LRACC], 0>,
408 InstrStage<1, [P440_IRACC]>,
409 InstrStage<1, [P440_FEXE1], 0>,
410 InstrStage<1, [P440_AGEN], 0>,
411 InstrStage<1, [P440_JEXE1], 0>,
412 InstrStage<1, [P440_IEXE1]>,
413 InstrStage<1, [P440_FEXE2], 0>,
414 InstrStage<1, [P440_CRD], 0>,
415 InstrStage<1, [P440_JEXE2], 0>,
416 InstrStage<1, [P440_IEXE2]>,
417 InstrStage<6, [P440_FEXE3], 0>,
418 InstrStage<6, [P440_LWB], 0>,
419 InstrStage<6, [P440_JWB], 0>,
420 InstrStage<6, [P440_IWB]>]>,
Hal Finkeldd063692013-11-29 05:58:38 +0000[diff] [blame]421 InstrItinData<IIC_SprMFSR, [InstrStage<1, [P440_DISS1, P440_DISS2]>,
Hal Finkel92720ab2013-11-28 06:05:59 +0000[diff] [blame]422 InstrStage<1, [P440_IRACC]>,
423 InstrStage<1, [P440_IEXE1]>,
424 InstrStage<1, [P440_IEXE2]>,
425 InstrStage<1, [P440_IWB]>],
Hal Finkela10bd1d2013-11-29 05:59:00 +0000[diff] [blame]426 [2, 0],
Hal Finkel92720ab2013-11-28 06:05:59 +0000[diff] [blame]427 [P440_GPR_Bypass, P440_GPR_Bypass]>,
Hal Finkeldd063692013-11-29 05:58:38 +0000[diff] [blame]428 InstrItinData<IIC_SprMTMSR, [InstrStage<1, [P440_DISS1, P440_DISS2]>,
Hal Finkel92720ab2013-11-28 06:05:59 +0000[diff] [blame]429 InstrStage<1, [P440_IRACC]>,
430 InstrStage<1, [P440_IEXE1]>,
431 InstrStage<1, [P440_IEXE2]>,
432 InstrStage<1, [P440_IWB]>],
Hal Finkela10bd1d2013-11-29 05:59:00 +0000[diff] [blame]433 [2, 0],
Hal Finkel92720ab2013-11-28 06:05:59 +0000[diff] [blame]434 [P440_GPR_Bypass, P440_GPR_Bypass]>,
Hal Finkeldd063692013-11-29 05:58:38 +0000[diff] [blame]435 InstrItinData<IIC_SprMTSR, [InstrStage<1, [P440_DISS1, P440_DISS2]>,
Hal Finkel92720ab2013-11-28 06:05:59 +0000[diff] [blame]436 InstrStage<1, [P440_IRACC]>,
437 InstrStage<1, [P440_IEXE1]>,
438 InstrStage<1, [P440_IEXE2]>,
439 InstrStage<3, [P440_IWB]>],
Hal Finkela10bd1d2013-11-29 05:59:00 +0000[diff] [blame]440 [5, 0],
Hal Finkel92720ab2013-11-28 06:05:59 +0000[diff] [blame]441 [NoBypass, P440_GPR_Bypass]>,
Hal Finkeldd063692013-11-29 05:58:38 +0000[diff] [blame]442 InstrItinData<IIC_SprTLBSYNC, [InstrStage<1, [P440_DISS1, P440_DISS2]>,
Hal Finkel92720ab2013-11-28 06:05:59 +0000[diff] [blame]443 InstrStage<1, [P440_IRACC]>,
444 InstrStage<1, [P440_IEXE1]>,
445 InstrStage<1, [P440_IEXE2]>,
446 InstrStage<1, [P440_IWB]>]>,
Hal Finkeldd063692013-11-29 05:58:38 +0000[diff] [blame]447 InstrItinData<IIC_SprMFCR, [InstrStage<1, [P440_DISS1, P440_DISS2]>,
Hal Finkel92720ab2013-11-28 06:05:59 +0000[diff] [blame]448 InstrStage<1, [P440_IRACC]>,
449 InstrStage<1, [P440_IEXE1]>,
450 InstrStage<1, [P440_IEXE2]>,
451 InstrStage<1, [P440_IWB]>],
Hal Finkela10bd1d2013-11-29 05:59:00 +0000[diff] [blame]452 [4, 0],
Hal Finkel92720ab2013-11-28 06:05:59 +0000[diff] [blame]453 [NoBypass, P440_GPR_Bypass]>,
Hal Finkeldd063692013-11-29 05:58:38 +0000[diff] [blame]454 InstrItinData<IIC_SprMFMSR, [InstrStage<1, [P440_DISS1, P440_DISS2]>,
Hal Finkel92720ab2013-11-28 06:05:59 +0000[diff] [blame]455 InstrStage<1, [P440_IRACC]>,
456 InstrStage<1, [P440_IEXE1]>,
457 InstrStage<1, [P440_IEXE2]>,
458 InstrStage<1, [P440_IWB]>],
Hal Finkela10bd1d2013-11-29 05:59:00 +0000[diff] [blame]459 [3, 0],
Hal Finkel92720ab2013-11-28 06:05:59 +0000[diff] [blame]460 [P440_GPR_Bypass, P440_GPR_Bypass]>,
Hal Finkeldd063692013-11-29 05:58:38 +0000[diff] [blame]461 InstrItinData<IIC_SprMFSPR, [InstrStage<1, [P440_DISS1, P440_DISS2]>,
Hal Finkel92720ab2013-11-28 06:05:59 +0000[diff] [blame]462 InstrStage<1, [P440_IRACC]>,
463 InstrStage<1, [P440_IEXE1]>,
464 InstrStage<1, [P440_IEXE2]>,
465 InstrStage<3, [P440_IWB]>],
Hal Finkela10bd1d2013-11-29 05:59:00 +0000[diff] [blame]466 [6, 0],
Hal Finkel92720ab2013-11-28 06:05:59 +0000[diff] [blame]467 [NoBypass, P440_GPR_Bypass]>,
Hal Finkeldd063692013-11-29 05:58:38 +0000[diff] [blame]468 InstrItinData<IIC_SprMFTB, [InstrStage<1, [P440_DISS1, P440_DISS2]>,
Hal Finkel92720ab2013-11-28 06:05:59 +0000[diff] [blame]469 InstrStage<1, [P440_IRACC]>,
470 InstrStage<1, [P440_IEXE1]>,
471 InstrStage<1, [P440_IEXE2]>,
472 InstrStage<3, [P440_IWB]>],
Hal Finkela10bd1d2013-11-29 05:59:00 +0000[diff] [blame]473 [6, 0],
Hal Finkel92720ab2013-11-28 06:05:59 +0000[diff] [blame]474 [NoBypass, P440_GPR_Bypass]>,
Hal Finkeldd063692013-11-29 05:58:38 +0000[diff] [blame]475 InstrItinData<IIC_SprMTSPR, [InstrStage<1, [P440_DISS1, P440_DISS2]>,
Hal Finkel92720ab2013-11-28 06:05:59 +0000[diff] [blame]476 InstrStage<1, [P440_IRACC]>,
477 InstrStage<1, [P440_IEXE1]>,
478 InstrStage<1, [P440_IEXE2]>,
479 InstrStage<3, [P440_IWB]>],
Hal Finkela10bd1d2013-11-29 05:59:00 +0000[diff] [blame]480 [6, 0],
Hal Finkel92720ab2013-11-28 06:05:59 +0000[diff] [blame]481 [NoBypass, P440_GPR_Bypass]>,
Hal Finkeldd063692013-11-29 05:58:38 +0000[diff] [blame]482 InstrItinData<IIC_SprMTSRIN, [InstrStage<1, [P440_DISS1, P440_DISS2]>,
Hal Finkel92720ab2013-11-28 06:05:59 +0000[diff] [blame]483 InstrStage<1, [P440_IRACC]>,
484 InstrStage<1, [P440_IEXE1]>,
485 InstrStage<1, [P440_IEXE2]>,
486 InstrStage<3, [P440_IWB]>],
Hal Finkela10bd1d2013-11-29 05:59:00 +0000[diff] [blame]487 [6, 0],
Hal Finkel92720ab2013-11-28 06:05:59 +0000[diff] [blame]488 [NoBypass, P440_GPR_Bypass]>,
Hal Finkeldd063692013-11-29 05:58:38 +0000[diff] [blame]489 InstrItinData<IIC_SprRFI, [InstrStage<1, [P440_DISS1, P440_DISS2]>,
Hal Finkel92720ab2013-11-28 06:05:59 +0000[diff] [blame]490 InstrStage<1, [P440_IRACC]>,
491 InstrStage<1, [P440_IEXE1]>,
492 InstrStage<1, [P440_IEXE2]>,
493 InstrStage<1, [P440_IWB]>],
Hal Finkela10bd1d2013-11-29 05:59:00 +0000[diff] [blame]494 [4, 0],
Hal Finkel92720ab2013-11-28 06:05:59 +0000[diff] [blame]495 [NoBypass, P440_GPR_Bypass]>,
Hal Finkeldd063692013-11-29 05:58:38 +0000[diff] [blame]496 InstrItinData<IIC_SprSC, [InstrStage<1, [P440_DISS1, P440_DISS2]>,
Hal Finkel92720ab2013-11-28 06:05:59 +0000[diff] [blame]497 InstrStage<1, [P440_IRACC]>,
498 InstrStage<1, [P440_IEXE1]>,
499 InstrStage<1, [P440_IEXE2]>,
500 InstrStage<1, [P440_IWB]>],
Hal Finkela10bd1d2013-11-29 05:59:00 +0000[diff] [blame]501 [4, 0],
Hal Finkel92720ab2013-11-28 06:05:59 +0000[diff] [blame]502 [NoBypass, P440_GPR_Bypass]>,
Hal Finkeldd063692013-11-29 05:58:38 +0000[diff] [blame]503 InstrItinData<IIC_FPGeneral, [InstrStage<1, [P440_DISS1, P440_DISS2]>,
Hal Finkel92720ab2013-11-28 06:05:59 +0000[diff] [blame]504 InstrStage<1, [P440_FRACC]>,
505 InstrStage<1, [P440_FEXE1]>,
506 InstrStage<1, [P440_FEXE2]>,
507 InstrStage<1, [P440_FEXE3]>,
508 InstrStage<1, [P440_FEXE4]>,
509 InstrStage<1, [P440_FEXE5]>,
510 InstrStage<1, [P440_FEXE6]>,
511 InstrStage<1, [P440_FWB]>],
Hal Finkela10bd1d2013-11-29 05:59:00 +0000[diff] [blame]512 [6, 0, 0],
Hal Finkel92720ab2013-11-28 06:05:59 +0000[diff] [blame]513 [P440_FPR_Bypass,
514 P440_FPR_Bypass, P440_FPR_Bypass]>,
Hal Finkeldd063692013-11-29 05:58:38 +0000[diff] [blame]515 InstrItinData<IIC_FPAddSub, [InstrStage<1, [P440_DISS1, P440_DISS2]>,
Hal Finkel92720ab2013-11-28 06:05:59 +0000[diff] [blame]516 InstrStage<1, [P440_FRACC]>,
517 InstrStage<1, [P440_FEXE1]>,
518 InstrStage<1, [P440_FEXE2]>,
519 InstrStage<1, [P440_FEXE3]>,
520 InstrStage<1, [P440_FEXE4]>,
521 InstrStage<1, [P440_FEXE5]>,
522 InstrStage<1, [P440_FEXE6]>,
523 InstrStage<1, [P440_FWB]>],
Hal Finkela10bd1d2013-11-29 05:59:00 +0000[diff] [blame]524 [6, 0, 0],
Hal Finkel92720ab2013-11-28 06:05:59 +0000[diff] [blame]525 [P440_FPR_Bypass,
526 P440_FPR_Bypass, P440_FPR_Bypass]>,
Hal Finkeldd063692013-11-29 05:58:38 +0000[diff] [blame]527 InstrItinData<IIC_FPCompare, [InstrStage<1, [P440_DISS1, P440_DISS2]>,
Hal Finkel92720ab2013-11-28 06:05:59 +0000[diff] [blame]528 InstrStage<1, [P440_FRACC]>,
529 InstrStage<1, [P440_FEXE1]>,
530 InstrStage<1, [P440_FEXE2]>,
531 InstrStage<1, [P440_FEXE3]>,
532 InstrStage<1, [P440_FEXE4]>,
533 InstrStage<1, [P440_FEXE5]>,
534 InstrStage<1, [P440_FEXE6]>,
535 InstrStage<1, [P440_FWB]>],
Hal Finkela10bd1d2013-11-29 05:59:00 +0000[diff] [blame]536 [6, 0, 0],
Hal Finkel92720ab2013-11-28 06:05:59 +0000[diff] [blame]537 [P440_FPR_Bypass, P440_FPR_Bypass,
538 P440_FPR_Bypass]>,
Hal Finkeldd063692013-11-29 05:58:38 +0000[diff] [blame]539 InstrItinData<IIC_FPDivD, [InstrStage<1, [P440_DISS1, P440_DISS2]>,
Hal Finkel92720ab2013-11-28 06:05:59 +0000[diff] [blame]540 InstrStage<1, [P440_FRACC]>,
541 InstrStage<1, [P440_FEXE1]>,
542 InstrStage<1, [P440_FEXE2]>,
543 InstrStage<1, [P440_FEXE3]>,
544 InstrStage<1, [P440_FEXE4]>,
545 InstrStage<1, [P440_FEXE5]>,
546 InstrStage<1, [P440_FEXE6]>,
547 InstrStage<25, [P440_FWB]>],
Hal Finkela10bd1d2013-11-29 05:59:00 +0000[diff] [blame]548 [31, 0, 0],
Hal Finkel92720ab2013-11-28 06:05:59 +0000[diff] [blame]549 [NoBypass, P440_FPR_Bypass, P440_FPR_Bypass]>,
Hal Finkeldd063692013-11-29 05:58:38 +0000[diff] [blame]550 InstrItinData<IIC_FPDivS, [InstrStage<1, [P440_DISS1, P440_DISS2]>,
Hal Finkel92720ab2013-11-28 06:05:59 +0000[diff] [blame]551 InstrStage<1, [P440_FRACC]>,
552 InstrStage<1, [P440_FEXE1]>,
553 InstrStage<1, [P440_FEXE2]>,
554 InstrStage<1, [P440_FEXE3]>,
555 InstrStage<1, [P440_FEXE4]>,
556 InstrStage<1, [P440_FEXE5]>,
557 InstrStage<1, [P440_FEXE6]>,
558 InstrStage<13, [P440_FWB]>],
Hal Finkela10bd1d2013-11-29 05:59:00 +0000[diff] [blame]559 [19, 0, 0],
Hal Finkel92720ab2013-11-28 06:05:59 +0000[diff] [blame]560 [NoBypass, P440_FPR_Bypass, P440_FPR_Bypass]>,
Hal Finkeldd063692013-11-29 05:58:38 +0000[diff] [blame]561 InstrItinData<IIC_FPFused, [InstrStage<1, [P440_DISS1, P440_DISS2]>,
Hal Finkel92720ab2013-11-28 06:05:59 +0000[diff] [blame]562 InstrStage<1, [P440_FRACC]>,
563 InstrStage<1, [P440_FEXE1]>,
564 InstrStage<1, [P440_FEXE2]>,
565 InstrStage<1, [P440_FEXE3]>,
566 InstrStage<1, [P440_FEXE4]>,
567 InstrStage<1, [P440_FEXE5]>,
568 InstrStage<1, [P440_FEXE6]>,
569 InstrStage<1, [P440_FWB]>],
Hal Finkela10bd1d2013-11-29 05:59:00 +0000[diff] [blame]570 [6, 0, 0, 0],
Hal Finkel92720ab2013-11-28 06:05:59 +0000[diff] [blame]571 [P440_FPR_Bypass,
572 P440_FPR_Bypass, P440_FPR_Bypass,
573 P440_FPR_Bypass]>,
Hal Finkeldd063692013-11-29 05:58:38 +0000[diff] [blame]574 InstrItinData<IIC_FPRes, [InstrStage<1, [P440_DISS1, P440_DISS2]>,
Hal Finkel92720ab2013-11-28 06:05:59 +0000[diff] [blame]575 InstrStage<1, [P440_FRACC]>,
576 InstrStage<1, [P440_FEXE1]>,
577 InstrStage<1, [P440_FEXE2]>,
578 InstrStage<1, [P440_FEXE3]>,
579 InstrStage<1, [P440_FEXE4]>,
580 InstrStage<1, [P440_FEXE5]>,
581 InstrStage<1, [P440_FEXE6]>,
582 InstrStage<1, [P440_FWB]>],
Hal Finkela10bd1d2013-11-29 05:59:00 +0000[diff] [blame]583 [6, 0],
Hal Finkel92720ab2013-11-28 06:05:59 +0000[diff] [blame]584 [P440_FPR_Bypass, P440_FPR_Bypass]>
Hal Finkelad677b62011-10-17 04:03:55 +0000[diff] [blame]585]>;
Hal Finkel5a7162f2013-11-29 06:32:17 +0000[diff] [blame]586
587// ===---------------------------------------------------------------------===//
588// PPC440 machine model for scheduling and other instruction cost heuristics.
589
590def PPC440Model : SchedMachineModel {
591 let IssueWidth = 2; // 2 instructions are dispatched per cycle.
592 let MinLatency = -1; // OperandCycles are interpreted as MinLatency.
593 let LoadLatency = 5; // Optimistic load latency assuming bypass.
594 // This is overriden by OperandCycles if the
595 // Itineraries are queried instead.
596
597 let Itineraries = PPC440Itineraries;
598}
599