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Clement Courbet44b4c542018-06-19 11:28:59 +00001//===-- Target.h ------------------------------------------------*- C++ -*-===//
2//
Chandler Carruth2946cd72019-01-19 08:50:56 +00003// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
Clement Courbet44b4c542018-06-19 11:28:59 +00006//
7//===----------------------------------------------------------------------===//
8///
9/// \file
10///
11/// Classes that handle the creation of target-specific objects. This is
Clement Courbet50cdd562019-10-09 11:58:42 +000012/// similar to Target/TargetRegistry.
Clement Courbet44b4c542018-06-19 11:28:59 +000013///
14//===----------------------------------------------------------------------===//
15
16#ifndef LLVM_TOOLS_LLVM_EXEGESIS_TARGET_H
17#define LLVM_TOOLS_LLVM_EXEGESIS_TARGET_H
18
Clement Courbet4860b982018-06-26 08:49:30 +000019#include "BenchmarkResult.h"
20#include "BenchmarkRunner.h"
Clement Courbet04fd2042020-01-22 15:49:10 +010021#include "Error.h"
Clement Courbet4860b982018-06-26 08:49:30 +000022#include "LlvmState.h"
Clement Courbetd939f6d2018-09-13 07:40:53 +000023#include "SnippetGenerator.h"
Clement Courbet44b4c542018-06-19 11:28:59 +000024#include "llvm/ADT/Triple.h"
Clement Courbet6fd00e32018-06-20 11:54:35 +000025#include "llvm/CodeGen/TargetPassConfig.h"
Guillaume Chateletfb943542018-08-01 14:41:45 +000026#include "llvm/IR/CallingConv.h"
Clement Courbet6fd00e32018-06-20 11:54:35 +000027#include "llvm/IR/LegacyPassManager.h"
Clement Courbeta51efc22018-06-25 13:12:02 +000028#include "llvm/MC/MCInst.h"
29#include "llvm/MC/MCRegisterInfo.h"
Clement Courbet44b4c542018-06-19 11:28:59 +000030
Fangrui Song32401af2018-10-22 17:10:47 +000031namespace llvm {
Clement Courbet44b4c542018-06-19 11:28:59 +000032namespace exegesis {
33
Clement Courbet41c8af32018-10-25 07:44:01 +000034struct PfmCountersInfo {
35 // An optional name of a performance counter that can be used to measure
36 // cycles.
Simon Pilgrim2a9c7282018-10-25 10:45:38 +000037 const char *CycleCounter;
Clement Courbet41c8af32018-10-25 07:44:01 +000038
39 // An optional name of a performance counter that can be used to measure
40 // uops.
Simon Pilgrim2a9c7282018-10-25 10:45:38 +000041 const char *UopsCounter;
Clement Courbet41c8af32018-10-25 07:44:01 +000042
43 // An IssueCounter specifies how to measure uops issued to specific proc
44 // resources.
45 struct IssueCounter {
Simon Pilgrim2a9c7282018-10-25 10:45:38 +000046 const char *Counter;
Clement Courbet41c8af32018-10-25 07:44:01 +000047 // The name of the ProcResource that this counter measures.
Simon Pilgrim2a9c7282018-10-25 10:45:38 +000048 const char *ProcResName;
Clement Courbet41c8af32018-10-25 07:44:01 +000049 };
50 // An optional list of IssueCounters.
Simon Pilgrim2a9c7282018-10-25 10:45:38 +000051 const IssueCounter *IssueCounters;
52 unsigned NumIssueCounters;
Clement Courbet41c8af32018-10-25 07:44:01 +000053
54 static const PfmCountersInfo Default;
55};
56
57struct CpuAndPfmCounters {
Simon Pilgrim2a9c7282018-10-25 10:45:38 +000058 const char *CpuName;
59 const PfmCountersInfo *PCI;
Clement Courbet50cdd562019-10-09 11:58:42 +000060 bool operator<(StringRef S) const { return StringRef(CpuName) < S; }
Clement Courbet41c8af32018-10-25 07:44:01 +000061};
62
Clement Courbet44b4c542018-06-19 11:28:59 +000063class ExegesisTarget {
64public:
Clement Courbet50cdd562019-10-09 11:58:42 +000065 explicit ExegesisTarget(ArrayRef<CpuAndPfmCounters> CpuPfmCounters)
Clement Courbet41c8af32018-10-25 07:44:01 +000066 : CpuPfmCounters(CpuPfmCounters) {}
67
Clement Courbet6fd00e32018-06-20 11:54:35 +000068 // Targets can use this to add target-specific passes in assembleToStream();
Clement Courbet50cdd562019-10-09 11:58:42 +000069 virtual void addTargetSpecificPasses(PassManagerBase &PM) const {}
Clement Courbet6fd00e32018-06-20 11:54:35 +000070
Clement Courbeta51efc22018-06-25 13:12:02 +000071 // Generates code to move a constant into a the given register.
Guillaume Chateletc96a97b2018-09-20 12:22:18 +000072 // Precondition: Value must fit into Reg.
Clement Courbet50cdd562019-10-09 11:58:42 +000073 virtual std::vector<MCInst> setRegTo(const MCSubtargetInfo &STI, unsigned Reg,
74 const APInt &Value) const = 0;
Guillaume Chatelet5ad29092018-09-18 11:26:27 +000075
76 // Returns the register pointing to scratch memory, or 0 if this target
77 // does not support memory operands. The benchmark function uses the
78 // default calling convention.
Clement Courbet50cdd562019-10-09 11:58:42 +000079 virtual unsigned getScratchMemoryRegister(const Triple &) const { return 0; }
Guillaume Chateletfb943542018-08-01 14:41:45 +000080
81 // Fills memory operands with references to the address at [Reg] + Offset.
Guillaume Chatelet70ac0192018-09-27 09:23:04 +000082 virtual void fillMemoryOperands(InstructionTemplate &IT, unsigned Reg,
Guillaume Chateletc96a97b2018-09-20 12:22:18 +000083 unsigned Offset) const {
Guillaume Chateletc96a97b2018-09-20 12:22:18 +000084 llvm_unreachable(
85 "fillMemoryOperands() requires getScratchMemoryRegister() > 0");
86 }
Guillaume Chateletfb943542018-08-01 14:41:45 +000087
Clement Courbet9431b722019-09-27 12:56:24 +000088 // Returns a counter usable as a loop counter.
Clement Courbet50cdd562019-10-09 11:58:42 +000089 virtual unsigned getLoopCounterRegister(const Triple &) const { return 0; }
Clement Courbet9431b722019-09-27 12:56:24 +000090
91 // Adds the code to decrement the loop counter and
Clement Courbetc0292742019-10-03 07:56:56 +000092 virtual void decrementLoopCounterAndJump(MachineBasicBlock &MBB,
93 MachineBasicBlock &TargetMBB,
Clement Courbet50cdd562019-10-09 11:58:42 +000094 const MCInstrInfo &MII) const {
Clement Courbet9431b722019-09-27 12:56:24 +000095 llvm_unreachable("decrementLoopCounterAndBranch() requires "
96 "getLoopCounterRegister() > 0");
97 }
98
Clement Courbet52da9382019-03-26 15:44:57 +000099 // Returns a list of unavailable registers.
100 // Targets can use this to prevent some registers to be automatically selected
101 // for use in snippets.
102 virtual ArrayRef<unsigned> getUnavailableRegisters() const { return {}; }
103
Guillaume Chateletfb943542018-08-01 14:41:45 +0000104 // Returns the maximum number of bytes a load/store instruction can access at
105 // once. This is typically the size of the largest register available on the
106 // processor. Note that this only used as a hint to generate independant
107 // load/stores to/from memory, so the exact returned value does not really
108 // matter as long as it's large enough.
Guillaume Chateletc96a97b2018-09-20 12:22:18 +0000109 virtual unsigned getMaxMemoryAccessSize() const { return 0; }
Guillaume Chateletfb943542018-08-01 14:41:45 +0000110
Roman Lebedev404bdb12019-04-06 14:16:26 +0000111 // Assigns a random operand of the right type to variable Var.
Clement Courbet04fd2042020-01-22 15:49:10 +0100112 // The target is responsible for handling any operand starting from
113 // OPERAND_FIRST_TARGET.
114 virtual Error randomizeTargetMCOperand(const Instruction &Instr,
115 const Variable &Var,
116 MCOperand &AssignedValue,
117 const BitVector &ForbiddenRegs) const {
118 return make_error<Failure>(
119 "targets with target-specific operands should implement this");
120 }
Roman Lebedev404bdb12019-04-06 14:16:26 +0000121
Clement Courbet5be8b2e2020-01-22 09:33:50 +0100122 // Returns true if this instruction is supported as a back-to-back
123 // instructions.
124 // FIXME: Eventually we should discover this dynamically.
125 virtual bool allowAsBackToBack(const Instruction &Instr) const {
126 return true;
127 }
128
Roman Lebedev6030fe02020-02-12 20:54:39 +0300129 // For some instructions, it is interesting to measure how it's performance
130 // characteristics differ depending on it's operands.
131 // This allows us to produce all the interesting variants.
132 virtual std::vector<InstructionTemplate>
133 generateInstructionVariants(const Instruction &Instr,
134 unsigned MaxConfigsPerOpcode) const {
135 // By default, we're happy with whatever randomizer will give us.
136 return {&Instr};
137 }
138
Clement Courbetd939f6d2018-09-13 07:40:53 +0000139 // Creates a snippet generator for the given mode.
140 std::unique_ptr<SnippetGenerator>
141 createSnippetGenerator(InstructionBenchmark::ModeE Mode,
Clement Courbet2cd0f282019-10-08 14:30:24 +0000142 const LLVMState &State,
143 const SnippetGenerator::Options &Opts) const;
Clement Courbet4860b982018-06-26 08:49:30 +0000144 // Creates a benchmark runner for the given mode.
Miloš Stojanović4bd40f72020-02-06 18:21:01 +0100145 Expected<std::unique_ptr<BenchmarkRunner>>
Clement Courbet4860b982018-06-26 08:49:30 +0000146 createBenchmarkRunner(InstructionBenchmark::ModeE Mode,
147 const LLVMState &State) const;
148
Clement Courbet44b4c542018-06-19 11:28:59 +0000149 // Returns the ExegesisTarget for the given triple or nullptr if the target
150 // does not exist.
Clement Courbet50cdd562019-10-09 11:58:42 +0000151 static const ExegesisTarget *lookup(Triple TT);
Clement Courbet4860b982018-06-26 08:49:30 +0000152 // Returns the default (unspecialized) ExegesisTarget.
153 static const ExegesisTarget &getDefault();
Clement Courbet44b4c542018-06-19 11:28:59 +0000154 // Registers a target. Not thread safe.
155 static void registerTarget(ExegesisTarget *T);
156
Roman Lebedev3de96642018-06-19 11:58:10 +0000157 virtual ~ExegesisTarget();
Clement Courbet44b4c542018-06-19 11:28:59 +0000158
Clement Courbet41c8af32018-10-25 07:44:01 +0000159 // Returns the Pfm counters for the given CPU (or the default if no pfm
160 // counters are defined for this CPU).
Clement Courbet50cdd562019-10-09 11:58:42 +0000161 const PfmCountersInfo &getPfmCounters(StringRef CpuName) const;
Clement Courbet41c8af32018-10-25 07:44:01 +0000162
Clement Courbet44b4c542018-06-19 11:28:59 +0000163private:
Clement Courbet50cdd562019-10-09 11:58:42 +0000164 virtual bool matchesArch(Triple::ArchType Arch) const = 0;
Clement Courbet4860b982018-06-26 08:49:30 +0000165
Clement Courbetd939f6d2018-09-13 07:40:53 +0000166 // Targets can implement their own snippet generators/benchmarks runners by
Clement Courbet4860b982018-06-26 08:49:30 +0000167 // implementing these.
Miloš Stojanović24b7b992020-01-17 14:28:54 +0100168 std::unique_ptr<SnippetGenerator> virtual createSerialSnippetGenerator(
Clement Courbet2cd0f282019-10-08 14:30:24 +0000169 const LLVMState &State, const SnippetGenerator::Options &Opts) const;
Miloš Stojanović24b7b992020-01-17 14:28:54 +0100170 std::unique_ptr<SnippetGenerator> virtual createParallelSnippetGenerator(
Clement Courbet2cd0f282019-10-08 14:30:24 +0000171 const LLVMState &State, const SnippetGenerator::Options &Opts) const;
Clement Courbet4860b982018-06-26 08:49:30 +0000172 std::unique_ptr<BenchmarkRunner> virtual createLatencyBenchmarkRunner(
Clement Courbet362653f2019-01-30 16:02:20 +0000173 const LLVMState &State, InstructionBenchmark::ModeE Mode) const;
Clement Courbet4860b982018-06-26 08:49:30 +0000174 std::unique_ptr<BenchmarkRunner> virtual createUopsBenchmarkRunner(
175 const LLVMState &State) const;
176
Clement Courbetcff2caa2018-06-25 11:22:23 +0000177 const ExegesisTarget *Next = nullptr;
Clement Courbet50cdd562019-10-09 11:58:42 +0000178 const ArrayRef<CpuAndPfmCounters> CpuPfmCounters;
Clement Courbet44b4c542018-06-19 11:28:59 +0000179};
180
Clement Courbetcff2caa2018-06-25 11:22:23 +0000181} // namespace exegesis
Fangrui Song32401af2018-10-22 17:10:47 +0000182} // namespace llvm
Clement Courbet44b4c542018-06-19 11:28:59 +0000183
184#endif // LLVM_TOOLS_LLVM_EXEGESIS_TARGET_H