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gerrit-public.fairphone.software / toolchain / llvm-project / 4b86d7904863b3d0e552db37f455fe76430e6d46 / . / llvm / test / CodeGen / RISCV / mul.ll
blob: c5a9dc9359f693754929185820b7bb3752c2ec78 [file] [log] [blame]
Alex Bradburyffc435e2017-11-21 08:11:03 +0000[diff] [blame]1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
3; RUN: | FileCheck %s -check-prefix=RV32I
4
5define i32 @square(i32 %a) {
6; RV32I-LABEL: square:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]7; RV32I: # %bb.0:
Alex Bradburyb014e3d2017-12-11 12:34:11 +0000[diff] [blame]8; RV32I-NEXT: addi sp, sp, -16
Alex Bradbury660bcce2017-12-11 11:53:54 +0000[diff] [blame]9; RV32I-NEXT: sw ra, 12(sp)
Alex Bradburyb014e3d2017-12-11 12:34:11 +0000[diff] [blame]10; RV32I-NEXT: sw s0, 8(sp)
11; RV32I-NEXT: addi s0, sp, 16
Alex Bradburyffc435e2017-11-21 08:11:03 +0000[diff] [blame]12; RV32I-NEXT: lui a1, %hi(__mulsi3)
13; RV32I-NEXT: addi a2, a1, %lo(__mulsi3)
14; RV32I-NEXT: addi a1, a0, 0
15; RV32I-NEXT: jalr ra, a2, 0
Alex Bradburyb014e3d2017-12-11 12:34:11 +0000[diff] [blame]16; RV32I-NEXT: lw s0, 8(sp)
Alex Bradbury660bcce2017-12-11 11:53:54 +0000[diff] [blame]17; RV32I-NEXT: lw ra, 12(sp)
Alex Bradburyb014e3d2017-12-11 12:34:11 +0000[diff] [blame]18; RV32I-NEXT: addi sp, sp, 16
Alex Bradburyffc435e2017-11-21 08:11:03 +0000[diff] [blame]19; RV32I-NEXT: jalr zero, ra, 0
20 %1 = mul i32 %a, %a
21 ret i32 %1
22}
23
24define i32 @mul(i32 %a, i32 %b) {
25; RV32I-LABEL: mul:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]26; RV32I: # %bb.0:
Alex Bradburyb014e3d2017-12-11 12:34:11 +0000[diff] [blame]27; RV32I-NEXT: addi sp, sp, -16
Alex Bradbury660bcce2017-12-11 11:53:54 +0000[diff] [blame]28; RV32I-NEXT: sw ra, 12(sp)
Alex Bradburyb014e3d2017-12-11 12:34:11 +0000[diff] [blame]29; RV32I-NEXT: sw s0, 8(sp)
30; RV32I-NEXT: addi s0, sp, 16
Alex Bradburyffc435e2017-11-21 08:11:03 +0000[diff] [blame]31; RV32I-NEXT: lui a2, %hi(__mulsi3)
32; RV32I-NEXT: addi a2, a2, %lo(__mulsi3)
33; RV32I-NEXT: jalr ra, a2, 0
Alex Bradburyb014e3d2017-12-11 12:34:11 +0000[diff] [blame]34; RV32I-NEXT: lw s0, 8(sp)
Alex Bradbury660bcce2017-12-11 11:53:54 +0000[diff] [blame]35; RV32I-NEXT: lw ra, 12(sp)
Alex Bradburyb014e3d2017-12-11 12:34:11 +0000[diff] [blame]36; RV32I-NEXT: addi sp, sp, 16
Alex Bradburyffc435e2017-11-21 08:11:03 +0000[diff] [blame]37; RV32I-NEXT: jalr zero, ra, 0
38 %1 = mul i32 %a, %b
39 ret i32 %1
40}
41
42define i32 @mul_constant(i32 %a) {
43; RV32I-LABEL: mul_constant:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]44; RV32I: # %bb.0:
Alex Bradburyb014e3d2017-12-11 12:34:11 +0000[diff] [blame]45; RV32I-NEXT: addi sp, sp, -16
Alex Bradbury660bcce2017-12-11 11:53:54 +0000[diff] [blame]46; RV32I-NEXT: sw ra, 12(sp)
Alex Bradburyb014e3d2017-12-11 12:34:11 +0000[diff] [blame]47; RV32I-NEXT: sw s0, 8(sp)
48; RV32I-NEXT: addi s0, sp, 16
Alex Bradburyffc435e2017-11-21 08:11:03 +0000[diff] [blame]49; RV32I-NEXT: lui a1, %hi(__mulsi3)
50; RV32I-NEXT: addi a2, a1, %lo(__mulsi3)
51; RV32I-NEXT: addi a1, zero, 5
52; RV32I-NEXT: jalr ra, a2, 0
Alex Bradburyb014e3d2017-12-11 12:34:11 +0000[diff] [blame]53; RV32I-NEXT: lw s0, 8(sp)
Alex Bradbury660bcce2017-12-11 11:53:54 +0000[diff] [blame]54; RV32I-NEXT: lw ra, 12(sp)
Alex Bradburyb014e3d2017-12-11 12:34:11 +0000[diff] [blame]55; RV32I-NEXT: addi sp, sp, 16
Alex Bradburyffc435e2017-11-21 08:11:03 +0000[diff] [blame]56; RV32I-NEXT: jalr zero, ra, 0
57 %1 = mul i32 %a, 5
58 ret i32 %1
59}
60
61define i32 @mul_pow2(i32 %a) {
62; RV32I-LABEL: mul_pow2:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]63; RV32I: # %bb.0:
Alex Bradburyb014e3d2017-12-11 12:34:11 +0000[diff] [blame]64; RV32I-NEXT: addi sp, sp, -16
65; RV32I-NEXT: sw ra, 12(sp)
66; RV32I-NEXT: sw s0, 8(sp)
67; RV32I-NEXT: addi s0, sp, 16
Alex Bradburyffc435e2017-11-21 08:11:03 +0000[diff] [blame]68; RV32I-NEXT: slli a0, a0, 3
Alex Bradburyb014e3d2017-12-11 12:34:11 +0000[diff] [blame]69; RV32I-NEXT: lw s0, 8(sp)
70; RV32I-NEXT: lw ra, 12(sp)
71; RV32I-NEXT: addi sp, sp, 16
Alex Bradburyffc435e2017-11-21 08:11:03 +0000[diff] [blame]72; RV32I-NEXT: jalr zero, ra, 0
73 %1 = mul i32 %a, 8
74 ret i32 %1
75}
76
77define i64 @mul64(i64 %a, i64 %b) {
78; RV32I-LABEL: mul64:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]79; RV32I: # %bb.0:
Alex Bradburyb014e3d2017-12-11 12:34:11 +0000[diff] [blame]80; RV32I-NEXT: addi sp, sp, -16
Alex Bradbury660bcce2017-12-11 11:53:54 +0000[diff] [blame]81; RV32I-NEXT: sw ra, 12(sp)
Alex Bradburyb014e3d2017-12-11 12:34:11 +0000[diff] [blame]82; RV32I-NEXT: sw s0, 8(sp)
83; RV32I-NEXT: addi s0, sp, 16
Alex Bradburyffc435e2017-11-21 08:11:03 +0000[diff] [blame]84; RV32I-NEXT: lui a4, %hi(__muldi3)
85; RV32I-NEXT: addi a4, a4, %lo(__muldi3)
86; RV32I-NEXT: jalr ra, a4, 0
Alex Bradburyb014e3d2017-12-11 12:34:11 +0000[diff] [blame]87; RV32I-NEXT: lw s0, 8(sp)
Alex Bradbury660bcce2017-12-11 11:53:54 +0000[diff] [blame]88; RV32I-NEXT: lw ra, 12(sp)
Alex Bradburyb014e3d2017-12-11 12:34:11 +0000[diff] [blame]89; RV32I-NEXT: addi sp, sp, 16
Alex Bradburyffc435e2017-11-21 08:11:03 +0000[diff] [blame]90; RV32I-NEXT: jalr zero, ra, 0
91 %1 = mul i64 %a, %b
92 ret i64 %1
93}
94
95define i64 @mul64_constant(i64 %a) {
96; RV32I-LABEL: mul64_constant:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]97; RV32I: # %bb.0:
Alex Bradburyb014e3d2017-12-11 12:34:11 +0000[diff] [blame]98; RV32I-NEXT: addi sp, sp, -16
Alex Bradbury660bcce2017-12-11 11:53:54 +0000[diff] [blame]99; RV32I-NEXT: sw ra, 12(sp)
Alex Bradburyb014e3d2017-12-11 12:34:11 +0000[diff] [blame]100; RV32I-NEXT: sw s0, 8(sp)
101; RV32I-NEXT: addi s0, sp, 16
Alex Bradburyffc435e2017-11-21 08:11:03 +0000[diff] [blame]102; RV32I-NEXT: lui a2, %hi(__muldi3)
103; RV32I-NEXT: addi a4, a2, %lo(__muldi3)
104; RV32I-NEXT: addi a2, zero, 5
105; RV32I-NEXT: addi a3, zero, 0
106; RV32I-NEXT: jalr ra, a4, 0
Alex Bradburyb014e3d2017-12-11 12:34:11 +0000[diff] [blame]107; RV32I-NEXT: lw s0, 8(sp)
Alex Bradbury660bcce2017-12-11 11:53:54 +0000[diff] [blame]108; RV32I-NEXT: lw ra, 12(sp)
Alex Bradburyb014e3d2017-12-11 12:34:11 +0000[diff] [blame]109; RV32I-NEXT: addi sp, sp, 16
Alex Bradburyffc435e2017-11-21 08:11:03 +0000[diff] [blame]110; RV32I-NEXT: jalr zero, ra, 0
111 %1 = mul i64 %a, 5
112 ret i64 %1
113}