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gerrit-public.fairphone.software / toolchain / llvm-project / 59136ffab1b0b051d2b56a90b8fb86d5721ed0b5 / . / llvm / test / CodeGen / RISCV / rem.ll
blob: 3f8f7ebea966d3e6d4f2fd85d46f164d02e8ab83 [file] [log] [blame]
Alex Bradburyffc435e2017-11-21 08:11:03 +0000[diff] [blame]1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
3; RUN: | FileCheck %s -check-prefix=RV32I
4
5define i32 @urem(i32 %a, i32 %b) nounwind {
6; RV32I-LABEL: urem:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]7; RV32I: # %bb.0:
Alex Bradburyb014e3d2017-12-11 12:34:11 +0000[diff] [blame]8; RV32I-NEXT: addi sp, sp, -16
Alex Bradbury660bcce2017-12-11 11:53:54 +0000[diff] [blame]9; RV32I-NEXT: sw ra, 12(sp)
Alex Bradburyb014e3d2017-12-11 12:34:11 +0000[diff] [blame]10; RV32I-NEXT: sw s0, 8(sp)
11; RV32I-NEXT: addi s0, sp, 16
Alex Bradburyffc435e2017-11-21 08:11:03 +0000[diff] [blame]12; RV32I-NEXT: lui a2, %hi(__umodsi3)
13; RV32I-NEXT: addi a2, a2, %lo(__umodsi3)
Alex Bradbury59136ff2017-12-15 09:47:01 +0000[diff] [blame^]14; RV32I-NEXT: jalr a2
Alex Bradburyb014e3d2017-12-11 12:34:11 +0000[diff] [blame]15; RV32I-NEXT: lw s0, 8(sp)
Alex Bradbury660bcce2017-12-11 11:53:54 +0000[diff] [blame]16; RV32I-NEXT: lw ra, 12(sp)
Alex Bradburyb014e3d2017-12-11 12:34:11 +0000[diff] [blame]17; RV32I-NEXT: addi sp, sp, 16
Alex Bradbury59136ff2017-12-15 09:47:01 +0000[diff] [blame^]18; RV32I-NEXT: ret
Alex Bradburyffc435e2017-11-21 08:11:03 +0000[diff] [blame]19 %1 = urem i32 %a, %b
20 ret i32 %1
21}
22
23define i32 @srem(i32 %a, i32 %b) nounwind {
24; RV32I-LABEL: srem:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]25; RV32I: # %bb.0:
Alex Bradburyb014e3d2017-12-11 12:34:11 +0000[diff] [blame]26; RV32I-NEXT: addi sp, sp, -16
Alex Bradbury660bcce2017-12-11 11:53:54 +0000[diff] [blame]27; RV32I-NEXT: sw ra, 12(sp)
Alex Bradburyb014e3d2017-12-11 12:34:11 +0000[diff] [blame]28; RV32I-NEXT: sw s0, 8(sp)
29; RV32I-NEXT: addi s0, sp, 16
Alex Bradburyffc435e2017-11-21 08:11:03 +0000[diff] [blame]30; RV32I-NEXT: lui a2, %hi(__modsi3)
31; RV32I-NEXT: addi a2, a2, %lo(__modsi3)
Alex Bradbury59136ff2017-12-15 09:47:01 +0000[diff] [blame^]32; RV32I-NEXT: jalr a2
Alex Bradburyb014e3d2017-12-11 12:34:11 +0000[diff] [blame]33; RV32I-NEXT: lw s0, 8(sp)
Alex Bradbury660bcce2017-12-11 11:53:54 +0000[diff] [blame]34; RV32I-NEXT: lw ra, 12(sp)
Alex Bradburyb014e3d2017-12-11 12:34:11 +0000[diff] [blame]35; RV32I-NEXT: addi sp, sp, 16
Alex Bradbury59136ff2017-12-15 09:47:01 +0000[diff] [blame^]36; RV32I-NEXT: ret
Alex Bradburyffc435e2017-11-21 08:11:03 +0000[diff] [blame]37 %1 = srem i32 %a, %b
38 ret i32 %1
39}