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Misha Brukman076b9f42005-02-04 20:25:52 +00001//===- AlphaInstrInfo.h - Alpha Instruction Information ---------*- C++ -*-===//
Misha Brukman89b8c8d2005-04-21 23:13:11 +00002//
Andrew Lenhartha1b5ca22005-01-22 23:41:55 +00003// The LLVM Compiler Infrastructure
4//
Chris Lattnerf3ebc3f2007-12-29 20:36:04 +00005// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
Misha Brukman89b8c8d2005-04-21 23:13:11 +00007//
Andrew Lenhartha1b5ca22005-01-22 23:41:55 +00008//===----------------------------------------------------------------------===//
9//
10// This file contains the Alpha implementation of the TargetInstrInfo class.
11//
12//===----------------------------------------------------------------------===//
13
14#ifndef ALPHAINSTRUCTIONINFO_H
15#define ALPHAINSTRUCTIONINFO_H
16
17#include "llvm/Target/TargetInstrInfo.h"
18#include "AlphaRegisterInfo.h"
19
20namespace llvm {
21
Chris Lattner25568e42008-01-01 01:03:04 +000022class AlphaInstrInfo : public TargetInstrInfoImpl {
Andrew Lenhartha1b5ca22005-01-22 23:41:55 +000023 const AlphaRegisterInfo RI;
24public:
25 AlphaInstrInfo();
26
27 /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As
28 /// such, whenever a client has an instance of instruction info, it should
29 /// always be able to get register info as well (through this method).
30 ///
Dan Gohmaneabd6472008-05-14 01:58:56 +000031 virtual const AlphaRegisterInfo &getRegisterInfo() const { return RI; }
Andrew Lenhartha1b5ca22005-01-22 23:41:55 +000032
Evan Chengc544cb02009-01-20 19:12:24 +000033 /// Return true if the instruction is a register to register move and return
34 /// the source and dest operands and their sub-register indices by reference.
Andrew Lenhartha1b5ca22005-01-22 23:41:55 +000035 virtual bool isMoveInstr(const MachineInstr &MI,
Evan Chengc544cb02009-01-20 19:12:24 +000036 unsigned &SrcReg, unsigned &DstReg,
37 unsigned &SrcSubIdx, unsigned &DstSubIdx) const;
Chris Lattnerbb53acd2006-02-02 20:12:32 +000038
Dan Gohman0b273252008-11-18 19:49:32 +000039 virtual unsigned isLoadFromStackSlot(const MachineInstr *MI,
40 int &FrameIndex) const;
41 virtual unsigned isStoreToStackSlot(const MachineInstr *MI,
42 int &FrameIndex) const;
Chris Lattner042d5622006-10-24 16:41:36 +000043
Evan Cheng99be49d2007-05-18 00:05:48 +000044 virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
Chris Lattner042d5622006-10-24 16:41:36 +000045 MachineBasicBlock *FBB,
Owen Anderson4f6bf042008-08-14 22:49:33 +000046 const SmallVectorImpl<MachineOperand> &Cond) const;
Owen Anderson27fb3dc2008-08-26 18:03:31 +000047 virtual bool copyRegToReg(MachineBasicBlock &MBB,
Owen Anderson7a73ae92007-12-31 06:32:00 +000048 MachineBasicBlock::iterator MI,
49 unsigned DestReg, unsigned SrcReg,
50 const TargetRegisterClass *DestRC,
51 const TargetRegisterClass *SrcRC) const;
Owen Andersoneee14602008-01-01 21:11:32 +000052 virtual void storeRegToStackSlot(MachineBasicBlock &MBB,
53 MachineBasicBlock::iterator MBBI,
54 unsigned SrcReg, bool isKill, int FrameIndex,
55 const TargetRegisterClass *RC) const;
56
Owen Andersoneee14602008-01-01 21:11:32 +000057 virtual void loadRegFromStackSlot(MachineBasicBlock &MBB,
58 MachineBasicBlock::iterator MBBI,
59 unsigned DestReg, int FrameIndex,
60 const TargetRegisterClass *RC) const;
Owen Anderson2a3be7b2008-01-07 01:35:02 +000061
Dan Gohman3f86b512008-12-03 18:43:12 +000062 virtual MachineInstr* foldMemoryOperandImpl(MachineFunction &MF,
63 MachineInstr* MI,
64 const SmallVectorImpl<unsigned> &Ops,
65 int FrameIndex) const;
Owen Anderson2a3be7b2008-01-07 01:35:02 +000066
Dan Gohman3f86b512008-12-03 18:43:12 +000067 virtual MachineInstr* foldMemoryOperandImpl(MachineFunction &MF,
68 MachineInstr* MI,
69 const SmallVectorImpl<unsigned> &Ops,
70 MachineInstr* LoadMI) const {
Owen Anderson2a3be7b2008-01-07 01:35:02 +000071 return 0;
72 }
73
Andrew Lenharth692e4152006-10-31 16:49:55 +000074 bool AnalyzeBranch(MachineBasicBlock &MBB,MachineBasicBlock *&TBB,
75 MachineBasicBlock *&FBB,
Evan Cheng64dfcac2009-02-09 07:14:22 +000076 SmallVectorImpl<MachineOperand> &Cond,
77 bool AllowModify) const;
Evan Cheng99be49d2007-05-18 00:05:48 +000078 unsigned RemoveBranch(MachineBasicBlock &MBB) const;
Andrew Lenharth692e4152006-10-31 16:49:55 +000079 void insertNoop(MachineBasicBlock &MBB,
80 MachineBasicBlock::iterator MI) const;
Owen Anderson4f6bf042008-08-14 22:49:33 +000081 bool ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const;
Dan Gohmand5ca70642009-06-03 20:30:14 +000082
83 /// getGlobalBaseReg - Return a virtual register initialized with the
84 /// the global base register value. Output instructions required to
85 /// initialize the register in the function entry block, if necessary.
86 ///
87 unsigned getGlobalBaseReg(MachineFunction *MF) const;
88
89 /// getGlobalRetAddr - Return a virtual register initialized with the
90 /// the global return address register value. Output instructions required to
91 /// initialize the register in the function entry block, if necessary.
92 ///
93 unsigned getGlobalRetAddr(MachineFunction *MF) const;
Andrew Lenhartha1b5ca22005-01-22 23:41:55 +000094};
95
96}
97
98#endif