Tom Stellard | cb6ba62 | 2016-04-30 00:23:06 +0000 | [diff] [blame] | 1 | //===-- GCNHazardRecognizers.h - GCN Hazard Recognizers ---------*- C++ -*-===// |
| 2 | // |
Chandler Carruth | 2946cd7 | 2019-01-19 08:50:56 +0000 | [diff] [blame] | 3 | // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. |
| 4 | // See https://llvm.org/LICENSE.txt for license information. |
| 5 | // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception |
Tom Stellard | cb6ba62 | 2016-04-30 00:23:06 +0000 | [diff] [blame] | 6 | // |
| 7 | //===----------------------------------------------------------------------===// |
| 8 | // |
| 9 | // This file defines hazard recognizers for scheduling on GCN processors. |
| 10 | // |
| 11 | //===----------------------------------------------------------------------===// |
| 12 | |
| 13 | #ifndef LLVM_LIB_TARGET_AMDGPUHAZARDRECOGNIZERS_H |
| 14 | #define LLVM_LIB_TARGET_AMDGPUHAZARDRECOGNIZERS_H |
| 15 | |
Matt Arsenault | 03c67d1 | 2017-11-17 04:18:24 +0000 | [diff] [blame] | 16 | #include "llvm/ADT/BitVector.h" |
Benjamin Kramer | d3f4c05 | 2016-06-12 16:13:55 +0000 | [diff] [blame] | 17 | #include "llvm/ADT/STLExtras.h" |
Tom Stellard | cb6ba62 | 2016-04-30 00:23:06 +0000 | [diff] [blame] | 18 | #include "llvm/CodeGen/ScheduleHazardRecognizer.h" |
Tom Stellard | cb6ba62 | 2016-04-30 00:23:06 +0000 | [diff] [blame] | 19 | #include <list> |
| 20 | |
| 21 | namespace llvm { |
| 22 | |
| 23 | class MachineFunction; |
| 24 | class MachineInstr; |
Mark Searles | d29f24a | 2017-12-07 20:34:25 +0000 | [diff] [blame] | 25 | class MachineOperand; |
| 26 | class MachineRegisterInfo; |
Tom Stellard | cb6ba62 | 2016-04-30 00:23:06 +0000 | [diff] [blame] | 27 | class ScheduleDAG; |
| 28 | class SIInstrInfo; |
Matt Arsenault | 03c67d1 | 2017-11-17 04:18:24 +0000 | [diff] [blame] | 29 | class SIRegisterInfo; |
Tom Stellard | 5bfbae5 | 2018-07-11 20:59:01 +0000 | [diff] [blame] | 30 | class GCNSubtarget; |
Tom Stellard | cb6ba62 | 2016-04-30 00:23:06 +0000 | [diff] [blame] | 31 | |
| 32 | class GCNHazardRecognizer final : public ScheduleHazardRecognizer { |
Stanislav Mekhanoshin | f92ed69 | 2019-01-21 19:11:26 +0000 | [diff] [blame] | 33 | public: |
| 34 | typedef function_ref<bool(MachineInstr *)> IsHazardFn; |
| 35 | |
| 36 | private: |
| 37 | // Distinguish if we are called from scheduler or hazard recognizer |
| 38 | bool IsHazardRecognizerMode; |
| 39 | |
Matt Arsenault | 43e92fe | 2016-06-24 06:30:11 +0000 | [diff] [blame] | 40 | // This variable stores the instruction that has been emitted this cycle. It |
| 41 | // will be added to EmittedInstrs, when AdvanceCycle() or RecedeCycle() is |
Tom Stellard | cb6ba62 | 2016-04-30 00:23:06 +0000 | [diff] [blame] | 42 | // called. |
| 43 | MachineInstr *CurrCycleInstr; |
| 44 | std::list<MachineInstr*> EmittedInstrs; |
| 45 | const MachineFunction &MF; |
Tom Stellard | 5bfbae5 | 2018-07-11 20:59:01 +0000 | [diff] [blame] | 46 | const GCNSubtarget &ST; |
Matt Arsenault | 59ece95 | 2017-03-17 21:36:28 +0000 | [diff] [blame] | 47 | const SIInstrInfo &TII; |
Matt Arsenault | 03c67d1 | 2017-11-17 04:18:24 +0000 | [diff] [blame] | 48 | const SIRegisterInfo &TRI; |
| 49 | |
| 50 | /// RegUnits of uses in the current soft memory clause. |
| 51 | BitVector ClauseUses; |
| 52 | |
| 53 | /// RegUnits of defs in the current soft memory clause. |
| 54 | BitVector ClauseDefs; |
| 55 | |
| 56 | void resetClause() { |
| 57 | ClauseUses.reset(); |
| 58 | ClauseDefs.reset(); |
| 59 | } |
| 60 | |
| 61 | void addClauseInst(const MachineInstr &MI); |
Tom Stellard | cb6ba62 | 2016-04-30 00:23:06 +0000 | [diff] [blame] | 62 | |
Austin Kerbow | 8a3d3a9 | 2019-05-07 22:12:15 +0000 | [diff] [blame] | 63 | // Advance over a MachineInstr bundle. Look for hazards in the bundled |
| 64 | // instructions. |
| 65 | void processBundle(); |
| 66 | |
Stanislav Mekhanoshin | f92ed69 | 2019-01-21 19:11:26 +0000 | [diff] [blame] | 67 | int getWaitStatesSince(IsHazardFn IsHazard, int Limit); |
| 68 | int getWaitStatesSinceDef(unsigned Reg, IsHazardFn IsHazardDef, int Limit); |
| 69 | int getWaitStatesSinceSetReg(IsHazardFn IsHazard, int Limit); |
Tom Stellard | cb6ba62 | 2016-04-30 00:23:06 +0000 | [diff] [blame] | 70 | |
Matt Arsenault | a41351e | 2017-11-17 21:35:32 +0000 | [diff] [blame] | 71 | int checkSoftClauseHazards(MachineInstr *SMEM); |
Tom Stellard | cb6ba62 | 2016-04-30 00:23:06 +0000 | [diff] [blame] | 72 | int checkSMRDHazards(MachineInstr *SMRD); |
| 73 | int checkVMEMHazards(MachineInstr* VMEM); |
Tom Stellard | a27007e | 2016-05-02 16:23:09 +0000 | [diff] [blame] | 74 | int checkDPPHazards(MachineInstr *DPP); |
Tom Stellard | 5ab6154 | 2016-10-07 23:42:48 +0000 | [diff] [blame] | 75 | int checkDivFMasHazards(MachineInstr *DivFMas); |
Tom Stellard | 961811c | 2016-10-15 00:58:14 +0000 | [diff] [blame] | 76 | int checkGetRegHazards(MachineInstr *GetRegInstr); |
Tom Stellard | 30d3082 | 2016-10-27 20:39:09 +0000 | [diff] [blame] | 77 | int checkSetRegHazards(MachineInstr *SetRegInstr); |
Tom Stellard | b133fbb | 2016-10-27 23:05:31 +0000 | [diff] [blame] | 78 | int createsVALUHazard(const MachineInstr &MI); |
| 79 | int checkVALUHazards(MachineInstr *VALU); |
Mark Searles | d29f24a | 2017-12-07 20:34:25 +0000 | [diff] [blame] | 80 | int checkVALUHazardsHelper(const MachineOperand &Def, const MachineRegisterInfo &MRI); |
Tom Stellard | 04051b5 | 2016-10-27 23:42:29 +0000 | [diff] [blame] | 81 | int checkRWLaneHazards(MachineInstr *RWLane); |
Tom Stellard | aea899e | 2016-10-27 23:50:21 +0000 | [diff] [blame] | 82 | int checkRFEHazards(MachineInstr *RFE); |
Mark Searles | d29f24a | 2017-12-07 20:34:25 +0000 | [diff] [blame] | 83 | int checkInlineAsmHazards(MachineInstr *IA); |
Matt Arsenault | e823d92 | 2017-02-18 18:29:53 +0000 | [diff] [blame] | 84 | int checkAnyInstHazards(MachineInstr *MI); |
| 85 | int checkReadM0Hazards(MachineInstr *SMovRel); |
Stanislav Mekhanoshin | 51d1415 | 2019-05-04 04:30:57 +0000 | [diff] [blame] | 86 | int checkNSAtoVMEMHazard(MachineInstr *MI); |
Austin Kerbow | 8a3d3a9 | 2019-05-07 22:12:15 +0000 | [diff] [blame] | 87 | void fixHazards(MachineInstr *MI); |
Stanislav Mekhanoshin | 5f581c9 | 2019-06-12 17:52:51 +0000 | [diff] [blame^] | 88 | bool fixVcmpxPermlaneHazards(MachineInstr *MI); |
Stanislav Mekhanoshin | 51d1415 | 2019-05-04 04:30:57 +0000 | [diff] [blame] | 89 | bool fixVMEMtoScalarWriteHazards(MachineInstr *MI); |
| 90 | bool fixSMEMtoVectorWriteHazards(MachineInstr *MI); |
| 91 | bool fixVcmpxExecWARHazard(MachineInstr *MI); |
| 92 | bool fixLdsBranchVmemWARHazard(MachineInstr *MI); |
| 93 | |
Tom Stellard | cb6ba62 | 2016-04-30 00:23:06 +0000 | [diff] [blame] | 94 | public: |
| 95 | GCNHazardRecognizer(const MachineFunction &MF); |
| 96 | // We can only issue one instruction per cycle. |
| 97 | bool atIssueLimit() const override { return true; } |
| 98 | void EmitInstruction(SUnit *SU) override; |
| 99 | void EmitInstruction(MachineInstr *MI) override; |
| 100 | HazardType getHazardType(SUnit *SU, int Stalls) override; |
| 101 | void EmitNoop() override; |
| 102 | unsigned PreEmitNoops(SUnit *SU) override; |
| 103 | unsigned PreEmitNoops(MachineInstr *) override; |
Stanislav Mekhanoshin | f92ed69 | 2019-01-21 19:11:26 +0000 | [diff] [blame] | 104 | unsigned PreEmitNoopsCommon(MachineInstr *); |
Tom Stellard | cb6ba62 | 2016-04-30 00:23:06 +0000 | [diff] [blame] | 105 | void AdvanceCycle() override; |
| 106 | void RecedeCycle() override; |
| 107 | }; |
| 108 | |
| 109 | } // end namespace llvm |
| 110 | |
| 111 | #endif //LLVM_LIB_TARGET_AMDGPUHAZARDRECOGNIZERS_H |