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Nadav Roteme7b6a8a2013-03-28 22:34:46 +00001//=- X86SchedHaswell.td - X86 Haswell Scheduling -------------*- tablegen -*-=//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file defines the machine model for Haswell to support instruction
11// scheduling and other instruction cost heuristics.
12//
13//===----------------------------------------------------------------------===//
14
15def HaswellModel : SchedMachineModel {
16 // All x86 instructions are modeled as a single micro-op, and HW can decode 4
17 // instructions per cycle.
18 let IssueWidth = 4;
Andrew Trick18dc3da2013-06-15 04:50:02 +000019 let MicroOpBufferSize = 192; // Based on the reorder buffer.
Gadi Haber2cf601f2017-12-08 09:48:44 +000020 let LoadLatency = 5;
Nadav Roteme7b6a8a2013-03-28 22:34:46 +000021 let MispredictPenalty = 16;
Andrew Trickb6854d82013-09-25 18:14:12 +000022
Hal Finkel6532c202014-05-08 09:14:44 +000023 // Based on the LSD (loop-stream detector) queue size and benchmarking data.
24 let LoopMicroOpBufferSize = 50;
25
Gadi Haberd76f7b82017-08-28 10:04:16 +000026 // This flag is set to allow the scheduler to assign a default model to
27 // unrecognized opcodes.
Andrew Trickb6854d82013-09-25 18:14:12 +000028 let CompleteModel = 0;
Nadav Roteme7b6a8a2013-03-28 22:34:46 +000029}
30
31let SchedModel = HaswellModel in {
32
33// Haswell can issue micro-ops to 8 different ports in one cycle.
34
Quentin Colombet9e16c8a2014-01-29 18:26:59 +000035// Ports 0, 1, 5, and 6 handle all computation.
Nadav Roteme7b6a8a2013-03-28 22:34:46 +000036// Port 4 gets the data half of stores. Store data can be available later than
37// the store address, but since we don't model the latency of stores, we can
38// ignore that.
39// Ports 2 and 3 are identical. They handle loads and the address half of
40// stores. Port 7 can handle address calculations.
41def HWPort0 : ProcResource<1>;
42def HWPort1 : ProcResource<1>;
43def HWPort2 : ProcResource<1>;
44def HWPort3 : ProcResource<1>;
45def HWPort4 : ProcResource<1>;
46def HWPort5 : ProcResource<1>;
47def HWPort6 : ProcResource<1>;
48def HWPort7 : ProcResource<1>;
49
50// Many micro-ops are capable of issuing on multiple ports.
Quentin Colombet0bc907e2014-08-18 17:55:26 +000051def HWPort01 : ProcResGroup<[HWPort0, HWPort1]>;
Nadav Roteme7b6a8a2013-03-28 22:34:46 +000052def HWPort23 : ProcResGroup<[HWPort2, HWPort3]>;
53def HWPort237 : ProcResGroup<[HWPort2, HWPort3, HWPort7]>;
Quentin Colombetf68e0942014-08-18 17:55:36 +000054def HWPort04 : ProcResGroup<[HWPort0, HWPort4]>;
Nadav Roteme7b6a8a2013-03-28 22:34:46 +000055def HWPort05 : ProcResGroup<[HWPort0, HWPort5]>;
Quentin Colombet7e939fb42014-08-18 17:56:01 +000056def HWPort06 : ProcResGroup<[HWPort0, HWPort6]>;
Nadav Roteme7b6a8a2013-03-28 22:34:46 +000057def HWPort15 : ProcResGroup<[HWPort1, HWPort5]>;
Quentin Colombetca498512014-02-24 19:33:51 +000058def HWPort16 : ProcResGroup<[HWPort1, HWPort6]>;
Quentin Colombet7e939fb42014-08-18 17:56:01 +000059def HWPort56 : ProcResGroup<[HWPort5, HWPort6]>;
Nadav Roteme7b6a8a2013-03-28 22:34:46 +000060def HWPort015 : ProcResGroup<[HWPort0, HWPort1, HWPort5]>;
Quentin Colombet7e939fb42014-08-18 17:56:01 +000061def HWPort056 : ProcResGroup<[HWPort0, HWPort5, HWPort6]>;
Nadav Roteme7b6a8a2013-03-28 22:34:46 +000062def HWPort0156: ProcResGroup<[HWPort0, HWPort1, HWPort5, HWPort6]>;
63
Andrew Trick40c4f382013-06-15 04:50:06 +000064// 60 Entry Unified Scheduler
65def HWPortAny : ProcResGroup<[HWPort0, HWPort1, HWPort2, HWPort3, HWPort4,
66 HWPort5, HWPort6, HWPort7]> {
67 let BufferSize=60;
68}
69
Andrew Tricke1d88cf2013-04-02 01:58:47 +000070// Integer division issued on port 0.
71def HWDivider : ProcResource<1>;
Nadav Roteme7b6a8a2013-03-28 22:34:46 +000072
Gadi Haber2cf601f2017-12-08 09:48:44 +000073// Loads are 5 cycles, so ReadAfterLd registers needn't be available until 5
Nadav Roteme7b6a8a2013-03-28 22:34:46 +000074// cycles after the memory operand.
Gadi Haber2cf601f2017-12-08 09:48:44 +000075def : ReadAdvance<ReadAfterLd, 5>;
Nadav Roteme7b6a8a2013-03-28 22:34:46 +000076
77// Many SchedWrites are defined in pairs with and without a folded load.
78// Instructions with folded loads are usually micro-fused, so they only appear
79// as two micro-ops when queued in the reservation station.
80// This multiclass defines the resource usage for variants with and without
81// folded loads.
82multiclass HWWriteResPair<X86FoldableSchedWrite SchedRW,
83 ProcResourceKind ExePort,
84 int Lat> {
85 // Register variant is using a single cycle on ExePort.
86 def : WriteRes<SchedRW, [ExePort]> { let Latency = Lat; }
87
Gadi Haber2cf601f2017-12-08 09:48:44 +000088 // Memory variant also uses a cycle on port 2/3 and adds 5 cycles to the
Nadav Roteme7b6a8a2013-03-28 22:34:46 +000089 // latency.
90 def : WriteRes<SchedRW.Folded, [HWPort23, ExePort]> {
Gadi Haber2cf601f2017-12-08 09:48:44 +000091 let Latency = !add(Lat, 5);
Nadav Roteme7b6a8a2013-03-28 22:34:46 +000092 }
93}
94
95// A folded store needs a cycle on port 4 for the store data, but it does not
96// need an extra port 2/3 cycle to recompute the address.
97def : WriteRes<WriteRMW, [HWPort4]>;
98
Quentin Colombet9e16c8a2014-01-29 18:26:59 +000099// Store_addr on 237.
100// Store_data on 4.
Nadav Roteme7b6a8a2013-03-28 22:34:46 +0000101def : WriteRes<WriteStore, [HWPort237, HWPort4]>;
Gadi Haber2cf601f2017-12-08 09:48:44 +0000102def : WriteRes<WriteLoad, [HWPort23]> { let Latency = 5; }
Nadav Roteme7b6a8a2013-03-28 22:34:46 +0000103def : WriteRes<WriteMove, [HWPort0156]>;
104def : WriteRes<WriteZero, []>;
105
106defm : HWWriteResPair<WriteALU, HWPort0156, 1>;
107defm : HWWriteResPair<WriteIMul, HWPort1, 3>;
Andrew Trick7201f4f2013-06-21 18:33:04 +0000108def : WriteRes<WriteIMulH, []> { let Latency = 3; }
Quentin Colombet9e16c8a2014-01-29 18:26:59 +0000109defm : HWWriteResPair<WriteShift, HWPort06, 1>;
110defm : HWWriteResPair<WriteJump, HWPort06, 1>;
Nadav Roteme7b6a8a2013-03-28 22:34:46 +0000111
112// This is for simple LEAs with one or two input operands.
113// The complex ones can only execute on port 1, and they require two cycles on
114// the port to read all inputs. We don't model that.
115def : WriteRes<WriteLEA, [HWPort15]>;
116
117// This is quite rough, latency depends on the dividend.
118def : WriteRes<WriteIDiv, [HWPort0, HWDivider]> {
119 let Latency = 25;
120 let ResourceCycles = [1, 10];
121}
122def : WriteRes<WriteIDivLd, [HWPort23, HWPort0, HWDivider]> {
123 let Latency = 29;
124 let ResourceCycles = [1, 1, 10];
125}
126
127// Scalar and vector floating point.
128defm : HWWriteResPair<WriteFAdd, HWPort1, 3>;
129defm : HWWriteResPair<WriteFMul, HWPort0, 5>;
130defm : HWWriteResPair<WriteFDiv, HWPort0, 12>; // 10-14 cycles.
131defm : HWWriteResPair<WriteFRcp, HWPort0, 5>;
Andrea Di Biagio196e873c2014-09-26 12:56:44 +0000132defm : HWWriteResPair<WriteFRsqrt, HWPort0, 5>;
Nadav Roteme7b6a8a2013-03-28 22:34:46 +0000133defm : HWWriteResPair<WriteFSqrt, HWPort0, 15>;
134defm : HWWriteResPair<WriteCvtF2I, HWPort1, 3>;
135defm : HWWriteResPair<WriteCvtI2F, HWPort1, 4>;
136defm : HWWriteResPair<WriteCvtF2F, HWPort1, 3>;
Simon Pilgrim97160be2017-11-27 10:41:32 +0000137defm : HWWriteResPair<WriteFMA, HWPort01, 5>;
Quentin Colombetca498512014-02-24 19:33:51 +0000138defm : HWWriteResPair<WriteFShuffle, HWPort5, 1>;
139defm : HWWriteResPair<WriteFBlend, HWPort015, 1>;
140defm : HWWriteResPair<WriteFShuffle256, HWPort5, 3>;
141
142def : WriteRes<WriteFVarBlend, [HWPort5]> {
143 let Latency = 2;
144 let ResourceCycles = [2];
145}
146def : WriteRes<WriteFVarBlendLd, [HWPort5, HWPort23]> {
147 let Latency = 6;
148 let ResourceCycles = [2, 1];
149}
Nadav Roteme7b6a8a2013-03-28 22:34:46 +0000150
151// Vector integer operations.
Quentin Colombet9e16c8a2014-01-29 18:26:59 +0000152defm : HWWriteResPair<WriteVecShift, HWPort0, 1>;
Nadav Roteme7b6a8a2013-03-28 22:34:46 +0000153defm : HWWriteResPair<WriteVecLogic, HWPort015, 1>;
154defm : HWWriteResPair<WriteVecALU, HWPort15, 1>;
155defm : HWWriteResPair<WriteVecIMul, HWPort0, 5>;
Quentin Colombet9e16c8a2014-01-29 18:26:59 +0000156defm : HWWriteResPair<WriteShuffle, HWPort5, 1>;
Quentin Colombetca498512014-02-24 19:33:51 +0000157defm : HWWriteResPair<WriteBlend, HWPort15, 1>;
158defm : HWWriteResPair<WriteShuffle256, HWPort5, 3>;
159
160def : WriteRes<WriteVarBlend, [HWPort5]> {
161 let Latency = 2;
162 let ResourceCycles = [2];
163}
164def : WriteRes<WriteVarBlendLd, [HWPort5, HWPort23]> {
165 let Latency = 6;
166 let ResourceCycles = [2, 1];
167}
168
169def : WriteRes<WriteVarVecShift, [HWPort0, HWPort5]> {
170 let Latency = 2;
171 let ResourceCycles = [2, 1];
172}
173def : WriteRes<WriteVarVecShiftLd, [HWPort0, HWPort5, HWPort23]> {
174 let Latency = 6;
175 let ResourceCycles = [2, 1, 1];
176}
177
178def : WriteRes<WriteMPSAD, [HWPort0, HWPort5]> {
179 let Latency = 6;
180 let ResourceCycles = [1, 2];
181}
182def : WriteRes<WriteMPSADLd, [HWPort23, HWPort0, HWPort5]> {
183 let Latency = 6;
184 let ResourceCycles = [1, 1, 2];
185}
186
187// String instructions.
188// Packed Compare Implicit Length Strings, Return Mask
189def : WriteRes<WritePCmpIStrM, [HWPort0]> {
190 let Latency = 10;
191 let ResourceCycles = [3];
192}
193def : WriteRes<WritePCmpIStrMLd, [HWPort0, HWPort23]> {
194 let Latency = 10;
195 let ResourceCycles = [3, 1];
196}
197
198// Packed Compare Explicit Length Strings, Return Mask
199def : WriteRes<WritePCmpEStrM, [HWPort0, HWPort16, HWPort5]> {
200 let Latency = 10;
201 let ResourceCycles = [3, 2, 4];
202}
203def : WriteRes<WritePCmpEStrMLd, [HWPort05, HWPort16, HWPort23]> {
204 let Latency = 10;
205 let ResourceCycles = [6, 2, 1];
206}
207
208// Packed Compare Implicit Length Strings, Return Index
209def : WriteRes<WritePCmpIStrI, [HWPort0]> {
210 let Latency = 11;
211 let ResourceCycles = [3];
212}
213def : WriteRes<WritePCmpIStrILd, [HWPort0, HWPort23]> {
214 let Latency = 11;
215 let ResourceCycles = [3, 1];
216}
217
218// Packed Compare Explicit Length Strings, Return Index
219def : WriteRes<WritePCmpEStrI, [HWPort05, HWPort16]> {
220 let Latency = 11;
221 let ResourceCycles = [6, 2];
222}
223def : WriteRes<WritePCmpEStrILd, [HWPort0, HWPort16, HWPort5, HWPort23]> {
224 let Latency = 11;
225 let ResourceCycles = [3, 2, 2, 1];
226}
227
228// AES Instructions.
229def : WriteRes<WriteAESDecEnc, [HWPort5]> {
230 let Latency = 7;
231 let ResourceCycles = [1];
232}
233def : WriteRes<WriteAESDecEncLd, [HWPort5, HWPort23]> {
234 let Latency = 7;
235 let ResourceCycles = [1, 1];
236}
237
238def : WriteRes<WriteAESIMC, [HWPort5]> {
239 let Latency = 14;
240 let ResourceCycles = [2];
241}
242def : WriteRes<WriteAESIMCLd, [HWPort5, HWPort23]> {
243 let Latency = 14;
244 let ResourceCycles = [2, 1];
245}
246
247def : WriteRes<WriteAESKeyGen, [HWPort0, HWPort5]> {
248 let Latency = 10;
249 let ResourceCycles = [2, 8];
250}
251def : WriteRes<WriteAESKeyGenLd, [HWPort0, HWPort5, HWPort23]> {
252 let Latency = 10;
253 let ResourceCycles = [2, 7, 1];
254}
255
256// Carry-less multiplication instructions.
257def : WriteRes<WriteCLMul, [HWPort0, HWPort5]> {
258 let Latency = 7;
259 let ResourceCycles = [2, 1];
260}
261def : WriteRes<WriteCLMulLd, [HWPort0, HWPort5, HWPort23]> {
262 let Latency = 7;
263 let ResourceCycles = [2, 1, 1];
264}
Nadav Roteme7b6a8a2013-03-28 22:34:46 +0000265
266def : WriteRes<WriteSystem, [HWPort0156]> { let Latency = 100; }
267def : WriteRes<WriteMicrocoded, [HWPort0156]> { let Latency = 100; }
Quentin Colombetca498512014-02-24 19:33:51 +0000268def : WriteRes<WriteFence, [HWPort23, HWPort4]>;
269def : WriteRes<WriteNop, []>;
Quentin Colombet35d37b72014-08-18 17:55:08 +0000270
Michael Zuckermanf6684002017-06-28 11:23:31 +0000271//================ Exceptions ================//
272
273//-- Specific Scheduling Models --//
274
275// Starting with P0.
276def WriteP0 : SchedWriteRes<[HWPort0]>;
277
278def WriteP0_P1_Lat4 : SchedWriteRes<[HWPort0, HWPort1]> {
279 let Latency = 4;
280 let NumMicroOps = 2;
281 let ResourceCycles = [1, 1];
282}
283
284def WriteP0_P1_Lat4Ld : SchedWriteRes<[HWPort0, HWPort1, HWPort23]> {
285 let Latency = 8;
286 let NumMicroOps = 3;
287 let ResourceCycles = [1, 1, 1];
288}
289
290def WriteP01 : SchedWriteRes<[HWPort01]>;
291
292def Write2P01 : SchedWriteRes<[HWPort01]> {
293 let NumMicroOps = 2;
294}
295def Write3P01 : SchedWriteRes<[HWPort01]> {
296 let NumMicroOps = 3;
297}
298
299def WriteP015 : SchedWriteRes<[HWPort015]>;
300
301def WriteP01_P5 : SchedWriteRes<[HWPort01, HWPort5]> {
302 let NumMicroOps = 2;
303}
304def WriteP06 : SchedWriteRes<[HWPort06]>;
305
306def Write2P06 : SchedWriteRes<[HWPort06]> {
307 let Latency = 1;
308 let NumMicroOps = 2;
309 let ResourceCycles = [2];
310}
311
312def Write3P06_Lat2 : SchedWriteRes<[HWPort06]> {
313 let Latency = 2;
314 let NumMicroOps = 3;
315 let ResourceCycles = [3];
316}
317
318def WriteP0156_P23 : SchedWriteRes<[HWPort0156, HWPort23]> {
319 let NumMicroOps = 2;
320}
321
322def Write2P0156_P23 : SchedWriteRes<[HWPort0156, HWPort23]> {
323 let NumMicroOps = 3;
324 let ResourceCycles = [2, 1];
325}
326
327def Write2P0156_Lat2 : SchedWriteRes<[HWPort0156]> {
328 let Latency = 2;
329 let ResourceCycles = [2];
330}
331def Write2P0156_Lat2Ld : SchedWriteRes<[HWPort0156, HWPort23]> {
332 let Latency = 6;
333 let ResourceCycles = [2, 1];
334}
335
336def Write5P0156 : SchedWriteRes<[HWPort0156]> {
337 let NumMicroOps = 5;
338 let ResourceCycles = [5];
339}
340
341def WriteP0156_2P237_P4 : SchedWriteRes<[HWPort0156, HWPort237, HWPort4]> {
342 let Latency = 1;
343 let ResourceCycles = [1, 2, 1];
344}
345
346def Write2P0156_2P237_P4 : SchedWriteRes<[HWPort0156, HWPort237, HWPort4]> {
347 let Latency = 1;
348 let ResourceCycles = [2, 2, 1];
349}
350
351def Write3P0156_2P237_P4 : SchedWriteRes<[HWPort0156, HWPort237, HWPort4]> {
352 let Latency = 1;
353 let ResourceCycles = [3, 2, 1];
354}
355
356// Starting with P1.
357def WriteP1 : SchedWriteRes<[HWPort1]>;
358
359def WriteP1_P23 : SchedWriteRes<[HWPort1, HWPort23]> {
360 let NumMicroOps = 2;
361}
362def WriteP1_Lat3 : SchedWriteRes<[HWPort1]> {
363 let Latency = 3;
364}
365def WriteP1_Lat3Ld : SchedWriteRes<[HWPort1, HWPort23]> {
366 let Latency = 7;
367}
368
369def Write2P1 : SchedWriteRes<[HWPort1]> {
370 let NumMicroOps = 2;
371 let ResourceCycles = [2];
372}
373def Write2P1_P23 : SchedWriteRes<[HWPort1, HWPort23]> {
374 let NumMicroOps = 3;
375 let ResourceCycles = [2, 1];
376}
377def WriteP15 : SchedWriteRes<[HWPort15]>;
378def WriteP15Ld : SchedWriteRes<[HWPort15, HWPort23]> {
379 let Latency = 4;
380}
381
382def WriteP1_P5_Lat4 : SchedWriteRes<[HWPort1, HWPort5]> {
383 let Latency = 4;
384 let NumMicroOps = 2;
385 let ResourceCycles = [1, 1];
386}
387
388def WriteP1_P5_Lat4Ld : SchedWriteRes<[HWPort1, HWPort5, HWPort23]> {
389 let Latency = 8;
390 let NumMicroOps = 3;
391 let ResourceCycles = [1, 1, 1];
392}
393
394def WriteP1_P5_Lat6 : SchedWriteRes<[HWPort1, HWPort5]> {
395 let Latency = 6;
396 let NumMicroOps = 2;
397 let ResourceCycles = [1, 1];
398}
399
400def WriteP1_P5_Lat6Ld : SchedWriteRes<[HWPort1, HWPort5, HWPort23]> {
401 let Latency = 10;
402 let NumMicroOps = 3;
403 let ResourceCycles = [1, 1, 1];
404}
405
406// Starting with P2.
407def Write2P237_P4 : SchedWriteRes<[HWPort237, HWPort4]> {
408 let Latency = 1;
409 let ResourceCycles = [2, 1];
410}
411
412// Starting with P5.
413def WriteP5 : SchedWriteRes<[HWPort5]>;
414def WriteP5Ld : SchedWriteRes<[HWPort5, HWPort23]> {
415 let Latency = 5;
416 let NumMicroOps = 2;
417 let ResourceCycles = [1, 1];
418}
419
420// Notation:
421// - r: register.
422// - mm: 64 bit mmx register.
423// - x = 128 bit xmm register.
424// - (x)mm = mmx or xmm register.
425// - y = 256 bit ymm register.
426// - v = any vector register.
427// - m = memory.
428
429//=== Integer Instructions ===//
430//-- Move instructions --//
431
432// MOV.
433// r16,m.
434def : InstRW<[WriteALULd], (instregex "MOV16rm")>;
435
436// MOVSX, MOVZX.
437// r,m.
Gadi Haber2cf601f2017-12-08 09:48:44 +0000438def : InstRW<[WriteLoad], (instregex "MOV(S|Z)X32rm8")>;
Michael Zuckermanf6684002017-06-28 11:23:31 +0000439
Michael Zuckermanf6684002017-06-28 11:23:31 +0000440// XLAT.
441def WriteXLAT : SchedWriteRes<[]> {
442 let Latency = 7;
443 let NumMicroOps = 3;
444}
445def : InstRW<[WriteXLAT], (instregex "XLAT")>;
446
447// PUSH.
448// m.
449def : InstRW<[Write2P237_P4], (instregex "PUSH(16|32)rmm")>;
450
Michael Zuckermanf6684002017-06-28 11:23:31 +0000451// PUSHA.
452def WritePushA : SchedWriteRes<[]> {
453 let NumMicroOps = 19;
454}
455def : InstRW<[WritePushA], (instregex "PUSHA(16|32)")>;
456
457// POP.
458// m.
459def : InstRW<[Write2P237_P4], (instregex "POP(16|32)rmm")>;
460
Michael Zuckermanf6684002017-06-28 11:23:31 +0000461// POPA.
462def WritePopA : SchedWriteRes<[]> {
463 let NumMicroOps = 18;
464}
465def : InstRW<[WritePopA], (instregex "POPA(16|32)")>;
466
Michael Zuckermanf6684002017-06-28 11:23:31 +0000467//-- Arithmetic instructions --//
468
Michael Zuckermanf6684002017-06-28 11:23:31 +0000469// DIV.
470// r8.
471def WriteDiv8 : SchedWriteRes<[HWPort0, HWPort1, HWPort5, HWPort6]> {
472 let Latency = 22;
473 let NumMicroOps = 9;
474}
475def : InstRW<[WriteDiv8], (instregex "DIV8r")>;
476
Michael Zuckermanf6684002017-06-28 11:23:31 +0000477// IDIV.
478// r8.
479def WriteIDiv8 : SchedWriteRes<[HWPort0, HWPort1, HWPort5, HWPort6]> {
480 let Latency = 23;
481 let NumMicroOps = 9;
482}
483def : InstRW<[WriteIDiv8], (instregex "IDIV8r")>;
484
Michael Zuckermanf6684002017-06-28 11:23:31 +0000485// BT.
Michael Zuckermanf6684002017-06-28 11:23:31 +0000486// m,r.
487def WriteBTmr : SchedWriteRes<[]> {
488 let NumMicroOps = 10;
489}
490def : InstRW<[WriteBTmr], (instregex "BT(16|32|64)mr")>;
491
Michael Zuckermanf6684002017-06-28 11:23:31 +0000492// BTR BTS BTC.
Michael Zuckermanf6684002017-06-28 11:23:31 +0000493// m,r.
494def WriteBTRSCmr : SchedWriteRes<[]> {
495 let NumMicroOps = 11;
496}
497def : InstRW<[WriteBTRSCmr], (instregex "BT(R|S|C)(16|32|64)mr")>;
498
Michael Zuckermanf6684002017-06-28 11:23:31 +0000499//-- Control transfer instructions --//
500
Michael Zuckermanf6684002017-06-28 11:23:31 +0000501// CALL.
Michael Zuckermanf6684002017-06-28 11:23:31 +0000502// i.
503def WriteRETI : SchedWriteRes<[HWPort23, HWPort6, HWPort015]> {
504 let NumMicroOps = 4;
505 let ResourceCycles = [1, 2, 1];
506}
507def : InstRW<[WriteRETI], (instregex "RETI(L|Q|W)", "LRETI(L|Q|W)")>;
508
509// BOUND.
510// r,m.
511def WriteBOUND : SchedWriteRes<[]> {
512 let NumMicroOps = 15;
513}
514def : InstRW<[WriteBOUND], (instregex "BOUNDS(16|32)rm")>;
515
516// INTO.
517def WriteINTO : SchedWriteRes<[]> {
518 let NumMicroOps = 4;
519}
520def : InstRW<[WriteINTO], (instregex "INTO")>;
521
522//-- String instructions --//
523
524// LODSB/W.
525def : InstRW<[Write2P0156_P23], (instregex "LODS(B|W)")>;
526
527// LODSD/Q.
528def : InstRW<[WriteP0156_P23], (instregex "LODS(L|Q)")>;
529
Michael Zuckermanf6684002017-06-28 11:23:31 +0000530// MOVS.
531def WriteMOVS : SchedWriteRes<[HWPort23, HWPort4, HWPort0156]> {
532 let Latency = 4;
533 let NumMicroOps = 5;
534 let ResourceCycles = [2, 1, 2];
535}
536def : InstRW<[WriteMOVS], (instregex "MOVS(B|L|Q|W)")>;
537
Michael Zuckermanf6684002017-06-28 11:23:31 +0000538// CMPS.
539def WriteCMPS : SchedWriteRes<[HWPort23, HWPort0156]> {
540 let Latency = 4;
541 let NumMicroOps = 5;
542 let ResourceCycles = [2, 3];
543}
544def : InstRW<[WriteCMPS], (instregex "CMPS(B|L|Q|W)")>;
545
Michael Zuckermanf6684002017-06-28 11:23:31 +0000546//-- Other --//
547
Gadi Haberd76f7b82017-08-28 10:04:16 +0000548// RDPMC.f
Michael Zuckermanf6684002017-06-28 11:23:31 +0000549def WriteRDPMC : SchedWriteRes<[]> {
550 let NumMicroOps = 34;
551}
552def : InstRW<[WriteRDPMC], (instregex "RDPMC")>;
553
554// RDRAND.
555def WriteRDRAND : SchedWriteRes<[HWPort23, HWPort015]> {
556 let NumMicroOps = 17;
557 let ResourceCycles = [1, 16];
558}
559def : InstRW<[WriteRDRAND], (instregex "RDRAND(16|32|64)r")>;
560
561//=== Floating Point x87 Instructions ===//
562//-- Move instructions --//
563
564// FLD.
565// m80.
566def : InstRW<[WriteP01], (instregex "LD_Frr")>;
567
Michael Zuckermanf6684002017-06-28 11:23:31 +0000568// FBLD.
569// m80.
570def WriteFBLD : SchedWriteRes<[]> {
571 let Latency = 47;
572 let NumMicroOps = 43;
573}
574def : InstRW<[WriteFBLD], (instregex "FBLDm")>;
575
576// FST(P).
577// r.
578def : InstRW<[WriteP01], (instregex "ST_(F|FP)rr")>;
579
Michael Zuckermanf6684002017-06-28 11:23:31 +0000580// FLDZ.
581def : InstRW<[WriteP01], (instregex "LD_F0")>;
582
Michael Zuckermanf6684002017-06-28 11:23:31 +0000583// FLDPI FLDL2E etc.
584def : InstRW<[Write2P01], (instregex "FLDPI", "FLDL2(T|E)" "FLDL(G|N)2")>;
585
Michael Zuckermanf6684002017-06-28 11:23:31 +0000586// FFREE.
587def : InstRW<[WriteP01], (instregex "FFREE")>;
588
589// FNSAVE.
590def WriteFNSAVE : SchedWriteRes<[]> {
591 let NumMicroOps = 147;
592}
593def : InstRW<[WriteFNSAVE], (instregex "FSAVEm")>;
594
595// FRSTOR.
596def WriteFRSTOR : SchedWriteRes<[]> {
597 let NumMicroOps = 90;
598}
599def : InstRW<[WriteFRSTOR], (instregex "FRSTORm")>;
600
601//-- Arithmetic instructions --//
602
603// FABS.
604def : InstRW<[WriteP0], (instregex "ABS_F")>;
605
606// FCHS.
607def : InstRW<[WriteP0], (instregex "CHS_F")>;
608
Michael Zuckermanf6684002017-06-28 11:23:31 +0000609// FCOMPP FUCOMPP.
610// r.
611def : InstRW<[Write2P01], (instregex "FCOMPP", "UCOM_FPPr")>;
612
613// FCOMI(P) FUCOMI(P).
614// m.
615def : InstRW<[Write3P01], (instregex "COM_FIr", "COM_FIPr", "UCOM_FIr",
616 "UCOM_FIPr")>;
617
Michael Zuckermanf6684002017-06-28 11:23:31 +0000618// FTST.
619def : InstRW<[WriteP1], (instregex "TST_F")>;
620
621// FXAM.
622def : InstRW<[Write2P1], (instregex "FXAM")>;
623
624// FPREM.
625def WriteFPREM : SchedWriteRes<[]> {
626 let Latency = 19;
627 let NumMicroOps = 28;
628}
629def : InstRW<[WriteFPREM], (instregex "FPREM")>;
630
631// FPREM1.
632def WriteFPREM1 : SchedWriteRes<[]> {
633 let Latency = 27;
634 let NumMicroOps = 41;
635}
636def : InstRW<[WriteFPREM1], (instregex "FPREM1")>;
637
638// FRNDINT.
639def WriteFRNDINT : SchedWriteRes<[]> {
640 let Latency = 11;
641 let NumMicroOps = 17;
642}
643def : InstRW<[WriteFRNDINT], (instregex "FRNDINT")>;
644
645//-- Math instructions --//
646
647// FSCALE.
648def WriteFSCALE : SchedWriteRes<[]> {
649 let Latency = 75; // 49-125
650 let NumMicroOps = 50; // 25-75
651}
652def : InstRW<[WriteFSCALE], (instregex "FSCALE")>;
653
654// FXTRACT.
655def WriteFXTRACT : SchedWriteRes<[]> {
656 let Latency = 15;
657 let NumMicroOps = 17;
658}
659def : InstRW<[WriteFXTRACT], (instregex "FXTRACT")>;
660
661//-- Other instructions --//
662
663// FNOP.
664def : InstRW<[WriteP01], (instregex "FNOP")>;
665
666// WAIT.
667def : InstRW<[Write2P01], (instregex "WAIT")>;
668
669// FNCLEX.
670def : InstRW<[Write5P0156], (instregex "FNCLEX")>;
671
672// FNINIT.
673def WriteFNINIT : SchedWriteRes<[]> {
674 let NumMicroOps = 26;
675}
676def : InstRW<[WriteFNINIT], (instregex "FNINIT")>;
677
Andrew V. Tischenko8cb1d092017-06-08 16:44:13 +0000678////////////////////////////////////////////////////////////////////////////////
679// Horizontal add/sub instructions.
680////////////////////////////////////////////////////////////////////////////////
681
682// HADD, HSUB PS/PD
683// x,x / v,v,v.
684def : WriteRes<WriteFHAdd, [HWPort1, HWPort5]> {
685 let Latency = 5;
686 let NumMicroOps = 3;
687 let ResourceCycles = [1, 2];
688}
689
690// x,m / v,v,m.
691def : WriteRes<WriteFHAddLd, [HWPort1, HWPort5, HWPort23]> {
692 let Latency = 9;
693 let NumMicroOps = 4;
694 let ResourceCycles = [1, 2, 1];
695}
696
697// PHADD|PHSUB (S) W/D.
698// v <- v,v.
699def : WriteRes<WritePHAdd, [HWPort1, HWPort5]> {
700 let Latency = 3;
701 let NumMicroOps = 3;
702 let ResourceCycles = [1, 2];
703}
704// v <- v,m.
705def : WriteRes<WritePHAddLd, [HWPort1, HWPort5, HWPort23]> {
706 let Latency = 6;
707 let NumMicroOps = 3;
708 let ResourceCycles = [1, 2, 1];
709}
710
Michael Zuckermanf6684002017-06-28 11:23:31 +0000711//=== Floating Point XMM and YMM Instructions ===//
Gadi Haber13759a72017-06-27 15:05:13 +0000712
Gadi Haberd76f7b82017-08-28 10:04:16 +0000713// Remaining instrs.
Michael Zuckermanf6684002017-06-28 11:23:31 +0000714
Gadi Haberd76f7b82017-08-28 10:04:16 +0000715def HWWriteResGroup0 : SchedWriteRes<[HWPort23]> {
Gadi Haber2cf601f2017-12-08 09:48:44 +0000716 let Latency = 6;
Gadi Haberd76f7b82017-08-28 10:04:16 +0000717 let NumMicroOps = 1;
718 let ResourceCycles = [1];
719}
720def: InstRW<[HWWriteResGroup0], (instregex "LDDQUrm")>;
Gadi Haberd76f7b82017-08-28 10:04:16 +0000721def: InstRW<[HWWriteResGroup0], (instregex "MOVAPDrm")>;
722def: InstRW<[HWWriteResGroup0], (instregex "MOVAPSrm")>;
Gadi Haberd76f7b82017-08-28 10:04:16 +0000723def: InstRW<[HWWriteResGroup0], (instregex "MOVDQArm")>;
724def: InstRW<[HWWriteResGroup0], (instregex "MOVDQUrm")>;
725def: InstRW<[HWWriteResGroup0], (instregex "MOVNTDQArm")>;
726def: InstRW<[HWWriteResGroup0], (instregex "MOVSHDUPrm")>;
727def: InstRW<[HWWriteResGroup0], (instregex "MOVSLDUPrm")>;
Gadi Haberd76f7b82017-08-28 10:04:16 +0000728def: InstRW<[HWWriteResGroup0], (instregex "MOVUPDrm")>;
729def: InstRW<[HWWriteResGroup0], (instregex "MOVUPSrm")>;
Gadi Haberd76f7b82017-08-28 10:04:16 +0000730def: InstRW<[HWWriteResGroup0], (instregex "VBROADCASTSSrm")>;
Gadi Haberd76f7b82017-08-28 10:04:16 +0000731def: InstRW<[HWWriteResGroup0], (instregex "VLDDQUrm")>;
Gadi Haberd76f7b82017-08-28 10:04:16 +0000732def: InstRW<[HWWriteResGroup0], (instregex "VMOVAPDrm")>;
Gadi Haberd76f7b82017-08-28 10:04:16 +0000733def: InstRW<[HWWriteResGroup0], (instregex "VMOVAPSrm")>;
Gadi Haberd76f7b82017-08-28 10:04:16 +0000734def: InstRW<[HWWriteResGroup0], (instregex "VMOVDQArm")>;
Gadi Haberd76f7b82017-08-28 10:04:16 +0000735def: InstRW<[HWWriteResGroup0], (instregex "VMOVDQUrm")>;
Gadi Haberd76f7b82017-08-28 10:04:16 +0000736def: InstRW<[HWWriteResGroup0], (instregex "VMOVNTDQArm")>;
Gadi Haberd76f7b82017-08-28 10:04:16 +0000737def: InstRW<[HWWriteResGroup0], (instregex "VMOVSHDUPrm")>;
Gadi Haberd76f7b82017-08-28 10:04:16 +0000738def: InstRW<[HWWriteResGroup0], (instregex "VMOVSLDUPrm")>;
Gadi Haberd76f7b82017-08-28 10:04:16 +0000739def: InstRW<[HWWriteResGroup0], (instregex "VMOVUPDrm")>;
Gadi Haberd76f7b82017-08-28 10:04:16 +0000740def: InstRW<[HWWriteResGroup0], (instregex "VMOVUPSrm")>;
Gadi Haberd76f7b82017-08-28 10:04:16 +0000741def: InstRW<[HWWriteResGroup0], (instregex "VPBROADCASTDrm")>;
Gadi Haberd76f7b82017-08-28 10:04:16 +0000742def: InstRW<[HWWriteResGroup0], (instregex "VPBROADCASTQrm")>;
Gadi Haber2cf601f2017-12-08 09:48:44 +0000743def: InstRW<[HWWriteResGroup0], (instregex "ROUNDPDr")>;
744def: InstRW<[HWWriteResGroup0], (instregex "ROUNDPSr")>;
745def: InstRW<[HWWriteResGroup0], (instregex "ROUNDSDr")>;
746def: InstRW<[HWWriteResGroup0], (instregex "ROUNDSSr")>;
747def: InstRW<[HWWriteResGroup0], (instregex "VROUNDPDr")>;
748def: InstRW<[HWWriteResGroup0], (instregex "VROUNDPSr")>;
749def: InstRW<[HWWriteResGroup0], (instregex "VROUNDSDr")>;
750def: InstRW<[HWWriteResGroup0], (instregex "VROUNDSSr")>;
751def: InstRW<[HWWriteResGroup0], (instregex "VROUNDYPDr")>;
752def: InstRW<[HWWriteResGroup0], (instregex "VROUNDYPSr")>;
753
754def HWWriteResGroup0_1 : SchedWriteRes<[HWPort23]> {
755 let Latency = 7;
756 let NumMicroOps = 1;
757 let ResourceCycles = [1];
758}
759def: InstRW<[HWWriteResGroup0_1], (instregex "LD_F32m")>;
760def: InstRW<[HWWriteResGroup0_1], (instregex "LD_F64m")>;
761def: InstRW<[HWWriteResGroup0_1], (instregex "LD_F80m")>;
762def: InstRW<[HWWriteResGroup0_1], (instregex "VBROADCASTF128")>;
763def: InstRW<[HWWriteResGroup0_1], (instregex "VBROADCASTI128")>;
764def: InstRW<[HWWriteResGroup0_1], (instregex "VBROADCASTSDYrm")>;
765def: InstRW<[HWWriteResGroup0_1], (instregex "VBROADCASTSSYrm")>;
766def: InstRW<[HWWriteResGroup0_1], (instregex "VLDDQUYrm")>;
767def: InstRW<[HWWriteResGroup0_1], (instregex "VMOVAPDYrm")>;
768def: InstRW<[HWWriteResGroup0_1], (instregex "VMOVAPSYrm")>;
769def: InstRW<[HWWriteResGroup0_1], (instregex "VMOVDDUPYrm")>;
770def: InstRW<[HWWriteResGroup0_1], (instregex "VMOVDQAYrm")>;
771def: InstRW<[HWWriteResGroup0_1], (instregex "VMOVDQUYrm")>;
772def: InstRW<[HWWriteResGroup0_1], (instregex "VMOVNTDQAYrm")>;
773def: InstRW<[HWWriteResGroup0_1], (instregex "VMOVSHDUPYrm")>;
774def: InstRW<[HWWriteResGroup0_1], (instregex "VMOVSLDUPYrm")>;
775def: InstRW<[HWWriteResGroup0_1], (instregex "VMOVUPDYrm")>;
776def: InstRW<[HWWriteResGroup0_1], (instregex "VMOVUPSYrm")>;
777def: InstRW<[HWWriteResGroup0_1], (instregex "VPBROADCASTDYrm")>;
778def: InstRW<[HWWriteResGroup0_1], (instregex "VPBROADCASTQYrm")>;
779
780def HWWriteResGroup0_2 : SchedWriteRes<[HWPort23]> {
781 let Latency = 5;
782 let NumMicroOps = 1;
783 let ResourceCycles = [1];
784}
785def: InstRW<[HWWriteResGroup0_2], (instregex "MMX_MOVD64from64rm")>;
786def: InstRW<[HWWriteResGroup0_2], (instregex "MMX_MOVD64rm")>;
787def: InstRW<[HWWriteResGroup0_2], (instregex "MMX_MOVD64to64rm")>;
788def: InstRW<[HWWriteResGroup0_2], (instregex "MMX_MOVQ64rm")>;
789def: InstRW<[HWWriteResGroup0_2], (instregex "MOV(16|32|64)rm")>;
790def: InstRW<[HWWriteResGroup0_2], (instregex "MOV64toPQIrm")>;
791def: InstRW<[HWWriteResGroup0_2], (instregex "MOV8rm")>;
792def: InstRW<[HWWriteResGroup0_2], (instregex "MOVDDUPrm")>;
793def: InstRW<[HWWriteResGroup0_2], (instregex "MOVDI2PDIrm")>;
794def: InstRW<[HWWriteResGroup0_2], (instregex "MOVSSrm")>;
795def: InstRW<[HWWriteResGroup0_2], (instregex "MOVSX(16|32|64)rm16")>;
796def: InstRW<[HWWriteResGroup0_2], (instregex "MOVSX(16|32|64)rm32")>;
797def: InstRW<[HWWriteResGroup0_2], (instregex "MOVSX(16|32|64)rm8")>;
798def: InstRW<[HWWriteResGroup0_2], (instregex "MOVZX(16|32|64)rm16")>;
799def: InstRW<[HWWriteResGroup0_2], (instregex "MOVZX(16|32|64)rm8")>;
800def: InstRW<[HWWriteResGroup0_2], (instregex "PREFETCHNTA")>;
801def: InstRW<[HWWriteResGroup0_2], (instregex "PREFETCHT0")>;
802def: InstRW<[HWWriteResGroup0_2], (instregex "PREFETCHT1")>;
803def: InstRW<[HWWriteResGroup0_2], (instregex "PREFETCHT2")>;
804def: InstRW<[HWWriteResGroup0_2], (instregex "VMOV64toPQIrm")>;
805def: InstRW<[HWWriteResGroup0_2], (instregex "VMOVDDUPrm")>;
806def: InstRW<[HWWriteResGroup0_2], (instregex "VMOVDI2PDIrm")>;
807def: InstRW<[HWWriteResGroup0_2], (instregex "VMOVQI2PQIrm")>;
808def: InstRW<[HWWriteResGroup0_2], (instregex "VMOVSDrm")>;
809def: InstRW<[HWWriteResGroup0_2], (instregex "VMOVSSrm")>;
Michael Zuckermanf6684002017-06-28 11:23:31 +0000810
Gadi Haberd76f7b82017-08-28 10:04:16 +0000811def HWWriteResGroup1 : SchedWriteRes<[HWPort4,HWPort237]> {
812 let Latency = 1;
Michael Zuckermanf6684002017-06-28 11:23:31 +0000813 let NumMicroOps = 2;
Gadi Haberd76f7b82017-08-28 10:04:16 +0000814 let ResourceCycles = [1,1];
Michael Zuckermanf6684002017-06-28 11:23:31 +0000815}
Gadi Haberd76f7b82017-08-28 10:04:16 +0000816def: InstRW<[HWWriteResGroup1], (instregex "FBSTPm")>;
817def: InstRW<[HWWriteResGroup1], (instregex "MMX_MOVD64from64rm")>;
818def: InstRW<[HWWriteResGroup1], (instregex "MMX_MOVD64mr")>;
819def: InstRW<[HWWriteResGroup1], (instregex "MMX_MOVNTQmr")>;
820def: InstRW<[HWWriteResGroup1], (instregex "MMX_MOVQ64mr")>;
821def: InstRW<[HWWriteResGroup1], (instregex "MOV(16|32|64)mr")>;
822def: InstRW<[HWWriteResGroup1], (instregex "MOV8mi")>;
823def: InstRW<[HWWriteResGroup1], (instregex "MOV8mr")>;
824def: InstRW<[HWWriteResGroup1], (instregex "MOVAPDmr")>;
825def: InstRW<[HWWriteResGroup1], (instregex "MOVAPSmr")>;
826def: InstRW<[HWWriteResGroup1], (instregex "MOVDQAmr")>;
827def: InstRW<[HWWriteResGroup1], (instregex "MOVDQUmr")>;
828def: InstRW<[HWWriteResGroup1], (instregex "MOVHPDmr")>;
829def: InstRW<[HWWriteResGroup1], (instregex "MOVHPSmr")>;
830def: InstRW<[HWWriteResGroup1], (instregex "MOVLPDmr")>;
831def: InstRW<[HWWriteResGroup1], (instregex "MOVLPSmr")>;
832def: InstRW<[HWWriteResGroup1], (instregex "MOVNTDQmr")>;
833def: InstRW<[HWWriteResGroup1], (instregex "MOVNTI_64mr")>;
834def: InstRW<[HWWriteResGroup1], (instregex "MOVNTImr")>;
835def: InstRW<[HWWriteResGroup1], (instregex "MOVNTPDmr")>;
836def: InstRW<[HWWriteResGroup1], (instregex "MOVNTPSmr")>;
837def: InstRW<[HWWriteResGroup1], (instregex "MOVPDI2DImr")>;
838def: InstRW<[HWWriteResGroup1], (instregex "MOVPQI2QImr")>;
839def: InstRW<[HWWriteResGroup1], (instregex "MOVPQIto64mr")>;
840def: InstRW<[HWWriteResGroup1], (instregex "MOVSSmr")>;
841def: InstRW<[HWWriteResGroup1], (instregex "MOVUPDmr")>;
842def: InstRW<[HWWriteResGroup1], (instregex "MOVUPSmr")>;
843def: InstRW<[HWWriteResGroup1], (instregex "ST_FP32m")>;
844def: InstRW<[HWWriteResGroup1], (instregex "ST_FP64m")>;
845def: InstRW<[HWWriteResGroup1], (instregex "ST_FP80m")>;
846def: InstRW<[HWWriteResGroup1], (instregex "VEXTRACTF128mr")>;
847def: InstRW<[HWWriteResGroup1], (instregex "VEXTRACTI128mr")>;
848def: InstRW<[HWWriteResGroup1], (instregex "VMOVAPDYmr")>;
849def: InstRW<[HWWriteResGroup1], (instregex "VMOVAPDmr")>;
850def: InstRW<[HWWriteResGroup1], (instregex "VMOVAPSYmr")>;
851def: InstRW<[HWWriteResGroup1], (instregex "VMOVAPSmr")>;
852def: InstRW<[HWWriteResGroup1], (instregex "VMOVDQAYmr")>;
853def: InstRW<[HWWriteResGroup1], (instregex "VMOVDQAmr")>;
854def: InstRW<[HWWriteResGroup1], (instregex "VMOVDQUYmr")>;
855def: InstRW<[HWWriteResGroup1], (instregex "VMOVDQUmr")>;
856def: InstRW<[HWWriteResGroup1], (instregex "VMOVHPDmr")>;
857def: InstRW<[HWWriteResGroup1], (instregex "VMOVHPSmr")>;
858def: InstRW<[HWWriteResGroup1], (instregex "VMOVLPDmr")>;
859def: InstRW<[HWWriteResGroup1], (instregex "VMOVLPSmr")>;
860def: InstRW<[HWWriteResGroup1], (instregex "VMOVNTDQYmr")>;
861def: InstRW<[HWWriteResGroup1], (instregex "VMOVNTDQmr")>;
862def: InstRW<[HWWriteResGroup1], (instregex "VMOVNTPDYmr")>;
863def: InstRW<[HWWriteResGroup1], (instregex "VMOVNTPDmr")>;
864def: InstRW<[HWWriteResGroup1], (instregex "VMOVNTPSYmr")>;
865def: InstRW<[HWWriteResGroup1], (instregex "VMOVNTPSmr")>;
866def: InstRW<[HWWriteResGroup1], (instregex "VMOVPDI2DImr")>;
867def: InstRW<[HWWriteResGroup1], (instregex "VMOVPQI2QImr")>;
868def: InstRW<[HWWriteResGroup1], (instregex "VMOVPQIto64mr")>;
869def: InstRW<[HWWriteResGroup1], (instregex "VMOVSDmr")>;
870def: InstRW<[HWWriteResGroup1], (instregex "VMOVSSmr")>;
871def: InstRW<[HWWriteResGroup1], (instregex "VMOVUPDYmr")>;
872def: InstRW<[HWWriteResGroup1], (instregex "VMOVUPDmr")>;
873def: InstRW<[HWWriteResGroup1], (instregex "VMOVUPSYmr")>;
874def: InstRW<[HWWriteResGroup1], (instregex "VMOVUPSmr")>;
875def: InstRW<[HWWriteResGroup1], (instregex "VMPTRSTm")>;
Michael Zuckermanf6684002017-06-28 11:23:31 +0000876
Gadi Haberd76f7b82017-08-28 10:04:16 +0000877def HWWriteResGroup2 : SchedWriteRes<[HWPort0]> {
878 let Latency = 1;
879 let NumMicroOps = 1;
880 let ResourceCycles = [1];
881}
882def: InstRW<[HWWriteResGroup2], (instregex "MMX_MOVD64from64rr")>;
883def: InstRW<[HWWriteResGroup2], (instregex "MMX_MOVD64grr")>;
884def: InstRW<[HWWriteResGroup2], (instregex "MMX_PMOVMSKBrr")>;
885def: InstRW<[HWWriteResGroup2], (instregex "MMX_PSLLDri")>;
886def: InstRW<[HWWriteResGroup2], (instregex "MMX_PSLLDrr")>;
887def: InstRW<[HWWriteResGroup2], (instregex "MMX_PSLLQri")>;
888def: InstRW<[HWWriteResGroup2], (instregex "MMX_PSLLQrr")>;
889def: InstRW<[HWWriteResGroup2], (instregex "MMX_PSLLWri")>;
890def: InstRW<[HWWriteResGroup2], (instregex "MMX_PSLLWrr")>;
891def: InstRW<[HWWriteResGroup2], (instregex "MMX_PSRADri")>;
892def: InstRW<[HWWriteResGroup2], (instregex "MMX_PSRADrr")>;
893def: InstRW<[HWWriteResGroup2], (instregex "MMX_PSRAWri")>;
894def: InstRW<[HWWriteResGroup2], (instregex "MMX_PSRAWrr")>;
895def: InstRW<[HWWriteResGroup2], (instregex "MMX_PSRLDri")>;
896def: InstRW<[HWWriteResGroup2], (instregex "MMX_PSRLDrr")>;
897def: InstRW<[HWWriteResGroup2], (instregex "MMX_PSRLQri")>;
898def: InstRW<[HWWriteResGroup2], (instregex "MMX_PSRLQrr")>;
899def: InstRW<[HWWriteResGroup2], (instregex "MMX_PSRLWri")>;
900def: InstRW<[HWWriteResGroup2], (instregex "MMX_PSRLWrr")>;
901def: InstRW<[HWWriteResGroup2], (instregex "MOVPDI2DIrr")>;
902def: InstRW<[HWWriteResGroup2], (instregex "MOVPQIto64rr")>;
903def: InstRW<[HWWriteResGroup2], (instregex "PSLLDri")>;
904def: InstRW<[HWWriteResGroup2], (instregex "PSLLQri")>;
905def: InstRW<[HWWriteResGroup2], (instregex "PSLLWri")>;
906def: InstRW<[HWWriteResGroup2], (instregex "PSRADri")>;
907def: InstRW<[HWWriteResGroup2], (instregex "PSRAWri")>;
908def: InstRW<[HWWriteResGroup2], (instregex "PSRLDri")>;
909def: InstRW<[HWWriteResGroup2], (instregex "PSRLQri")>;
910def: InstRW<[HWWriteResGroup2], (instregex "PSRLWri")>;
911def: InstRW<[HWWriteResGroup2], (instregex "VMOVPDI2DIrr")>;
912def: InstRW<[HWWriteResGroup2], (instregex "VMOVPQIto64rr")>;
913def: InstRW<[HWWriteResGroup2], (instregex "VPSLLDYri")>;
914def: InstRW<[HWWriteResGroup2], (instregex "VPSLLDri")>;
915def: InstRW<[HWWriteResGroup2], (instregex "VPSLLQYri")>;
916def: InstRW<[HWWriteResGroup2], (instregex "VPSLLQri")>;
917def: InstRW<[HWWriteResGroup2], (instregex "VPSLLVQYrr")>;
918def: InstRW<[HWWriteResGroup2], (instregex "VPSLLVQrr")>;
919def: InstRW<[HWWriteResGroup2], (instregex "VPSLLWYri")>;
920def: InstRW<[HWWriteResGroup2], (instregex "VPSLLWri")>;
921def: InstRW<[HWWriteResGroup2], (instregex "VPSRADYri")>;
922def: InstRW<[HWWriteResGroup2], (instregex "VPSRADri")>;
923def: InstRW<[HWWriteResGroup2], (instregex "VPSRAWYri")>;
924def: InstRW<[HWWriteResGroup2], (instregex "VPSRAWri")>;
925def: InstRW<[HWWriteResGroup2], (instregex "VPSRLDYri")>;
926def: InstRW<[HWWriteResGroup2], (instregex "VPSRLDri")>;
927def: InstRW<[HWWriteResGroup2], (instregex "VPSRLQYri")>;
928def: InstRW<[HWWriteResGroup2], (instregex "VPSRLQri")>;
929def: InstRW<[HWWriteResGroup2], (instregex "VPSRLVQYrr")>;
930def: InstRW<[HWWriteResGroup2], (instregex "VPSRLVQrr")>;
931def: InstRW<[HWWriteResGroup2], (instregex "VPSRLWYri")>;
932def: InstRW<[HWWriteResGroup2], (instregex "VPSRLWri")>;
933def: InstRW<[HWWriteResGroup2], (instregex "VTESTPDYrr")>;
934def: InstRW<[HWWriteResGroup2], (instregex "VTESTPDrr")>;
935def: InstRW<[HWWriteResGroup2], (instregex "VTESTPSYrr")>;
936def: InstRW<[HWWriteResGroup2], (instregex "VTESTPSrr")>;
937
938def HWWriteResGroup3 : SchedWriteRes<[HWPort1]> {
939 let Latency = 1;
940 let NumMicroOps = 1;
941 let ResourceCycles = [1];
942}
943def: InstRW<[HWWriteResGroup3], (instregex "COMP_FST0r")>;
944def: InstRW<[HWWriteResGroup3], (instregex "COM_FST0r")>;
945def: InstRW<[HWWriteResGroup3], (instregex "MMX_MASKMOVQ64")>;
946def: InstRW<[HWWriteResGroup3], (instregex "MMX_MASKMOVQ64")>;
947def: InstRW<[HWWriteResGroup3], (instregex "UCOM_FPr")>;
948def: InstRW<[HWWriteResGroup3], (instregex "UCOM_Fr")>;
949def: InstRW<[HWWriteResGroup3], (instregex "VMASKMOVDQU")>;
950
951def HWWriteResGroup4 : SchedWriteRes<[HWPort5]> {
952 let Latency = 1;
953 let NumMicroOps = 1;
954 let ResourceCycles = [1];
955}
956def: InstRW<[HWWriteResGroup4], (instregex "ANDNPDrr")>;
957def: InstRW<[HWWriteResGroup4], (instregex "ANDNPSrr")>;
958def: InstRW<[HWWriteResGroup4], (instregex "ANDPDrr")>;
959def: InstRW<[HWWriteResGroup4], (instregex "ANDPSrr")>;
960def: InstRW<[HWWriteResGroup4], (instregex "INSERTPSrr")>;
961def: InstRW<[HWWriteResGroup4], (instregex "MMX_MOVD64rr")>;
962def: InstRW<[HWWriteResGroup4], (instregex "MMX_MOVD64to64rr")>;
963def: InstRW<[HWWriteResGroup4], (instregex "MMX_MOVQ2DQrr")>;
964def: InstRW<[HWWriteResGroup4], (instregex "MMX_PALIGNR64irr")>;
965def: InstRW<[HWWriteResGroup4], (instregex "MMX_PSHUFBrr64")>;
966def: InstRW<[HWWriteResGroup4], (instregex "MMX_PSHUFWri")>;
967def: InstRW<[HWWriteResGroup4], (instregex "MMX_PUNPCKHBWirr")>;
968def: InstRW<[HWWriteResGroup4], (instregex "MMX_PUNPCKHDQirr")>;
969def: InstRW<[HWWriteResGroup4], (instregex "MMX_PUNPCKHWDirr")>;
970def: InstRW<[HWWriteResGroup4], (instregex "MMX_PUNPCKLBWirr")>;
971def: InstRW<[HWWriteResGroup4], (instregex "MMX_PUNPCKLDQirr")>;
972def: InstRW<[HWWriteResGroup4], (instregex "MMX_PUNPCKLWDirr")>;
973def: InstRW<[HWWriteResGroup4], (instregex "MOV64toPQIrr")>;
974def: InstRW<[HWWriteResGroup4], (instregex "MOVAPDrr")>;
975def: InstRW<[HWWriteResGroup4], (instregex "MOVAPSrr")>;
976def: InstRW<[HWWriteResGroup4], (instregex "MOVDDUPrr")>;
977def: InstRW<[HWWriteResGroup4], (instregex "MOVDI2PDIrr")>;
978def: InstRW<[HWWriteResGroup4], (instregex "MOVHLPSrr")>;
979def: InstRW<[HWWriteResGroup4], (instregex "MOVLHPSrr")>;
980def: InstRW<[HWWriteResGroup4], (instregex "MOVSDrr(_REV?)")>;
981def: InstRW<[HWWriteResGroup4], (instregex "MOVSHDUPrr")>;
982def: InstRW<[HWWriteResGroup4], (instregex "MOVSLDUPrr")>;
983def: InstRW<[HWWriteResGroup4], (instregex "MOVSSrr(_REV?)")>;
984def: InstRW<[HWWriteResGroup4], (instregex "MOVUPDrr(_REV?)")>;
985def: InstRW<[HWWriteResGroup4], (instregex "MOVUPSrr(_REV?)")>;
986def: InstRW<[HWWriteResGroup4], (instregex "ORPDrr")>;
987def: InstRW<[HWWriteResGroup4], (instregex "ORPSrr")>;
988def: InstRW<[HWWriteResGroup4], (instregex "PACKSSDWrr")>;
989def: InstRW<[HWWriteResGroup4], (instregex "PACKSSWBrr")>;
990def: InstRW<[HWWriteResGroup4], (instregex "PACKUSDWrr")>;
991def: InstRW<[HWWriteResGroup4], (instregex "PACKUSWBrr")>;
992def: InstRW<[HWWriteResGroup4], (instregex "PALIGNRrri")>;
993def: InstRW<[HWWriteResGroup4], (instregex "PBLENDWrri")>;
994def: InstRW<[HWWriteResGroup4], (instregex "PMOVSXBDrr")>;
995def: InstRW<[HWWriteResGroup4], (instregex "PMOVSXBQrr")>;
996def: InstRW<[HWWriteResGroup4], (instregex "PMOVSXBWrr")>;
997def: InstRW<[HWWriteResGroup4], (instregex "PMOVSXDQrr")>;
998def: InstRW<[HWWriteResGroup4], (instregex "PMOVSXWDrr")>;
999def: InstRW<[HWWriteResGroup4], (instregex "PMOVSXWQrr")>;
1000def: InstRW<[HWWriteResGroup4], (instregex "PMOVZXBDrr")>;
1001def: InstRW<[HWWriteResGroup4], (instregex "PMOVZXBQrr")>;
1002def: InstRW<[HWWriteResGroup4], (instregex "PMOVZXBWrr")>;
1003def: InstRW<[HWWriteResGroup4], (instregex "PMOVZXDQrr")>;
1004def: InstRW<[HWWriteResGroup4], (instregex "PMOVZXWDrr")>;
1005def: InstRW<[HWWriteResGroup4], (instregex "PMOVZXWQrr")>;
1006def: InstRW<[HWWriteResGroup4], (instregex "PSHUFBrr")>;
1007def: InstRW<[HWWriteResGroup4], (instregex "PSHUFDri")>;
1008def: InstRW<[HWWriteResGroup4], (instregex "PSHUFHWri")>;
1009def: InstRW<[HWWriteResGroup4], (instregex "PSHUFLWri")>;
1010def: InstRW<[HWWriteResGroup4], (instregex "PSLLDQri")>;
1011def: InstRW<[HWWriteResGroup4], (instregex "PSRLDQri")>;
1012def: InstRW<[HWWriteResGroup4], (instregex "PUNPCKHBWrr")>;
1013def: InstRW<[HWWriteResGroup4], (instregex "PUNPCKHDQrr")>;
1014def: InstRW<[HWWriteResGroup4], (instregex "PUNPCKHQDQrr")>;
1015def: InstRW<[HWWriteResGroup4], (instregex "PUNPCKHWDrr")>;
1016def: InstRW<[HWWriteResGroup4], (instregex "PUNPCKLBWrr")>;
1017def: InstRW<[HWWriteResGroup4], (instregex "PUNPCKLDQrr")>;
1018def: InstRW<[HWWriteResGroup4], (instregex "PUNPCKLQDQrr")>;
1019def: InstRW<[HWWriteResGroup4], (instregex "PUNPCKLWDrr")>;
1020def: InstRW<[HWWriteResGroup4], (instregex "SHUFPDrri")>;
1021def: InstRW<[HWWriteResGroup4], (instregex "SHUFPSrri")>;
1022def: InstRW<[HWWriteResGroup4], (instregex "UNPCKHPDrr")>;
1023def: InstRW<[HWWriteResGroup4], (instregex "UNPCKHPSrr")>;
1024def: InstRW<[HWWriteResGroup4], (instregex "UNPCKLPDrr")>;
1025def: InstRW<[HWWriteResGroup4], (instregex "UNPCKLPSrr")>;
1026def: InstRW<[HWWriteResGroup4], (instregex "VANDNPDYrr")>;
1027def: InstRW<[HWWriteResGroup4], (instregex "VANDNPDrr")>;
1028def: InstRW<[HWWriteResGroup4], (instregex "VANDNPSYrr")>;
1029def: InstRW<[HWWriteResGroup4], (instregex "VANDNPSrr")>;
1030def: InstRW<[HWWriteResGroup4], (instregex "VANDPDYrr")>;
1031def: InstRW<[HWWriteResGroup4], (instregex "VANDPDrr")>;
1032def: InstRW<[HWWriteResGroup4], (instregex "VANDPSYrr")>;
1033def: InstRW<[HWWriteResGroup4], (instregex "VANDPSrr")>;
1034def: InstRW<[HWWriteResGroup4], (instregex "VBROADCASTSSrr")>;
1035def: InstRW<[HWWriteResGroup4], (instregex "VINSERTPSrr")>;
1036def: InstRW<[HWWriteResGroup4], (instregex "VMOV64toPQIrr")>;
1037def: InstRW<[HWWriteResGroup4], (instregex "VMOVAPDYrr(_REV?)")>;
1038def: InstRW<[HWWriteResGroup4], (instregex "VMOVAPDrr(_REV?)")>;
1039def: InstRW<[HWWriteResGroup4], (instregex "VMOVAPSYrr(_REV?)")>;
1040def: InstRW<[HWWriteResGroup4], (instregex "VMOVAPSrr(_REV?)")>;
1041def: InstRW<[HWWriteResGroup4], (instregex "VMOVDDUPYrr")>;
1042def: InstRW<[HWWriteResGroup4], (instregex "VMOVDDUPrr")>;
1043def: InstRW<[HWWriteResGroup4], (instregex "VMOVDI2PDIrr")>;
1044def: InstRW<[HWWriteResGroup4], (instregex "VMOVHLPSrr")>;
1045def: InstRW<[HWWriteResGroup4], (instregex "VMOVLHPSrr")>;
1046def: InstRW<[HWWriteResGroup4], (instregex "VMOVSDrr(_REV?)")>;
1047def: InstRW<[HWWriteResGroup4], (instregex "VMOVSHDUPYrr")>;
1048def: InstRW<[HWWriteResGroup4], (instregex "VMOVSHDUPrr")>;
1049def: InstRW<[HWWriteResGroup4], (instregex "VMOVSLDUPYrr")>;
1050def: InstRW<[HWWriteResGroup4], (instregex "VMOVSLDUPrr")>;
1051def: InstRW<[HWWriteResGroup4], (instregex "VMOVSSrr(_REV?)")>;
1052def: InstRW<[HWWriteResGroup4], (instregex "VMOVUPDYrr(_REV?)")>;
1053def: InstRW<[HWWriteResGroup4], (instregex "VMOVUPDrr(_REV?)")>;
1054def: InstRW<[HWWriteResGroup4], (instregex "VMOVUPSYrr(_REV?)")>;
1055def: InstRW<[HWWriteResGroup4], (instregex "VMOVUPSrr(_REV?)")>;
1056def: InstRW<[HWWriteResGroup4], (instregex "VORPDYrr")>;
1057def: InstRW<[HWWriteResGroup4], (instregex "VORPDrr")>;
1058def: InstRW<[HWWriteResGroup4], (instregex "VORPSYrr")>;
1059def: InstRW<[HWWriteResGroup4], (instregex "VORPSrr")>;
1060def: InstRW<[HWWriteResGroup4], (instregex "VPACKSSDWYrr")>;
1061def: InstRW<[HWWriteResGroup4], (instregex "VPACKSSDWrr")>;
1062def: InstRW<[HWWriteResGroup4], (instregex "VPACKSSWBYrr")>;
1063def: InstRW<[HWWriteResGroup4], (instregex "VPACKSSWBrr")>;
1064def: InstRW<[HWWriteResGroup4], (instregex "VPACKUSDWYrr")>;
1065def: InstRW<[HWWriteResGroup4], (instregex "VPACKUSDWrr")>;
1066def: InstRW<[HWWriteResGroup4], (instregex "VPACKUSWBYrr")>;
1067def: InstRW<[HWWriteResGroup4], (instregex "VPACKUSWBrr")>;
1068def: InstRW<[HWWriteResGroup4], (instregex "VPALIGNRYrri")>;
1069def: InstRW<[HWWriteResGroup4], (instregex "VPALIGNRrri")>;
1070def: InstRW<[HWWriteResGroup4], (instregex "VPBLENDWYrri")>;
1071def: InstRW<[HWWriteResGroup4], (instregex "VPBLENDWrri")>;
1072def: InstRW<[HWWriteResGroup4], (instregex "VPBROADCASTDrr")>;
1073def: InstRW<[HWWriteResGroup4], (instregex "VPBROADCASTQrr")>;
1074def: InstRW<[HWWriteResGroup4], (instregex "VPERMILPDYri")>;
1075def: InstRW<[HWWriteResGroup4], (instregex "VPERMILPDYrr")>;
1076def: InstRW<[HWWriteResGroup4], (instregex "VPERMILPDri")>;
1077def: InstRW<[HWWriteResGroup4], (instregex "VPERMILPDrr")>;
1078def: InstRW<[HWWriteResGroup4], (instregex "VPERMILPSYri")>;
1079def: InstRW<[HWWriteResGroup4], (instregex "VPERMILPSYrr")>;
1080def: InstRW<[HWWriteResGroup4], (instregex "VPERMILPSri")>;
1081def: InstRW<[HWWriteResGroup4], (instregex "VPERMILPSrr")>;
1082def: InstRW<[HWWriteResGroup4], (instregex "VPMOVSXBDrr")>;
1083def: InstRW<[HWWriteResGroup4], (instregex "VPMOVSXBQrr")>;
1084def: InstRW<[HWWriteResGroup4], (instregex "VPMOVSXBWrr")>;
1085def: InstRW<[HWWriteResGroup4], (instregex "VPMOVSXDQrr")>;
1086def: InstRW<[HWWriteResGroup4], (instregex "VPMOVSXWDrr")>;
1087def: InstRW<[HWWriteResGroup4], (instregex "VPMOVSXWQrr")>;
1088def: InstRW<[HWWriteResGroup4], (instregex "VPMOVZXBDrr")>;
1089def: InstRW<[HWWriteResGroup4], (instregex "VPMOVZXBQrr")>;
1090def: InstRW<[HWWriteResGroup4], (instregex "VPMOVZXBWrr")>;
1091def: InstRW<[HWWriteResGroup4], (instregex "VPMOVZXDQrr")>;
1092def: InstRW<[HWWriteResGroup4], (instregex "VPMOVZXWDrr")>;
1093def: InstRW<[HWWriteResGroup4], (instregex "VPMOVZXWQrr")>;
1094def: InstRW<[HWWriteResGroup4], (instregex "VPSHUFBYrr")>;
1095def: InstRW<[HWWriteResGroup4], (instregex "VPSHUFBrr")>;
1096def: InstRW<[HWWriteResGroup4], (instregex "VPSHUFDYri")>;
1097def: InstRW<[HWWriteResGroup4], (instregex "VPSHUFDri")>;
1098def: InstRW<[HWWriteResGroup4], (instregex "VPSHUFHWYri")>;
1099def: InstRW<[HWWriteResGroup4], (instregex "VPSHUFHWri")>;
1100def: InstRW<[HWWriteResGroup4], (instregex "VPSHUFLWYri")>;
1101def: InstRW<[HWWriteResGroup4], (instregex "VPSHUFLWri")>;
1102def: InstRW<[HWWriteResGroup4], (instregex "VPSLLDQYri")>;
1103def: InstRW<[HWWriteResGroup4], (instregex "VPSLLDQri")>;
1104def: InstRW<[HWWriteResGroup4], (instregex "VPSRLDQYri")>;
1105def: InstRW<[HWWriteResGroup4], (instregex "VPSRLDQri")>;
1106def: InstRW<[HWWriteResGroup4], (instregex "VPUNPCKHBWYrr")>;
1107def: InstRW<[HWWriteResGroup4], (instregex "VPUNPCKHBWrr")>;
1108def: InstRW<[HWWriteResGroup4], (instregex "VPUNPCKHDQYrr")>;
1109def: InstRW<[HWWriteResGroup4], (instregex "VPUNPCKHDQrr")>;
1110def: InstRW<[HWWriteResGroup4], (instregex "VPUNPCKHQDQYrr")>;
1111def: InstRW<[HWWriteResGroup4], (instregex "VPUNPCKHQDQrr")>;
1112def: InstRW<[HWWriteResGroup4], (instregex "VPUNPCKHWDYrr")>;
1113def: InstRW<[HWWriteResGroup4], (instregex "VPUNPCKHWDrr")>;
1114def: InstRW<[HWWriteResGroup4], (instregex "VPUNPCKLBWYrr")>;
1115def: InstRW<[HWWriteResGroup4], (instregex "VPUNPCKLBWrr")>;
1116def: InstRW<[HWWriteResGroup4], (instregex "VPUNPCKLDQYrr")>;
1117def: InstRW<[HWWriteResGroup4], (instregex "VPUNPCKLDQrr")>;
1118def: InstRW<[HWWriteResGroup4], (instregex "VPUNPCKLQDQYrr")>;
1119def: InstRW<[HWWriteResGroup4], (instregex "VPUNPCKLQDQrr")>;
1120def: InstRW<[HWWriteResGroup4], (instregex "VPUNPCKLWDYrr")>;
1121def: InstRW<[HWWriteResGroup4], (instregex "VPUNPCKLWDrr")>;
1122def: InstRW<[HWWriteResGroup4], (instregex "VSHUFPDYrri")>;
1123def: InstRW<[HWWriteResGroup4], (instregex "VSHUFPDrri")>;
1124def: InstRW<[HWWriteResGroup4], (instregex "VSHUFPSYrri")>;
1125def: InstRW<[HWWriteResGroup4], (instregex "VSHUFPSrri")>;
1126def: InstRW<[HWWriteResGroup4], (instregex "VUNPCKHPDYrr")>;
1127def: InstRW<[HWWriteResGroup4], (instregex "VUNPCKHPDrr")>;
1128def: InstRW<[HWWriteResGroup4], (instregex "VUNPCKHPSYrr")>;
1129def: InstRW<[HWWriteResGroup4], (instregex "VUNPCKHPSrr")>;
1130def: InstRW<[HWWriteResGroup4], (instregex "VUNPCKLPDYrr")>;
1131def: InstRW<[HWWriteResGroup4], (instregex "VUNPCKLPDrr")>;
1132def: InstRW<[HWWriteResGroup4], (instregex "VUNPCKLPSYrr")>;
1133def: InstRW<[HWWriteResGroup4], (instregex "VUNPCKLPSrr")>;
1134def: InstRW<[HWWriteResGroup4], (instregex "VXORPDYrr")>;
1135def: InstRW<[HWWriteResGroup4], (instregex "VXORPDrr")>;
1136def: InstRW<[HWWriteResGroup4], (instregex "VXORPSYrr")>;
1137def: InstRW<[HWWriteResGroup4], (instregex "VXORPSrr")>;
1138def: InstRW<[HWWriteResGroup4], (instregex "XORPDrr")>;
1139def: InstRW<[HWWriteResGroup4], (instregex "XORPSrr")>;
1140
1141def HWWriteResGroup5 : SchedWriteRes<[HWPort6]> {
1142 let Latency = 1;
1143 let NumMicroOps = 1;
1144 let ResourceCycles = [1];
1145}
1146def: InstRW<[HWWriteResGroup5], (instregex "JMP(16|32|64)r")>;
1147
1148def HWWriteResGroup6 : SchedWriteRes<[HWPort01]> {
1149 let Latency = 1;
1150 let NumMicroOps = 1;
1151 let ResourceCycles = [1];
1152}
1153def: InstRW<[HWWriteResGroup6], (instregex "FINCSTP")>;
1154def: InstRW<[HWWriteResGroup6], (instregex "FNOP")>;
1155
1156def HWWriteResGroup7 : SchedWriteRes<[HWPort06]> {
1157 let Latency = 1;
1158 let NumMicroOps = 1;
1159 let ResourceCycles = [1];
1160}
1161def: InstRW<[HWWriteResGroup7], (instregex "BT(16|32|64)ri8")>;
1162def: InstRW<[HWWriteResGroup7], (instregex "BT(16|32|64)rr")>;
1163def: InstRW<[HWWriteResGroup7], (instregex "BTC(16|32|64)ri8")>;
1164def: InstRW<[HWWriteResGroup7], (instregex "BTC(16|32|64)rr")>;
1165def: InstRW<[HWWriteResGroup7], (instregex "BTR(16|32|64)ri8")>;
1166def: InstRW<[HWWriteResGroup7], (instregex "BTR(16|32|64)rr")>;
1167def: InstRW<[HWWriteResGroup7], (instregex "BTS(16|32|64)ri8")>;
1168def: InstRW<[HWWriteResGroup7], (instregex "BTS(16|32|64)rr")>;
1169def: InstRW<[HWWriteResGroup7], (instregex "CDQ")>;
1170def: InstRW<[HWWriteResGroup7], (instregex "CQO")>;
1171def: InstRW<[HWWriteResGroup7], (instregex "JAE_1")>;
1172def: InstRW<[HWWriteResGroup7], (instregex "JAE_4")>;
1173def: InstRW<[HWWriteResGroup7], (instregex "JA_1")>;
1174def: InstRW<[HWWriteResGroup7], (instregex "JA_4")>;
1175def: InstRW<[HWWriteResGroup7], (instregex "JBE_1")>;
1176def: InstRW<[HWWriteResGroup7], (instregex "JBE_4")>;
1177def: InstRW<[HWWriteResGroup7], (instregex "JB_1")>;
1178def: InstRW<[HWWriteResGroup7], (instregex "JB_4")>;
1179def: InstRW<[HWWriteResGroup7], (instregex "JE_1")>;
1180def: InstRW<[HWWriteResGroup7], (instregex "JE_4")>;
1181def: InstRW<[HWWriteResGroup7], (instregex "JGE_1")>;
1182def: InstRW<[HWWriteResGroup7], (instregex "JGE_4")>;
1183def: InstRW<[HWWriteResGroup7], (instregex "JG_1")>;
1184def: InstRW<[HWWriteResGroup7], (instregex "JG_4")>;
1185def: InstRW<[HWWriteResGroup7], (instregex "JLE_1")>;
1186def: InstRW<[HWWriteResGroup7], (instregex "JLE_4")>;
1187def: InstRW<[HWWriteResGroup7], (instregex "JL_1")>;
1188def: InstRW<[HWWriteResGroup7], (instregex "JL_4")>;
1189def: InstRW<[HWWriteResGroup7], (instregex "JMP_1")>;
1190def: InstRW<[HWWriteResGroup7], (instregex "JMP_4")>;
1191def: InstRW<[HWWriteResGroup7], (instregex "JNE_1")>;
1192def: InstRW<[HWWriteResGroup7], (instregex "JNE_4")>;
1193def: InstRW<[HWWriteResGroup7], (instregex "JNO_1")>;
1194def: InstRW<[HWWriteResGroup7], (instregex "JNO_4")>;
1195def: InstRW<[HWWriteResGroup7], (instregex "JNP_1")>;
1196def: InstRW<[HWWriteResGroup7], (instregex "JNP_4")>;
1197def: InstRW<[HWWriteResGroup7], (instregex "JNS_1")>;
1198def: InstRW<[HWWriteResGroup7], (instregex "JNS_4")>;
1199def: InstRW<[HWWriteResGroup7], (instregex "JO_1")>;
1200def: InstRW<[HWWriteResGroup7], (instregex "JO_4")>;
1201def: InstRW<[HWWriteResGroup7], (instregex "JP_1")>;
1202def: InstRW<[HWWriteResGroup7], (instregex "JP_4")>;
1203def: InstRW<[HWWriteResGroup7], (instregex "JS_1")>;
1204def: InstRW<[HWWriteResGroup7], (instregex "JS_4")>;
1205def: InstRW<[HWWriteResGroup7], (instregex "RORX32ri")>;
1206def: InstRW<[HWWriteResGroup7], (instregex "RORX64ri")>;
1207def: InstRW<[HWWriteResGroup7], (instregex "SAR(16|32|64)r1")>;
1208def: InstRW<[HWWriteResGroup7], (instregex "SAR(16|32|64)ri")>;
1209def: InstRW<[HWWriteResGroup7], (instregex "SAR8r1")>;
1210def: InstRW<[HWWriteResGroup7], (instregex "SAR8ri")>;
1211def: InstRW<[HWWriteResGroup7], (instregex "SARX32rr")>;
1212def: InstRW<[HWWriteResGroup7], (instregex "SARX64rr")>;
1213def: InstRW<[HWWriteResGroup7], (instregex "SETAEr")>;
1214def: InstRW<[HWWriteResGroup7], (instregex "SETBr")>;
1215def: InstRW<[HWWriteResGroup7], (instregex "SETEr")>;
1216def: InstRW<[HWWriteResGroup7], (instregex "SETGEr")>;
1217def: InstRW<[HWWriteResGroup7], (instregex "SETGr")>;
1218def: InstRW<[HWWriteResGroup7], (instregex "SETLEr")>;
1219def: InstRW<[HWWriteResGroup7], (instregex "SETLr")>;
1220def: InstRW<[HWWriteResGroup7], (instregex "SETNEr")>;
1221def: InstRW<[HWWriteResGroup7], (instregex "SETNOr")>;
1222def: InstRW<[HWWriteResGroup7], (instregex "SETNPr")>;
1223def: InstRW<[HWWriteResGroup7], (instregex "SETNSr")>;
1224def: InstRW<[HWWriteResGroup7], (instregex "SETOr")>;
1225def: InstRW<[HWWriteResGroup7], (instregex "SETPr")>;
1226def: InstRW<[HWWriteResGroup7], (instregex "SETSr")>;
1227def: InstRW<[HWWriteResGroup7], (instregex "SHL(16|32|64)r1")>;
1228def: InstRW<[HWWriteResGroup7], (instregex "SHL(16|32|64)ri")>;
1229def: InstRW<[HWWriteResGroup7], (instregex "SHL8r1")>;
1230def: InstRW<[HWWriteResGroup7], (instregex "SHL8ri")>;
1231def: InstRW<[HWWriteResGroup7], (instregex "SHLX32rr")>;
1232def: InstRW<[HWWriteResGroup7], (instregex "SHLX64rr")>;
1233def: InstRW<[HWWriteResGroup7], (instregex "SHR(16|32|64)r1")>;
1234def: InstRW<[HWWriteResGroup7], (instregex "SHR(16|32|64)ri")>;
1235def: InstRW<[HWWriteResGroup7], (instregex "SHR8r1")>;
1236def: InstRW<[HWWriteResGroup7], (instregex "SHR8ri")>;
1237def: InstRW<[HWWriteResGroup7], (instregex "SHRX32rr")>;
1238def: InstRW<[HWWriteResGroup7], (instregex "SHRX64rr")>;
1239
1240def HWWriteResGroup8 : SchedWriteRes<[HWPort15]> {
1241 let Latency = 1;
1242 let NumMicroOps = 1;
1243 let ResourceCycles = [1];
1244}
1245def: InstRW<[HWWriteResGroup8], (instregex "ANDN32rr")>;
1246def: InstRW<[HWWriteResGroup8], (instregex "ANDN64rr")>;
1247def: InstRW<[HWWriteResGroup8], (instregex "BLSI32rr")>;
1248def: InstRW<[HWWriteResGroup8], (instregex "BLSI64rr")>;
1249def: InstRW<[HWWriteResGroup8], (instregex "BLSMSK32rr")>;
1250def: InstRW<[HWWriteResGroup8], (instregex "BLSMSK64rr")>;
1251def: InstRW<[HWWriteResGroup8], (instregex "BLSR32rr")>;
1252def: InstRW<[HWWriteResGroup8], (instregex "BLSR64rr")>;
1253def: InstRW<[HWWriteResGroup8], (instregex "BZHI32rr")>;
1254def: InstRW<[HWWriteResGroup8], (instregex "BZHI64rr")>;
1255def: InstRW<[HWWriteResGroup8], (instregex "LEA(16|32|64)r")>;
1256def: InstRW<[HWWriteResGroup8], (instregex "MMX_PABSBrr64")>;
1257def: InstRW<[HWWriteResGroup8], (instregex "MMX_PABSDrr64")>;
1258def: InstRW<[HWWriteResGroup8], (instregex "MMX_PABSWrr64")>;
1259def: InstRW<[HWWriteResGroup8], (instregex "MMX_PADDBirr")>;
1260def: InstRW<[HWWriteResGroup8], (instregex "MMX_PADDDirr")>;
1261def: InstRW<[HWWriteResGroup8], (instregex "MMX_PADDQirr")>;
1262def: InstRW<[HWWriteResGroup8], (instregex "MMX_PADDSBirr")>;
1263def: InstRW<[HWWriteResGroup8], (instregex "MMX_PADDSWirr")>;
1264def: InstRW<[HWWriteResGroup8], (instregex "MMX_PADDUSBirr")>;
1265def: InstRW<[HWWriteResGroup8], (instregex "MMX_PADDUSWirr")>;
1266def: InstRW<[HWWriteResGroup8], (instregex "MMX_PADDWirr")>;
1267def: InstRW<[HWWriteResGroup8], (instregex "MMX_PAVGBirr")>;
1268def: InstRW<[HWWriteResGroup8], (instregex "MMX_PAVGWirr")>;
1269def: InstRW<[HWWriteResGroup8], (instregex "MMX_PCMPEQBirr")>;
1270def: InstRW<[HWWriteResGroup8], (instregex "MMX_PCMPEQDirr")>;
1271def: InstRW<[HWWriteResGroup8], (instregex "MMX_PCMPEQWirr")>;
1272def: InstRW<[HWWriteResGroup8], (instregex "MMX_PCMPGTBirr")>;
1273def: InstRW<[HWWriteResGroup8], (instregex "MMX_PCMPGTDirr")>;
1274def: InstRW<[HWWriteResGroup8], (instregex "MMX_PCMPGTWirr")>;
1275def: InstRW<[HWWriteResGroup8], (instregex "MMX_PMAXSWirr")>;
1276def: InstRW<[HWWriteResGroup8], (instregex "MMX_PMAXUBirr")>;
1277def: InstRW<[HWWriteResGroup8], (instregex "MMX_PMINSWirr")>;
1278def: InstRW<[HWWriteResGroup8], (instregex "MMX_PMINUBirr")>;
1279def: InstRW<[HWWriteResGroup8], (instregex "MMX_PSIGNBrr64")>;
1280def: InstRW<[HWWriteResGroup8], (instregex "MMX_PSIGNDrr64")>;
1281def: InstRW<[HWWriteResGroup8], (instregex "MMX_PSIGNWrr64")>;
1282def: InstRW<[HWWriteResGroup8], (instregex "MMX_PSUBBirr")>;
1283def: InstRW<[HWWriteResGroup8], (instregex "MMX_PSUBDirr")>;
1284def: InstRW<[HWWriteResGroup8], (instregex "MMX_PSUBQirr")>;
1285def: InstRW<[HWWriteResGroup8], (instregex "MMX_PSUBSBirr")>;
1286def: InstRW<[HWWriteResGroup8], (instregex "MMX_PSUBSWirr")>;
1287def: InstRW<[HWWriteResGroup8], (instregex "MMX_PSUBUSBirr")>;
1288def: InstRW<[HWWriteResGroup8], (instregex "MMX_PSUBUSWirr")>;
1289def: InstRW<[HWWriteResGroup8], (instregex "MMX_PSUBWirr")>;
1290def: InstRW<[HWWriteResGroup8], (instregex "PABSBrr")>;
1291def: InstRW<[HWWriteResGroup8], (instregex "PABSDrr")>;
1292def: InstRW<[HWWriteResGroup8], (instregex "PABSWrr")>;
1293def: InstRW<[HWWriteResGroup8], (instregex "PADDBrr")>;
1294def: InstRW<[HWWriteResGroup8], (instregex "PADDDrr")>;
1295def: InstRW<[HWWriteResGroup8], (instregex "PADDQrr")>;
1296def: InstRW<[HWWriteResGroup8], (instregex "PADDSBrr")>;
1297def: InstRW<[HWWriteResGroup8], (instregex "PADDSWrr")>;
1298def: InstRW<[HWWriteResGroup8], (instregex "PADDUSBrr")>;
1299def: InstRW<[HWWriteResGroup8], (instregex "PADDUSWrr")>;
1300def: InstRW<[HWWriteResGroup8], (instregex "PADDWrr")>;
1301def: InstRW<[HWWriteResGroup8], (instregex "PAVGBrr")>;
1302def: InstRW<[HWWriteResGroup8], (instregex "PAVGWrr")>;
1303def: InstRW<[HWWriteResGroup8], (instregex "PCMPEQBrr")>;
1304def: InstRW<[HWWriteResGroup8], (instregex "PCMPEQDrr")>;
1305def: InstRW<[HWWriteResGroup8], (instregex "PCMPEQQrr")>;
1306def: InstRW<[HWWriteResGroup8], (instregex "PCMPEQWrr")>;
1307def: InstRW<[HWWriteResGroup8], (instregex "PCMPGTBrr")>;
1308def: InstRW<[HWWriteResGroup8], (instregex "PCMPGTDrr")>;
1309def: InstRW<[HWWriteResGroup8], (instregex "PCMPGTWrr")>;
1310def: InstRW<[HWWriteResGroup8], (instregex "PMAXSBrr")>;
1311def: InstRW<[HWWriteResGroup8], (instregex "PMAXSDrr")>;
1312def: InstRW<[HWWriteResGroup8], (instregex "PMAXSWrr")>;
1313def: InstRW<[HWWriteResGroup8], (instregex "PMAXUBrr")>;
1314def: InstRW<[HWWriteResGroup8], (instregex "PMAXUDrr")>;
1315def: InstRW<[HWWriteResGroup8], (instregex "PMAXUWrr")>;
1316def: InstRW<[HWWriteResGroup8], (instregex "PMINSBrr")>;
1317def: InstRW<[HWWriteResGroup8], (instregex "PMINSDrr")>;
1318def: InstRW<[HWWriteResGroup8], (instregex "PMINSWrr")>;
1319def: InstRW<[HWWriteResGroup8], (instregex "PMINUBrr")>;
1320def: InstRW<[HWWriteResGroup8], (instregex "PMINUDrr")>;
1321def: InstRW<[HWWriteResGroup8], (instregex "PMINUWrr")>;
1322def: InstRW<[HWWriteResGroup8], (instregex "PSIGNBrr128")>;
1323def: InstRW<[HWWriteResGroup8], (instregex "PSIGNDrr128")>;
1324def: InstRW<[HWWriteResGroup8], (instregex "PSIGNWrr128")>;
1325def: InstRW<[HWWriteResGroup8], (instregex "PSUBBrr")>;
1326def: InstRW<[HWWriteResGroup8], (instregex "PSUBDrr")>;
1327def: InstRW<[HWWriteResGroup8], (instregex "PSUBQrr")>;
1328def: InstRW<[HWWriteResGroup8], (instregex "PSUBSBrr")>;
1329def: InstRW<[HWWriteResGroup8], (instregex "PSUBSWrr")>;
1330def: InstRW<[HWWriteResGroup8], (instregex "PSUBUSBrr")>;
1331def: InstRW<[HWWriteResGroup8], (instregex "PSUBUSWrr")>;
1332def: InstRW<[HWWriteResGroup8], (instregex "PSUBWrr")>;
1333def: InstRW<[HWWriteResGroup8], (instregex "VPABSBYrr")>;
1334def: InstRW<[HWWriteResGroup8], (instregex "VPABSBrr")>;
1335def: InstRW<[HWWriteResGroup8], (instregex "VPABSDYrr")>;
1336def: InstRW<[HWWriteResGroup8], (instregex "VPABSDrr")>;
1337def: InstRW<[HWWriteResGroup8], (instregex "VPABSWYrr")>;
1338def: InstRW<[HWWriteResGroup8], (instregex "VPABSWrr")>;
1339def: InstRW<[HWWriteResGroup8], (instregex "VPADDBYrr")>;
1340def: InstRW<[HWWriteResGroup8], (instregex "VPADDBrr")>;
1341def: InstRW<[HWWriteResGroup8], (instregex "VPADDDYrr")>;
1342def: InstRW<[HWWriteResGroup8], (instregex "VPADDDrr")>;
1343def: InstRW<[HWWriteResGroup8], (instregex "VPADDQYrr")>;
1344def: InstRW<[HWWriteResGroup8], (instregex "VPADDQrr")>;
1345def: InstRW<[HWWriteResGroup8], (instregex "VPADDSBYrr")>;
1346def: InstRW<[HWWriteResGroup8], (instregex "VPADDSBrr")>;
1347def: InstRW<[HWWriteResGroup8], (instregex "VPADDSWYrr")>;
1348def: InstRW<[HWWriteResGroup8], (instregex "VPADDSWrr")>;
1349def: InstRW<[HWWriteResGroup8], (instregex "VPADDUSBYrr")>;
1350def: InstRW<[HWWriteResGroup8], (instregex "VPADDUSBrr")>;
1351def: InstRW<[HWWriteResGroup8], (instregex "VPADDUSWYrr")>;
1352def: InstRW<[HWWriteResGroup8], (instregex "VPADDUSWrr")>;
1353def: InstRW<[HWWriteResGroup8], (instregex "VPADDWYrr")>;
1354def: InstRW<[HWWriteResGroup8], (instregex "VPADDWrr")>;
1355def: InstRW<[HWWriteResGroup8], (instregex "VPAVGBYrr")>;
1356def: InstRW<[HWWriteResGroup8], (instregex "VPAVGBrr")>;
1357def: InstRW<[HWWriteResGroup8], (instregex "VPAVGWYrr")>;
1358def: InstRW<[HWWriteResGroup8], (instregex "VPAVGWrr")>;
1359def: InstRW<[HWWriteResGroup8], (instregex "VPCMPEQBYrr")>;
1360def: InstRW<[HWWriteResGroup8], (instregex "VPCMPEQBrr")>;
1361def: InstRW<[HWWriteResGroup8], (instregex "VPCMPEQDYrr")>;
1362def: InstRW<[HWWriteResGroup8], (instregex "VPCMPEQDrr")>;
1363def: InstRW<[HWWriteResGroup8], (instregex "VPCMPEQQYrr")>;
1364def: InstRW<[HWWriteResGroup8], (instregex "VPCMPEQQrr")>;
1365def: InstRW<[HWWriteResGroup8], (instregex "VPCMPEQWYrr")>;
1366def: InstRW<[HWWriteResGroup8], (instregex "VPCMPEQWrr")>;
1367def: InstRW<[HWWriteResGroup8], (instregex "VPCMPGTBYrr")>;
1368def: InstRW<[HWWriteResGroup8], (instregex "VPCMPGTBrr")>;
1369def: InstRW<[HWWriteResGroup8], (instregex "VPCMPGTDYrr")>;
1370def: InstRW<[HWWriteResGroup8], (instregex "VPCMPGTDrr")>;
1371def: InstRW<[HWWriteResGroup8], (instregex "VPCMPGTWYrr")>;
1372def: InstRW<[HWWriteResGroup8], (instregex "VPCMPGTWrr")>;
1373def: InstRW<[HWWriteResGroup8], (instregex "VPMAXSBYrr")>;
1374def: InstRW<[HWWriteResGroup8], (instregex "VPMAXSBrr")>;
1375def: InstRW<[HWWriteResGroup8], (instregex "VPMAXSDYrr")>;
1376def: InstRW<[HWWriteResGroup8], (instregex "VPMAXSDrr")>;
1377def: InstRW<[HWWriteResGroup8], (instregex "VPMAXSWYrr")>;
1378def: InstRW<[HWWriteResGroup8], (instregex "VPMAXSWrr")>;
1379def: InstRW<[HWWriteResGroup8], (instregex "VPMAXUBYrr")>;
1380def: InstRW<[HWWriteResGroup8], (instregex "VPMAXUBrr")>;
1381def: InstRW<[HWWriteResGroup8], (instregex "VPMAXUDYrr")>;
1382def: InstRW<[HWWriteResGroup8], (instregex "VPMAXUDrr")>;
1383def: InstRW<[HWWriteResGroup8], (instregex "VPMAXUWYrr")>;
1384def: InstRW<[HWWriteResGroup8], (instregex "VPMAXUWrr")>;
1385def: InstRW<[HWWriteResGroup8], (instregex "VPMINSBYrr")>;
1386def: InstRW<[HWWriteResGroup8], (instregex "VPMINSBrr")>;
1387def: InstRW<[HWWriteResGroup8], (instregex "VPMINSDYrr")>;
1388def: InstRW<[HWWriteResGroup8], (instregex "VPMINSDrr")>;
1389def: InstRW<[HWWriteResGroup8], (instregex "VPMINSWYrr")>;
1390def: InstRW<[HWWriteResGroup8], (instregex "VPMINSWrr")>;
1391def: InstRW<[HWWriteResGroup8], (instregex "VPMINUBYrr")>;
1392def: InstRW<[HWWriteResGroup8], (instregex "VPMINUBrr")>;
1393def: InstRW<[HWWriteResGroup8], (instregex "VPMINUDYrr")>;
1394def: InstRW<[HWWriteResGroup8], (instregex "VPMINUDrr")>;
1395def: InstRW<[HWWriteResGroup8], (instregex "VPMINUWYrr")>;
1396def: InstRW<[HWWriteResGroup8], (instregex "VPMINUWrr")>;
1397def: InstRW<[HWWriteResGroup8], (instregex "VPSIGNBYrr256")>;
1398def: InstRW<[HWWriteResGroup8], (instregex "VPSIGNBrr128")>;
1399def: InstRW<[HWWriteResGroup8], (instregex "VPSIGNDYrr256")>;
1400def: InstRW<[HWWriteResGroup8], (instregex "VPSIGNDrr128")>;
1401def: InstRW<[HWWriteResGroup8], (instregex "VPSIGNWYrr256")>;
1402def: InstRW<[HWWriteResGroup8], (instregex "VPSIGNWrr128")>;
1403def: InstRW<[HWWriteResGroup8], (instregex "VPSUBBYrr")>;
1404def: InstRW<[HWWriteResGroup8], (instregex "VPSUBBrr")>;
1405def: InstRW<[HWWriteResGroup8], (instregex "VPSUBDYrr")>;
1406def: InstRW<[HWWriteResGroup8], (instregex "VPSUBDrr")>;
1407def: InstRW<[HWWriteResGroup8], (instregex "VPSUBQYrr")>;
1408def: InstRW<[HWWriteResGroup8], (instregex "VPSUBQrr")>;
1409def: InstRW<[HWWriteResGroup8], (instregex "VPSUBSBYrr")>;
1410def: InstRW<[HWWriteResGroup8], (instregex "VPSUBSBrr")>;
1411def: InstRW<[HWWriteResGroup8], (instregex "VPSUBSWYrr")>;
1412def: InstRW<[HWWriteResGroup8], (instregex "VPSUBSWrr")>;
1413def: InstRW<[HWWriteResGroup8], (instregex "VPSUBUSBYrr")>;
1414def: InstRW<[HWWriteResGroup8], (instregex "VPSUBUSBrr")>;
1415def: InstRW<[HWWriteResGroup8], (instregex "VPSUBUSWYrr")>;
1416def: InstRW<[HWWriteResGroup8], (instregex "VPSUBUSWrr")>;
1417def: InstRW<[HWWriteResGroup8], (instregex "VPSUBWYrr")>;
1418def: InstRW<[HWWriteResGroup8], (instregex "VPSUBWrr")>;
1419
1420def HWWriteResGroup9 : SchedWriteRes<[HWPort015]> {
1421 let Latency = 1;
1422 let NumMicroOps = 1;
1423 let ResourceCycles = [1];
1424}
1425def: InstRW<[HWWriteResGroup9], (instregex "BLENDPDrri")>;
1426def: InstRW<[HWWriteResGroup9], (instregex "BLENDPSrri")>;
1427def: InstRW<[HWWriteResGroup9], (instregex "MMX_MOVD64from64rr")>;
1428def: InstRW<[HWWriteResGroup9], (instregex "MMX_MOVQ64rr(_REV?)")>;
1429def: InstRW<[HWWriteResGroup9], (instregex "MMX_PANDNirr")>;
1430def: InstRW<[HWWriteResGroup9], (instregex "MMX_PANDirr")>;
1431def: InstRW<[HWWriteResGroup9], (instregex "MMX_PORirr")>;
1432def: InstRW<[HWWriteResGroup9], (instregex "MMX_PXORirr")>;
1433def: InstRW<[HWWriteResGroup9], (instregex "MOVDQArr(_REV?)")>;
1434def: InstRW<[HWWriteResGroup9], (instregex "MOVDQUrr(_REV?)")>;
1435def: InstRW<[HWWriteResGroup9], (instregex "MOVPQI2QIrr")>;
1436def: InstRW<[HWWriteResGroup9], (instregex "PANDNrr")>;
1437def: InstRW<[HWWriteResGroup9], (instregex "PANDrr")>;
1438def: InstRW<[HWWriteResGroup9], (instregex "PORrr")>;
1439def: InstRW<[HWWriteResGroup9], (instregex "PXORrr")>;
1440def: InstRW<[HWWriteResGroup9], (instregex "VBLENDPDYrri")>;
1441def: InstRW<[HWWriteResGroup9], (instregex "VBLENDPDrri")>;
1442def: InstRW<[HWWriteResGroup9], (instregex "VBLENDPSYrri")>;
1443def: InstRW<[HWWriteResGroup9], (instregex "VBLENDPSrri")>;
1444def: InstRW<[HWWriteResGroup9], (instregex "VMOVDQAYrr(_REV?)")>;
1445def: InstRW<[HWWriteResGroup9], (instregex "VMOVDQArr(_REV?)")>;
1446def: InstRW<[HWWriteResGroup9], (instregex "VMOVDQUYrr(_REV?)")>;
1447def: InstRW<[HWWriteResGroup9], (instregex "VMOVDQUrr(_REV?)")>;
1448def: InstRW<[HWWriteResGroup9], (instregex "VMOVPQI2QIrr")>;
1449def: InstRW<[HWWriteResGroup9], (instregex "VMOVZPQILo2PQIrr")>;
1450def: InstRW<[HWWriteResGroup9], (instregex "VPANDNYrr")>;
1451def: InstRW<[HWWriteResGroup9], (instregex "VPANDNrr")>;
1452def: InstRW<[HWWriteResGroup9], (instregex "VPANDYrr")>;
1453def: InstRW<[HWWriteResGroup9], (instregex "VPANDrr")>;
1454def: InstRW<[HWWriteResGroup9], (instregex "VPBLENDDYrri")>;
1455def: InstRW<[HWWriteResGroup9], (instregex "VPBLENDDrri")>;
1456def: InstRW<[HWWriteResGroup9], (instregex "VPORYrr")>;
1457def: InstRW<[HWWriteResGroup9], (instregex "VPORrr")>;
1458def: InstRW<[HWWriteResGroup9], (instregex "VPXORYrr")>;
1459def: InstRW<[HWWriteResGroup9], (instregex "VPXORrr")>;
1460
1461def HWWriteResGroup10 : SchedWriteRes<[HWPort0156]> {
1462 let Latency = 1;
1463 let NumMicroOps = 1;
1464 let ResourceCycles = [1];
1465}
1466def: InstRW<[HWWriteResGroup10], (instregex "ADD(16|32|64)ri8")>;
1467def: InstRW<[HWWriteResGroup10], (instregex "ADD(16|32|64)rr(_REV?)")>;
1468def: InstRW<[HWWriteResGroup10], (instregex "ADD8i8")>;
1469def: InstRW<[HWWriteResGroup10], (instregex "ADD8ri")>;
1470def: InstRW<[HWWriteResGroup10], (instregex "ADD8rr(_REV?)")>;
1471def: InstRW<[HWWriteResGroup10], (instregex "AND(16|32|64)ri8")>;
1472def: InstRW<[HWWriteResGroup10], (instregex "AND(16|32|64)rr(_REV?)")>;
1473def: InstRW<[HWWriteResGroup10], (instregex "AND8i8")>;
1474def: InstRW<[HWWriteResGroup10], (instregex "AND8ri")>;
1475def: InstRW<[HWWriteResGroup10], (instregex "AND8rr(_REV?)")>;
1476def: InstRW<[HWWriteResGroup10], (instregex "CBW")>;
1477def: InstRW<[HWWriteResGroup10], (instregex "CLC")>;
1478def: InstRW<[HWWriteResGroup10], (instregex "CMC")>;
1479def: InstRW<[HWWriteResGroup10], (instregex "CMP(16|32|64)ri8")>;
1480def: InstRW<[HWWriteResGroup10], (instregex "CMP(16|32|64)rr(_REV?)")>;
1481def: InstRW<[HWWriteResGroup10], (instregex "CMP8i8")>;
1482def: InstRW<[HWWriteResGroup10], (instregex "CMP8ri")>;
1483def: InstRW<[HWWriteResGroup10], (instregex "CMP8rr(_REV?)")>;
1484def: InstRW<[HWWriteResGroup10], (instregex "CWDE")>;
1485def: InstRW<[HWWriteResGroup10], (instregex "DEC(16|32|64)r")>;
1486def: InstRW<[HWWriteResGroup10], (instregex "DEC8r")>;
1487def: InstRW<[HWWriteResGroup10], (instregex "INC(16|32|64)r")>;
1488def: InstRW<[HWWriteResGroup10], (instregex "INC8r")>;
1489def: InstRW<[HWWriteResGroup10], (instregex "LAHF")>;
1490def: InstRW<[HWWriteResGroup10], (instregex "MOV(16|32|64)rr(_REV?)")>;
1491def: InstRW<[HWWriteResGroup10], (instregex "MOV8ri(_alt?)")>;
1492def: InstRW<[HWWriteResGroup10], (instregex "MOV8rr(_REV?)")>;
1493def: InstRW<[HWWriteResGroup10], (instregex "MOVSX(16|32|64)rr16")>;
1494def: InstRW<[HWWriteResGroup10], (instregex "MOVSX(16|32|64)rr32")>;
1495def: InstRW<[HWWriteResGroup10], (instregex "MOVSX(16|32|64)rr8")>;
1496def: InstRW<[HWWriteResGroup10], (instregex "MOVZX(16|32|64)rr16")>;
1497def: InstRW<[HWWriteResGroup10], (instregex "MOVZX(16|32|64)rr8")>;
1498def: InstRW<[HWWriteResGroup10], (instregex "NEG(16|32|64)r")>;
1499def: InstRW<[HWWriteResGroup10], (instregex "NEG8r")>;
1500def: InstRW<[HWWriteResGroup10], (instregex "NOOP")>;
1501def: InstRW<[HWWriteResGroup10], (instregex "NOT(16|32|64)r")>;
1502def: InstRW<[HWWriteResGroup10], (instregex "NOT8r")>;
1503def: InstRW<[HWWriteResGroup10], (instregex "OR(16|32|64)ri8")>;
1504def: InstRW<[HWWriteResGroup10], (instregex "OR(16|32|64)rr(_REV?)")>;
1505def: InstRW<[HWWriteResGroup10], (instregex "OR8i8")>;
1506def: InstRW<[HWWriteResGroup10], (instregex "OR8ri")>;
1507def: InstRW<[HWWriteResGroup10], (instregex "OR8rr(_REV?)")>;
1508def: InstRW<[HWWriteResGroup10], (instregex "SAHF")>;
1509def: InstRW<[HWWriteResGroup10], (instregex "SGDT64m")>;
1510def: InstRW<[HWWriteResGroup10], (instregex "SIDT64m")>;
1511def: InstRW<[HWWriteResGroup10], (instregex "SLDT64m")>;
1512def: InstRW<[HWWriteResGroup10], (instregex "SMSW16m")>;
1513def: InstRW<[HWWriteResGroup10], (instregex "STC")>;
1514def: InstRW<[HWWriteResGroup10], (instregex "STRm")>;
1515def: InstRW<[HWWriteResGroup10], (instregex "SUB(16|32|64)ri8")>;
1516def: InstRW<[HWWriteResGroup10], (instregex "SUB(16|32|64)rr(_REV?)")>;
1517def: InstRW<[HWWriteResGroup10], (instregex "SUB8i8")>;
1518def: InstRW<[HWWriteResGroup10], (instregex "SUB8ri")>;
1519def: InstRW<[HWWriteResGroup10], (instregex "SUB8rr(_REV?)")>;
1520def: InstRW<[HWWriteResGroup10], (instregex "SYSCALL")>;
1521def: InstRW<[HWWriteResGroup10], (instregex "TEST(16|32|64)rr")>;
1522def: InstRW<[HWWriteResGroup10], (instregex "TEST8i8")>;
1523def: InstRW<[HWWriteResGroup10], (instregex "TEST8ri")>;
1524def: InstRW<[HWWriteResGroup10], (instregex "TEST8rr")>;
1525def: InstRW<[HWWriteResGroup10], (instregex "XCHG(16|32|64)rr")>;
1526def: InstRW<[HWWriteResGroup10], (instregex "XOR(16|32|64)ri8")>;
1527def: InstRW<[HWWriteResGroup10], (instregex "XOR(16|32|64)rr")>;
1528def: InstRW<[HWWriteResGroup10], (instregex "XOR8i8")>;
1529def: InstRW<[HWWriteResGroup10], (instregex "XOR8ri")>;
1530def: InstRW<[HWWriteResGroup10], (instregex "XOR8rr")>;
1531
1532def HWWriteResGroup11 : SchedWriteRes<[HWPort0,HWPort23]> {
Gadi Haber2cf601f2017-12-08 09:48:44 +00001533 let Latency = 6;
Gadi Haberd76f7b82017-08-28 10:04:16 +00001534 let NumMicroOps = 2;
1535 let ResourceCycles = [1,1];
1536}
1537def: InstRW<[HWWriteResGroup11], (instregex "CVTPS2PDrm")>;
Gadi Haberd76f7b82017-08-28 10:04:16 +00001538def: InstRW<[HWWriteResGroup11], (instregex "MMX_PSLLDrm")>;
1539def: InstRW<[HWWriteResGroup11], (instregex "MMX_PSLLQrm")>;
1540def: InstRW<[HWWriteResGroup11], (instregex "MMX_PSLLWrm")>;
1541def: InstRW<[HWWriteResGroup11], (instregex "MMX_PSRADrm")>;
1542def: InstRW<[HWWriteResGroup11], (instregex "MMX_PSRAWrm")>;
1543def: InstRW<[HWWriteResGroup11], (instregex "MMX_PSRLDrm")>;
1544def: InstRW<[HWWriteResGroup11], (instregex "MMX_PSRLQrm")>;
1545def: InstRW<[HWWriteResGroup11], (instregex "MMX_PSRLWrm")>;
Gadi Haberd76f7b82017-08-28 10:04:16 +00001546def: InstRW<[HWWriteResGroup11], (instregex "VCVTPH2PSrm")>;
1547def: InstRW<[HWWriteResGroup11], (instregex "VCVTPS2PDrm")>;
Gadi Haberd76f7b82017-08-28 10:04:16 +00001548
Gadi Haber2cf601f2017-12-08 09:48:44 +00001549def HWWriteResGroup11_1 : SchedWriteRes<[HWPort0,HWPort23]> {
1550 let Latency = 7;
Gadi Haberd76f7b82017-08-28 10:04:16 +00001551 let NumMicroOps = 2;
1552 let ResourceCycles = [1,1];
1553}
Gadi Haber2cf601f2017-12-08 09:48:44 +00001554def: InstRW<[HWWriteResGroup11_1], (instregex "CVTSS2SDrm")>;
1555def: InstRW<[HWWriteResGroup11_1], (instregex "VCVTPH2PSYrm")>;
1556def: InstRW<[HWWriteResGroup11_1], (instregex "VCVTSS2SDrm")>;
1557def: InstRW<[HWWriteResGroup11_1], (instregex "VPSLLVQrm")>;
1558def: InstRW<[HWWriteResGroup11_1], (instregex "VPSRLVQrm")>;
1559def: InstRW<[HWWriteResGroup11_1], (instregex "VTESTPDrm")>;
1560def: InstRW<[HWWriteResGroup11_1], (instregex "VTESTPSrm")>;
1561
1562def HWWriteResGroup11_2 : SchedWriteRes<[HWPort0,HWPort23]> {
1563 let Latency = 8;
1564 let NumMicroOps = 2;
1565 let ResourceCycles = [1,1];
1566}
1567def: InstRW<[HWWriteResGroup11_2], (instregex "VPSLLDYrm")>;
1568def: InstRW<[HWWriteResGroup11_2], (instregex "VPSLLQYrm")>;
1569def: InstRW<[HWWriteResGroup11_2], (instregex "VPSLLVQYrm")>;
1570def: InstRW<[HWWriteResGroup11_2], (instregex "VPSLLWYrm")>;
1571def: InstRW<[HWWriteResGroup11_2], (instregex "VPSRADYrm")>;
1572def: InstRW<[HWWriteResGroup11_2], (instregex "VPSRAWYrm")>;
1573def: InstRW<[HWWriteResGroup11_2], (instregex "VPSRLDYrm")>;
1574def: InstRW<[HWWriteResGroup11_2], (instregex "VPSRLQYrm")>;
1575def: InstRW<[HWWriteResGroup11_2], (instregex "VPSRLVQYrm")>;
1576def: InstRW<[HWWriteResGroup11_2], (instregex "VPSRLWYrm")>;
1577def: InstRW<[HWWriteResGroup11_2], (instregex "VTESTPDYrm")>;
1578def: InstRW<[HWWriteResGroup11_2], (instregex "VTESTPSYrm")>;
1579
1580def HWWriteResGroup12 : SchedWriteRes<[HWPort1,HWPort23]> {
1581 let Latency = 8;
1582 let NumMicroOps = 2;
1583 let ResourceCycles = [1,1];
1584}
1585def: InstRW<[HWWriteResGroup12], (instregex "ADDSDrm")>;
1586def: InstRW<[HWWriteResGroup12], (instregex "ADDSSrm")>;
1587def: InstRW<[HWWriteResGroup12], (instregex "BSF(16|32|64)rm")>;
1588def: InstRW<[HWWriteResGroup12], (instregex "BSR(16|32|64)rm")>;
1589def: InstRW<[HWWriteResGroup12], (instregex "CMPSSrm")>;
1590def: InstRW<[HWWriteResGroup12], (instregex "COMISDrm")>;
1591def: InstRW<[HWWriteResGroup12], (instregex "COMISSrm")>;
Gadi Haberd76f7b82017-08-28 10:04:16 +00001592def: InstRW<[HWWriteResGroup12], (instregex "FCOM32m")>;
1593def: InstRW<[HWWriteResGroup12], (instregex "FCOM64m")>;
1594def: InstRW<[HWWriteResGroup12], (instregex "FCOMP32m")>;
1595def: InstRW<[HWWriteResGroup12], (instregex "FCOMP64m")>;
Gadi Haber2cf601f2017-12-08 09:48:44 +00001596def: InstRW<[HWWriteResGroup12], (instregex "IMUL(16|32|64)m")>;
1597def: InstRW<[HWWriteResGroup12], (instregex "IMUL(16|32|64)rm(i8?)")>;
1598def: InstRW<[HWWriteResGroup12], (instregex "IMUL8m")>;
1599def: InstRW<[HWWriteResGroup12], (instregex "LZCNT(16|32|64)rm")>;
Craig Topper5ffe8012017-12-10 01:24:05 +00001600def: InstRW<[HWWriteResGroup12], (instregex "MAX(C?)SDrm")>;
1601def: InstRW<[HWWriteResGroup12], (instregex "MAX(C?)SSrm")>;
1602def: InstRW<[HWWriteResGroup12], (instregex "MIN(C?)SDrm")>;
1603def: InstRW<[HWWriteResGroup12], (instregex "MIN(C?)SSrm")>;
Gadi Haber2cf601f2017-12-08 09:48:44 +00001604def: InstRW<[HWWriteResGroup12], (instregex "MMX_CVTPI2PSirm")>;
1605def: InstRW<[HWWriteResGroup12], (instregex "MMX_CVTPS2PIirm")>;
1606def: InstRW<[HWWriteResGroup12], (instregex "MMX_CVTTPS2PIirm")>;
1607def: InstRW<[HWWriteResGroup12], (instregex "MUL(16|32|64)m")>;
1608def: InstRW<[HWWriteResGroup12], (instregex "MUL8m")>;
1609def: InstRW<[HWWriteResGroup12], (instregex "PDEP32rm")>;
1610def: InstRW<[HWWriteResGroup12], (instregex "PDEP64rm")>;
1611def: InstRW<[HWWriteResGroup12], (instregex "PEXT32rm")>;
1612def: InstRW<[HWWriteResGroup12], (instregex "PEXT64rm")>;
1613def: InstRW<[HWWriteResGroup12], (instregex "POPCNT(16|32|64)rm")>;
1614def: InstRW<[HWWriteResGroup12], (instregex "SUBSDrm")>;
1615def: InstRW<[HWWriteResGroup12], (instregex "SUBSSrm")>;
1616def: InstRW<[HWWriteResGroup12], (instregex "TZCNT(16|32|64)rm")>;
1617def: InstRW<[HWWriteResGroup12], (instregex "UCOMISDrm")>;
1618def: InstRW<[HWWriteResGroup12], (instregex "UCOMISSrm")>;
1619def: InstRW<[HWWriteResGroup12], (instregex "VADDSDrm")>;
1620def: InstRW<[HWWriteResGroup12], (instregex "VADDSSrm")>;
1621def: InstRW<[HWWriteResGroup12], (instregex "VCMPSDrm")>;
1622def: InstRW<[HWWriteResGroup12], (instregex "VCMPSSrm")>;
1623def: InstRW<[HWWriteResGroup12], (instregex "VCOMISDrm")>;
1624def: InstRW<[HWWriteResGroup12], (instregex "VCOMISSrm")>;
Craig Topper5ffe8012017-12-10 01:24:05 +00001625def: InstRW<[HWWriteResGroup12], (instregex "VMAX(C?)SDrm")>;
1626def: InstRW<[HWWriteResGroup12], (instregex "VMAX(C?)SSrm")>;
1627def: InstRW<[HWWriteResGroup12], (instregex "VMIN(C?)SDrm")>;
1628def: InstRW<[HWWriteResGroup12], (instregex "VMIN(C?)SSrm")>;
Gadi Haber2cf601f2017-12-08 09:48:44 +00001629def: InstRW<[HWWriteResGroup12], (instregex "VSUBSDrm")>;
1630def: InstRW<[HWWriteResGroup12], (instregex "VSUBSSrm")>;
1631def: InstRW<[HWWriteResGroup12], (instregex "VUCOMISDrm")>;
1632def: InstRW<[HWWriteResGroup12], (instregex "VUCOMISSrm")>;
Gadi Haberd76f7b82017-08-28 10:04:16 +00001633
1634def HWWriteResGroup13 : SchedWriteRes<[HWPort5,HWPort23]> {
Gadi Haber2cf601f2017-12-08 09:48:44 +00001635 let Latency = 7;
Gadi Haberd76f7b82017-08-28 10:04:16 +00001636 let NumMicroOps = 2;
1637 let ResourceCycles = [1,1];
1638}
1639def: InstRW<[HWWriteResGroup13], (instregex "ANDNPDrm")>;
1640def: InstRW<[HWWriteResGroup13], (instregex "ANDNPSrm")>;
1641def: InstRW<[HWWriteResGroup13], (instregex "ANDPDrm")>;
1642def: InstRW<[HWWriteResGroup13], (instregex "ANDPSrm")>;
1643def: InstRW<[HWWriteResGroup13], (instregex "INSERTPSrm")>;
Gadi Haberd76f7b82017-08-28 10:04:16 +00001644def: InstRW<[HWWriteResGroup13], (instregex "ORPDrm")>;
1645def: InstRW<[HWWriteResGroup13], (instregex "ORPSrm")>;
1646def: InstRW<[HWWriteResGroup13], (instregex "PACKSSDWrm")>;
1647def: InstRW<[HWWriteResGroup13], (instregex "PACKSSWBrm")>;
1648def: InstRW<[HWWriteResGroup13], (instregex "PACKUSDWrm")>;
1649def: InstRW<[HWWriteResGroup13], (instregex "PACKUSWBrm")>;
1650def: InstRW<[HWWriteResGroup13], (instregex "PALIGNRrmi")>;
1651def: InstRW<[HWWriteResGroup13], (instregex "PBLENDWrmi")>;
Gadi Haberd76f7b82017-08-28 10:04:16 +00001652def: InstRW<[HWWriteResGroup13], (instregex "PSHUFBrm")>;
1653def: InstRW<[HWWriteResGroup13], (instregex "PSHUFDmi")>;
1654def: InstRW<[HWWriteResGroup13], (instregex "PSHUFHWmi")>;
1655def: InstRW<[HWWriteResGroup13], (instregex "PSHUFLWmi")>;
1656def: InstRW<[HWWriteResGroup13], (instregex "PUNPCKHBWrm")>;
1657def: InstRW<[HWWriteResGroup13], (instregex "PUNPCKHDQrm")>;
1658def: InstRW<[HWWriteResGroup13], (instregex "PUNPCKHQDQrm")>;
1659def: InstRW<[HWWriteResGroup13], (instregex "PUNPCKHWDrm")>;
1660def: InstRW<[HWWriteResGroup13], (instregex "PUNPCKLBWrm")>;
1661def: InstRW<[HWWriteResGroup13], (instregex "PUNPCKLDQrm")>;
1662def: InstRW<[HWWriteResGroup13], (instregex "PUNPCKLQDQrm")>;
1663def: InstRW<[HWWriteResGroup13], (instregex "PUNPCKLWDrm")>;
1664def: InstRW<[HWWriteResGroup13], (instregex "SHUFPDrmi")>;
1665def: InstRW<[HWWriteResGroup13], (instregex "SHUFPSrmi")>;
1666def: InstRW<[HWWriteResGroup13], (instregex "UNPCKHPDrm")>;
1667def: InstRW<[HWWriteResGroup13], (instregex "UNPCKHPSrm")>;
1668def: InstRW<[HWWriteResGroup13], (instregex "UNPCKLPDrm")>;
1669def: InstRW<[HWWriteResGroup13], (instregex "UNPCKLPSrm")>;
Gadi Haberd76f7b82017-08-28 10:04:16 +00001670def: InstRW<[HWWriteResGroup13], (instregex "VANDNPDrm")>;
Gadi Haberd76f7b82017-08-28 10:04:16 +00001671def: InstRW<[HWWriteResGroup13], (instregex "VANDNPSrm")>;
Gadi Haberd76f7b82017-08-28 10:04:16 +00001672def: InstRW<[HWWriteResGroup13], (instregex "VANDPDrm")>;
Gadi Haberd76f7b82017-08-28 10:04:16 +00001673def: InstRW<[HWWriteResGroup13], (instregex "VANDPSrm")>;
1674def: InstRW<[HWWriteResGroup13], (instregex "VINSERTPSrm")>;
Gadi Haberd76f7b82017-08-28 10:04:16 +00001675def: InstRW<[HWWriteResGroup13], (instregex "VORPDrm")>;
Gadi Haberd76f7b82017-08-28 10:04:16 +00001676def: InstRW<[HWWriteResGroup13], (instregex "VORPSrm")>;
Gadi Haberd76f7b82017-08-28 10:04:16 +00001677def: InstRW<[HWWriteResGroup13], (instregex "VPACKSSDWrm")>;
Gadi Haberd76f7b82017-08-28 10:04:16 +00001678def: InstRW<[HWWriteResGroup13], (instregex "VPACKSSWBrm")>;
Gadi Haberd76f7b82017-08-28 10:04:16 +00001679def: InstRW<[HWWriteResGroup13], (instregex "VPACKUSDWrm")>;
Gadi Haberd76f7b82017-08-28 10:04:16 +00001680def: InstRW<[HWWriteResGroup13], (instregex "VPACKUSWBrm")>;
Gadi Haberd76f7b82017-08-28 10:04:16 +00001681def: InstRW<[HWWriteResGroup13], (instregex "VPALIGNRrmi")>;
Gadi Haberd76f7b82017-08-28 10:04:16 +00001682def: InstRW<[HWWriteResGroup13], (instregex "VPBLENDWrmi")>;
Gadi Haberd76f7b82017-08-28 10:04:16 +00001683def: InstRW<[HWWriteResGroup13], (instregex "VPERMILPDmi")>;
1684def: InstRW<[HWWriteResGroup13], (instregex "VPERMILPDrm")>;
Gadi Haberd76f7b82017-08-28 10:04:16 +00001685def: InstRW<[HWWriteResGroup13], (instregex "VPERMILPSmi")>;
1686def: InstRW<[HWWriteResGroup13], (instregex "VPERMILPSrm")>;
Gadi Haberd76f7b82017-08-28 10:04:16 +00001687def: InstRW<[HWWriteResGroup13], (instregex "VPSHUFBrm")>;
Gadi Haberd76f7b82017-08-28 10:04:16 +00001688def: InstRW<[HWWriteResGroup13], (instregex "VPSHUFDmi")>;
Gadi Haberd76f7b82017-08-28 10:04:16 +00001689def: InstRW<[HWWriteResGroup13], (instregex "VPSHUFHWmi")>;
Gadi Haberd76f7b82017-08-28 10:04:16 +00001690def: InstRW<[HWWriteResGroup13], (instregex "VPSHUFLWmi")>;
Gadi Haberd76f7b82017-08-28 10:04:16 +00001691def: InstRW<[HWWriteResGroup13], (instregex "VPUNPCKHBWrm")>;
Gadi Haberd76f7b82017-08-28 10:04:16 +00001692def: InstRW<[HWWriteResGroup13], (instregex "VPUNPCKHDQrm")>;
Gadi Haberd76f7b82017-08-28 10:04:16 +00001693def: InstRW<[HWWriteResGroup13], (instregex "VPUNPCKHQDQrm")>;
Gadi Haberd76f7b82017-08-28 10:04:16 +00001694def: InstRW<[HWWriteResGroup13], (instregex "VPUNPCKHWDrm")>;
Gadi Haberd76f7b82017-08-28 10:04:16 +00001695def: InstRW<[HWWriteResGroup13], (instregex "VPUNPCKLBWrm")>;
Gadi Haberd76f7b82017-08-28 10:04:16 +00001696def: InstRW<[HWWriteResGroup13], (instregex "VPUNPCKLDQrm")>;
Gadi Haberd76f7b82017-08-28 10:04:16 +00001697def: InstRW<[HWWriteResGroup13], (instregex "VPUNPCKLQDQrm")>;
Gadi Haberd76f7b82017-08-28 10:04:16 +00001698def: InstRW<[HWWriteResGroup13], (instregex "VPUNPCKLWDrm")>;
Gadi Haberd76f7b82017-08-28 10:04:16 +00001699def: InstRW<[HWWriteResGroup13], (instregex "VSHUFPDrmi")>;
Gadi Haberd76f7b82017-08-28 10:04:16 +00001700def: InstRW<[HWWriteResGroup13], (instregex "VSHUFPSrmi")>;
Gadi Haberd76f7b82017-08-28 10:04:16 +00001701def: InstRW<[HWWriteResGroup13], (instregex "VUNPCKHPDrm")>;
Gadi Haberd76f7b82017-08-28 10:04:16 +00001702def: InstRW<[HWWriteResGroup13], (instregex "VUNPCKHPSrm")>;
Gadi Haberd76f7b82017-08-28 10:04:16 +00001703def: InstRW<[HWWriteResGroup13], (instregex "VUNPCKLPDrm")>;
Gadi Haberd76f7b82017-08-28 10:04:16 +00001704def: InstRW<[HWWriteResGroup13], (instregex "VUNPCKLPSrm")>;
Gadi Haberd76f7b82017-08-28 10:04:16 +00001705def: InstRW<[HWWriteResGroup13], (instregex "VXORPDrm")>;
Gadi Haberd76f7b82017-08-28 10:04:16 +00001706def: InstRW<[HWWriteResGroup13], (instregex "VXORPSrm")>;
1707def: InstRW<[HWWriteResGroup13], (instregex "XORPDrm")>;
1708def: InstRW<[HWWriteResGroup13], (instregex "XORPSrm")>;
1709
Gadi Haber2cf601f2017-12-08 09:48:44 +00001710def HWWriteResGroup13_1 : SchedWriteRes<[HWPort5,HWPort23]> {
1711 let Latency = 8;
1712 let NumMicroOps = 2;
1713 let ResourceCycles = [1,1];
1714}
1715def: InstRW<[HWWriteResGroup13_1], (instregex "VANDNPDYrm")>;
1716def: InstRW<[HWWriteResGroup13_1], (instregex "VANDNPSYrm")>;
1717def: InstRW<[HWWriteResGroup13_1], (instregex "VANDPDYrm")>;
1718def: InstRW<[HWWriteResGroup13_1], (instregex "VANDPSYrm")>;
1719def: InstRW<[HWWriteResGroup13_1], (instregex "VORPDYrm")>;
1720def: InstRW<[HWWriteResGroup13_1], (instregex "VORPSYrm")>;
1721def: InstRW<[HWWriteResGroup13_1], (instregex "VPACKSSDWYrm")>;
1722def: InstRW<[HWWriteResGroup13_1], (instregex "VPACKSSWBYrm")>;
1723def: InstRW<[HWWriteResGroup13_1], (instregex "VPACKUSDWYrm")>;
1724def: InstRW<[HWWriteResGroup13_1], (instregex "VPACKUSWBYrm")>;
1725def: InstRW<[HWWriteResGroup13_1], (instregex "VPALIGNRYrmi")>;
1726def: InstRW<[HWWriteResGroup13_1], (instregex "VPBLENDWYrmi")>;
1727def: InstRW<[HWWriteResGroup13_1], (instregex "VPERMILPDYmi")>;
1728def: InstRW<[HWWriteResGroup13_1], (instregex "VPERMILPDYrm")>;
1729def: InstRW<[HWWriteResGroup13_1], (instregex "VPERMILPSYmi")>;
1730def: InstRW<[HWWriteResGroup13_1], (instregex "VPERMILPSYrm")>;
1731def: InstRW<[HWWriteResGroup13_1], (instregex "VPMOVSXBDYrm")>;
1732def: InstRW<[HWWriteResGroup13_1], (instregex "VPMOVSXBQYrm")>;
1733def: InstRW<[HWWriteResGroup13_1], (instregex "VPMOVSXWQYrm")>;
1734def: InstRW<[HWWriteResGroup13_1], (instregex "VPSHUFBYrm")>;
1735def: InstRW<[HWWriteResGroup13_1], (instregex "VPSHUFDYmi")>;
1736def: InstRW<[HWWriteResGroup13_1], (instregex "VPSHUFHWYmi")>;
1737def: InstRW<[HWWriteResGroup13_1], (instregex "VPSHUFLWYmi")>;
1738def: InstRW<[HWWriteResGroup13_1], (instregex "VPUNPCKHBWYrm")>;
1739def: InstRW<[HWWriteResGroup13_1], (instregex "VPUNPCKHDQYrm")>;
1740def: InstRW<[HWWriteResGroup13_1], (instregex "VPUNPCKHQDQYrm")>;
1741def: InstRW<[HWWriteResGroup13_1], (instregex "VPUNPCKHWDYrm")>;
1742def: InstRW<[HWWriteResGroup13_1], (instregex "VPUNPCKLBWYrm")>;
1743def: InstRW<[HWWriteResGroup13_1], (instregex "VPUNPCKLDQYrm")>;
1744def: InstRW<[HWWriteResGroup13_1], (instregex "VPUNPCKLQDQYrm")>;
1745def: InstRW<[HWWriteResGroup13_1], (instregex "VPUNPCKLWDYrm")>;
1746def: InstRW<[HWWriteResGroup13_1], (instregex "VSHUFPDYrmi")>;
1747def: InstRW<[HWWriteResGroup13_1], (instregex "VSHUFPSYrmi")>;
1748def: InstRW<[HWWriteResGroup13_1], (instregex "VUNPCKHPDYrm")>;
1749def: InstRW<[HWWriteResGroup13_1], (instregex "VUNPCKHPSYrm")>;
1750def: InstRW<[HWWriteResGroup13_1], (instregex "VUNPCKLPDYrm")>;
1751def: InstRW<[HWWriteResGroup13_1], (instregex "VUNPCKLPSYrm")>;
1752def: InstRW<[HWWriteResGroup13_1], (instregex "VXORPDYrm")>;
1753def: InstRW<[HWWriteResGroup13_1], (instregex "VXORPSYrm")>;
1754
1755def HWWriteResGroup13_2 : SchedWriteRes<[HWPort5,HWPort23]> {
1756 let Latency = 6;
1757 let NumMicroOps = 2;
1758 let ResourceCycles = [1,1];
1759}
1760def: InstRW<[HWWriteResGroup13_2], (instregex "MMX_PALIGNR64irm")>;
1761def: InstRW<[HWWriteResGroup13_2], (instregex "MMX_PINSRWirmi")>;
1762def: InstRW<[HWWriteResGroup13_2], (instregex "MMX_PSHUFBrm64")>;
1763def: InstRW<[HWWriteResGroup13_2], (instregex "MMX_PSHUFWmi")>;
1764def: InstRW<[HWWriteResGroup13_2], (instregex "MMX_PUNPCKHBWirm")>;
1765def: InstRW<[HWWriteResGroup13_2], (instregex "MMX_PUNPCKHDQirm")>;
1766def: InstRW<[HWWriteResGroup13_2], (instregex "MMX_PUNPCKHWDirm")>;
1767def: InstRW<[HWWriteResGroup13_2], (instregex "MMX_PUNPCKLBWirm")>;
1768def: InstRW<[HWWriteResGroup13_2], (instregex "MMX_PUNPCKLDQirm")>;
1769def: InstRW<[HWWriteResGroup13_2], (instregex "MMX_PUNPCKLWDirm")>;
1770def: InstRW<[HWWriteResGroup13_2], (instregex "MOVHPDrm")>;
1771def: InstRW<[HWWriteResGroup13_2], (instregex "MOVHPSrm")>;
1772def: InstRW<[HWWriteResGroup13_2], (instregex "MOVLPDrm")>;
1773def: InstRW<[HWWriteResGroup13_2], (instregex "MOVLPSrm")>;
1774def: InstRW<[HWWriteResGroup13_2], (instregex "PINSRBrm")>;
1775def: InstRW<[HWWriteResGroup13_2], (instregex "PINSRDrm")>;
1776def: InstRW<[HWWriteResGroup13_2], (instregex "PINSRQrm")>;
1777def: InstRW<[HWWriteResGroup13_2], (instregex "PINSRWrmi")>;
1778def: InstRW<[HWWriteResGroup13_2], (instregex "PMOVSXBDrm")>;
1779def: InstRW<[HWWriteResGroup13_2], (instregex "PMOVSXBQrm")>;
1780def: InstRW<[HWWriteResGroup13_2], (instregex "PMOVSXBWrm")>;
1781def: InstRW<[HWWriteResGroup13_2], (instregex "PMOVSXDQrm")>;
1782def: InstRW<[HWWriteResGroup13_2], (instregex "PMOVSXWDrm")>;
1783def: InstRW<[HWWriteResGroup13_2], (instregex "PMOVSXWQrm")>;
1784def: InstRW<[HWWriteResGroup13_2], (instregex "PMOVZXBDrm")>;
1785def: InstRW<[HWWriteResGroup13_2], (instregex "PMOVZXBQrm")>;
1786def: InstRW<[HWWriteResGroup13_2], (instregex "PMOVZXBWrm")>;
1787def: InstRW<[HWWriteResGroup13_2], (instregex "PMOVZXDQrm")>;
1788def: InstRW<[HWWriteResGroup13_2], (instregex "PMOVZXWDrm")>;
1789def: InstRW<[HWWriteResGroup13_2], (instregex "PMOVZXWQrm")>;
1790def: InstRW<[HWWriteResGroup13_2], (instregex "VMOVHPDrm")>;
1791def: InstRW<[HWWriteResGroup13_2], (instregex "VMOVHPSrm")>;
1792def: InstRW<[HWWriteResGroup13_2], (instregex "VMOVLPDrm")>;
1793def: InstRW<[HWWriteResGroup13_2], (instregex "VMOVLPSrm")>;
1794def: InstRW<[HWWriteResGroup13_2], (instregex "VPINSRBrm")>;
1795def: InstRW<[HWWriteResGroup13_2], (instregex "VPINSRDrm")>;
1796def: InstRW<[HWWriteResGroup13_2], (instregex "VPINSRQrm")>;
1797def: InstRW<[HWWriteResGroup13_2], (instregex "VPINSRWrmi")>;
1798def: InstRW<[HWWriteResGroup13_2], (instregex "VPMOVSXBDrm")>;
1799def: InstRW<[HWWriteResGroup13_2], (instregex "VPMOVSXBQrm")>;
1800def: InstRW<[HWWriteResGroup13_2], (instregex "VPMOVSXBWrm")>;
1801def: InstRW<[HWWriteResGroup13_2], (instregex "VPMOVSXDQrm")>;
1802def: InstRW<[HWWriteResGroup13_2], (instregex "VPMOVSXWDrm")>;
1803def: InstRW<[HWWriteResGroup13_2], (instregex "VPMOVSXWQrm")>;
1804def: InstRW<[HWWriteResGroup13_2], (instregex "VPMOVZXBDrm")>;
1805def: InstRW<[HWWriteResGroup13_2], (instregex "VPMOVZXBQrm")>;
1806def: InstRW<[HWWriteResGroup13_2], (instregex "VPMOVZXBWrm")>;
1807def: InstRW<[HWWriteResGroup13_2], (instregex "VPMOVZXDQrm")>;
1808def: InstRW<[HWWriteResGroup13_2], (instregex "VPMOVZXWDrm")>;
1809def: InstRW<[HWWriteResGroup13_2], (instregex "VPMOVZXWQrm")>;
1810
Gadi Haberd76f7b82017-08-28 10:04:16 +00001811def HWWriteResGroup14 : SchedWriteRes<[HWPort6,HWPort23]> {
Gadi Haber2cf601f2017-12-08 09:48:44 +00001812 let Latency = 6;
Gadi Haberd76f7b82017-08-28 10:04:16 +00001813 let NumMicroOps = 2;
1814 let ResourceCycles = [1,1];
1815}
1816def: InstRW<[HWWriteResGroup14], (instregex "FARJMP64")>;
1817def: InstRW<[HWWriteResGroup14], (instregex "JMP(16|32|64)m")>;
1818
1819def HWWriteResGroup15 : SchedWriteRes<[HWPort23,HWPort06]> {
Gadi Haber2cf601f2017-12-08 09:48:44 +00001820 let Latency = 6;
Gadi Haberd76f7b82017-08-28 10:04:16 +00001821 let NumMicroOps = 2;
1822 let ResourceCycles = [1,1];
1823}
1824def: InstRW<[HWWriteResGroup15], (instregex "BT(16|32|64)mi8")>;
1825def: InstRW<[HWWriteResGroup15], (instregex "RORX32mi")>;
1826def: InstRW<[HWWriteResGroup15], (instregex "RORX64mi")>;
1827def: InstRW<[HWWriteResGroup15], (instregex "SARX32rm")>;
1828def: InstRW<[HWWriteResGroup15], (instregex "SARX64rm")>;
1829def: InstRW<[HWWriteResGroup15], (instregex "SHLX32rm")>;
1830def: InstRW<[HWWriteResGroup15], (instregex "SHLX64rm")>;
1831def: InstRW<[HWWriteResGroup15], (instregex "SHRX32rm")>;
1832def: InstRW<[HWWriteResGroup15], (instregex "SHRX64rm")>;
1833
1834def HWWriteResGroup16 : SchedWriteRes<[HWPort23,HWPort15]> {
Gadi Haber2cf601f2017-12-08 09:48:44 +00001835 let Latency = 6;
Gadi Haberd76f7b82017-08-28 10:04:16 +00001836 let NumMicroOps = 2;
1837 let ResourceCycles = [1,1];
1838}
1839def: InstRW<[HWWriteResGroup16], (instregex "ANDN32rm")>;
1840def: InstRW<[HWWriteResGroup16], (instregex "ANDN64rm")>;
1841def: InstRW<[HWWriteResGroup16], (instregex "BLSI32rm")>;
1842def: InstRW<[HWWriteResGroup16], (instregex "BLSI64rm")>;
1843def: InstRW<[HWWriteResGroup16], (instregex "BLSMSK32rm")>;
1844def: InstRW<[HWWriteResGroup16], (instregex "BLSMSK64rm")>;
1845def: InstRW<[HWWriteResGroup16], (instregex "BLSR32rm")>;
1846def: InstRW<[HWWriteResGroup16], (instregex "BLSR64rm")>;
1847def: InstRW<[HWWriteResGroup16], (instregex "BZHI32rm")>;
1848def: InstRW<[HWWriteResGroup16], (instregex "BZHI64rm")>;
1849def: InstRW<[HWWriteResGroup16], (instregex "MMX_PABSBrm64")>;
1850def: InstRW<[HWWriteResGroup16], (instregex "MMX_PABSDrm64")>;
1851def: InstRW<[HWWriteResGroup16], (instregex "MMX_PABSWrm64")>;
1852def: InstRW<[HWWriteResGroup16], (instregex "MMX_PADDBirm")>;
1853def: InstRW<[HWWriteResGroup16], (instregex "MMX_PADDDirm")>;
1854def: InstRW<[HWWriteResGroup16], (instregex "MMX_PADDQirm")>;
1855def: InstRW<[HWWriteResGroup16], (instregex "MMX_PADDSBirm")>;
1856def: InstRW<[HWWriteResGroup16], (instregex "MMX_PADDSWirm")>;
1857def: InstRW<[HWWriteResGroup16], (instregex "MMX_PADDUSBirm")>;
1858def: InstRW<[HWWriteResGroup16], (instregex "MMX_PADDUSWirm")>;
1859def: InstRW<[HWWriteResGroup16], (instregex "MMX_PADDWirm")>;
1860def: InstRW<[HWWriteResGroup16], (instregex "MMX_PAVGBirm")>;
1861def: InstRW<[HWWriteResGroup16], (instregex "MMX_PAVGWirm")>;
1862def: InstRW<[HWWriteResGroup16], (instregex "MMX_PCMPEQBirm")>;
1863def: InstRW<[HWWriteResGroup16], (instregex "MMX_PCMPEQDirm")>;
1864def: InstRW<[HWWriteResGroup16], (instregex "MMX_PCMPEQWirm")>;
1865def: InstRW<[HWWriteResGroup16], (instregex "MMX_PCMPGTBirm")>;
1866def: InstRW<[HWWriteResGroup16], (instregex "MMX_PCMPGTDirm")>;
1867def: InstRW<[HWWriteResGroup16], (instregex "MMX_PCMPGTWirm")>;
1868def: InstRW<[HWWriteResGroup16], (instregex "MMX_PMAXSWirm")>;
1869def: InstRW<[HWWriteResGroup16], (instregex "MMX_PMAXUBirm")>;
1870def: InstRW<[HWWriteResGroup16], (instregex "MMX_PMINSWirm")>;
1871def: InstRW<[HWWriteResGroup16], (instregex "MMX_PMINUBirm")>;
1872def: InstRW<[HWWriteResGroup16], (instregex "MMX_PSIGNBrm64")>;
1873def: InstRW<[HWWriteResGroup16], (instregex "MMX_PSIGNDrm64")>;
1874def: InstRW<[HWWriteResGroup16], (instregex "MMX_PSIGNWrm64")>;
1875def: InstRW<[HWWriteResGroup16], (instregex "MMX_PSUBBirm")>;
1876def: InstRW<[HWWriteResGroup16], (instregex "MMX_PSUBDirm")>;
1877def: InstRW<[HWWriteResGroup16], (instregex "MMX_PSUBQirm")>;
1878def: InstRW<[HWWriteResGroup16], (instregex "MMX_PSUBSBirm")>;
1879def: InstRW<[HWWriteResGroup16], (instregex "MMX_PSUBSWirm")>;
1880def: InstRW<[HWWriteResGroup16], (instregex "MMX_PSUBUSBirm")>;
1881def: InstRW<[HWWriteResGroup16], (instregex "MMX_PSUBUSWirm")>;
1882def: InstRW<[HWWriteResGroup16], (instregex "MMX_PSUBWirm")>;
1883def: InstRW<[HWWriteResGroup16], (instregex "MOVBE(16|32|64)rm")>;
Gadi Haber2cf601f2017-12-08 09:48:44 +00001884
1885def HWWriteResGroup16_1 : SchedWriteRes<[HWPort23,HWPort15]> {
1886 let Latency = 7;
1887 let NumMicroOps = 2;
1888 let ResourceCycles = [1,1];
1889}
1890def: InstRW<[HWWriteResGroup16_1], (instregex "PABSBrm")>;
1891def: InstRW<[HWWriteResGroup16_1], (instregex "PABSDrm")>;
1892def: InstRW<[HWWriteResGroup16_1], (instregex "PABSWrm")>;
1893def: InstRW<[HWWriteResGroup16_1], (instregex "PADDBrm")>;
1894def: InstRW<[HWWriteResGroup16_1], (instregex "PADDDrm")>;
1895def: InstRW<[HWWriteResGroup16_1], (instregex "PADDQrm")>;
1896def: InstRW<[HWWriteResGroup16_1], (instregex "PADDSBrm")>;
1897def: InstRW<[HWWriteResGroup16_1], (instregex "PADDSWrm")>;
1898def: InstRW<[HWWriteResGroup16_1], (instregex "PADDUSBrm")>;
1899def: InstRW<[HWWriteResGroup16_1], (instregex "PADDUSWrm")>;
1900def: InstRW<[HWWriteResGroup16_1], (instregex "PADDWrm")>;
1901def: InstRW<[HWWriteResGroup16_1], (instregex "PAVGBrm")>;
1902def: InstRW<[HWWriteResGroup16_1], (instregex "PAVGWrm")>;
1903def: InstRW<[HWWriteResGroup16_1], (instregex "PCMPEQBrm")>;
1904def: InstRW<[HWWriteResGroup16_1], (instregex "PCMPEQDrm")>;
1905def: InstRW<[HWWriteResGroup16_1], (instregex "PCMPEQQrm")>;
1906def: InstRW<[HWWriteResGroup16_1], (instregex "PCMPEQWrm")>;
1907def: InstRW<[HWWriteResGroup16_1], (instregex "PCMPGTBrm")>;
1908def: InstRW<[HWWriteResGroup16_1], (instregex "PCMPGTDrm")>;
1909def: InstRW<[HWWriteResGroup16_1], (instregex "PCMPGTWrm")>;
1910def: InstRW<[HWWriteResGroup16_1], (instregex "PMAXSBrm")>;
1911def: InstRW<[HWWriteResGroup16_1], (instregex "PMAXSDrm")>;
1912def: InstRW<[HWWriteResGroup16_1], (instregex "PMAXSWrm")>;
1913def: InstRW<[HWWriteResGroup16_1], (instregex "PMAXUBrm")>;
1914def: InstRW<[HWWriteResGroup16_1], (instregex "PMAXUDrm")>;
1915def: InstRW<[HWWriteResGroup16_1], (instregex "PMAXUWrm")>;
1916def: InstRW<[HWWriteResGroup16_1], (instregex "PMINSBrm")>;
1917def: InstRW<[HWWriteResGroup16_1], (instregex "PMINSDrm")>;
1918def: InstRW<[HWWriteResGroup16_1], (instregex "PMINSWrm")>;
1919def: InstRW<[HWWriteResGroup16_1], (instregex "PMINUBrm")>;
1920def: InstRW<[HWWriteResGroup16_1], (instregex "PMINUDrm")>;
1921def: InstRW<[HWWriteResGroup16_1], (instregex "PMINUWrm")>;
1922def: InstRW<[HWWriteResGroup16_1], (instregex "PSIGNBrm128")>;
1923def: InstRW<[HWWriteResGroup16_1], (instregex "PSIGNDrm128")>;
1924def: InstRW<[HWWriteResGroup16_1], (instregex "PSIGNWrm128")>;
1925def: InstRW<[HWWriteResGroup16_1], (instregex "PSUBBrm")>;
1926def: InstRW<[HWWriteResGroup16_1], (instregex "PSUBDrm")>;
1927def: InstRW<[HWWriteResGroup16_1], (instregex "PSUBQrm")>;
1928def: InstRW<[HWWriteResGroup16_1], (instregex "PSUBSBrm")>;
1929def: InstRW<[HWWriteResGroup16_1], (instregex "PSUBSWrm")>;
1930def: InstRW<[HWWriteResGroup16_1], (instregex "PSUBUSBrm")>;
1931def: InstRW<[HWWriteResGroup16_1], (instregex "PSUBUSWrm")>;
1932def: InstRW<[HWWriteResGroup16_1], (instregex "PSUBWrm")>;
1933def: InstRW<[HWWriteResGroup16_1], (instregex "VPABSBrm")>;
1934def: InstRW<[HWWriteResGroup16_1], (instregex "VPABSDrm")>;
1935def: InstRW<[HWWriteResGroup16_1], (instregex "VPABSWrm")>;
1936def: InstRW<[HWWriteResGroup16_1], (instregex "VPADDBrm")>;
1937def: InstRW<[HWWriteResGroup16_1], (instregex "VPADDDrm")>;
1938def: InstRW<[HWWriteResGroup16_1], (instregex "VPADDQrm")>;
1939def: InstRW<[HWWriteResGroup16_1], (instregex "VPADDSBrm")>;
1940def: InstRW<[HWWriteResGroup16_1], (instregex "VPADDSWrm")>;
1941def: InstRW<[HWWriteResGroup16_1], (instregex "VPADDUSBrm")>;
1942def: InstRW<[HWWriteResGroup16_1], (instregex "VPADDUSWrm")>;
1943def: InstRW<[HWWriteResGroup16_1], (instregex "VPADDWrm")>;
1944def: InstRW<[HWWriteResGroup16_1], (instregex "VPAVGBrm")>;
1945def: InstRW<[HWWriteResGroup16_1], (instregex "VPAVGWrm")>;
1946def: InstRW<[HWWriteResGroup16_1], (instregex "VPCMPEQBrm")>;
1947def: InstRW<[HWWriteResGroup16_1], (instregex "VPCMPEQDrm")>;
1948def: InstRW<[HWWriteResGroup16_1], (instregex "VPCMPEQQrm")>;
1949def: InstRW<[HWWriteResGroup16_1], (instregex "VPCMPEQWrm")>;
1950def: InstRW<[HWWriteResGroup16_1], (instregex "VPCMPGTBrm")>;
1951def: InstRW<[HWWriteResGroup16_1], (instregex "VPCMPGTDrm")>;
1952def: InstRW<[HWWriteResGroup16_1], (instregex "VPCMPGTWrm")>;
1953def: InstRW<[HWWriteResGroup16_1], (instregex "VPMAXSBrm")>;
1954def: InstRW<[HWWriteResGroup16_1], (instregex "VPMAXSDrm")>;
1955def: InstRW<[HWWriteResGroup16_1], (instregex "VPMAXSWrm")>;
1956def: InstRW<[HWWriteResGroup16_1], (instregex "VPMAXUBrm")>;
1957def: InstRW<[HWWriteResGroup16_1], (instregex "VPMAXUDrm")>;
1958def: InstRW<[HWWriteResGroup16_1], (instregex "VPMAXUWrm")>;
1959def: InstRW<[HWWriteResGroup16_1], (instregex "VPMINSBrm")>;
1960def: InstRW<[HWWriteResGroup16_1], (instregex "VPMINSDrm")>;
1961def: InstRW<[HWWriteResGroup16_1], (instregex "VPMINSWrm")>;
1962def: InstRW<[HWWriteResGroup16_1], (instregex "VPMINUBrm")>;
1963def: InstRW<[HWWriteResGroup16_1], (instregex "VPMINUDrm")>;
1964def: InstRW<[HWWriteResGroup16_1], (instregex "VPMINUWrm")>;
1965def: InstRW<[HWWriteResGroup16_1], (instregex "VPSIGNBrm128")>;
1966def: InstRW<[HWWriteResGroup16_1], (instregex "VPSIGNDrm128")>;
1967def: InstRW<[HWWriteResGroup16_1], (instregex "VPSIGNWrm128")>;
1968def: InstRW<[HWWriteResGroup16_1], (instregex "VPSUBBrm")>;
1969def: InstRW<[HWWriteResGroup16_1], (instregex "VPSUBDrm")>;
1970def: InstRW<[HWWriteResGroup16_1], (instregex "VPSUBQrm")>;
1971def: InstRW<[HWWriteResGroup16_1], (instregex "VPSUBSBrm")>;
1972def: InstRW<[HWWriteResGroup16_1], (instregex "VPSUBSWrm")>;
1973def: InstRW<[HWWriteResGroup16_1], (instregex "VPSUBUSBrm")>;
1974def: InstRW<[HWWriteResGroup16_1], (instregex "VPSUBUSWrm")>;
1975def: InstRW<[HWWriteResGroup16_1], (instregex "VPSUBWrm")>;
1976
1977def HWWriteResGroup16_2 : SchedWriteRes<[HWPort23,HWPort15]> {
1978 let Latency = 8;
1979 let NumMicroOps = 2;
1980 let ResourceCycles = [1,1];
1981}
1982def: InstRW<[HWWriteResGroup16_2], (instregex "VPABSBYrm")>;
1983def: InstRW<[HWWriteResGroup16_2], (instregex "VPABSDYrm")>;
1984def: InstRW<[HWWriteResGroup16_2], (instregex "VPABSWYrm")>;
1985def: InstRW<[HWWriteResGroup16_2], (instregex "VPADDBYrm")>;
1986def: InstRW<[HWWriteResGroup16_2], (instregex "VPADDDYrm")>;
1987def: InstRW<[HWWriteResGroup16_2], (instregex "VPADDQYrm")>;
1988def: InstRW<[HWWriteResGroup16_2], (instregex "VPADDSBYrm")>;
1989def: InstRW<[HWWriteResGroup16_2], (instregex "VPADDSWYrm")>;
1990def: InstRW<[HWWriteResGroup16_2], (instregex "VPADDUSBYrm")>;
1991def: InstRW<[HWWriteResGroup16_2], (instregex "VPADDUSWYrm")>;
1992def: InstRW<[HWWriteResGroup16_2], (instregex "VPADDWYrm")>;
1993def: InstRW<[HWWriteResGroup16_2], (instregex "VPAVGBYrm")>;
1994def: InstRW<[HWWriteResGroup16_2], (instregex "VPAVGWYrm")>;
1995def: InstRW<[HWWriteResGroup16_2], (instregex "VPCMPEQBYrm")>;
1996def: InstRW<[HWWriteResGroup16_2], (instregex "VPCMPEQDYrm")>;
1997def: InstRW<[HWWriteResGroup16_2], (instregex "VPCMPEQQYrm")>;
1998def: InstRW<[HWWriteResGroup16_2], (instregex "VPCMPEQWYrm")>;
1999def: InstRW<[HWWriteResGroup16_2], (instregex "VPCMPGTBYrm")>;
2000def: InstRW<[HWWriteResGroup16_2], (instregex "VPCMPGTDYrm")>;
2001def: InstRW<[HWWriteResGroup16_2], (instregex "VPCMPGTWYrm")>;
2002def: InstRW<[HWWriteResGroup16_2], (instregex "VPMAXSBYrm")>;
2003def: InstRW<[HWWriteResGroup16_2], (instregex "VPMAXSDYrm")>;
2004def: InstRW<[HWWriteResGroup16_2], (instregex "VPMAXSWYrm")>;
2005def: InstRW<[HWWriteResGroup16_2], (instregex "VPMAXUBYrm")>;
2006def: InstRW<[HWWriteResGroup16_2], (instregex "VPMAXUDYrm")>;
2007def: InstRW<[HWWriteResGroup16_2], (instregex "VPMAXUWYrm")>;
2008def: InstRW<[HWWriteResGroup16_2], (instregex "VPMINSBYrm")>;
2009def: InstRW<[HWWriteResGroup16_2], (instregex "VPMINSDYrm")>;
2010def: InstRW<[HWWriteResGroup16_2], (instregex "VPMINSWYrm")>;
2011def: InstRW<[HWWriteResGroup16_2], (instregex "VPMINUBYrm")>;
2012def: InstRW<[HWWriteResGroup16_2], (instregex "VPMINUDYrm")>;
2013def: InstRW<[HWWriteResGroup16_2], (instregex "VPMINUWYrm")>;
2014def: InstRW<[HWWriteResGroup16_2], (instregex "VPSIGNBYrm256")>;
2015def: InstRW<[HWWriteResGroup16_2], (instregex "VPSIGNDYrm256")>;
2016def: InstRW<[HWWriteResGroup16_2], (instregex "VPSIGNWYrm256")>;
2017def: InstRW<[HWWriteResGroup16_2], (instregex "VPSUBBYrm")>;
2018def: InstRW<[HWWriteResGroup16_2], (instregex "VPSUBDYrm")>;
2019def: InstRW<[HWWriteResGroup16_2], (instregex "VPSUBQYrm")>;
2020def: InstRW<[HWWriteResGroup16_2], (instregex "VPSUBSBYrm")>;
2021def: InstRW<[HWWriteResGroup16_2], (instregex "VPSUBSWYrm")>;
2022def: InstRW<[HWWriteResGroup16_2], (instregex "VPSUBUSBYrm")>;
2023def: InstRW<[HWWriteResGroup16_2], (instregex "VPSUBUSWYrm")>;
2024def: InstRW<[HWWriteResGroup16_2], (instregex "VPSUBWYrm")>;
Gadi Haberd76f7b82017-08-28 10:04:16 +00002025
2026def HWWriteResGroup17 : SchedWriteRes<[HWPort23,HWPort015]> {
Gadi Haber2cf601f2017-12-08 09:48:44 +00002027 let Latency = 7;
Gadi Haberd76f7b82017-08-28 10:04:16 +00002028 let NumMicroOps = 2;
2029 let ResourceCycles = [1,1];
2030}
2031def: InstRW<[HWWriteResGroup17], (instregex "BLENDPDrmi")>;
2032def: InstRW<[HWWriteResGroup17], (instregex "BLENDPSrmi")>;
Gadi Haberd76f7b82017-08-28 10:04:16 +00002033def: InstRW<[HWWriteResGroup17], (instregex "PANDNrm")>;
2034def: InstRW<[HWWriteResGroup17], (instregex "PANDrm")>;
2035def: InstRW<[HWWriteResGroup17], (instregex "PORrm")>;
2036def: InstRW<[HWWriteResGroup17], (instregex "PXORrm")>;
Gadi Haberd76f7b82017-08-28 10:04:16 +00002037def: InstRW<[HWWriteResGroup17], (instregex "VBLENDPDrmi")>;
Gadi Haberd76f7b82017-08-28 10:04:16 +00002038def: InstRW<[HWWriteResGroup17], (instregex "VBLENDPSrmi")>;
2039def: InstRW<[HWWriteResGroup17], (instregex "VINSERTF128rm")>;
2040def: InstRW<[HWWriteResGroup17], (instregex "VINSERTI128rm")>;
Gadi Haberd76f7b82017-08-28 10:04:16 +00002041def: InstRW<[HWWriteResGroup17], (instregex "VPANDNrm")>;
Gadi Haberd76f7b82017-08-28 10:04:16 +00002042def: InstRW<[HWWriteResGroup17], (instregex "VPANDrm")>;
Gadi Haberd76f7b82017-08-28 10:04:16 +00002043def: InstRW<[HWWriteResGroup17], (instregex "VPBLENDDrmi")>;
Gadi Haberd76f7b82017-08-28 10:04:16 +00002044def: InstRW<[HWWriteResGroup17], (instregex "VPORrm")>;
Gadi Haberd76f7b82017-08-28 10:04:16 +00002045def: InstRW<[HWWriteResGroup17], (instregex "VPXORrm")>;
2046
Gadi Haber2cf601f2017-12-08 09:48:44 +00002047def HWWriteResGroup17_1 : SchedWriteRes<[HWPort23,HWPort015]> {
2048 let Latency = 6;
2049 let NumMicroOps = 2;
2050 let ResourceCycles = [1,1];
2051}
2052def: InstRW<[HWWriteResGroup17_1], (instregex "MMX_PANDNirm")>;
2053def: InstRW<[HWWriteResGroup17_1], (instregex "MMX_PANDirm")>;
2054def: InstRW<[HWWriteResGroup17_1], (instregex "MMX_PORirm")>;
2055def: InstRW<[HWWriteResGroup17_1], (instregex "MMX_PXORirm")>;
2056
2057def HWWriteResGroup17_2 : SchedWriteRes<[HWPort23,HWPort015]> {
2058 let Latency = 8;
2059 let NumMicroOps = 2;
2060 let ResourceCycles = [1,1];
2061}
2062def: InstRW<[HWWriteResGroup17_2], (instregex "VBLENDPDYrmi")>;
2063def: InstRW<[HWWriteResGroup17_2], (instregex "VBLENDPSYrmi")>;
2064def: InstRW<[HWWriteResGroup17_2], (instregex "VPANDNYrm")>;
2065def: InstRW<[HWWriteResGroup17_2], (instregex "VPANDYrm")>;
2066def: InstRW<[HWWriteResGroup17_2], (instregex "VPBLENDDYrmi")>;
2067def: InstRW<[HWWriteResGroup17_2], (instregex "VPORYrm")>;
2068def: InstRW<[HWWriteResGroup17_2], (instregex "VPXORYrm")>;
2069
Gadi Haberd76f7b82017-08-28 10:04:16 +00002070def HWWriteResGroup18 : SchedWriteRes<[HWPort23,HWPort0156]> {
Gadi Haber2cf601f2017-12-08 09:48:44 +00002071 let Latency = 6;
Gadi Haberd76f7b82017-08-28 10:04:16 +00002072 let NumMicroOps = 2;
2073 let ResourceCycles = [1,1];
2074}
2075def: InstRW<[HWWriteResGroup18], (instregex "ADD(16|32|64)rm")>;
2076def: InstRW<[HWWriteResGroup18], (instregex "ADD8rm")>;
2077def: InstRW<[HWWriteResGroup18], (instregex "AND(16|32|64)rm")>;
2078def: InstRW<[HWWriteResGroup18], (instregex "AND8rm")>;
2079def: InstRW<[HWWriteResGroup18], (instregex "CMP(16|32|64)mi8")>;
2080def: InstRW<[HWWriteResGroup18], (instregex "CMP(16|32|64)mr")>;
2081def: InstRW<[HWWriteResGroup18], (instregex "CMP(16|32|64)rm")>;
2082def: InstRW<[HWWriteResGroup18], (instregex "CMP8mi")>;
2083def: InstRW<[HWWriteResGroup18], (instregex "CMP8mr")>;
2084def: InstRW<[HWWriteResGroup18], (instregex "CMP8rm")>;
2085def: InstRW<[HWWriteResGroup18], (instregex "OR(16|32|64)rm")>;
2086def: InstRW<[HWWriteResGroup18], (instregex "OR8rm")>;
2087def: InstRW<[HWWriteResGroup18], (instregex "POP(16|32|64)r(mr?)")>;
2088def: InstRW<[HWWriteResGroup18], (instregex "SUB(16|32|64)rm")>;
2089def: InstRW<[HWWriteResGroup18], (instregex "SUB8rm")>;
Craig Topperc20b46d2017-10-01 23:53:53 +00002090def: InstRW<[HWWriteResGroup18], (instregex "TEST(16|32|64)mr")>;
Gadi Haberd76f7b82017-08-28 10:04:16 +00002091def: InstRW<[HWWriteResGroup18], (instregex "TEST8mi")>;
Craig Topperc20b46d2017-10-01 23:53:53 +00002092def: InstRW<[HWWriteResGroup18], (instregex "TEST8mr")>;
Gadi Haberd76f7b82017-08-28 10:04:16 +00002093def: InstRW<[HWWriteResGroup18], (instregex "XOR(16|32|64)rm")>;
2094def: InstRW<[HWWriteResGroup18], (instregex "XOR8rm")>;
2095
2096def HWWriteResGroup19 : SchedWriteRes<[HWPort237,HWPort0156]> {
Gadi Haber2cf601f2017-12-08 09:48:44 +00002097 let Latency = 2;
Gadi Haberd76f7b82017-08-28 10:04:16 +00002098 let NumMicroOps = 2;
2099 let ResourceCycles = [1,1];
2100}
2101def: InstRW<[HWWriteResGroup19], (instregex "SFENCE")>;
2102
2103def HWWriteResGroup20 : SchedWriteRes<[HWPort4,HWPort5,HWPort237]> {
Gadi Haber2cf601f2017-12-08 09:48:44 +00002104 let Latency = 2;
Michael Zuckermanf6684002017-06-28 11:23:31 +00002105 let NumMicroOps = 3;
Gadi Haberd76f7b82017-08-28 10:04:16 +00002106 let ResourceCycles = [1,1,1];
Michael Zuckermanf6684002017-06-28 11:23:31 +00002107}
Gadi Haberd76f7b82017-08-28 10:04:16 +00002108def: InstRW<[HWWriteResGroup20], (instregex "EXTRACTPSmr")>;
2109def: InstRW<[HWWriteResGroup20], (instregex "PEXTRBmr")>;
2110def: InstRW<[HWWriteResGroup20], (instregex "PEXTRDmr")>;
2111def: InstRW<[HWWriteResGroup20], (instregex "PEXTRQmr")>;
2112def: InstRW<[HWWriteResGroup20], (instregex "PEXTRWmr")>;
2113def: InstRW<[HWWriteResGroup20], (instregex "STMXCSR")>;
2114def: InstRW<[HWWriteResGroup20], (instregex "VEXTRACTPSmr")>;
2115def: InstRW<[HWWriteResGroup20], (instregex "VPEXTRBmr")>;
2116def: InstRW<[HWWriteResGroup20], (instregex "VPEXTRDmr")>;
2117def: InstRW<[HWWriteResGroup20], (instregex "VPEXTRQmr")>;
2118def: InstRW<[HWWriteResGroup20], (instregex "VPEXTRWmr")>;
2119def: InstRW<[HWWriteResGroup20], (instregex "VSTMXCSR")>;
Michael Zuckermanf6684002017-06-28 11:23:31 +00002120
Gadi Haberd76f7b82017-08-28 10:04:16 +00002121def HWWriteResGroup21 : SchedWriteRes<[HWPort4,HWPort6,HWPort237]> {
Gadi Haber2cf601f2017-12-08 09:48:44 +00002122 let Latency = 2;
Gadi Haberd76f7b82017-08-28 10:04:16 +00002123 let NumMicroOps = 3;
2124 let ResourceCycles = [1,1,1];
2125}
2126def: InstRW<[HWWriteResGroup21], (instregex "FNSTCW16m")>;
Michael Zuckermanf6684002017-06-28 11:23:31 +00002127
Gadi Haberd76f7b82017-08-28 10:04:16 +00002128def HWWriteResGroup22 : SchedWriteRes<[HWPort4,HWPort237,HWPort06]> {
Gadi Haber2cf601f2017-12-08 09:48:44 +00002129 let Latency = 2;
Gadi Haberd76f7b82017-08-28 10:04:16 +00002130 let NumMicroOps = 3;
2131 let ResourceCycles = [1,1,1];
2132}
2133def: InstRW<[HWWriteResGroup22], (instregex "SETAEm")>;
2134def: InstRW<[HWWriteResGroup22], (instregex "SETBm")>;
2135def: InstRW<[HWWriteResGroup22], (instregex "SETEm")>;
2136def: InstRW<[HWWriteResGroup22], (instregex "SETGEm")>;
2137def: InstRW<[HWWriteResGroup22], (instregex "SETGm")>;
2138def: InstRW<[HWWriteResGroup22], (instregex "SETLEm")>;
2139def: InstRW<[HWWriteResGroup22], (instregex "SETLm")>;
2140def: InstRW<[HWWriteResGroup22], (instregex "SETNEm")>;
2141def: InstRW<[HWWriteResGroup22], (instregex "SETNOm")>;
2142def: InstRW<[HWWriteResGroup22], (instregex "SETNPm")>;
2143def: InstRW<[HWWriteResGroup22], (instregex "SETNSm")>;
2144def: InstRW<[HWWriteResGroup22], (instregex "SETOm")>;
2145def: InstRW<[HWWriteResGroup22], (instregex "SETPm")>;
2146def: InstRW<[HWWriteResGroup22], (instregex "SETSm")>;
Michael Zuckermanf6684002017-06-28 11:23:31 +00002147
Gadi Haberd76f7b82017-08-28 10:04:16 +00002148def HWWriteResGroup23 : SchedWriteRes<[HWPort4,HWPort237,HWPort15]> {
Gadi Haber2cf601f2017-12-08 09:48:44 +00002149 let Latency = 2;
Gadi Haberd76f7b82017-08-28 10:04:16 +00002150 let NumMicroOps = 3;
2151 let ResourceCycles = [1,1,1];
2152}
2153def: InstRW<[HWWriteResGroup23], (instregex "MOVBE(32|64)mr")>;
2154
2155def HWWriteResGroup23_16 : SchedWriteRes<[HWPort06, HWPort237, HWPort4]> {
Gadi Haber2cf601f2017-12-08 09:48:44 +00002156 let Latency = 2;
Gadi Haberd76f7b82017-08-28 10:04:16 +00002157 let NumMicroOps = 3;
2158 let ResourceCycles = [1,1,1];
2159}
2160def: InstRW<[HWWriteResGroup23_16], (instregex "MOVBE16mr")>;
2161
2162def HWWriteResGroup24 : SchedWriteRes<[HWPort4,HWPort237,HWPort0156]> {
Gadi Haber2cf601f2017-12-08 09:48:44 +00002163 let Latency = 2;
Gadi Haberd76f7b82017-08-28 10:04:16 +00002164 let NumMicroOps = 3;
2165 let ResourceCycles = [1,1,1];
2166}
2167def: InstRW<[HWWriteResGroup24], (instregex "PUSH(16|32|64)r(mr?)")>;
2168def: InstRW<[HWWriteResGroup24], (instregex "PUSH64i8")>;
2169def: InstRW<[HWWriteResGroup24], (instregex "STOSB")>;
2170def: InstRW<[HWWriteResGroup24], (instregex "STOSL")>;
2171def: InstRW<[HWWriteResGroup24], (instregex "STOSQ")>;
2172def: InstRW<[HWWriteResGroup24], (instregex "STOSW")>;
2173
2174def HWWriteResGroup25 : SchedWriteRes<[HWPort4,HWPort23,HWPort237,HWPort06]> {
Gadi Haber2cf601f2017-12-08 09:48:44 +00002175 let Latency = 7;
Gadi Haberd76f7b82017-08-28 10:04:16 +00002176 let NumMicroOps = 4;
2177 let ResourceCycles = [1,1,1,1];
2178}
2179def: InstRW<[HWWriteResGroup25], (instregex "BTC(16|32|64)mi8")>;
2180def: InstRW<[HWWriteResGroup25], (instregex "BTR(16|32|64)mi8")>;
2181def: InstRW<[HWWriteResGroup25], (instregex "BTS(16|32|64)mi8")>;
2182def: InstRW<[HWWriteResGroup25], (instregex "SAR(16|32|64)m1")>;
2183def: InstRW<[HWWriteResGroup25], (instregex "SAR(16|32|64)mi")>;
2184def: InstRW<[HWWriteResGroup25], (instregex "SAR8m1")>;
2185def: InstRW<[HWWriteResGroup25], (instregex "SAR8mi")>;
2186def: InstRW<[HWWriteResGroup25], (instregex "SHL(16|32|64)m1")>;
2187def: InstRW<[HWWriteResGroup25], (instregex "SHL(16|32|64)mi")>;
2188def: InstRW<[HWWriteResGroup25], (instregex "SHL8m1")>;
2189def: InstRW<[HWWriteResGroup25], (instregex "SHL8mi")>;
2190def: InstRW<[HWWriteResGroup25], (instregex "SHR(16|32|64)m1")>;
2191def: InstRW<[HWWriteResGroup25], (instregex "SHR(16|32|64)mi")>;
2192def: InstRW<[HWWriteResGroup25], (instregex "SHR8m1")>;
2193def: InstRW<[HWWriteResGroup25], (instregex "SHR8mi")>;
2194
2195def HWWriteResGroup26 : SchedWriteRes<[HWPort4,HWPort23,HWPort237,HWPort0156]> {
Gadi Haber2cf601f2017-12-08 09:48:44 +00002196 let Latency = 7;
Gadi Haberd76f7b82017-08-28 10:04:16 +00002197 let NumMicroOps = 4;
2198 let ResourceCycles = [1,1,1,1];
2199}
2200def: InstRW<[HWWriteResGroup26], (instregex "ADD(16|32|64)mi8")>;
2201def: InstRW<[HWWriteResGroup26], (instregex "ADD(16|32|64)mr")>;
2202def: InstRW<[HWWriteResGroup26], (instregex "ADD8mi")>;
2203def: InstRW<[HWWriteResGroup26], (instregex "ADD8mr")>;
2204def: InstRW<[HWWriteResGroup26], (instregex "AND(16|32|64)mi8")>;
2205def: InstRW<[HWWriteResGroup26], (instregex "AND(16|32|64)mr")>;
2206def: InstRW<[HWWriteResGroup26], (instregex "AND8mi")>;
2207def: InstRW<[HWWriteResGroup26], (instregex "AND8mr")>;
2208def: InstRW<[HWWriteResGroup26], (instregex "DEC(16|32|64)m")>;
2209def: InstRW<[HWWriteResGroup26], (instregex "DEC8m")>;
2210def: InstRW<[HWWriteResGroup26], (instregex "INC(16|32|64)m")>;
2211def: InstRW<[HWWriteResGroup26], (instregex "INC8m")>;
2212def: InstRW<[HWWriteResGroup26], (instregex "NEG(16|32|64)m")>;
2213def: InstRW<[HWWriteResGroup26], (instregex "NEG8m")>;
2214def: InstRW<[HWWriteResGroup26], (instregex "NOT(16|32|64)m")>;
2215def: InstRW<[HWWriteResGroup26], (instregex "NOT8m")>;
2216def: InstRW<[HWWriteResGroup26], (instregex "OR(16|32|64)mi8")>;
2217def: InstRW<[HWWriteResGroup26], (instregex "OR(16|32|64)mr")>;
2218def: InstRW<[HWWriteResGroup26], (instregex "OR8mi")>;
2219def: InstRW<[HWWriteResGroup26], (instregex "OR8mr")>;
Gadi Haber2cf601f2017-12-08 09:48:44 +00002220def: InstRW<[HWWriteResGroup26], (instregex "POP(16|32|64)rmm")>;
2221def: InstRW<[HWWriteResGroup26], (instregex "PUSH(16|32|64)rmm")>;
Gadi Haberd76f7b82017-08-28 10:04:16 +00002222def: InstRW<[HWWriteResGroup26], (instregex "SUB(16|32|64)mi8")>;
2223def: InstRW<[HWWriteResGroup26], (instregex "SUB(16|32|64)mr")>;
2224def: InstRW<[HWWriteResGroup26], (instregex "SUB8mi")>;
2225def: InstRW<[HWWriteResGroup26], (instregex "SUB8mr")>;
2226def: InstRW<[HWWriteResGroup26], (instregex "XOR(16|32|64)mi8")>;
2227def: InstRW<[HWWriteResGroup26], (instregex "XOR(16|32|64)mr")>;
2228def: InstRW<[HWWriteResGroup26], (instregex "XOR8mi")>;
2229def: InstRW<[HWWriteResGroup26], (instregex "XOR8mr")>;
2230
2231def HWWriteResGroup27 : SchedWriteRes<[HWPort5]> {
Michael Zuckermanf6684002017-06-28 11:23:31 +00002232 let Latency = 2;
2233 let NumMicroOps = 2;
Michael Zuckermanf6684002017-06-28 11:23:31 +00002234 let ResourceCycles = [2];
2235}
Gadi Haberd76f7b82017-08-28 10:04:16 +00002236def: InstRW<[HWWriteResGroup27], (instregex "BLENDVPDrr0")>;
2237def: InstRW<[HWWriteResGroup27], (instregex "BLENDVPSrr0")>;
2238def: InstRW<[HWWriteResGroup27], (instregex "MMX_PINSRWirri")>;
2239def: InstRW<[HWWriteResGroup27], (instregex "PBLENDVBrr0")>;
2240def: InstRW<[HWWriteResGroup27], (instregex "PINSRBrr")>;
2241def: InstRW<[HWWriteResGroup27], (instregex "PINSRDrr")>;
2242def: InstRW<[HWWriteResGroup27], (instregex "PINSRQrr")>;
2243def: InstRW<[HWWriteResGroup27], (instregex "PINSRWrri")>;
2244def: InstRW<[HWWriteResGroup27], (instregex "VBLENDVPDYrr")>;
2245def: InstRW<[HWWriteResGroup27], (instregex "VBLENDVPDrr")>;
2246def: InstRW<[HWWriteResGroup27], (instregex "VBLENDVPSYrr")>;
2247def: InstRW<[HWWriteResGroup27], (instregex "VBLENDVPSrr")>;
2248def: InstRW<[HWWriteResGroup27], (instregex "VPBLENDVBYrr")>;
2249def: InstRW<[HWWriteResGroup27], (instregex "VPBLENDVBrr")>;
2250def: InstRW<[HWWriteResGroup27], (instregex "VPINSRBrr")>;
2251def: InstRW<[HWWriteResGroup27], (instregex "VPINSRDrr")>;
2252def: InstRW<[HWWriteResGroup27], (instregex "VPINSRQrr")>;
2253def: InstRW<[HWWriteResGroup27], (instregex "VPINSRWrri")>;
Michael Zuckermanf6684002017-06-28 11:23:31 +00002254
Gadi Haberd76f7b82017-08-28 10:04:16 +00002255def HWWriteResGroup28 : SchedWriteRes<[HWPort01]> {
2256 let Latency = 2;
2257 let NumMicroOps = 2;
2258 let ResourceCycles = [2];
2259}
2260def: InstRW<[HWWriteResGroup28], (instregex "FDECSTP")>;
2261
2262def HWWriteResGroup29 : SchedWriteRes<[HWPort06]> {
2263 let Latency = 2;
2264 let NumMicroOps = 2;
2265 let ResourceCycles = [2];
2266}
2267def: InstRW<[HWWriteResGroup29], (instregex "ROL(16|32|64)r1")>;
2268def: InstRW<[HWWriteResGroup29], (instregex "ROL(16|32|64)ri")>;
2269def: InstRW<[HWWriteResGroup29], (instregex "ROL8r1")>;
2270def: InstRW<[HWWriteResGroup29], (instregex "ROL8ri")>;
2271def: InstRW<[HWWriteResGroup29], (instregex "ROR(16|32|64)r1")>;
2272def: InstRW<[HWWriteResGroup29], (instregex "ROR(16|32|64)ri")>;
2273def: InstRW<[HWWriteResGroup29], (instregex "ROR8r1")>;
2274def: InstRW<[HWWriteResGroup29], (instregex "ROR8ri")>;
2275
2276def HWWriteResGroup30 : SchedWriteRes<[HWPort0156]> {
2277 let Latency = 2;
2278 let NumMicroOps = 2;
2279 let ResourceCycles = [2];
2280}
2281def: InstRW<[HWWriteResGroup30], (instregex "LFENCE")>;
2282def: InstRW<[HWWriteResGroup30], (instregex "MFENCE")>;
2283def: InstRW<[HWWriteResGroup30], (instregex "WAIT")>;
2284def: InstRW<[HWWriteResGroup30], (instregex "XGETBV")>;
2285
2286def HWWriteResGroup31 : SchedWriteRes<[HWPort0,HWPort5]> {
2287 let Latency = 2;
2288 let NumMicroOps = 2;
2289 let ResourceCycles = [1,1];
2290}
2291def: InstRW<[HWWriteResGroup31], (instregex "CVTPS2PDrr")>;
2292def: InstRW<[HWWriteResGroup31], (instregex "CVTSS2SDrr")>;
2293def: InstRW<[HWWriteResGroup31], (instregex "EXTRACTPSrr")>;
2294def: InstRW<[HWWriteResGroup31], (instregex "MMX_PEXTRWirri")>;
2295def: InstRW<[HWWriteResGroup31], (instregex "PEXTRBrr")>;
2296def: InstRW<[HWWriteResGroup31], (instregex "PEXTRDrr")>;
2297def: InstRW<[HWWriteResGroup31], (instregex "PEXTRQrr")>;
2298def: InstRW<[HWWriteResGroup31], (instregex "PEXTRWri")>;
2299def: InstRW<[HWWriteResGroup31], (instregex "PEXTRWrr_REV")>;
2300def: InstRW<[HWWriteResGroup31], (instregex "PSLLDrr")>;
2301def: InstRW<[HWWriteResGroup31], (instregex "PSLLQrr")>;
2302def: InstRW<[HWWriteResGroup31], (instregex "PSLLWrr")>;
2303def: InstRW<[HWWriteResGroup31], (instregex "PSRADrr")>;
2304def: InstRW<[HWWriteResGroup31], (instregex "PSRAWrr")>;
2305def: InstRW<[HWWriteResGroup31], (instregex "PSRLDrr")>;
2306def: InstRW<[HWWriteResGroup31], (instregex "PSRLQrr")>;
2307def: InstRW<[HWWriteResGroup31], (instregex "PSRLWrr")>;
2308def: InstRW<[HWWriteResGroup31], (instregex "PTESTrr")>;
2309def: InstRW<[HWWriteResGroup31], (instregex "VCVTPH2PSYrr")>;
2310def: InstRW<[HWWriteResGroup31], (instregex "VCVTPH2PSrr")>;
2311def: InstRW<[HWWriteResGroup31], (instregex "VCVTPS2PDrr")>;
2312def: InstRW<[HWWriteResGroup31], (instregex "VCVTSS2SDrr")>;
2313def: InstRW<[HWWriteResGroup31], (instregex "VEXTRACTPSrr")>;
2314def: InstRW<[HWWriteResGroup31], (instregex "VPEXTRBrr")>;
2315def: InstRW<[HWWriteResGroup31], (instregex "VPEXTRDrr")>;
2316def: InstRW<[HWWriteResGroup31], (instregex "VPEXTRQrr")>;
2317def: InstRW<[HWWriteResGroup31], (instregex "VPEXTRWri")>;
2318def: InstRW<[HWWriteResGroup31], (instregex "VPEXTRWrr_REV")>;
2319def: InstRW<[HWWriteResGroup31], (instregex "VPSLLDrr")>;
2320def: InstRW<[HWWriteResGroup31], (instregex "VPSLLQrr")>;
2321def: InstRW<[HWWriteResGroup31], (instregex "VPSLLWrr")>;
2322def: InstRW<[HWWriteResGroup31], (instregex "VPSRADrr")>;
2323def: InstRW<[HWWriteResGroup31], (instregex "VPSRAWrr")>;
2324def: InstRW<[HWWriteResGroup31], (instregex "VPSRLDrr")>;
2325def: InstRW<[HWWriteResGroup31], (instregex "VPSRLQrr")>;
2326def: InstRW<[HWWriteResGroup31], (instregex "VPSRLWrr")>;
2327def: InstRW<[HWWriteResGroup31], (instregex "VPTESTrr")>;
2328
2329def HWWriteResGroup32 : SchedWriteRes<[HWPort6,HWPort0156]> {
2330 let Latency = 2;
2331 let NumMicroOps = 2;
2332 let ResourceCycles = [1,1];
2333}
2334def: InstRW<[HWWriteResGroup32], (instregex "CLFLUSH")>;
2335
2336def HWWriteResGroup33 : SchedWriteRes<[HWPort01,HWPort015]> {
2337 let Latency = 2;
2338 let NumMicroOps = 2;
2339 let ResourceCycles = [1,1];
2340}
2341def: InstRW<[HWWriteResGroup33], (instregex "MMX_MOVDQ2Qrr")>;
2342
2343def HWWriteResGroup34 : SchedWriteRes<[HWPort06,HWPort15]> {
2344 let Latency = 2;
2345 let NumMicroOps = 2;
2346 let ResourceCycles = [1,1];
2347}
2348def: InstRW<[HWWriteResGroup34], (instregex "BEXTR32rr")>;
2349def: InstRW<[HWWriteResGroup34], (instregex "BEXTR64rr")>;
2350def: InstRW<[HWWriteResGroup34], (instregex "BSWAP(16|32|64)r")>;
2351
2352def HWWriteResGroup35 : SchedWriteRes<[HWPort06,HWPort0156]> {
2353 let Latency = 2;
2354 let NumMicroOps = 2;
2355 let ResourceCycles = [1,1];
2356}
2357def: InstRW<[HWWriteResGroup35], (instregex "ADC(16|32|64)ri8")>;
2358def: InstRW<[HWWriteResGroup35], (instregex "ADC(16|32|64)rr(_REV?)")>;
2359def: InstRW<[HWWriteResGroup35], (instregex "ADC8i8")>;
2360def: InstRW<[HWWriteResGroup35], (instregex "ADC8ri")>;
2361def: InstRW<[HWWriteResGroup35], (instregex "ADC8rr(_REV?)")>;
2362def: InstRW<[HWWriteResGroup35], (instregex "CMOVAE(16|32|64)rr")>;
2363def: InstRW<[HWWriteResGroup35], (instregex "CMOVB(16|32|64)rr")>;
2364def: InstRW<[HWWriteResGroup35], (instregex "CMOVE(16|32|64)rr")>;
2365def: InstRW<[HWWriteResGroup35], (instregex "CMOVG(16|32|64)rr")>;
2366def: InstRW<[HWWriteResGroup35], (instregex "CMOVGE(16|32|64)rr")>;
2367def: InstRW<[HWWriteResGroup35], (instregex "CMOVL(16|32|64)rr")>;
2368def: InstRW<[HWWriteResGroup35], (instregex "CMOVLE(16|32|64)rr")>;
2369def: InstRW<[HWWriteResGroup35], (instregex "CMOVNE(16|32|64)rr")>;
2370def: InstRW<[HWWriteResGroup35], (instregex "CMOVNO(16|32|64)rr")>;
2371def: InstRW<[HWWriteResGroup35], (instregex "CMOVNP(16|32|64)rr")>;
2372def: InstRW<[HWWriteResGroup35], (instregex "CMOVNS(16|32|64)rr")>;
2373def: InstRW<[HWWriteResGroup35], (instregex "CMOVO(16|32|64)rr")>;
2374def: InstRW<[HWWriteResGroup35], (instregex "CMOVP(16|32|64)rr")>;
2375def: InstRW<[HWWriteResGroup35], (instregex "CMOVS(16|32|64)rr")>;
2376def: InstRW<[HWWriteResGroup35], (instregex "CWD")>;
2377def: InstRW<[HWWriteResGroup35], (instregex "JRCXZ")>;
2378def: InstRW<[HWWriteResGroup35], (instregex "SBB(16|32|64)ri8")>;
2379def: InstRW<[HWWriteResGroup35], (instregex "SBB(16|32|64)rr(_REV?)")>;
2380def: InstRW<[HWWriteResGroup35], (instregex "SBB8i8")>;
2381def: InstRW<[HWWriteResGroup35], (instregex "SBB8ri")>;
2382def: InstRW<[HWWriteResGroup35], (instregex "SBB8rr(_REV?)")>;
2383def: InstRW<[HWWriteResGroup35], (instregex "SETAr")>;
2384def: InstRW<[HWWriteResGroup35], (instregex "SETBEr")>;
2385
2386def HWWriteResGroup36 : SchedWriteRes<[HWPort5,HWPort23]> {
Gadi Haber2cf601f2017-12-08 09:48:44 +00002387 let Latency = 8;
Michael Zuckermanf6684002017-06-28 11:23:31 +00002388 let NumMicroOps = 3;
Gadi Haberd76f7b82017-08-28 10:04:16 +00002389 let ResourceCycles = [2,1];
Michael Zuckermanf6684002017-06-28 11:23:31 +00002390}
Gadi Haberd76f7b82017-08-28 10:04:16 +00002391def: InstRW<[HWWriteResGroup36], (instregex "BLENDVPDrm0")>;
2392def: InstRW<[HWWriteResGroup36], (instregex "BLENDVPSrm0")>;
Gadi Haberd76f7b82017-08-28 10:04:16 +00002393def: InstRW<[HWWriteResGroup36], (instregex "PBLENDVBrm0")>;
Gadi Haberd76f7b82017-08-28 10:04:16 +00002394def: InstRW<[HWWriteResGroup36], (instregex "VBLENDVPDrm")>;
Gadi Haberd76f7b82017-08-28 10:04:16 +00002395def: InstRW<[HWWriteResGroup36], (instregex "VBLENDVPSrm")>;
Gadi Haberd76f7b82017-08-28 10:04:16 +00002396def: InstRW<[HWWriteResGroup36], (instregex "VMASKMOVPDrm")>;
Gadi Haberd76f7b82017-08-28 10:04:16 +00002397def: InstRW<[HWWriteResGroup36], (instregex "VMASKMOVPSrm")>;
Gadi Haberd76f7b82017-08-28 10:04:16 +00002398def: InstRW<[HWWriteResGroup36], (instregex "VPBLENDVBrm")>;
Gadi Haberd76f7b82017-08-28 10:04:16 +00002399def: InstRW<[HWWriteResGroup36], (instregex "VPMASKMOVDrm")>;
Gadi Haberd76f7b82017-08-28 10:04:16 +00002400def: InstRW<[HWWriteResGroup36], (instregex "VPMASKMOVQrm")>;
Michael Zuckermanf6684002017-06-28 11:23:31 +00002401
Gadi Haber2cf601f2017-12-08 09:48:44 +00002402def HWWriteResGroup36_1 : SchedWriteRes<[HWPort5,HWPort23]> {
2403 let Latency = 9;
2404 let NumMicroOps = 3;
2405 let ResourceCycles = [2,1];
2406}
2407def: InstRW<[HWWriteResGroup36_1], (instregex "VBLENDVPDYrm")>;
2408def: InstRW<[HWWriteResGroup36_1], (instregex "VBLENDVPSYrm")>;
2409def: InstRW<[HWWriteResGroup36_1], (instregex "VMASKMOVPDYrm")>;
2410def: InstRW<[HWWriteResGroup36_1], (instregex "VMASKMOVPSYrm")>;
2411def: InstRW<[HWWriteResGroup36_1], (instregex "VPBLENDVBYrm")>;
2412def: InstRW<[HWWriteResGroup36_1], (instregex "VPMASKMOVDYrm")>;
2413def: InstRW<[HWWriteResGroup36_1], (instregex "VPMASKMOVQYrm")>;
2414
2415def HWWriteResGroup36_2 : SchedWriteRes<[HWPort5,HWPort23]> {
2416 let Latency = 7;
2417 let NumMicroOps = 3;
2418 let ResourceCycles = [2,1];
2419}
2420def: InstRW<[HWWriteResGroup36_2], (instregex "MMX_PACKSSDWirm")>;
2421def: InstRW<[HWWriteResGroup36_2], (instregex "MMX_PACKSSWBirm")>;
2422def: InstRW<[HWWriteResGroup36_2], (instregex "MMX_PACKUSWBirm")>;
2423
Gadi Haberd76f7b82017-08-28 10:04:16 +00002424def HWWriteResGroup37 : SchedWriteRes<[HWPort23,HWPort0156]> {
Gadi Haber2cf601f2017-12-08 09:48:44 +00002425 let Latency = 7;
Gadi Haberd76f7b82017-08-28 10:04:16 +00002426 let NumMicroOps = 3;
2427 let ResourceCycles = [1,2];
2428}
2429def: InstRW<[HWWriteResGroup37], (instregex "LEAVE64")>;
2430def: InstRW<[HWWriteResGroup37], (instregex "SCASB")>;
2431def: InstRW<[HWWriteResGroup37], (instregex "SCASL")>;
2432def: InstRW<[HWWriteResGroup37], (instregex "SCASQ")>;
2433def: InstRW<[HWWriteResGroup37], (instregex "SCASW")>;
2434
2435def HWWriteResGroup38 : SchedWriteRes<[HWPort0,HWPort5,HWPort23]> {
Gadi Haber2cf601f2017-12-08 09:48:44 +00002436 let Latency = 8;
Gadi Haberd76f7b82017-08-28 10:04:16 +00002437 let NumMicroOps = 3;
2438 let ResourceCycles = [1,1,1];
2439}
2440def: InstRW<[HWWriteResGroup38], (instregex "PSLLDrm")>;
2441def: InstRW<[HWWriteResGroup38], (instregex "PSLLQrm")>;
2442def: InstRW<[HWWriteResGroup38], (instregex "PSLLWrm")>;
2443def: InstRW<[HWWriteResGroup38], (instregex "PSRADrm")>;
2444def: InstRW<[HWWriteResGroup38], (instregex "PSRAWrm")>;
2445def: InstRW<[HWWriteResGroup38], (instregex "PSRLDrm")>;
2446def: InstRW<[HWWriteResGroup38], (instregex "PSRLQrm")>;
2447def: InstRW<[HWWriteResGroup38], (instregex "PSRLWrm")>;
2448def: InstRW<[HWWriteResGroup38], (instregex "PTESTrm")>;
2449def: InstRW<[HWWriteResGroup38], (instregex "VPSLLDrm")>;
2450def: InstRW<[HWWriteResGroup38], (instregex "VPSLLQrm")>;
2451def: InstRW<[HWWriteResGroup38], (instregex "VPSLLWrm")>;
2452def: InstRW<[HWWriteResGroup38], (instregex "VPSRADrm")>;
2453def: InstRW<[HWWriteResGroup38], (instregex "VPSRAWrm")>;
2454def: InstRW<[HWWriteResGroup38], (instregex "VPSRLDrm")>;
2455def: InstRW<[HWWriteResGroup38], (instregex "VPSRLQrm")>;
2456def: InstRW<[HWWriteResGroup38], (instregex "VPSRLWrm")>;
2457def: InstRW<[HWWriteResGroup38], (instregex "VPTESTrm")>;
2458
2459def HWWriteResGroup39 : SchedWriteRes<[HWPort0,HWPort01,HWPort23]> {
Gadi Haber2cf601f2017-12-08 09:48:44 +00002460 let Latency = 7;
Gadi Haberd76f7b82017-08-28 10:04:16 +00002461 let NumMicroOps = 3;
2462 let ResourceCycles = [1,1,1];
2463}
2464def: InstRW<[HWWriteResGroup39], (instregex "FLDCW16m")>;
2465
2466def HWWriteResGroup40 : SchedWriteRes<[HWPort0,HWPort23,HWPort0156]> {
Gadi Haber2cf601f2017-12-08 09:48:44 +00002467 let Latency = 7;
Gadi Haberd76f7b82017-08-28 10:04:16 +00002468 let NumMicroOps = 3;
2469 let ResourceCycles = [1,1,1];
2470}
2471def: InstRW<[HWWriteResGroup40], (instregex "LDMXCSR")>;
2472def: InstRW<[HWWriteResGroup40], (instregex "VLDMXCSR")>;
2473
2474def HWWriteResGroup41 : SchedWriteRes<[HWPort6,HWPort23,HWPort0156]> {
Gadi Haber2cf601f2017-12-08 09:48:44 +00002475 let Latency = 7;
Gadi Haberd76f7b82017-08-28 10:04:16 +00002476 let NumMicroOps = 3;
2477 let ResourceCycles = [1,1,1];
2478}
2479def: InstRW<[HWWriteResGroup41], (instregex "LRETQ")>;
Gadi Haber2cf601f2017-12-08 09:48:44 +00002480def: InstRW<[HWWriteResGroup41], (instregex "RETL")>;
Gadi Haberd76f7b82017-08-28 10:04:16 +00002481def: InstRW<[HWWriteResGroup41], (instregex "RETQ")>;
2482
2483def HWWriteResGroup42 : SchedWriteRes<[HWPort23,HWPort06,HWPort15]> {
Gadi Haber2cf601f2017-12-08 09:48:44 +00002484 let Latency = 7;
Gadi Haberd76f7b82017-08-28 10:04:16 +00002485 let NumMicroOps = 3;
2486 let ResourceCycles = [1,1,1];
2487}
2488def: InstRW<[HWWriteResGroup42], (instregex "BEXTR32rm")>;
2489def: InstRW<[HWWriteResGroup42], (instregex "BEXTR64rm")>;
2490
2491def HWWriteResGroup43 : SchedWriteRes<[HWPort23,HWPort06,HWPort0156]> {
Gadi Haber2cf601f2017-12-08 09:48:44 +00002492 let Latency = 7;
Gadi Haberd76f7b82017-08-28 10:04:16 +00002493 let NumMicroOps = 3;
2494 let ResourceCycles = [1,1,1];
2495}
2496def: InstRW<[HWWriteResGroup43], (instregex "ADC(16|32|64)rm")>;
2497def: InstRW<[HWWriteResGroup43], (instregex "ADC8rm")>;
2498def: InstRW<[HWWriteResGroup43], (instregex "CMOVAE(16|32|64)rm")>;
2499def: InstRW<[HWWriteResGroup43], (instregex "CMOVB(16|32|64)rm")>;
2500def: InstRW<[HWWriteResGroup43], (instregex "CMOVE(16|32|64)rm")>;
2501def: InstRW<[HWWriteResGroup43], (instregex "CMOVG(16|32|64)rm")>;
2502def: InstRW<[HWWriteResGroup43], (instregex "CMOVGE(16|32|64)rm")>;
2503def: InstRW<[HWWriteResGroup43], (instregex "CMOVL(16|32|64)rm")>;
2504def: InstRW<[HWWriteResGroup43], (instregex "CMOVLE(16|32|64)rm")>;
2505def: InstRW<[HWWriteResGroup43], (instregex "CMOVNE(16|32|64)rm")>;
2506def: InstRW<[HWWriteResGroup43], (instregex "CMOVNO(16|32|64)rm")>;
2507def: InstRW<[HWWriteResGroup43], (instregex "CMOVNP(16|32|64)rm")>;
2508def: InstRW<[HWWriteResGroup43], (instregex "CMOVNS(16|32|64)rm")>;
2509def: InstRW<[HWWriteResGroup43], (instregex "CMOVO(16|32|64)rm")>;
2510def: InstRW<[HWWriteResGroup43], (instregex "CMOVP(16|32|64)rm")>;
2511def: InstRW<[HWWriteResGroup43], (instregex "CMOVS(16|32|64)rm")>;
2512def: InstRW<[HWWriteResGroup43], (instregex "SBB(16|32|64)rm")>;
2513def: InstRW<[HWWriteResGroup43], (instregex "SBB8rm")>;
2514
2515def HWWriteResGroup44 : SchedWriteRes<[HWPort4,HWPort6,HWPort237,HWPort0156]> {
Gadi Haber2cf601f2017-12-08 09:48:44 +00002516 let Latency = 3;
Michael Zuckermanf6684002017-06-28 11:23:31 +00002517 let NumMicroOps = 4;
Gadi Haberd76f7b82017-08-28 10:04:16 +00002518 let ResourceCycles = [1,1,1,1];
Michael Zuckermanf6684002017-06-28 11:23:31 +00002519}
Gadi Haberd76f7b82017-08-28 10:04:16 +00002520def: InstRW<[HWWriteResGroup44], (instregex "CALL(16|32|64)r")>;
Michael Zuckermanf6684002017-06-28 11:23:31 +00002521
Gadi Haberd76f7b82017-08-28 10:04:16 +00002522def HWWriteResGroup45 : SchedWriteRes<[HWPort4,HWPort237,HWPort06,HWPort0156]> {
Gadi Haber2cf601f2017-12-08 09:48:44 +00002523 let Latency = 3;
Gadi Haberd76f7b82017-08-28 10:04:16 +00002524 let NumMicroOps = 4;
2525 let ResourceCycles = [1,1,1,1];
2526}
2527def: InstRW<[HWWriteResGroup45], (instregex "CALL64pcrel32")>;
2528def: InstRW<[HWWriteResGroup45], (instregex "SETAm")>;
2529def: InstRW<[HWWriteResGroup45], (instregex "SETBEm")>;
2530
2531def HWWriteResGroup46 : SchedWriteRes<[HWPort4,HWPort23,HWPort237,HWPort06]> {
Gadi Haber2cf601f2017-12-08 09:48:44 +00002532 let Latency = 8;
Gadi Haberd76f7b82017-08-28 10:04:16 +00002533 let NumMicroOps = 5;
2534 let ResourceCycles = [1,1,1,2];
2535}
2536def: InstRW<[HWWriteResGroup46], (instregex "ROL(16|32|64)m1")>;
2537def: InstRW<[HWWriteResGroup46], (instregex "ROL(16|32|64)mi")>;
2538def: InstRW<[HWWriteResGroup46], (instregex "ROL8m1")>;
2539def: InstRW<[HWWriteResGroup46], (instregex "ROL8mi")>;
2540def: InstRW<[HWWriteResGroup46], (instregex "ROR(16|32|64)m1")>;
2541def: InstRW<[HWWriteResGroup46], (instregex "ROR(16|32|64)mi")>;
2542def: InstRW<[HWWriteResGroup46], (instregex "ROR8m1")>;
2543def: InstRW<[HWWriteResGroup46], (instregex "ROR8mi")>;
2544
2545def HWWriteResGroup47 : SchedWriteRes<[HWPort4,HWPort23,HWPort237,HWPort0156]> {
Gadi Haber2cf601f2017-12-08 09:48:44 +00002546 let Latency = 8;
Gadi Haberd76f7b82017-08-28 10:04:16 +00002547 let NumMicroOps = 5;
2548 let ResourceCycles = [1,1,1,2];
2549}
2550def: InstRW<[HWWriteResGroup47], (instregex "XADD(16|32|64)rm")>;
2551def: InstRW<[HWWriteResGroup47], (instregex "XADD8rm")>;
2552
2553def HWWriteResGroup48 : SchedWriteRes<[HWPort4,HWPort6,HWPort23,HWPort237,HWPort0156]> {
Gadi Haber2cf601f2017-12-08 09:48:44 +00002554 let Latency = 8;
Gadi Haberd76f7b82017-08-28 10:04:16 +00002555 let NumMicroOps = 5;
2556 let ResourceCycles = [1,1,1,1,1];
2557}
2558def: InstRW<[HWWriteResGroup48], (instregex "CALL(16|32|64)m")>;
2559def: InstRW<[HWWriteResGroup48], (instregex "FARCALL64")>;
2560
2561def HWWriteResGroup49 : SchedWriteRes<[HWPort0]> {
2562 let Latency = 3;
2563 let NumMicroOps = 1;
2564 let ResourceCycles = [1];
2565}
2566def: InstRW<[HWWriteResGroup49], (instregex "MOVMSKPDrr")>;
2567def: InstRW<[HWWriteResGroup49], (instregex "MOVMSKPSrr")>;
2568def: InstRW<[HWWriteResGroup49], (instregex "PMOVMSKBrr")>;
2569def: InstRW<[HWWriteResGroup49], (instregex "VMOVMSKPDYrr")>;
2570def: InstRW<[HWWriteResGroup49], (instregex "VMOVMSKPDrr")>;
2571def: InstRW<[HWWriteResGroup49], (instregex "VMOVMSKPSYrr")>;
2572def: InstRW<[HWWriteResGroup49], (instregex "VMOVMSKPSrr")>;
2573def: InstRW<[HWWriteResGroup49], (instregex "VPMOVMSKBYrr")>;
2574def: InstRW<[HWWriteResGroup49], (instregex "VPMOVMSKBrr")>;
2575
2576def HWWriteResGroup50 : SchedWriteRes<[HWPort1]> {
2577 let Latency = 3;
2578 let NumMicroOps = 1;
2579 let ResourceCycles = [1];
2580}
2581def: InstRW<[HWWriteResGroup50], (instregex "ADDPDrr")>;
2582def: InstRW<[HWWriteResGroup50], (instregex "ADDPSrr")>;
2583def: InstRW<[HWWriteResGroup50], (instregex "ADDSDrr")>;
2584def: InstRW<[HWWriteResGroup50], (instregex "ADDSSrr")>;
2585def: InstRW<[HWWriteResGroup50], (instregex "ADDSUBPDrr")>;
2586def: InstRW<[HWWriteResGroup50], (instregex "ADDSUBPSrr")>;
2587def: InstRW<[HWWriteResGroup50], (instregex "ADD_FPrST0")>;
2588def: InstRW<[HWWriteResGroup50], (instregex "ADD_FST0r")>;
2589def: InstRW<[HWWriteResGroup50], (instregex "ADD_FrST0")>;
2590def: InstRW<[HWWriteResGroup50], (instregex "BSF(16|32|64)rr")>;
2591def: InstRW<[HWWriteResGroup50], (instregex "BSR(16|32|64)rr")>;
2592def: InstRW<[HWWriteResGroup50], (instregex "CMPPDrri")>;
2593def: InstRW<[HWWriteResGroup50], (instregex "CMPPSrri")>;
2594def: InstRW<[HWWriteResGroup50], (instregex "CMPSSrr")>;
2595def: InstRW<[HWWriteResGroup50], (instregex "COMISDrr")>;
2596def: InstRW<[HWWriteResGroup50], (instregex "COMISSrr")>;
2597def: InstRW<[HWWriteResGroup50], (instregex "CVTDQ2PSrr")>;
2598def: InstRW<[HWWriteResGroup50], (instregex "CVTPS2DQrr")>;
2599def: InstRW<[HWWriteResGroup50], (instregex "CVTTPS2DQrr")>;
2600def: InstRW<[HWWriteResGroup50], (instregex "IMUL64rr(i8?)")>;
2601def: InstRW<[HWWriteResGroup50], (instregex "IMUL8r")>;
2602def: InstRW<[HWWriteResGroup50], (instregex "LZCNT(16|32|64)rr")>;
Craig Topper5ffe8012017-12-10 01:24:05 +00002603def: InstRW<[HWWriteResGroup50], (instregex "MAX(C?)PDrr")>;
2604def: InstRW<[HWWriteResGroup50], (instregex "MAX(C?)PSrr")>;
2605def: InstRW<[HWWriteResGroup50], (instregex "MAX(C?)SDrr")>;
2606def: InstRW<[HWWriteResGroup50], (instregex "MAX(C?)SSrr")>;
2607def: InstRW<[HWWriteResGroup50], (instregex "MIN(C?)PDrr")>;
2608def: InstRW<[HWWriteResGroup50], (instregex "MIN(C?)PSrr")>;
2609def: InstRW<[HWWriteResGroup50], (instregex "MIN(C?)SDrr")>;
2610def: InstRW<[HWWriteResGroup50], (instregex "MIN(C?)SSrr")>;
Gadi Haberd76f7b82017-08-28 10:04:16 +00002611def: InstRW<[HWWriteResGroup50], (instregex "MMX_CVTPI2PSirr")>;
2612def: InstRW<[HWWriteResGroup50], (instregex "MUL8r")>;
2613def: InstRW<[HWWriteResGroup50], (instregex "PDEP32rr")>;
2614def: InstRW<[HWWriteResGroup50], (instregex "PDEP64rr")>;
2615def: InstRW<[HWWriteResGroup50], (instregex "PEXT32rr")>;
2616def: InstRW<[HWWriteResGroup50], (instregex "PEXT64rr")>;
2617def: InstRW<[HWWriteResGroup50], (instregex "POPCNT(16|32|64)rr")>;
2618def: InstRW<[HWWriteResGroup50], (instregex "SHLD(16|32|64)rri8")>;
2619def: InstRW<[HWWriteResGroup50], (instregex "SHRD(16|32|64)rri8")>;
2620def: InstRW<[HWWriteResGroup50], (instregex "SUBPDrr")>;
2621def: InstRW<[HWWriteResGroup50], (instregex "SUBPSrr")>;
2622def: InstRW<[HWWriteResGroup50], (instregex "SUBR_FPrST0")>;
2623def: InstRW<[HWWriteResGroup50], (instregex "SUBR_FST0r")>;
2624def: InstRW<[HWWriteResGroup50], (instregex "SUBR_FrST0")>;
2625def: InstRW<[HWWriteResGroup50], (instregex "SUBSDrr")>;
2626def: InstRW<[HWWriteResGroup50], (instregex "SUBSSrr")>;
2627def: InstRW<[HWWriteResGroup50], (instregex "SUB_FPrST0")>;
2628def: InstRW<[HWWriteResGroup50], (instregex "SUB_FST0r")>;
2629def: InstRW<[HWWriteResGroup50], (instregex "SUB_FrST0")>;
2630def: InstRW<[HWWriteResGroup50], (instregex "TZCNT(16|32|64)rr")>;
2631def: InstRW<[HWWriteResGroup50], (instregex "UCOMISDrr")>;
2632def: InstRW<[HWWriteResGroup50], (instregex "UCOMISSrr")>;
2633def: InstRW<[HWWriteResGroup50], (instregex "VADDPDYrr")>;
2634def: InstRW<[HWWriteResGroup50], (instregex "VADDPDrr")>;
2635def: InstRW<[HWWriteResGroup50], (instregex "VADDPSYrr")>;
2636def: InstRW<[HWWriteResGroup50], (instregex "VADDPSrr")>;
2637def: InstRW<[HWWriteResGroup50], (instregex "VADDSDrr")>;
2638def: InstRW<[HWWriteResGroup50], (instregex "VADDSSrr")>;
2639def: InstRW<[HWWriteResGroup50], (instregex "VADDSUBPDYrr")>;
2640def: InstRW<[HWWriteResGroup50], (instregex "VADDSUBPDrr")>;
2641def: InstRW<[HWWriteResGroup50], (instregex "VADDSUBPSYrr")>;
2642def: InstRW<[HWWriteResGroup50], (instregex "VADDSUBPSrr")>;
2643def: InstRW<[HWWriteResGroup50], (instregex "VCMPPDYrri")>;
2644def: InstRW<[HWWriteResGroup50], (instregex "VCMPPDrri")>;
2645def: InstRW<[HWWriteResGroup50], (instregex "VCMPPSYrri")>;
2646def: InstRW<[HWWriteResGroup50], (instregex "VCMPPSrri")>;
2647def: InstRW<[HWWriteResGroup50], (instregex "VCMPSDrr")>;
2648def: InstRW<[HWWriteResGroup50], (instregex "VCMPSSrr")>;
2649def: InstRW<[HWWriteResGroup50], (instregex "VCOMISDrr")>;
2650def: InstRW<[HWWriteResGroup50], (instregex "VCOMISSrr")>;
2651def: InstRW<[HWWriteResGroup50], (instregex "VCVTDQ2PSYrr")>;
2652def: InstRW<[HWWriteResGroup50], (instregex "VCVTDQ2PSrr")>;
2653def: InstRW<[HWWriteResGroup50], (instregex "VCVTPS2DQYrr")>;
2654def: InstRW<[HWWriteResGroup50], (instregex "VCVTPS2DQrr")>;
2655def: InstRW<[HWWriteResGroup50], (instregex "VCVTTPS2DQYrr")>;
2656def: InstRW<[HWWriteResGroup50], (instregex "VCVTTPS2DQrr")>;
Craig Topper5ffe8012017-12-10 01:24:05 +00002657def: InstRW<[HWWriteResGroup50], (instregex "VMAX(C?)PDYrr")>;
2658def: InstRW<[HWWriteResGroup50], (instregex "VMAX(C?)PDrr")>;
2659def: InstRW<[HWWriteResGroup50], (instregex "VMAX(C?)PSYrr")>;
2660def: InstRW<[HWWriteResGroup50], (instregex "VMAX(C?)PSrr")>;
2661def: InstRW<[HWWriteResGroup50], (instregex "VMAX(C?)SDrr")>;
2662def: InstRW<[HWWriteResGroup50], (instregex "VMAX(C?)SSrr")>;
2663def: InstRW<[HWWriteResGroup50], (instregex "VMIN(C?)PDYrr")>;
2664def: InstRW<[HWWriteResGroup50], (instregex "VMIN(C?)PDrr")>;
2665def: InstRW<[HWWriteResGroup50], (instregex "VMIN(C?)PSYrr")>;
2666def: InstRW<[HWWriteResGroup50], (instregex "VMIN(C?)PSrr")>;
2667def: InstRW<[HWWriteResGroup50], (instregex "VMIN(C?)SDrr")>;
2668def: InstRW<[HWWriteResGroup50], (instregex "VMIN(C?)SSrr")>;
Gadi Haberd76f7b82017-08-28 10:04:16 +00002669def: InstRW<[HWWriteResGroup50], (instregex "VSUBPDYrr")>;
2670def: InstRW<[HWWriteResGroup50], (instregex "VSUBPDrr")>;
2671def: InstRW<[HWWriteResGroup50], (instregex "VSUBPSYrr")>;
2672def: InstRW<[HWWriteResGroup50], (instregex "VSUBPSrr")>;
2673def: InstRW<[HWWriteResGroup50], (instregex "VSUBSDrr")>;
2674def: InstRW<[HWWriteResGroup50], (instregex "VSUBSSrr")>;
2675def: InstRW<[HWWriteResGroup50], (instregex "VUCOMISDrr")>;
2676def: InstRW<[HWWriteResGroup50], (instregex "VUCOMISSrr")>;
2677
2678def HWWriteResGroup50_16 : SchedWriteRes<[HWPort1, HWPort0156]> {
2679 let Latency = 3;
2680 let NumMicroOps = 4;
2681}
2682def: InstRW<[HWWriteResGroup50_16], (instregex "IMUL16rr(i8?)")>;
2683
2684def HWWriteResGroup50_32 : SchedWriteRes<[HWPort1, HWPort0156]> {
2685 let Latency = 3;
2686 let NumMicroOps = 3;
2687}
2688def: InstRW<[HWWriteResGroup50_32], (instregex "IMUL32rr(i8?)")>;
2689
2690def HWWriteResGroup51 : SchedWriteRes<[HWPort5]> {
2691 let Latency = 3;
2692 let NumMicroOps = 1;
2693 let ResourceCycles = [1];
2694}
2695def: InstRW<[HWWriteResGroup51], (instregex "VBROADCASTSDYrr")>;
2696def: InstRW<[HWWriteResGroup51], (instregex "VBROADCASTSSYrr")>;
2697def: InstRW<[HWWriteResGroup51], (instregex "VEXTRACTF128rr")>;
2698def: InstRW<[HWWriteResGroup51], (instregex "VEXTRACTI128rr")>;
2699def: InstRW<[HWWriteResGroup51], (instregex "VINSERTF128rr")>;
2700def: InstRW<[HWWriteResGroup51], (instregex "VINSERTI128rr")>;
2701def: InstRW<[HWWriteResGroup51], (instregex "VPBROADCASTBYrr")>;
2702def: InstRW<[HWWriteResGroup51], (instregex "VPBROADCASTBrr")>;
2703def: InstRW<[HWWriteResGroup51], (instregex "VPBROADCASTDYrr")>;
2704def: InstRW<[HWWriteResGroup51], (instregex "VPBROADCASTQYrr")>;
2705def: InstRW<[HWWriteResGroup51], (instregex "VPBROADCASTWYrr")>;
2706def: InstRW<[HWWriteResGroup51], (instregex "VPBROADCASTWrr")>;
2707def: InstRW<[HWWriteResGroup51], (instregex "VPERM2F128rr")>;
2708def: InstRW<[HWWriteResGroup51], (instregex "VPERM2I128rr")>;
2709def: InstRW<[HWWriteResGroup51], (instregex "VPERMDYrr")>;
2710def: InstRW<[HWWriteResGroup51], (instregex "VPERMPDYri")>;
2711def: InstRW<[HWWriteResGroup51], (instregex "VPERMPSYrr")>;
2712def: InstRW<[HWWriteResGroup51], (instregex "VPERMQYri")>;
2713def: InstRW<[HWWriteResGroup51], (instregex "VPMOVSXBDYrr")>;
2714def: InstRW<[HWWriteResGroup51], (instregex "VPMOVSXBQYrr")>;
2715def: InstRW<[HWWriteResGroup51], (instregex "VPMOVSXBWYrr")>;
2716def: InstRW<[HWWriteResGroup51], (instregex "VPMOVSXDQYrr")>;
2717def: InstRW<[HWWriteResGroup51], (instregex "VPMOVSXWDYrr")>;
2718def: InstRW<[HWWriteResGroup51], (instregex "VPMOVSXWQYrr")>;
2719def: InstRW<[HWWriteResGroup51], (instregex "VPMOVZXBDYrr")>;
2720def: InstRW<[HWWriteResGroup51], (instregex "VPMOVZXBQYrr")>;
2721def: InstRW<[HWWriteResGroup51], (instregex "VPMOVZXBWYrr")>;
2722def: InstRW<[HWWriteResGroup51], (instregex "VPMOVZXDQYrr")>;
2723def: InstRW<[HWWriteResGroup51], (instregex "VPMOVZXWDYrr")>;
2724def: InstRW<[HWWriteResGroup51], (instregex "VPMOVZXWQYrr")>;
2725
2726def HWWriteResGroup52 : SchedWriteRes<[HWPort1,HWPort23]> {
Gadi Haber2cf601f2017-12-08 09:48:44 +00002727 let Latency = 9;
Gadi Haberd76f7b82017-08-28 10:04:16 +00002728 let NumMicroOps = 2;
2729 let ResourceCycles = [1,1];
2730}
2731def: InstRW<[HWWriteResGroup52], (instregex "ADDPDrm")>;
2732def: InstRW<[HWWriteResGroup52], (instregex "ADDPSrm")>;
Gadi Haberd76f7b82017-08-28 10:04:16 +00002733def: InstRW<[HWWriteResGroup52], (instregex "ADDSUBPDrm")>;
2734def: InstRW<[HWWriteResGroup52], (instregex "ADDSUBPSrm")>;
Gadi Haberd76f7b82017-08-28 10:04:16 +00002735def: InstRW<[HWWriteResGroup52], (instregex "CMPPDrmi")>;
2736def: InstRW<[HWWriteResGroup52], (instregex "CMPPSrmi")>;
Gadi Haberd76f7b82017-08-28 10:04:16 +00002737def: InstRW<[HWWriteResGroup52], (instregex "CVTDQ2PSrm")>;
2738def: InstRW<[HWWriteResGroup52], (instregex "CVTPS2DQrm")>;
2739def: InstRW<[HWWriteResGroup52], (instregex "CVTTPS2DQrm")>;
Craig Topper5ffe8012017-12-10 01:24:05 +00002740def: InstRW<[HWWriteResGroup52], (instregex "MAX(C?)PDrm")>;
2741def: InstRW<[HWWriteResGroup52], (instregex "MAX(C?)PSrm")>;
2742def: InstRW<[HWWriteResGroup52], (instregex "MIN(C?)PDrm")>;
2743def: InstRW<[HWWriteResGroup52], (instregex "MIN(C?)PSrm")>;
Gadi Haberd76f7b82017-08-28 10:04:16 +00002744def: InstRW<[HWWriteResGroup52], (instregex "SUBPDrm")>;
2745def: InstRW<[HWWriteResGroup52], (instregex "SUBPSrm")>;
Gadi Haberd76f7b82017-08-28 10:04:16 +00002746def: InstRW<[HWWriteResGroup52], (instregex "VADDPDrm")>;
Gadi Haberd76f7b82017-08-28 10:04:16 +00002747def: InstRW<[HWWriteResGroup52], (instregex "VADDPSrm")>;
Gadi Haberd76f7b82017-08-28 10:04:16 +00002748def: InstRW<[HWWriteResGroup52], (instregex "VADDSUBPDrm")>;
Gadi Haberd76f7b82017-08-28 10:04:16 +00002749def: InstRW<[HWWriteResGroup52], (instregex "VADDSUBPSrm")>;
Gadi Haberd76f7b82017-08-28 10:04:16 +00002750def: InstRW<[HWWriteResGroup52], (instregex "VCMPPDrmi")>;
Gadi Haberd76f7b82017-08-28 10:04:16 +00002751def: InstRW<[HWWriteResGroup52], (instregex "VCMPPSrmi")>;
Gadi Haberd76f7b82017-08-28 10:04:16 +00002752def: InstRW<[HWWriteResGroup52], (instregex "VCVTDQ2PSrm")>;
Gadi Haberd76f7b82017-08-28 10:04:16 +00002753def: InstRW<[HWWriteResGroup52], (instregex "VCVTPS2DQrm")>;
Gadi Haberd76f7b82017-08-28 10:04:16 +00002754def: InstRW<[HWWriteResGroup52], (instregex "VCVTTPS2DQrm")>;
Craig Topper5ffe8012017-12-10 01:24:05 +00002755def: InstRW<[HWWriteResGroup52], (instregex "VMAX(C?)PDrm")>;
2756def: InstRW<[HWWriteResGroup52], (instregex "VMAX(C?)PSrm")>;
2757def: InstRW<[HWWriteResGroup52], (instregex "VMIN(C?)PDrm")>;
2758def: InstRW<[HWWriteResGroup52], (instregex "VMIN(C?)PSrm")>;
Gadi Haberd76f7b82017-08-28 10:04:16 +00002759def: InstRW<[HWWriteResGroup52], (instregex "VSUBPDrm")>;
Gadi Haberd76f7b82017-08-28 10:04:16 +00002760def: InstRW<[HWWriteResGroup52], (instregex "VSUBPSrm")>;
Gadi Haberd76f7b82017-08-28 10:04:16 +00002761
Gadi Haber2cf601f2017-12-08 09:48:44 +00002762def HWWriteResGroup52_1 : SchedWriteRes<[HWPort1,HWPort23]> {
2763 let Latency = 10;
2764 let NumMicroOps = 2;
2765 let ResourceCycles = [1,1];
Gadi Haberd76f7b82017-08-28 10:04:16 +00002766}
Gadi Haber2cf601f2017-12-08 09:48:44 +00002767def: InstRW<[HWWriteResGroup52_1], (instregex "ADD_F32m")>;
2768def: InstRW<[HWWriteResGroup52_1], (instregex "ADD_F64m")>;
2769def: InstRW<[HWWriteResGroup52_1], (instregex "ILD_F16m")>;
2770def: InstRW<[HWWriteResGroup52_1], (instregex "ILD_F32m")>;
2771def: InstRW<[HWWriteResGroup52_1], (instregex "ILD_F64m")>;
2772def: InstRW<[HWWriteResGroup52_1], (instregex "SUBR_F32m")>;
2773def: InstRW<[HWWriteResGroup52_1], (instregex "SUBR_F64m")>;
2774def: InstRW<[HWWriteResGroup52_1], (instregex "SUB_F32m")>;
2775def: InstRW<[HWWriteResGroup52_1], (instregex "SUB_F64m")>;
2776def: InstRW<[HWWriteResGroup52_1], (instregex "VADDPDYrm")>;
2777def: InstRW<[HWWriteResGroup52_1], (instregex "VADDPSYrm")>;
2778def: InstRW<[HWWriteResGroup52_1], (instregex "VADDSUBPDYrm")>;
2779def: InstRW<[HWWriteResGroup52_1], (instregex "VADDSUBPSYrm")>;
2780def: InstRW<[HWWriteResGroup52_1], (instregex "VCMPPDYrmi")>;
2781def: InstRW<[HWWriteResGroup52_1], (instregex "VCMPPSYrmi")>;
2782def: InstRW<[HWWriteResGroup52_1], (instregex "VCVTDQ2PSYrm")>;
2783def: InstRW<[HWWriteResGroup52_1], (instregex "VCVTPS2DQYrm")>;
2784def: InstRW<[HWWriteResGroup52_1], (instregex "VCVTTPS2DQYrm")>;
Craig Topper5ffe8012017-12-10 01:24:05 +00002785def: InstRW<[HWWriteResGroup52_1], (instregex "VMAX(C?)PDYrm")>;
2786def: InstRW<[HWWriteResGroup52_1], (instregex "VMAX(C?)PSYrm")>;
2787def: InstRW<[HWWriteResGroup52_1], (instregex "VMIN(C?)PDYrm")>;
2788def: InstRW<[HWWriteResGroup52_1], (instregex "VMIN(C?)PSYrm")>;
Gadi Haber2cf601f2017-12-08 09:48:44 +00002789def: InstRW<[HWWriteResGroup52_1], (instregex "VSUBPDYrm")>;
2790def: InstRW<[HWWriteResGroup52_1], (instregex "VSUBPSYrm")>;
Gadi Haberd76f7b82017-08-28 10:04:16 +00002791
2792def HWWriteResGroup53 : SchedWriteRes<[HWPort5,HWPort23]> {
Gadi Haber2cf601f2017-12-08 09:48:44 +00002793 let Latency = 10;
Gadi Haberd76f7b82017-08-28 10:04:16 +00002794 let NumMicroOps = 2;
2795 let ResourceCycles = [1,1];
2796}
2797def: InstRW<[HWWriteResGroup53], (instregex "VPERM2F128rm")>;
2798def: InstRW<[HWWriteResGroup53], (instregex "VPERM2I128rm")>;
2799def: InstRW<[HWWriteResGroup53], (instregex "VPERMDYrm")>;
2800def: InstRW<[HWWriteResGroup53], (instregex "VPERMPDYmi")>;
2801def: InstRW<[HWWriteResGroup53], (instregex "VPERMPSYrm")>;
2802def: InstRW<[HWWriteResGroup53], (instregex "VPERMQYmi")>;
Gadi Haberd76f7b82017-08-28 10:04:16 +00002803def: InstRW<[HWWriteResGroup53], (instregex "VPMOVZXBDYrm")>;
2804def: InstRW<[HWWriteResGroup53], (instregex "VPMOVZXBQYrm")>;
2805def: InstRW<[HWWriteResGroup53], (instregex "VPMOVZXBWYrm")>;
2806def: InstRW<[HWWriteResGroup53], (instregex "VPMOVZXDQYrm")>;
Gadi Haberd76f7b82017-08-28 10:04:16 +00002807def: InstRW<[HWWriteResGroup53], (instregex "VPMOVZXWQYrm")>;
2808
Gadi Haber2cf601f2017-12-08 09:48:44 +00002809def HWWriteResGroup53_1 : SchedWriteRes<[HWPort5,HWPort23]> {
2810 let Latency = 9;
2811 let NumMicroOps = 2;
2812 let ResourceCycles = [1,1];
2813}
2814def: InstRW<[HWWriteResGroup53_1], (instregex "VPMOVSXBWYrm")>;
2815def: InstRW<[HWWriteResGroup53_1], (instregex "VPMOVSXDQYrm")>;
2816def: InstRW<[HWWriteResGroup53_1], (instregex "VPMOVSXWDYrm")>;
2817def: InstRW<[HWWriteResGroup53_1], (instregex "VPMOVZXWDYrm")>;
2818
Gadi Haberd76f7b82017-08-28 10:04:16 +00002819def HWWriteResGroup54 : SchedWriteRes<[HWPort0156]> {
2820 let Latency = 3;
2821 let NumMicroOps = 3;
2822 let ResourceCycles = [3];
2823}
2824def: InstRW<[HWWriteResGroup54], (instregex "XADD(16|32|64)rr")>;
2825def: InstRW<[HWWriteResGroup54], (instregex "XADD8rr")>;
2826def: InstRW<[HWWriteResGroup54], (instregex "XCHG8rr")>;
2827
2828def HWWriteResGroup55 : SchedWriteRes<[HWPort0,HWPort5]> {
2829 let Latency = 3;
2830 let NumMicroOps = 3;
2831 let ResourceCycles = [2,1];
2832}
2833def: InstRW<[HWWriteResGroup55], (instregex "VPSLLVDYrr")>;
2834def: InstRW<[HWWriteResGroup55], (instregex "VPSLLVDrr")>;
2835def: InstRW<[HWWriteResGroup55], (instregex "VPSRAVDYrr")>;
2836def: InstRW<[HWWriteResGroup55], (instregex "VPSRAVDrr")>;
2837def: InstRW<[HWWriteResGroup55], (instregex "VPSRLVDYrr")>;
2838def: InstRW<[HWWriteResGroup55], (instregex "VPSRLVDrr")>;
2839
2840def HWWriteResGroup56 : SchedWriteRes<[HWPort5,HWPort15]> {
2841 let Latency = 3;
2842 let NumMicroOps = 3;
2843 let ResourceCycles = [2,1];
2844}
2845def: InstRW<[HWWriteResGroup56], (instregex "MMX_PHADDSWrr64")>;
2846def: InstRW<[HWWriteResGroup56], (instregex "MMX_PHADDWrr64")>;
2847def: InstRW<[HWWriteResGroup56], (instregex "MMX_PHADDrr64")>;
2848def: InstRW<[HWWriteResGroup56], (instregex "MMX_PHSUBDrr64")>;
2849def: InstRW<[HWWriteResGroup56], (instregex "MMX_PHSUBSWrr64")>;
2850def: InstRW<[HWWriteResGroup56], (instregex "MMX_PHSUBWrr64")>;
2851def: InstRW<[HWWriteResGroup56], (instregex "PHADDDrr")>;
2852def: InstRW<[HWWriteResGroup56], (instregex "PHADDSWrr128")>;
2853def: InstRW<[HWWriteResGroup56], (instregex "PHADDWrr")>;
2854def: InstRW<[HWWriteResGroup56], (instregex "PHSUBDrr")>;
2855def: InstRW<[HWWriteResGroup56], (instregex "PHSUBSWrr128")>;
2856def: InstRW<[HWWriteResGroup56], (instregex "PHSUBWrr")>;
2857def: InstRW<[HWWriteResGroup56], (instregex "VPHADDDYrr")>;
2858def: InstRW<[HWWriteResGroup56], (instregex "VPHADDDrr")>;
2859def: InstRW<[HWWriteResGroup56], (instregex "VPHADDSWrr128")>;
2860def: InstRW<[HWWriteResGroup56], (instregex "VPHADDSWrr256")>;
2861def: InstRW<[HWWriteResGroup56], (instregex "VPHADDWYrr")>;
2862def: InstRW<[HWWriteResGroup56], (instregex "VPHADDWrr")>;
2863def: InstRW<[HWWriteResGroup56], (instregex "VPHSUBDYrr")>;
2864def: InstRW<[HWWriteResGroup56], (instregex "VPHSUBDrr")>;
2865def: InstRW<[HWWriteResGroup56], (instregex "VPHSUBSWrr128")>;
2866def: InstRW<[HWWriteResGroup56], (instregex "VPHSUBSWrr256")>;
2867def: InstRW<[HWWriteResGroup56], (instregex "VPHSUBWYrr")>;
2868def: InstRW<[HWWriteResGroup56], (instregex "VPHSUBWrr")>;
2869
2870def HWWriteResGroup57 : SchedWriteRes<[HWPort5,HWPort0156]> {
2871 let Latency = 3;
2872 let NumMicroOps = 3;
2873 let ResourceCycles = [2,1];
2874}
2875def: InstRW<[HWWriteResGroup57], (instregex "MMX_PACKSSDWirr")>;
2876def: InstRW<[HWWriteResGroup57], (instregex "MMX_PACKSSWBirr")>;
2877def: InstRW<[HWWriteResGroup57], (instregex "MMX_PACKUSWBirr")>;
2878
2879def HWWriteResGroup58 : SchedWriteRes<[HWPort6,HWPort0156]> {
2880 let Latency = 3;
2881 let NumMicroOps = 3;
2882 let ResourceCycles = [1,2];
2883}
2884def: InstRW<[HWWriteResGroup58], (instregex "CLD")>;
2885
2886def HWWriteResGroup59 : SchedWriteRes<[HWPort06,HWPort0156]> {
2887 let Latency = 3;
2888 let NumMicroOps = 3;
2889 let ResourceCycles = [1,2];
2890}
2891def: InstRW<[HWWriteResGroup59], (instregex "CMOVA(16|32|64)rr")>;
2892def: InstRW<[HWWriteResGroup59], (instregex "CMOVBE(16|32|64)rr")>;
2893def: InstRW<[HWWriteResGroup59], (instregex "RCL(16|32|64)r1")>;
2894def: InstRW<[HWWriteResGroup59], (instregex "RCL(16|32|64)ri")>;
2895def: InstRW<[HWWriteResGroup59], (instregex "RCL8r1")>;
2896def: InstRW<[HWWriteResGroup59], (instregex "RCL8ri")>;
2897def: InstRW<[HWWriteResGroup59], (instregex "RCR(16|32|64)r1")>;
2898def: InstRW<[HWWriteResGroup59], (instregex "RCR(16|32|64)ri")>;
2899def: InstRW<[HWWriteResGroup59], (instregex "RCR8r1")>;
2900def: InstRW<[HWWriteResGroup59], (instregex "RCR8ri")>;
2901
2902def HWWriteResGroup60 : SchedWriteRes<[HWPort06,HWPort0156]> {
2903 let Latency = 3;
2904 let NumMicroOps = 3;
2905 let ResourceCycles = [2,1];
2906}
2907def: InstRW<[HWWriteResGroup60], (instregex "ROL(16|32|64)rCL")>;
2908def: InstRW<[HWWriteResGroup60], (instregex "ROL8rCL")>;
2909def: InstRW<[HWWriteResGroup60], (instregex "ROR(16|32|64)rCL")>;
2910def: InstRW<[HWWriteResGroup60], (instregex "ROR8rCL")>;
2911def: InstRW<[HWWriteResGroup60], (instregex "SAR(16|32|64)rCL")>;
2912def: InstRW<[HWWriteResGroup60], (instregex "SAR8rCL")>;
2913def: InstRW<[HWWriteResGroup60], (instregex "SHL(16|32|64)rCL")>;
2914def: InstRW<[HWWriteResGroup60], (instregex "SHL8rCL")>;
2915def: InstRW<[HWWriteResGroup60], (instregex "SHR(16|32|64)rCL")>;
2916def: InstRW<[HWWriteResGroup60], (instregex "SHR8rCL")>;
2917
2918def HWWriteResGroup61 : SchedWriteRes<[HWPort0,HWPort4,HWPort237]> {
Gadi Haber2cf601f2017-12-08 09:48:44 +00002919 let Latency = 4;
Gadi Haberd76f7b82017-08-28 10:04:16 +00002920 let NumMicroOps = 3;
2921 let ResourceCycles = [1,1,1];
2922}
2923def: InstRW<[HWWriteResGroup61], (instregex "FNSTSWm")>;
2924
2925def HWWriteResGroup62 : SchedWriteRes<[HWPort1,HWPort4,HWPort237]> {
Gadi Haber2cf601f2017-12-08 09:48:44 +00002926 let Latency = 4;
Gadi Haberd76f7b82017-08-28 10:04:16 +00002927 let NumMicroOps = 3;
2928 let ResourceCycles = [1,1,1];
2929}
2930def: InstRW<[HWWriteResGroup62], (instregex "ISTT_FP16m")>;
2931def: InstRW<[HWWriteResGroup62], (instregex "ISTT_FP32m")>;
2932def: InstRW<[HWWriteResGroup62], (instregex "ISTT_FP64m")>;
2933def: InstRW<[HWWriteResGroup62], (instregex "IST_F16m")>;
2934def: InstRW<[HWWriteResGroup62], (instregex "IST_F32m")>;
2935def: InstRW<[HWWriteResGroup62], (instregex "IST_FP16m")>;
2936def: InstRW<[HWWriteResGroup62], (instregex "IST_FP32m")>;
2937def: InstRW<[HWWriteResGroup62], (instregex "IST_FP64m")>;
2938
2939def HWWriteResGroup63 : SchedWriteRes<[HWPort0,HWPort5,HWPort23]> {
Gadi Haber2cf601f2017-12-08 09:48:44 +00002940 let Latency = 10;
Gadi Haberd76f7b82017-08-28 10:04:16 +00002941 let NumMicroOps = 4;
2942 let ResourceCycles = [2,1,1];
2943}
2944def: InstRW<[HWWriteResGroup63], (instregex "VPSLLVDYrm")>;
Gadi Haberd76f7b82017-08-28 10:04:16 +00002945def: InstRW<[HWWriteResGroup63], (instregex "VPSRAVDYrm")>;
Gadi Haberd76f7b82017-08-28 10:04:16 +00002946def: InstRW<[HWWriteResGroup63], (instregex "VPSRLVDYrm")>;
Gadi Haber2cf601f2017-12-08 09:48:44 +00002947
2948def HWWriteResGroup63_1 : SchedWriteRes<[HWPort0,HWPort5,HWPort23]> {
2949 let Latency = 9;
2950 let NumMicroOps = 4;
2951 let ResourceCycles = [2,1,1];
2952}
2953def: InstRW<[HWWriteResGroup63_1], (instregex "VPSLLVDrm")>;
2954def: InstRW<[HWWriteResGroup63_1], (instregex "VPSRAVDrm")>;
2955def: InstRW<[HWWriteResGroup63_1], (instregex "VPSRLVDrm")>;
Gadi Haberd76f7b82017-08-28 10:04:16 +00002956
2957def HWWriteResGroup64 : SchedWriteRes<[HWPort5,HWPort23,HWPort15]> {
Gadi Haber2cf601f2017-12-08 09:48:44 +00002958 let Latency = 8;
Gadi Haberd76f7b82017-08-28 10:04:16 +00002959 let NumMicroOps = 4;
2960 let ResourceCycles = [2,1,1];
2961}
2962def: InstRW<[HWWriteResGroup64], (instregex "MMX_PHADDSWrm64")>;
2963def: InstRW<[HWWriteResGroup64], (instregex "MMX_PHADDWrm64")>;
2964def: InstRW<[HWWriteResGroup64], (instregex "MMX_PHADDrm64")>;
2965def: InstRW<[HWWriteResGroup64], (instregex "MMX_PHSUBDrm64")>;
2966def: InstRW<[HWWriteResGroup64], (instregex "MMX_PHSUBSWrm64")>;
2967def: InstRW<[HWWriteResGroup64], (instregex "MMX_PHSUBWrm64")>;
Gadi Haber2cf601f2017-12-08 09:48:44 +00002968
2969def HWWriteResGroup64_1 : SchedWriteRes<[HWPort5,HWPort23,HWPort15]> {
2970 let Latency = 10;
2971 let NumMicroOps = 4;
2972 let ResourceCycles = [2,1,1];
2973}
2974def: InstRW<[HWWriteResGroup64_1], (instregex "VPHADDDYrm")>;
2975def: InstRW<[HWWriteResGroup64_1], (instregex "VPHADDSWrm256")>;
2976def: InstRW<[HWWriteResGroup64_1], (instregex "VPHADDWYrm")>;
2977def: InstRW<[HWWriteResGroup64_1], (instregex "VPHSUBDYrm")>;
2978def: InstRW<[HWWriteResGroup64_1], (instregex "VPHSUBSWrm256")>;
2979def: InstRW<[HWWriteResGroup64_1], (instregex "VPHSUBWYrm")>;
2980
2981def HWWriteResGroup64_2 : SchedWriteRes<[HWPort5,HWPort23,HWPort15]> {
2982 let Latency = 9;
2983 let NumMicroOps = 4;
2984 let ResourceCycles = [2,1,1];
2985}
2986def: InstRW<[HWWriteResGroup64_2], (instregex "PHADDDrm")>;
2987def: InstRW<[HWWriteResGroup64_2], (instregex "PHADDSWrm128")>;
2988def: InstRW<[HWWriteResGroup64_2], (instregex "PHADDWrm")>;
2989def: InstRW<[HWWriteResGroup64_2], (instregex "PHSUBDrm")>;
2990def: InstRW<[HWWriteResGroup64_2], (instregex "PHSUBSWrm128")>;
2991def: InstRW<[HWWriteResGroup64_2], (instregex "PHSUBWrm")>;
2992def: InstRW<[HWWriteResGroup64_2], (instregex "VPHADDDrm")>;
2993def: InstRW<[HWWriteResGroup64_2], (instregex "VPHADDSWrm128")>;
2994def: InstRW<[HWWriteResGroup64_2], (instregex "VPHADDWrm")>;
2995def: InstRW<[HWWriteResGroup64_2], (instregex "VPHSUBDrm")>;
2996def: InstRW<[HWWriteResGroup64_2], (instregex "VPHSUBSWrm128")>;
2997def: InstRW<[HWWriteResGroup64_2], (instregex "VPHSUBWrm")>;
Gadi Haberd76f7b82017-08-28 10:04:16 +00002998
2999def HWWriteResGroup65 : SchedWriteRes<[HWPort23,HWPort06,HWPort0156]> {
Gadi Haber2cf601f2017-12-08 09:48:44 +00003000 let Latency = 8;
Gadi Haberd76f7b82017-08-28 10:04:16 +00003001 let NumMicroOps = 4;
3002 let ResourceCycles = [1,1,2];
3003}
3004def: InstRW<[HWWriteResGroup65], (instregex "CMOVA(16|32|64)rm")>;
3005def: InstRW<[HWWriteResGroup65], (instregex "CMOVBE(16|32|64)rm")>;
3006
3007def HWWriteResGroup66 : SchedWriteRes<[HWPort23,HWPort237,HWPort06,HWPort0156]> {
Gadi Haber2cf601f2017-12-08 09:48:44 +00003008 let Latency = 9;
Gadi Haberd76f7b82017-08-28 10:04:16 +00003009 let NumMicroOps = 5;
3010 let ResourceCycles = [1,1,1,2];
3011}
3012def: InstRW<[HWWriteResGroup66], (instregex "RCL(16|32|64)m1")>;
3013def: InstRW<[HWWriteResGroup66], (instregex "RCL(16|32|64)mi")>;
3014def: InstRW<[HWWriteResGroup66], (instregex "RCL8m1")>;
3015def: InstRW<[HWWriteResGroup66], (instregex "RCL8mi")>;
3016def: InstRW<[HWWriteResGroup66], (instregex "RCR(16|32|64)m1")>;
3017def: InstRW<[HWWriteResGroup66], (instregex "RCR(16|32|64)mi")>;
3018def: InstRW<[HWWriteResGroup66], (instregex "RCR8m1")>;
3019def: InstRW<[HWWriteResGroup66], (instregex "RCR8mi")>;
3020
3021def HWWriteResGroup67 : SchedWriteRes<[HWPort23,HWPort237,HWPort06,HWPort0156]> {
Gadi Haber2cf601f2017-12-08 09:48:44 +00003022 let Latency = 9;
Gadi Haberd76f7b82017-08-28 10:04:16 +00003023 let NumMicroOps = 5;
3024 let ResourceCycles = [1,1,2,1];
3025}
3026def: InstRW<[HWWriteResGroup67], (instregex "ROR(16|32|64)mCL")>;
3027def: InstRW<[HWWriteResGroup67], (instregex "ROR8mCL")>;
3028
3029def HWWriteResGroup68 : SchedWriteRes<[HWPort4,HWPort23,HWPort237,HWPort0156]> {
Gadi Haber2cf601f2017-12-08 09:48:44 +00003030 let Latency = 9;
Michael Zuckermanf6684002017-06-28 11:23:31 +00003031 let NumMicroOps = 6;
Gadi Haberd76f7b82017-08-28 10:04:16 +00003032 let ResourceCycles = [1,1,1,3];
Michael Zuckermanf6684002017-06-28 11:23:31 +00003033}
Gadi Haberd76f7b82017-08-28 10:04:16 +00003034def: InstRW<[HWWriteResGroup68], (instregex "ADC(16|32|64)mi8")>;
3035def: InstRW<[HWWriteResGroup68], (instregex "ADC8mi")>;
3036def: InstRW<[HWWriteResGroup68], (instregex "ADD8mi")>;
3037def: InstRW<[HWWriteResGroup68], (instregex "AND8mi")>;
3038def: InstRW<[HWWriteResGroup68], (instregex "OR8mi")>;
3039def: InstRW<[HWWriteResGroup68], (instregex "SUB8mi")>;
3040def: InstRW<[HWWriteResGroup68], (instregex "XCHG(16|32|64)rm")>;
3041def: InstRW<[HWWriteResGroup68], (instregex "XCHG8rm")>;
3042def: InstRW<[HWWriteResGroup68], (instregex "XOR8mi")>;
Michael Zuckermanf6684002017-06-28 11:23:31 +00003043
Gadi Haberd76f7b82017-08-28 10:04:16 +00003044def HWWriteResGroup69 : SchedWriteRes<[HWPort4,HWPort23,HWPort237,HWPort06,HWPort0156]> {
Gadi Haber2cf601f2017-12-08 09:48:44 +00003045 let Latency = 9;
Gadi Haberd76f7b82017-08-28 10:04:16 +00003046 let NumMicroOps = 6;
3047 let ResourceCycles = [1,1,1,2,1];
Michael Zuckermanf6684002017-06-28 11:23:31 +00003048}
Gadi Haberd76f7b82017-08-28 10:04:16 +00003049def: InstRW<[HWWriteResGroup69], (instregex "ADC(16|32|64)mr")>;
3050def: InstRW<[HWWriteResGroup69], (instregex "ADC8mr")>;
3051def: InstRW<[HWWriteResGroup69], (instregex "CMPXCHG(16|32|64)rm")>;
3052def: InstRW<[HWWriteResGroup69], (instregex "CMPXCHG8rm")>;
3053def: InstRW<[HWWriteResGroup69], (instregex "ROL(16|32|64)mCL")>;
3054def: InstRW<[HWWriteResGroup69], (instregex "ROL8mCL")>;
3055def: InstRW<[HWWriteResGroup69], (instregex "SAR(16|32|64)mCL")>;
3056def: InstRW<[HWWriteResGroup69], (instregex "SAR8mCL")>;
3057def: InstRW<[HWWriteResGroup69], (instregex "SBB(16|32|64)mi8")>;
3058def: InstRW<[HWWriteResGroup69], (instregex "SBB(16|32|64)mr")>;
3059def: InstRW<[HWWriteResGroup69], (instregex "SBB8mi")>;
3060def: InstRW<[HWWriteResGroup69], (instregex "SBB8mr")>;
3061def: InstRW<[HWWriteResGroup69], (instregex "SHL(16|32|64)mCL")>;
3062def: InstRW<[HWWriteResGroup69], (instregex "SHL8mCL")>;
3063def: InstRW<[HWWriteResGroup69], (instregex "SHR(16|32|64)mCL")>;
3064def: InstRW<[HWWriteResGroup69], (instregex "SHR8mCL")>;
Michael Zuckermanf6684002017-06-28 11:23:31 +00003065
Gadi Haberd76f7b82017-08-28 10:04:16 +00003066def HWWriteResGroup70 : SchedWriteRes<[HWPort0,HWPort1]> {
3067 let Latency = 4;
3068 let NumMicroOps = 2;
3069 let ResourceCycles = [1,1];
3070}
3071def: InstRW<[HWWriteResGroup70], (instregex "CVTSD2SI64rr")>;
3072def: InstRW<[HWWriteResGroup70], (instregex "CVTSD2SIrr")>;
3073def: InstRW<[HWWriteResGroup70], (instregex "CVTSS2SI64rr")>;
3074def: InstRW<[HWWriteResGroup70], (instregex "CVTSS2SIrr")>;
3075def: InstRW<[HWWriteResGroup70], (instregex "CVTTSD2SI64rr")>;
3076def: InstRW<[HWWriteResGroup70], (instregex "CVTTSD2SIrr")>;
3077def: InstRW<[HWWriteResGroup70], (instregex "CVTTSS2SI64rr")>;
3078def: InstRW<[HWWriteResGroup70], (instregex "CVTTSS2SIrr")>;
3079def: InstRW<[HWWriteResGroup70], (instregex "VCVTSD2SI64rr")>;
3080def: InstRW<[HWWriteResGroup70], (instregex "VCVTSD2SIrr")>;
3081def: InstRW<[HWWriteResGroup70], (instregex "VCVTSS2SI64rr")>;
3082def: InstRW<[HWWriteResGroup70], (instregex "VCVTSS2SIrr")>;
3083def: InstRW<[HWWriteResGroup70], (instregex "VCVTTSD2SI64rr")>;
3084def: InstRW<[HWWriteResGroup70], (instregex "VCVTTSD2SIrr")>;
3085def: InstRW<[HWWriteResGroup70], (instregex "VCVTTSS2SI64rr")>;
3086def: InstRW<[HWWriteResGroup70], (instregex "VCVTTSS2SIrr")>;
3087
3088def HWWriteResGroup71 : SchedWriteRes<[HWPort0,HWPort5]> {
3089 let Latency = 4;
3090 let NumMicroOps = 2;
3091 let ResourceCycles = [1,1];
3092}
3093def: InstRW<[HWWriteResGroup71], (instregex "VCVTPS2PDYrr")>;
3094def: InstRW<[HWWriteResGroup71], (instregex "VPSLLDYrr")>;
3095def: InstRW<[HWWriteResGroup71], (instregex "VPSLLQYrr")>;
3096def: InstRW<[HWWriteResGroup71], (instregex "VPSLLWYrr")>;
3097def: InstRW<[HWWriteResGroup71], (instregex "VPSRADYrr")>;
3098def: InstRW<[HWWriteResGroup71], (instregex "VPSRAWYrr")>;
3099def: InstRW<[HWWriteResGroup71], (instregex "VPSRLDYrr")>;
3100def: InstRW<[HWWriteResGroup71], (instregex "VPSRLQYrr")>;
3101def: InstRW<[HWWriteResGroup71], (instregex "VPSRLWYrr")>;
3102def: InstRW<[HWWriteResGroup71], (instregex "VPTESTYrr")>;
3103
3104def HWWriteResGroup72 : SchedWriteRes<[HWPort0,HWPort0156]> {
3105 let Latency = 4;
3106 let NumMicroOps = 2;
3107 let ResourceCycles = [1,1];
3108}
3109def: InstRW<[HWWriteResGroup72], (instregex "FNSTSW16r")>;
3110
3111def HWWriteResGroup73 : SchedWriteRes<[HWPort1,HWPort5]> {
3112 let Latency = 4;
3113 let NumMicroOps = 2;
3114 let ResourceCycles = [1,1];
3115}
3116def: InstRW<[HWWriteResGroup73], (instregex "CVTDQ2PDrr")>;
3117def: InstRW<[HWWriteResGroup73], (instregex "CVTPD2DQrr")>;
3118def: InstRW<[HWWriteResGroup73], (instregex "CVTPD2PSrr")>;
3119def: InstRW<[HWWriteResGroup73], (instregex "CVTSD2SSrr")>;
3120def: InstRW<[HWWriteResGroup73], (instregex "CVTSI2SD64rr")>;
3121def: InstRW<[HWWriteResGroup73], (instregex "CVTSI2SDrr")>;
3122def: InstRW<[HWWriteResGroup73], (instregex "CVTSI2SSrr")>;
3123def: InstRW<[HWWriteResGroup73], (instregex "CVTTPD2DQrr")>;
3124def: InstRW<[HWWriteResGroup73], (instregex "MMX_CVTPD2PIirr")>;
3125def: InstRW<[HWWriteResGroup73], (instregex "MMX_CVTPI2PDirr")>;
3126def: InstRW<[HWWriteResGroup73], (instregex "MMX_CVTPS2PIirr")>;
3127def: InstRW<[HWWriteResGroup73], (instregex "MMX_CVTTPD2PIirr")>;
3128def: InstRW<[HWWriteResGroup73], (instregex "MMX_CVTTPS2PIirr")>;
3129def: InstRW<[HWWriteResGroup73], (instregex "VCVTDQ2PDrr")>;
3130def: InstRW<[HWWriteResGroup73], (instregex "VCVTPD2DQrr")>;
3131def: InstRW<[HWWriteResGroup73], (instregex "VCVTPD2PSrr")>;
3132def: InstRW<[HWWriteResGroup73], (instregex "VCVTPS2PHrr")>;
3133def: InstRW<[HWWriteResGroup73], (instregex "VCVTSD2SSrr")>;
3134def: InstRW<[HWWriteResGroup73], (instregex "VCVTSI2SD64rr")>;
3135def: InstRW<[HWWriteResGroup73], (instregex "VCVTSI2SDrr")>;
3136def: InstRW<[HWWriteResGroup73], (instregex "VCVTSI2SSrr")>;
3137def: InstRW<[HWWriteResGroup73], (instregex "VCVTTPD2DQrr")>;
3138
3139def HWWriteResGroup74 : SchedWriteRes<[HWPort1,HWPort6]> {
3140 let Latency = 4;
3141 let NumMicroOps = 2;
3142 let ResourceCycles = [1,1];
3143}
3144def: InstRW<[HWWriteResGroup74], (instregex "IMUL64r")>;
3145def: InstRW<[HWWriteResGroup74], (instregex "MUL64r")>;
3146def: InstRW<[HWWriteResGroup74], (instregex "MULX64rr")>;
3147
3148def HWWriteResGroup74_16 : SchedWriteRes<[HWPort1, HWPort0156]> {
3149 let Latency = 4;
Michael Zuckermanf6684002017-06-28 11:23:31 +00003150 let NumMicroOps = 4;
Michael Zuckermanf6684002017-06-28 11:23:31 +00003151}
Gadi Haberd76f7b82017-08-28 10:04:16 +00003152def: InstRW<[HWWriteResGroup74_16], (instregex "IMUL16r")>;
3153def: InstRW<[HWWriteResGroup74_16], (instregex "MUL16r")>;
Michael Zuckermanf6684002017-06-28 11:23:31 +00003154
Gadi Haberd76f7b82017-08-28 10:04:16 +00003155def HWWriteResGroup74_32 : SchedWriteRes<[HWPort1,HWPort0156]> {
3156 let Latency = 4;
3157 let NumMicroOps = 3;
3158}
3159def: InstRW<[HWWriteResGroup74_32], (instregex "IMUL32r")>;
3160def: InstRW<[HWWriteResGroup74_32], (instregex "MUL32r")>;
3161
3162def HWWriteResGroup75 : SchedWriteRes<[HWPort1,HWPort23]> {
Gadi Haber2cf601f2017-12-08 09:48:44 +00003163 let Latency = 11;
Gadi Haberd76f7b82017-08-28 10:04:16 +00003164 let NumMicroOps = 3;
3165 let ResourceCycles = [2,1];
3166}
3167def: InstRW<[HWWriteResGroup75], (instregex "FICOM16m")>;
3168def: InstRW<[HWWriteResGroup75], (instregex "FICOM32m")>;
3169def: InstRW<[HWWriteResGroup75], (instregex "FICOMP16m")>;
3170def: InstRW<[HWWriteResGroup75], (instregex "FICOMP32m")>;
3171
3172def HWWriteResGroup76 : SchedWriteRes<[HWPort0,HWPort1,HWPort23]> {
Gadi Haber2cf601f2017-12-08 09:48:44 +00003173 let Latency = 9;
Gadi Haberd76f7b82017-08-28 10:04:16 +00003174 let NumMicroOps = 3;
3175 let ResourceCycles = [1,1,1];
3176}
3177def: InstRW<[HWWriteResGroup76], (instregex "CVTSD2SI64rm")>;
3178def: InstRW<[HWWriteResGroup76], (instregex "CVTSD2SIrm")>;
3179def: InstRW<[HWWriteResGroup76], (instregex "CVTSS2SI64rm")>;
3180def: InstRW<[HWWriteResGroup76], (instregex "CVTSS2SIrm")>;
3181def: InstRW<[HWWriteResGroup76], (instregex "CVTTSD2SI64rm")>;
3182def: InstRW<[HWWriteResGroup76], (instregex "CVTTSD2SIrm")>;
3183def: InstRW<[HWWriteResGroup76], (instregex "CVTTSS2SIrm")>;
3184def: InstRW<[HWWriteResGroup76], (instregex "VCVTSD2SI64rm")>;
3185def: InstRW<[HWWriteResGroup76], (instregex "VCVTSD2SIrm")>;
3186def: InstRW<[HWWriteResGroup76], (instregex "VCVTSS2SI64rm")>;
3187def: InstRW<[HWWriteResGroup76], (instregex "VCVTSS2SIrm")>;
3188def: InstRW<[HWWriteResGroup76], (instregex "VCVTTSD2SI64rm")>;
3189def: InstRW<[HWWriteResGroup76], (instregex "VCVTTSD2SIrm")>;
3190def: InstRW<[HWWriteResGroup76], (instregex "VCVTTSS2SI64rm")>;
3191def: InstRW<[HWWriteResGroup76], (instregex "VCVTTSS2SIrm")>;
3192
3193def HWWriteResGroup77 : SchedWriteRes<[HWPort0,HWPort5,HWPort23]> {
Gadi Haber2cf601f2017-12-08 09:48:44 +00003194 let Latency = 10;
Gadi Haberd76f7b82017-08-28 10:04:16 +00003195 let NumMicroOps = 3;
3196 let ResourceCycles = [1,1,1];
3197}
3198def: InstRW<[HWWriteResGroup77], (instregex "VCVTPS2PDYrm")>;
Gadi Haber2cf601f2017-12-08 09:48:44 +00003199
3200def HWWriteResGroup77_1 : SchedWriteRes<[HWPort0,HWPort5,HWPort23]> {
3201 let Latency = 11;
3202 let NumMicroOps = 3;
3203 let ResourceCycles = [1,1,1];
3204}
3205def: InstRW<[HWWriteResGroup77_1], (instregex "VPTESTYrm")>;
Gadi Haberd76f7b82017-08-28 10:04:16 +00003206
3207def HWWriteResGroup78 : SchedWriteRes<[HWPort1,HWPort5,HWPort23]> {
Gadi Haber2cf601f2017-12-08 09:48:44 +00003208 let Latency = 10;
Gadi Haberd76f7b82017-08-28 10:04:16 +00003209 let NumMicroOps = 3;
3210 let ResourceCycles = [1,1,1];
3211}
3212def: InstRW<[HWWriteResGroup78], (instregex "CVTDQ2PDrm")>;
3213def: InstRW<[HWWriteResGroup78], (instregex "CVTPD2DQrm")>;
3214def: InstRW<[HWWriteResGroup78], (instregex "CVTPD2PSrm")>;
Gadi Haberd76f7b82017-08-28 10:04:16 +00003215def: InstRW<[HWWriteResGroup78], (instregex "CVTTPD2DQrm")>;
3216def: InstRW<[HWWriteResGroup78], (instregex "MMX_CVTPD2PIirm")>;
Gadi Haberd76f7b82017-08-28 10:04:16 +00003217def: InstRW<[HWWriteResGroup78], (instregex "MMX_CVTTPD2PIirm")>;
3218def: InstRW<[HWWriteResGroup78], (instregex "VCVTDQ2PDrm")>;
Gadi Haber2cf601f2017-12-08 09:48:44 +00003219
3220def HWWriteResGroup78_1 : SchedWriteRes<[HWPort1,HWPort5,HWPort23]> {
3221 let Latency = 9;
3222 let NumMicroOps = 3;
3223 let ResourceCycles = [1,1,1];
3224}
3225def: InstRW<[HWWriteResGroup78_1], (instregex "CVTSD2SSrm")>;
3226def: InstRW<[HWWriteResGroup78_1], (instregex "MMX_CVTPI2PDirm")>;
3227def: InstRW<[HWWriteResGroup78_1], (instregex "VCVTSD2SSrm")>;
Gadi Haberd76f7b82017-08-28 10:04:16 +00003228
3229def HWWriteResGroup79 : SchedWriteRes<[HWPort1,HWPort6,HWPort23]> {
Gadi Haber2cf601f2017-12-08 09:48:44 +00003230 let Latency = 9;
Gadi Haberd76f7b82017-08-28 10:04:16 +00003231 let NumMicroOps = 3;
3232 let ResourceCycles = [1,1,1];
3233}
3234def: InstRW<[HWWriteResGroup79], (instregex "MULX64rm")>;
3235
3236def HWWriteResGroup80 : SchedWriteRes<[HWPort5,HWPort23,HWPort015]> {
Gadi Haber2cf601f2017-12-08 09:48:44 +00003237 let Latency = 9;
Gadi Haberd76f7b82017-08-28 10:04:16 +00003238 let NumMicroOps = 3;
3239 let ResourceCycles = [1,1,1];
3240}
3241def: InstRW<[HWWriteResGroup80], (instregex "VPBROADCASTBYrm")>;
3242def: InstRW<[HWWriteResGroup80], (instregex "VPBROADCASTBrm")>;
3243def: InstRW<[HWWriteResGroup80], (instregex "VPBROADCASTWYrm")>;
3244def: InstRW<[HWWriteResGroup80], (instregex "VPBROADCASTWrm")>;
3245
3246def HWWriteResGroup81 : SchedWriteRes<[HWPort0156]> {
3247 let Latency = 4;
3248 let NumMicroOps = 4;
3249 let ResourceCycles = [4];
3250}
3251def: InstRW<[HWWriteResGroup81], (instregex "FNCLEX")>;
3252
3253def HWWriteResGroup82 : SchedWriteRes<[HWPort015,HWPort0156]> {
3254 let Latency = 4;
3255 let NumMicroOps = 4;
3256 let ResourceCycles = [1,3];
3257}
3258def: InstRW<[HWWriteResGroup82], (instregex "VZEROUPPER")>;
3259
3260def HWWriteResGroup83 : SchedWriteRes<[HWPort1,HWPort6,HWPort0156]> {
3261 let Latency = 4;
3262 let NumMicroOps = 4;
3263 let ResourceCycles = [1,1,2];
3264}
3265def: InstRW<[HWWriteResGroup83], (instregex "LAR(16|32|64)rr")>;
3266
3267def HWWriteResGroup84 : SchedWriteRes<[HWPort0,HWPort4,HWPort237,HWPort15]> {
Gadi Haber2cf601f2017-12-08 09:48:44 +00003268 let Latency = 5;
Gadi Haberd76f7b82017-08-28 10:04:16 +00003269 let NumMicroOps = 4;
3270 let ResourceCycles = [1,1,1,1];
3271}
3272def: InstRW<[HWWriteResGroup84], (instregex "VMASKMOVPDYmr")>;
3273def: InstRW<[HWWriteResGroup84], (instregex "VMASKMOVPDmr")>;
3274def: InstRW<[HWWriteResGroup84], (instregex "VMASKMOVPSYmr")>;
3275def: InstRW<[HWWriteResGroup84], (instregex "VMASKMOVPSmr")>;
3276def: InstRW<[HWWriteResGroup84], (instregex "VPMASKMOVDYmr")>;
3277def: InstRW<[HWWriteResGroup84], (instregex "VPMASKMOVDmr")>;
3278def: InstRW<[HWWriteResGroup84], (instregex "VPMASKMOVQYmr")>;
3279def: InstRW<[HWWriteResGroup84], (instregex "VPMASKMOVQmr")>;
3280
3281def HWWriteResGroup85 : SchedWriteRes<[HWPort1,HWPort4,HWPort5,HWPort237]> {
Gadi Haber2cf601f2017-12-08 09:48:44 +00003282 let Latency = 5;
Gadi Haberd76f7b82017-08-28 10:04:16 +00003283 let NumMicroOps = 4;
3284 let ResourceCycles = [1,1,1,1];
3285}
3286def: InstRW<[HWWriteResGroup85], (instregex "VCVTPS2PHmr")>;
3287
3288def HWWriteResGroup86 : SchedWriteRes<[HWPort1,HWPort23,HWPort237,HWPort0156]> {
Gadi Haber2cf601f2017-12-08 09:48:44 +00003289 let Latency = 10;
Gadi Haberd76f7b82017-08-28 10:04:16 +00003290 let NumMicroOps = 4;
3291 let ResourceCycles = [1,1,1,1];
3292}
3293def: InstRW<[HWWriteResGroup86], (instregex "SHLD(16|32|64)mri8")>;
3294def: InstRW<[HWWriteResGroup86], (instregex "SHRD(16|32|64)mri8")>;
3295
3296def HWWriteResGroup87 : SchedWriteRes<[HWPort1,HWPort6,HWPort23,HWPort0156]> {
Gadi Haber2cf601f2017-12-08 09:48:44 +00003297 let Latency = 9;
Gadi Haberd76f7b82017-08-28 10:04:16 +00003298 let NumMicroOps = 5;
3299 let ResourceCycles = [1,2,1,1];
3300}
3301def: InstRW<[HWWriteResGroup87], (instregex "LAR(16|32|64)rm")>;
3302def: InstRW<[HWWriteResGroup87], (instregex "LSL(16|32|64)rm")>;
3303
3304def HWWriteResGroup88 : SchedWriteRes<[HWPort4,HWPort237,HWPort0156]> {
Gadi Haber2cf601f2017-12-08 09:48:44 +00003305 let Latency = 5;
Gadi Haberd76f7b82017-08-28 10:04:16 +00003306 let NumMicroOps = 6;
3307 let ResourceCycles = [1,1,4];
3308}
3309def: InstRW<[HWWriteResGroup88], (instregex "PUSHF16")>;
3310def: InstRW<[HWWriteResGroup88], (instregex "PUSHF64")>;
3311
3312def HWWriteResGroup89 : SchedWriteRes<[HWPort0]> {
Michael Zuckermanf6684002017-06-28 11:23:31 +00003313 let Latency = 5;
3314 let NumMicroOps = 1;
Gadi Haberd76f7b82017-08-28 10:04:16 +00003315 let ResourceCycles = [1];
Michael Zuckermanf6684002017-06-28 11:23:31 +00003316}
Gadi Haberd76f7b82017-08-28 10:04:16 +00003317def: InstRW<[HWWriteResGroup89], (instregex "MMX_PMADDUBSWrr64")>;
3318def: InstRW<[HWWriteResGroup89], (instregex "MMX_PMADDWDirr")>;
3319def: InstRW<[HWWriteResGroup89], (instregex "MMX_PMULHRSWrr64")>;
3320def: InstRW<[HWWriteResGroup89], (instregex "MMX_PMULHUWirr")>;
3321def: InstRW<[HWWriteResGroup89], (instregex "MMX_PMULHWirr")>;
3322def: InstRW<[HWWriteResGroup89], (instregex "MMX_PMULLWirr")>;
3323def: InstRW<[HWWriteResGroup89], (instregex "MMX_PMULUDQirr")>;
3324def: InstRW<[HWWriteResGroup89], (instregex "MMX_PSADBWirr")>;
3325def: InstRW<[HWWriteResGroup89], (instregex "MUL_FPrST0")>;
3326def: InstRW<[HWWriteResGroup89], (instregex "MUL_FST0r")>;
3327def: InstRW<[HWWriteResGroup89], (instregex "MUL_FrST0")>;
3328def: InstRW<[HWWriteResGroup89], (instregex "PCMPGTQrr")>;
3329def: InstRW<[HWWriteResGroup89], (instregex "PHMINPOSUWrr128")>;
3330def: InstRW<[HWWriteResGroup89], (instregex "PMADDUBSWrr")>;
3331def: InstRW<[HWWriteResGroup89], (instregex "PMADDWDrr")>;
3332def: InstRW<[HWWriteResGroup89], (instregex "PMULDQrr")>;
3333def: InstRW<[HWWriteResGroup89], (instregex "PMULHRSWrr")>;
3334def: InstRW<[HWWriteResGroup89], (instregex "PMULHUWrr")>;
3335def: InstRW<[HWWriteResGroup89], (instregex "PMULHWrr")>;
3336def: InstRW<[HWWriteResGroup89], (instregex "PMULLWrr")>;
3337def: InstRW<[HWWriteResGroup89], (instregex "PMULUDQrr")>;
3338def: InstRW<[HWWriteResGroup89], (instregex "PSADBWrr")>;
3339def: InstRW<[HWWriteResGroup89], (instregex "RCPPSr")>;
3340def: InstRW<[HWWriteResGroup89], (instregex "RCPSSr")>;
3341def: InstRW<[HWWriteResGroup89], (instregex "RSQRTPSr")>;
3342def: InstRW<[HWWriteResGroup89], (instregex "RSQRTSSr")>;
3343def: InstRW<[HWWriteResGroup89], (instregex "VPCMPGTQYrr")>;
3344def: InstRW<[HWWriteResGroup89], (instregex "VPCMPGTQrr")>;
3345def: InstRW<[HWWriteResGroup89], (instregex "VPHMINPOSUWrr128")>;
3346def: InstRW<[HWWriteResGroup89], (instregex "VPMADDUBSWYrr")>;
3347def: InstRW<[HWWriteResGroup89], (instregex "VPMADDUBSWrr")>;
3348def: InstRW<[HWWriteResGroup89], (instregex "VPMADDWDYrr")>;
3349def: InstRW<[HWWriteResGroup89], (instregex "VPMADDWDrr")>;
3350def: InstRW<[HWWriteResGroup89], (instregex "VPMULDQYrr")>;
3351def: InstRW<[HWWriteResGroup89], (instregex "VPMULDQrr")>;
3352def: InstRW<[HWWriteResGroup89], (instregex "VPMULHRSWYrr")>;
3353def: InstRW<[HWWriteResGroup89], (instregex "VPMULHRSWrr")>;
3354def: InstRW<[HWWriteResGroup89], (instregex "VPMULHUWYrr")>;
3355def: InstRW<[HWWriteResGroup89], (instregex "VPMULHUWrr")>;
3356def: InstRW<[HWWriteResGroup89], (instregex "VPMULHWYrr")>;
3357def: InstRW<[HWWriteResGroup89], (instregex "VPMULHWrr")>;
3358def: InstRW<[HWWriteResGroup89], (instregex "VPMULLWYrr")>;
3359def: InstRW<[HWWriteResGroup89], (instregex "VPMULLWrr")>;
3360def: InstRW<[HWWriteResGroup89], (instregex "VPMULUDQYrr")>;
3361def: InstRW<[HWWriteResGroup89], (instregex "VPMULUDQrr")>;
3362def: InstRW<[HWWriteResGroup89], (instregex "VPSADBWYrr")>;
3363def: InstRW<[HWWriteResGroup89], (instregex "VPSADBWrr")>;
3364def: InstRW<[HWWriteResGroup89], (instregex "VRCPPSr")>;
3365def: InstRW<[HWWriteResGroup89], (instregex "VRCPSSr")>;
3366def: InstRW<[HWWriteResGroup89], (instregex "VRSQRTPSr")>;
3367def: InstRW<[HWWriteResGroup89], (instregex "VRSQRTSSr")>;
Michael Zuckermanf6684002017-06-28 11:23:31 +00003368
Gadi Haberd76f7b82017-08-28 10:04:16 +00003369def HWWriteResGroup90 : SchedWriteRes<[HWPort01]> {
Michael Zuckermanf6684002017-06-28 11:23:31 +00003370 let Latency = 5;
Gadi Haberd76f7b82017-08-28 10:04:16 +00003371 let NumMicroOps = 1;
3372 let ResourceCycles = [1];
Michael Zuckermanf6684002017-06-28 11:23:31 +00003373}
Gadi Haberd76f7b82017-08-28 10:04:16 +00003374def: InstRW<[HWWriteResGroup90], (instregex "MULPDrr")>;
3375def: InstRW<[HWWriteResGroup90], (instregex "MULPSrr")>;
3376def: InstRW<[HWWriteResGroup90], (instregex "MULSDrr")>;
3377def: InstRW<[HWWriteResGroup90], (instregex "MULSSrr")>;
3378def: InstRW<[HWWriteResGroup90], (instregex "VFMADD132PDYr")>;
3379def: InstRW<[HWWriteResGroup90], (instregex "VFMADD132PDr")>;
3380def: InstRW<[HWWriteResGroup90], (instregex "VFMADD132PSYr")>;
3381def: InstRW<[HWWriteResGroup90], (instregex "VFMADD132PSr")>;
3382def: InstRW<[HWWriteResGroup90], (instregex "VFMADD132SDr")>;
3383def: InstRW<[HWWriteResGroup90], (instregex "VFMADD132SSr")>;
3384def: InstRW<[HWWriteResGroup90], (instregex "VFMADD213PDYr")>;
3385def: InstRW<[HWWriteResGroup90], (instregex "VFMADD213PDr")>;
3386def: InstRW<[HWWriteResGroup90], (instregex "VFMADD213PSYr")>;
3387def: InstRW<[HWWriteResGroup90], (instregex "VFMADD213PSr")>;
3388def: InstRW<[HWWriteResGroup90], (instregex "VFMADD213SDr")>;
3389def: InstRW<[HWWriteResGroup90], (instregex "VFMADD213SSr")>;
3390def: InstRW<[HWWriteResGroup90], (instregex "VFMADD231PDYr")>;
3391def: InstRW<[HWWriteResGroup90], (instregex "VFMADD231PDr")>;
3392def: InstRW<[HWWriteResGroup90], (instregex "VFMADD231PSYr")>;
3393def: InstRW<[HWWriteResGroup90], (instregex "VFMADD231PSr")>;
3394def: InstRW<[HWWriteResGroup90], (instregex "VFMADD231SDr")>;
3395def: InstRW<[HWWriteResGroup90], (instregex "VFMADD231SSr")>;
3396def: InstRW<[HWWriteResGroup90], (instregex "VFMADDSUB132PDYr")>;
3397def: InstRW<[HWWriteResGroup90], (instregex "VFMADDSUB132PDr")>;
3398def: InstRW<[HWWriteResGroup90], (instregex "VFMADDSUB132PSYr")>;
3399def: InstRW<[HWWriteResGroup90], (instregex "VFMADDSUB132PSr")>;
3400def: InstRW<[HWWriteResGroup90], (instregex "VFMADDSUB213PDYr")>;
3401def: InstRW<[HWWriteResGroup90], (instregex "VFMADDSUB213PDr")>;
3402def: InstRW<[HWWriteResGroup90], (instregex "VFMADDSUB213PSYr")>;
3403def: InstRW<[HWWriteResGroup90], (instregex "VFMADDSUB213PSr")>;
3404def: InstRW<[HWWriteResGroup90], (instregex "VFMADDSUB231PDYr")>;
3405def: InstRW<[HWWriteResGroup90], (instregex "VFMADDSUB231PDr")>;
3406def: InstRW<[HWWriteResGroup90], (instregex "VFMADDSUB231PSYr")>;
3407def: InstRW<[HWWriteResGroup90], (instregex "VFMADDSUB231PSr")>;
3408def: InstRW<[HWWriteResGroup90], (instregex "VFMSUB132PDYr")>;
3409def: InstRW<[HWWriteResGroup90], (instregex "VFMSUB132PDr")>;
3410def: InstRW<[HWWriteResGroup90], (instregex "VFMSUB132PSYr")>;
3411def: InstRW<[HWWriteResGroup90], (instregex "VFMSUB132PSr")>;
3412def: InstRW<[HWWriteResGroup90], (instregex "VFMSUB132SDr")>;
3413def: InstRW<[HWWriteResGroup90], (instregex "VFMSUB132SSr")>;
3414def: InstRW<[HWWriteResGroup90], (instregex "VFMSUB213PDYr")>;
3415def: InstRW<[HWWriteResGroup90], (instregex "VFMSUB213PDr")>;
3416def: InstRW<[HWWriteResGroup90], (instregex "VFMSUB213PSYr")>;
3417def: InstRW<[HWWriteResGroup90], (instregex "VFMSUB213PSr")>;
3418def: InstRW<[HWWriteResGroup90], (instregex "VFMSUB213SDr")>;
3419def: InstRW<[HWWriteResGroup90], (instregex "VFMSUB213SSr")>;
3420def: InstRW<[HWWriteResGroup90], (instregex "VFMSUB231PDYr")>;
3421def: InstRW<[HWWriteResGroup90], (instregex "VFMSUB231PDr")>;
3422def: InstRW<[HWWriteResGroup90], (instregex "VFMSUB231PSYr")>;
3423def: InstRW<[HWWriteResGroup90], (instregex "VFMSUB231PSr")>;
3424def: InstRW<[HWWriteResGroup90], (instregex "VFMSUB231SDr")>;
3425def: InstRW<[HWWriteResGroup90], (instregex "VFMSUB231SSr")>;
3426def: InstRW<[HWWriteResGroup90], (instregex "VFMSUBADD132PDYr")>;
3427def: InstRW<[HWWriteResGroup90], (instregex "VFMSUBADD132PDr")>;
3428def: InstRW<[HWWriteResGroup90], (instregex "VFMSUBADD132PSYr")>;
3429def: InstRW<[HWWriteResGroup90], (instregex "VFMSUBADD132PSr")>;
3430def: InstRW<[HWWriteResGroup90], (instregex "VFMSUBADD213PDYr")>;
3431def: InstRW<[HWWriteResGroup90], (instregex "VFMSUBADD213PDr")>;
3432def: InstRW<[HWWriteResGroup90], (instregex "VFMSUBADD213PSYr")>;
3433def: InstRW<[HWWriteResGroup90], (instregex "VFMSUBADD213PSr")>;
3434def: InstRW<[HWWriteResGroup90], (instregex "VFMSUBADD231PDYr")>;
3435def: InstRW<[HWWriteResGroup90], (instregex "VFMSUBADD231PDr")>;
3436def: InstRW<[HWWriteResGroup90], (instregex "VFMSUBADD231PSYr")>;
3437def: InstRW<[HWWriteResGroup90], (instregex "VFMSUBADD231PSr")>;
3438def: InstRW<[HWWriteResGroup90], (instregex "VFNMADD132PDYr")>;
3439def: InstRW<[HWWriteResGroup90], (instregex "VFNMADD132PDr")>;
3440def: InstRW<[HWWriteResGroup90], (instregex "VFNMADD132PSYr")>;
3441def: InstRW<[HWWriteResGroup90], (instregex "VFNMADD132PSr")>;
3442def: InstRW<[HWWriteResGroup90], (instregex "VFNMADD132SDr")>;
3443def: InstRW<[HWWriteResGroup90], (instregex "VFNMADD132SSr")>;
3444def: InstRW<[HWWriteResGroup90], (instregex "VFNMADD213PDYr")>;
3445def: InstRW<[HWWriteResGroup90], (instregex "VFNMADD213PDr")>;
3446def: InstRW<[HWWriteResGroup90], (instregex "VFNMADD213PSYr")>;
3447def: InstRW<[HWWriteResGroup90], (instregex "VFNMADD213PSr")>;
3448def: InstRW<[HWWriteResGroup90], (instregex "VFNMADD213SDr")>;
3449def: InstRW<[HWWriteResGroup90], (instregex "VFNMADD213SSr")>;
3450def: InstRW<[HWWriteResGroup90], (instregex "VFNMADD231PDYr")>;
3451def: InstRW<[HWWriteResGroup90], (instregex "VFNMADD231PDr")>;
3452def: InstRW<[HWWriteResGroup90], (instregex "VFNMADD231PSYr")>;
3453def: InstRW<[HWWriteResGroup90], (instregex "VFNMADD231PSr")>;
3454def: InstRW<[HWWriteResGroup90], (instregex "VFNMADD231SDr")>;
3455def: InstRW<[HWWriteResGroup90], (instregex "VFNMADD231SSr")>;
3456def: InstRW<[HWWriteResGroup90], (instregex "VFNMSUB132PDYr")>;
3457def: InstRW<[HWWriteResGroup90], (instregex "VFNMSUB132PDr")>;
3458def: InstRW<[HWWriteResGroup90], (instregex "VFNMSUB132PSYr")>;
3459def: InstRW<[HWWriteResGroup90], (instregex "VFNMSUB132PSr")>;
3460def: InstRW<[HWWriteResGroup90], (instregex "VFNMSUB132SDr")>;
3461def: InstRW<[HWWriteResGroup90], (instregex "VFNMSUB132SSr")>;
3462def: InstRW<[HWWriteResGroup90], (instregex "VFNMSUB213PDYr")>;
3463def: InstRW<[HWWriteResGroup90], (instregex "VFNMSUB213PDr")>;
3464def: InstRW<[HWWriteResGroup90], (instregex "VFNMSUB213PSYr")>;
3465def: InstRW<[HWWriteResGroup90], (instregex "VFNMSUB213PSr")>;
3466def: InstRW<[HWWriteResGroup90], (instregex "VFNMSUB213SDr")>;
3467def: InstRW<[HWWriteResGroup90], (instregex "VFNMSUB213SSr")>;
3468def: InstRW<[HWWriteResGroup90], (instregex "VFNMSUB231PDYr")>;
3469def: InstRW<[HWWriteResGroup90], (instregex "VFNMSUB231PDr")>;
3470def: InstRW<[HWWriteResGroup90], (instregex "VFNMSUB231PSYr")>;
3471def: InstRW<[HWWriteResGroup90], (instregex "VFNMSUB231PSr")>;
3472def: InstRW<[HWWriteResGroup90], (instregex "VFNMSUB231SDr")>;
3473def: InstRW<[HWWriteResGroup90], (instregex "VFNMSUB231SSr")>;
3474def: InstRW<[HWWriteResGroup90], (instregex "VMULPDYrr")>;
3475def: InstRW<[HWWriteResGroup90], (instregex "VMULPDrr")>;
3476def: InstRW<[HWWriteResGroup90], (instregex "VMULPSYrr")>;
3477def: InstRW<[HWWriteResGroup90], (instregex "VMULPSrr")>;
3478def: InstRW<[HWWriteResGroup90], (instregex "VMULSDrr")>;
3479def: InstRW<[HWWriteResGroup90], (instregex "VMULSSrr")>;
Michael Zuckermanf6684002017-06-28 11:23:31 +00003480
Gadi Haberd76f7b82017-08-28 10:04:16 +00003481def HWWriteResGroup91 : SchedWriteRes<[HWPort0,HWPort23]> {
Gadi Haber2cf601f2017-12-08 09:48:44 +00003482 let Latency = 10;
Michael Zuckermanf6684002017-06-28 11:23:31 +00003483 let NumMicroOps = 2;
Gadi Haberd76f7b82017-08-28 10:04:16 +00003484 let ResourceCycles = [1,1];
Michael Zuckermanf6684002017-06-28 11:23:31 +00003485}
Gadi Haberd76f7b82017-08-28 10:04:16 +00003486def: InstRW<[HWWriteResGroup91], (instregex "MMX_PMADDUBSWrm64")>;
3487def: InstRW<[HWWriteResGroup91], (instregex "MMX_PMADDWDirm")>;
3488def: InstRW<[HWWriteResGroup91], (instregex "MMX_PMULHRSWrm64")>;
3489def: InstRW<[HWWriteResGroup91], (instregex "MMX_PMULHUWirm")>;
3490def: InstRW<[HWWriteResGroup91], (instregex "MMX_PMULHWirm")>;
3491def: InstRW<[HWWriteResGroup91], (instregex "MMX_PMULLWirm")>;
3492def: InstRW<[HWWriteResGroup91], (instregex "MMX_PMULUDQirm")>;
3493def: InstRW<[HWWriteResGroup91], (instregex "MMX_PSADBWirm")>;
Gadi Haberd76f7b82017-08-28 10:04:16 +00003494def: InstRW<[HWWriteResGroup91], (instregex "RCPSSm")>;
Gadi Haberd76f7b82017-08-28 10:04:16 +00003495def: InstRW<[HWWriteResGroup91], (instregex "RSQRTSSm")>;
Gadi Haberd76f7b82017-08-28 10:04:16 +00003496def: InstRW<[HWWriteResGroup91], (instregex "VRCPSSm")>;
Gadi Haberd76f7b82017-08-28 10:04:16 +00003497def: InstRW<[HWWriteResGroup91], (instregex "VRSQRTSSm")>;
Michael Zuckermanf6684002017-06-28 11:23:31 +00003498
Gadi Haber2cf601f2017-12-08 09:48:44 +00003499def HWWriteResGroup91_1 : SchedWriteRes<[HWPort0,HWPort23]> {
3500 let Latency = 18;
3501 let NumMicroOps = 2;
3502 let ResourceCycles = [1,1];
3503}
3504def: InstRW<[HWWriteResGroup91_1], (instregex "SQRTSSm")>;
3505def: InstRW<[HWWriteResGroup91_1], (instregex "VDIVSSrm")>;
3506
3507def HWWriteResGroup91_2 : SchedWriteRes<[HWPort0,HWPort23]> {
3508 let Latency = 11;
3509 let NumMicroOps = 2;
3510 let ResourceCycles = [1,1];
3511}
3512def: InstRW<[HWWriteResGroup91_2], (instregex "PCMPGTQrm")>;
3513def: InstRW<[HWWriteResGroup91_2], (instregex "PHMINPOSUWrm128")>;
3514def: InstRW<[HWWriteResGroup91_2], (instregex "PMADDUBSWrm")>;
3515def: InstRW<[HWWriteResGroup91_2], (instregex "PMADDWDrm")>;
3516def: InstRW<[HWWriteResGroup91_2], (instregex "PMULDQrm")>;
3517def: InstRW<[HWWriteResGroup91_2], (instregex "PMULHRSWrm")>;
3518def: InstRW<[HWWriteResGroup91_2], (instregex "PMULHUWrm")>;
3519def: InstRW<[HWWriteResGroup91_2], (instregex "PMULHWrm")>;
3520def: InstRW<[HWWriteResGroup91_2], (instregex "PMULLWrm")>;
3521def: InstRW<[HWWriteResGroup91_2], (instregex "PMULUDQrm")>;
3522def: InstRW<[HWWriteResGroup91_2], (instregex "PSADBWrm")>;
3523def: InstRW<[HWWriteResGroup91_2], (instregex "RCPPSm")>;
3524def: InstRW<[HWWriteResGroup91_2], (instregex "RSQRTPSm")>;
3525def: InstRW<[HWWriteResGroup91_2], (instregex "VPCMPGTQrm")>;
3526def: InstRW<[HWWriteResGroup91_2], (instregex "VPHMINPOSUWrm128")>;
3527def: InstRW<[HWWriteResGroup91_2], (instregex "VPMADDUBSWrm")>;
3528def: InstRW<[HWWriteResGroup91_2], (instregex "VPMADDWDrm")>;
3529def: InstRW<[HWWriteResGroup91_2], (instregex "VPMULDQrm")>;
3530def: InstRW<[HWWriteResGroup91_2], (instregex "VPMULHRSWrm")>;
3531def: InstRW<[HWWriteResGroup91_2], (instregex "VPMULHUWrm")>;
3532def: InstRW<[HWWriteResGroup91_2], (instregex "VPMULHWrm")>;
3533def: InstRW<[HWWriteResGroup91_2], (instregex "VPMULLWrm")>;
3534def: InstRW<[HWWriteResGroup91_2], (instregex "VPMULUDQrm")>;
3535def: InstRW<[HWWriteResGroup91_2], (instregex "VPSADBWrm")>;
3536def: InstRW<[HWWriteResGroup91_2], (instregex "VRCPPSm")>;
3537def: InstRW<[HWWriteResGroup91_2], (instregex "VRSQRTPSm")>;
3538
3539def HWWriteResGroup91_3 : SchedWriteRes<[HWPort0,HWPort23]> {
3540 let Latency = 12;
3541 let NumMicroOps = 2;
3542 let ResourceCycles = [1,1];
3543}
3544def: InstRW<[HWWriteResGroup91_3], (instregex "MUL_F32m")>;
3545def: InstRW<[HWWriteResGroup91_3], (instregex "MUL_F64m")>;
3546def: InstRW<[HWWriteResGroup91_3], (instregex "VPCMPGTQYrm")>;
3547def: InstRW<[HWWriteResGroup91_3], (instregex "VPMADDUBSWYrm")>;
3548def: InstRW<[HWWriteResGroup91_3], (instregex "VPMADDWDYrm")>;
3549def: InstRW<[HWWriteResGroup91_3], (instregex "VPMULDQYrm")>;
3550def: InstRW<[HWWriteResGroup91_3], (instregex "VPMULHRSWYrm")>;
3551def: InstRW<[HWWriteResGroup91_3], (instregex "VPMULHUWYrm")>;
3552def: InstRW<[HWWriteResGroup91_3], (instregex "VPMULHWYrm")>;
3553def: InstRW<[HWWriteResGroup91_3], (instregex "VPMULLWYrm")>;
3554def: InstRW<[HWWriteResGroup91_3], (instregex "VPMULUDQYrm")>;
3555def: InstRW<[HWWriteResGroup91_3], (instregex "VPSADBWYrm")>;
3556
Gadi Haberd76f7b82017-08-28 10:04:16 +00003557def HWWriteResGroup92 : SchedWriteRes<[HWPort01,HWPort23]> {
Gadi Haber2cf601f2017-12-08 09:48:44 +00003558 let Latency = 11;
Gadi Haberd76f7b82017-08-28 10:04:16 +00003559 let NumMicroOps = 2;
3560 let ResourceCycles = [1,1];
3561}
3562def: InstRW<[HWWriteResGroup92], (instregex "MULPDrm")>;
3563def: InstRW<[HWWriteResGroup92], (instregex "MULPSrm")>;
Gadi Haberd76f7b82017-08-28 10:04:16 +00003564def: InstRW<[HWWriteResGroup92], (instregex "VFMADD132PDm")>;
Gadi Haberd76f7b82017-08-28 10:04:16 +00003565def: InstRW<[HWWriteResGroup92], (instregex "VFMADD132PSm")>;
Gadi Haberd76f7b82017-08-28 10:04:16 +00003566def: InstRW<[HWWriteResGroup92], (instregex "VFMADD213PDm")>;
Gadi Haberd76f7b82017-08-28 10:04:16 +00003567def: InstRW<[HWWriteResGroup92], (instregex "VFMADD213PSm")>;
Gadi Haberd76f7b82017-08-28 10:04:16 +00003568def: InstRW<[HWWriteResGroup92], (instregex "VFMADD231PDm")>;
Gadi Haberd76f7b82017-08-28 10:04:16 +00003569def: InstRW<[HWWriteResGroup92], (instregex "VFMADD231PSm")>;
Gadi Haberd76f7b82017-08-28 10:04:16 +00003570def: InstRW<[HWWriteResGroup92], (instregex "VFMADDSUB132PDm")>;
Gadi Haberd76f7b82017-08-28 10:04:16 +00003571def: InstRW<[HWWriteResGroup92], (instregex "VFMADDSUB132PSm")>;
Gadi Haberd76f7b82017-08-28 10:04:16 +00003572def: InstRW<[HWWriteResGroup92], (instregex "VFMADDSUB213PDm")>;
Gadi Haberd76f7b82017-08-28 10:04:16 +00003573def: InstRW<[HWWriteResGroup92], (instregex "VFMADDSUB213PSm")>;
Gadi Haberd76f7b82017-08-28 10:04:16 +00003574def: InstRW<[HWWriteResGroup92], (instregex "VFMADDSUB231PDm")>;
Gadi Haberd76f7b82017-08-28 10:04:16 +00003575def: InstRW<[HWWriteResGroup92], (instregex "VFMADDSUB231PSm")>;
Gadi Haberd76f7b82017-08-28 10:04:16 +00003576def: InstRW<[HWWriteResGroup92], (instregex "VFMSUB132PDm")>;
Gadi Haberd76f7b82017-08-28 10:04:16 +00003577def: InstRW<[HWWriteResGroup92], (instregex "VFMSUB132PSm")>;
Gadi Haberd76f7b82017-08-28 10:04:16 +00003578def: InstRW<[HWWriteResGroup92], (instregex "VFMSUB213PDm")>;
Gadi Haberd76f7b82017-08-28 10:04:16 +00003579def: InstRW<[HWWriteResGroup92], (instregex "VFMSUB213PSm")>;
Gadi Haberd76f7b82017-08-28 10:04:16 +00003580def: InstRW<[HWWriteResGroup92], (instregex "VFMSUB231PDm")>;
Gadi Haberd76f7b82017-08-28 10:04:16 +00003581def: InstRW<[HWWriteResGroup92], (instregex "VFMSUB231PSm")>;
Gadi Haberd76f7b82017-08-28 10:04:16 +00003582def: InstRW<[HWWriteResGroup92], (instregex "VFMSUBADD132PDm")>;
Gadi Haberd76f7b82017-08-28 10:04:16 +00003583def: InstRW<[HWWriteResGroup92], (instregex "VFMSUBADD132PSm")>;
Gadi Haberd76f7b82017-08-28 10:04:16 +00003584def: InstRW<[HWWriteResGroup92], (instregex "VFMSUBADD213PDm")>;
Gadi Haberd76f7b82017-08-28 10:04:16 +00003585def: InstRW<[HWWriteResGroup92], (instregex "VFMSUBADD213PSm")>;
Gadi Haberd76f7b82017-08-28 10:04:16 +00003586def: InstRW<[HWWriteResGroup92], (instregex "VFMSUBADD231PDm")>;
Gadi Haberd76f7b82017-08-28 10:04:16 +00003587def: InstRW<[HWWriteResGroup92], (instregex "VFMSUBADD231PSm")>;
Gadi Haberd76f7b82017-08-28 10:04:16 +00003588def: InstRW<[HWWriteResGroup92], (instregex "VFNMADD132PDm")>;
Gadi Haberd76f7b82017-08-28 10:04:16 +00003589def: InstRW<[HWWriteResGroup92], (instregex "VFNMADD132PSm")>;
Gadi Haberd76f7b82017-08-28 10:04:16 +00003590def: InstRW<[HWWriteResGroup92], (instregex "VFNMADD213PDm")>;
Gadi Haberd76f7b82017-08-28 10:04:16 +00003591def: InstRW<[HWWriteResGroup92], (instregex "VFNMADD213PSm")>;
Gadi Haberd76f7b82017-08-28 10:04:16 +00003592def: InstRW<[HWWriteResGroup92], (instregex "VFNMADD231PDm")>;
Gadi Haberd76f7b82017-08-28 10:04:16 +00003593def: InstRW<[HWWriteResGroup92], (instregex "VFNMADD231PSm")>;
Gadi Haberd76f7b82017-08-28 10:04:16 +00003594def: InstRW<[HWWriteResGroup92], (instregex "VFNMSUB132PDm")>;
Gadi Haberd76f7b82017-08-28 10:04:16 +00003595def: InstRW<[HWWriteResGroup92], (instregex "VFNMSUB132PSm")>;
Gadi Haberd76f7b82017-08-28 10:04:16 +00003596def: InstRW<[HWWriteResGroup92], (instregex "VFNMSUB213PDm")>;
Gadi Haberd76f7b82017-08-28 10:04:16 +00003597def: InstRW<[HWWriteResGroup92], (instregex "VFNMSUB213PSm")>;
Gadi Haberd76f7b82017-08-28 10:04:16 +00003598def: InstRW<[HWWriteResGroup92], (instregex "VFNMSUB231PDm")>;
Gadi Haberd76f7b82017-08-28 10:04:16 +00003599def: InstRW<[HWWriteResGroup92], (instregex "VFNMSUB231PSm")>;
Gadi Haberd76f7b82017-08-28 10:04:16 +00003600def: InstRW<[HWWriteResGroup92], (instregex "VMULPDrm")>;
Gadi Haberd76f7b82017-08-28 10:04:16 +00003601def: InstRW<[HWWriteResGroup92], (instregex "VMULPSrm")>;
Gadi Haber2cf601f2017-12-08 09:48:44 +00003602
3603def HWWriteResGroup92_1 : SchedWriteRes<[HWPort01,HWPort23]> {
3604 let Latency = 12;
3605 let NumMicroOps = 2;
3606 let ResourceCycles = [1,1];
3607}
3608def: InstRW<[HWWriteResGroup92_1], (instregex "VFMADD132PDYm")>;
3609def: InstRW<[HWWriteResGroup92_1], (instregex "VFMADD132PSYm")>;
3610def: InstRW<[HWWriteResGroup92_1], (instregex "VFMADD213PDYm")>;
3611def: InstRW<[HWWriteResGroup92_1], (instregex "VFMADD213PSYm")>;
3612def: InstRW<[HWWriteResGroup92_1], (instregex "VFMADD231PDYm")>;
3613def: InstRW<[HWWriteResGroup92_1], (instregex "VFMADD231PSYm")>;
3614def: InstRW<[HWWriteResGroup92_1], (instregex "VFMADDSUB132PDYm")>;
3615def: InstRW<[HWWriteResGroup92_1], (instregex "VFMADDSUB132PSYm")>;
3616def: InstRW<[HWWriteResGroup92_1], (instregex "VFMADDSUB213PDYm")>;
3617def: InstRW<[HWWriteResGroup92_1], (instregex "VFMADDSUB213PSYm")>;
3618def: InstRW<[HWWriteResGroup92_1], (instregex "VFMADDSUB231PDYm")>;
3619def: InstRW<[HWWriteResGroup92_1], (instregex "VFMADDSUB231PSYm")>;
3620def: InstRW<[HWWriteResGroup92_1], (instregex "VFMSUB132PDYm")>;
3621def: InstRW<[HWWriteResGroup92_1], (instregex "VFMSUB132PSYm")>;
3622def: InstRW<[HWWriteResGroup92_1], (instregex "VFMSUB213PDYm")>;
3623def: InstRW<[HWWriteResGroup92_1], (instregex "VFMSUB213PSYm")>;
3624def: InstRW<[HWWriteResGroup92_1], (instregex "VFMSUB231PDYm")>;
3625def: InstRW<[HWWriteResGroup92_1], (instregex "VFMSUB231PSYm")>;
3626def: InstRW<[HWWriteResGroup92_1], (instregex "VFMSUBADD132PDYm")>;
3627def: InstRW<[HWWriteResGroup92_1], (instregex "VFMSUBADD132PSYm")>;
3628def: InstRW<[HWWriteResGroup92_1], (instregex "VFMSUBADD213PDYm")>;
3629def: InstRW<[HWWriteResGroup92_1], (instregex "VFMSUBADD213PSYm")>;
3630def: InstRW<[HWWriteResGroup92_1], (instregex "VFMSUBADD231PDYm")>;
3631def: InstRW<[HWWriteResGroup92_1], (instregex "VFMSUBADD231PSYm")>;
3632def: InstRW<[HWWriteResGroup92_1], (instregex "VFNMADD132PDYm")>;
3633def: InstRW<[HWWriteResGroup92_1], (instregex "VFNMADD132PSYm")>;
3634def: InstRW<[HWWriteResGroup92_1], (instregex "VFNMADD213PDYm")>;
3635def: InstRW<[HWWriteResGroup92_1], (instregex "VFNMADD213PSYm")>;
3636def: InstRW<[HWWriteResGroup92_1], (instregex "VFNMADD231PDYm")>;
3637def: InstRW<[HWWriteResGroup92_1], (instregex "VFNMADD231PSYm")>;
3638def: InstRW<[HWWriteResGroup92_1], (instregex "VFNMSUB132PDYm")>;
3639def: InstRW<[HWWriteResGroup92_1], (instregex "VFNMSUB132PSYm")>;
3640def: InstRW<[HWWriteResGroup92_1], (instregex "VFNMSUB213PDYm")>;
3641def: InstRW<[HWWriteResGroup92_1], (instregex "VFNMSUB213PSYm")>;
3642def: InstRW<[HWWriteResGroup92_1], (instregex "VFNMSUB231PDYm")>;
3643def: InstRW<[HWWriteResGroup92_1], (instregex "VFNMSUB231PSYm")>;
3644def: InstRW<[HWWriteResGroup92_1], (instregex "VMULPDYrm")>;
3645def: InstRW<[HWWriteResGroup92_1], (instregex "VMULPSYrm")>;
3646
3647def HWWriteResGroup92_2 : SchedWriteRes<[HWPort01,HWPort23]> {
3648 let Latency = 10;
3649 let NumMicroOps = 2;
3650 let ResourceCycles = [1,1];
3651}
3652def: InstRW<[HWWriteResGroup92_2], (instregex "MULSDrm")>;
3653def: InstRW<[HWWriteResGroup92_2], (instregex "MULSSrm")>;
3654def: InstRW<[HWWriteResGroup92_2], (instregex "VFMADD132SDm")>;
3655def: InstRW<[HWWriteResGroup92_2], (instregex "VFMADD132SSm")>;
3656def: InstRW<[HWWriteResGroup92_2], (instregex "VFMADD213SDm")>;
3657def: InstRW<[HWWriteResGroup92_2], (instregex "VFMADD213SSm")>;
3658def: InstRW<[HWWriteResGroup92_2], (instregex "VFMADD231SDm")>;
3659def: InstRW<[HWWriteResGroup92_2], (instregex "VFMADD231SSm")>;
3660def: InstRW<[HWWriteResGroup92_2], (instregex "VFMSUB132SDm")>;
3661def: InstRW<[HWWriteResGroup92_2], (instregex "VFMSUB132SSm")>;
3662def: InstRW<[HWWriteResGroup92_2], (instregex "VFMSUB213SDm")>;
3663def: InstRW<[HWWriteResGroup92_2], (instregex "VFMSUB213SSm")>;
3664def: InstRW<[HWWriteResGroup92_2], (instregex "VFMSUB231SDm")>;
3665def: InstRW<[HWWriteResGroup92_2], (instregex "VFMSUB231SSm")>;
3666def: InstRW<[HWWriteResGroup92_2], (instregex "VFNMADD132SDm")>;
3667def: InstRW<[HWWriteResGroup92_2], (instregex "VFNMADD132SSm")>;
3668def: InstRW<[HWWriteResGroup92_2], (instregex "VFNMADD213SDm")>;
3669def: InstRW<[HWWriteResGroup92_2], (instregex "VFNMADD213SSm")>;
3670def: InstRW<[HWWriteResGroup92_2], (instregex "VFNMADD231SDm")>;
3671def: InstRW<[HWWriteResGroup92_2], (instregex "VFNMADD231SSm")>;
3672def: InstRW<[HWWriteResGroup92_2], (instregex "VFNMSUB132SDm")>;
3673def: InstRW<[HWWriteResGroup92_2], (instregex "VFNMSUB132SSm")>;
3674def: InstRW<[HWWriteResGroup92_2], (instregex "VFNMSUB213SDm")>;
3675def: InstRW<[HWWriteResGroup92_2], (instregex "VFNMSUB213SSm")>;
3676def: InstRW<[HWWriteResGroup92_2], (instregex "VFNMSUB231SDm")>;
3677def: InstRW<[HWWriteResGroup92_2], (instregex "VFNMSUB231SSm")>;
3678def: InstRW<[HWWriteResGroup92_2], (instregex "VMULSDrm")>;
3679def: InstRW<[HWWriteResGroup92_2], (instregex "VMULSSrm")>;
Gadi Haberd76f7b82017-08-28 10:04:16 +00003680
3681def HWWriteResGroup93 : SchedWriteRes<[HWPort1,HWPort5]> {
3682 let Latency = 5;
Michael Zuckermanf6684002017-06-28 11:23:31 +00003683 let NumMicroOps = 3;
Gadi Haberd76f7b82017-08-28 10:04:16 +00003684 let ResourceCycles = [1,2];
Michael Zuckermanf6684002017-06-28 11:23:31 +00003685}
Gadi Haberd76f7b82017-08-28 10:04:16 +00003686def: InstRW<[HWWriteResGroup93], (instregex "CVTSI2SS64rr")>;
3687def: InstRW<[HWWriteResGroup93], (instregex "HADDPDrr")>;
3688def: InstRW<[HWWriteResGroup93], (instregex "HADDPSrr")>;
3689def: InstRW<[HWWriteResGroup93], (instregex "HSUBPDrr")>;
3690def: InstRW<[HWWriteResGroup93], (instregex "HSUBPSrr")>;
3691def: InstRW<[HWWriteResGroup93], (instregex "VCVTSI2SS64rr")>;
3692def: InstRW<[HWWriteResGroup93], (instregex "VHADDPDYrr")>;
3693def: InstRW<[HWWriteResGroup93], (instregex "VHADDPDrr")>;
3694def: InstRW<[HWWriteResGroup93], (instregex "VHADDPSYrr")>;
3695def: InstRW<[HWWriteResGroup93], (instregex "VHADDPSrr")>;
3696def: InstRW<[HWWriteResGroup93], (instregex "VHSUBPDYrr")>;
3697def: InstRW<[HWWriteResGroup93], (instregex "VHSUBPDrr")>;
3698def: InstRW<[HWWriteResGroup93], (instregex "VHSUBPSYrr")>;
3699def: InstRW<[HWWriteResGroup93], (instregex "VHSUBPSrr")>;
Michael Zuckermanf6684002017-06-28 11:23:31 +00003700
Gadi Haberd76f7b82017-08-28 10:04:16 +00003701def HWWriteResGroup94 : SchedWriteRes<[HWPort1,HWPort6,HWPort06]> {
3702 let Latency = 5;
3703 let NumMicroOps = 3;
3704 let ResourceCycles = [1,1,1];
3705}
3706def: InstRW<[HWWriteResGroup94], (instregex "STR(16|32|64)r")>;
3707
3708def HWWriteResGroup95 : SchedWriteRes<[HWPort1,HWPort06,HWPort0156]> {
3709 let Latency = 5;
3710 let NumMicroOps = 3;
3711 let ResourceCycles = [1,1,1];
3712}
3713def: InstRW<[HWWriteResGroup95], (instregex "MULX32rr")>;
3714
3715def HWWriteResGroup96 : SchedWriteRes<[HWPort1,HWPort5,HWPort23]> {
Gadi Haber2cf601f2017-12-08 09:48:44 +00003716 let Latency = 11;
Michael Zuckermanf6684002017-06-28 11:23:31 +00003717 let NumMicroOps = 4;
Gadi Haberd76f7b82017-08-28 10:04:16 +00003718 let ResourceCycles = [1,2,1];
Michael Zuckermanf6684002017-06-28 11:23:31 +00003719}
Gadi Haberd76f7b82017-08-28 10:04:16 +00003720def: InstRW<[HWWriteResGroup96], (instregex "HADDPDrm")>;
3721def: InstRW<[HWWriteResGroup96], (instregex "HADDPSrm")>;
3722def: InstRW<[HWWriteResGroup96], (instregex "HSUBPDrm")>;
3723def: InstRW<[HWWriteResGroup96], (instregex "HSUBPSrm")>;
Gadi Haberd76f7b82017-08-28 10:04:16 +00003724def: InstRW<[HWWriteResGroup96], (instregex "VHADDPDrm")>;
Gadi Haberd76f7b82017-08-28 10:04:16 +00003725def: InstRW<[HWWriteResGroup96], (instregex "VHADDPSrm")>;
Gadi Haberd76f7b82017-08-28 10:04:16 +00003726def: InstRW<[HWWriteResGroup96], (instregex "VHSUBPDrm")>;
Gadi Haberd76f7b82017-08-28 10:04:16 +00003727def: InstRW<[HWWriteResGroup96], (instregex "VHSUBPSrm")>;
Michael Zuckermanf6684002017-06-28 11:23:31 +00003728
Gadi Haber2cf601f2017-12-08 09:48:44 +00003729def HWWriteResGroup96_1 : SchedWriteRes<[HWPort1,HWPort5,HWPort23]> {
3730 let Latency = 12;
3731 let NumMicroOps = 4;
3732 let ResourceCycles = [1,2,1];
3733}
3734def: InstRW<[HWWriteResGroup96_1], (instregex "VHADDPDYrm")>;
3735def: InstRW<[HWWriteResGroup96_1], (instregex "VHADDPSYrm")>;
3736def: InstRW<[HWWriteResGroup96_1], (instregex "VHSUBPDYrm")>;
3737def: InstRW<[HWWriteResGroup96_1], (instregex "VHSUBPSYrm")>;
3738
Gadi Haberd76f7b82017-08-28 10:04:16 +00003739def HWWriteResGroup97 : SchedWriteRes<[HWPort0,HWPort1,HWPort5,HWPort23]> {
Gadi Haber2cf601f2017-12-08 09:48:44 +00003740 let Latency = 10;
Michael Zuckermanf6684002017-06-28 11:23:31 +00003741 let NumMicroOps = 4;
Gadi Haberd76f7b82017-08-28 10:04:16 +00003742 let ResourceCycles = [1,1,1,1];
Michael Zuckermanf6684002017-06-28 11:23:31 +00003743}
Gadi Haberd76f7b82017-08-28 10:04:16 +00003744def: InstRW<[HWWriteResGroup97], (instregex "CVTTSS2SI64rm")>;
Michael Zuckermanf6684002017-06-28 11:23:31 +00003745
Gadi Haberd76f7b82017-08-28 10:04:16 +00003746def HWWriteResGroup98 : SchedWriteRes<[HWPort1,HWPort23,HWPort06,HWPort0156]> {
Gadi Haber2cf601f2017-12-08 09:48:44 +00003747 let Latency = 10;
Gadi Haberd76f7b82017-08-28 10:04:16 +00003748 let NumMicroOps = 4;
3749 let ResourceCycles = [1,1,1,1];
Michael Zuckermanf6684002017-06-28 11:23:31 +00003750}
Gadi Haberd76f7b82017-08-28 10:04:16 +00003751def: InstRW<[HWWriteResGroup98], (instregex "MULX32rm")>;
Michael Zuckermanf6684002017-06-28 11:23:31 +00003752
Gadi Haberd76f7b82017-08-28 10:04:16 +00003753def HWWriteResGroup99 : SchedWriteRes<[HWPort6,HWPort0156]> {
3754 let Latency = 5;
3755 let NumMicroOps = 5;
3756 let ResourceCycles = [1,4];
3757}
3758def: InstRW<[HWWriteResGroup99], (instregex "PAUSE")>;
3759
3760def HWWriteResGroup100 : SchedWriteRes<[HWPort06,HWPort0156]> {
3761 let Latency = 5;
3762 let NumMicroOps = 5;
3763 let ResourceCycles = [1,4];
3764}
3765def: InstRW<[HWWriteResGroup100], (instregex "XSETBV")>;
3766
3767def HWWriteResGroup101 : SchedWriteRes<[HWPort06,HWPort0156]> {
3768 let Latency = 5;
3769 let NumMicroOps = 5;
3770 let ResourceCycles = [2,3];
3771}
3772def: InstRW<[HWWriteResGroup101], (instregex "CMPXCHG(16|32|64)rr")>;
3773def: InstRW<[HWWriteResGroup101], (instregex "CMPXCHG8rr")>;
Gadi Haberd76f7b82017-08-28 10:04:16 +00003774
3775def HWWriteResGroup102 : SchedWriteRes<[HWPort1,HWPort5]> {
3776 let Latency = 6;
3777 let NumMicroOps = 2;
3778 let ResourceCycles = [1,1];
3779}
3780def: InstRW<[HWWriteResGroup102], (instregex "VCVTDQ2PDYrr")>;
3781def: InstRW<[HWWriteResGroup102], (instregex "VCVTPD2DQYrr")>;
3782def: InstRW<[HWWriteResGroup102], (instregex "VCVTPD2PSYrr")>;
3783def: InstRW<[HWWriteResGroup102], (instregex "VCVTPS2PHYrr")>;
3784def: InstRW<[HWWriteResGroup102], (instregex "VCVTTPD2DQYrr")>;
3785
3786def HWWriteResGroup103 : SchedWriteRes<[HWPort1,HWPort23]> {
Gadi Haber2cf601f2017-12-08 09:48:44 +00003787 let Latency = 13;
Michael Zuckermanf6684002017-06-28 11:23:31 +00003788 let NumMicroOps = 3;
Gadi Haberd76f7b82017-08-28 10:04:16 +00003789 let ResourceCycles = [2,1];
Michael Zuckermanf6684002017-06-28 11:23:31 +00003790}
Gadi Haberd76f7b82017-08-28 10:04:16 +00003791def: InstRW<[HWWriteResGroup103], (instregex "ADD_FI16m")>;
3792def: InstRW<[HWWriteResGroup103], (instregex "ADD_FI32m")>;
Gadi Haberd76f7b82017-08-28 10:04:16 +00003793def: InstRW<[HWWriteResGroup103], (instregex "SUBR_FI16m")>;
3794def: InstRW<[HWWriteResGroup103], (instregex "SUBR_FI32m")>;
3795def: InstRW<[HWWriteResGroup103], (instregex "SUB_FI16m")>;
3796def: InstRW<[HWWriteResGroup103], (instregex "SUB_FI32m")>;
Gadi Haberd76f7b82017-08-28 10:04:16 +00003797def: InstRW<[HWWriteResGroup103], (instregex "VROUNDYPDm")>;
3798def: InstRW<[HWWriteResGroup103], (instregex "VROUNDYPSm")>;
Michael Zuckermanf6684002017-06-28 11:23:31 +00003799
Gadi Haber2cf601f2017-12-08 09:48:44 +00003800def HWWriteResGroup103_1 : SchedWriteRes<[HWPort1,HWPort23]> {
3801 let Latency = 12;
3802 let NumMicroOps = 3;
3803 let ResourceCycles = [2,1];
3804}
3805def: InstRW<[HWWriteResGroup103_1], (instregex "ROUNDPDm")>;
3806def: InstRW<[HWWriteResGroup103_1], (instregex "ROUNDPSm")>;
3807def: InstRW<[HWWriteResGroup103_1], (instregex "ROUNDSDm")>;
3808def: InstRW<[HWWriteResGroup103_1], (instregex "ROUNDSSm")>;
3809def: InstRW<[HWWriteResGroup103_1], (instregex "VROUNDPDm")>;
3810def: InstRW<[HWWriteResGroup103_1], (instregex "VROUNDPSm")>;
3811def: InstRW<[HWWriteResGroup103_1], (instregex "VROUNDSDm")>;
3812def: InstRW<[HWWriteResGroup103_1], (instregex "VROUNDSSm")>;
3813
Gadi Haberd76f7b82017-08-28 10:04:16 +00003814def HWWriteResGroup104 : SchedWriteRes<[HWPort1,HWPort5,HWPort23]> {
Gadi Haber2cf601f2017-12-08 09:48:44 +00003815 let Latency = 12;
Gadi Haberd76f7b82017-08-28 10:04:16 +00003816 let NumMicroOps = 3;
3817 let ResourceCycles = [1,1,1];
3818}
3819def: InstRW<[HWWriteResGroup104], (instregex "VCVTDQ2PDYrm")>;
3820
3821def HWWriteResGroup105 : SchedWriteRes<[HWPort1,HWPort06,HWPort0156]> {
3822 let Latency = 6;
3823 let NumMicroOps = 4;
3824 let ResourceCycles = [1,1,2];
3825}
3826def: InstRW<[HWWriteResGroup105], (instregex "SHLD(16|32|64)rrCL")>;
3827def: InstRW<[HWWriteResGroup105], (instregex "SHRD(16|32|64)rrCL")>;
3828
3829def HWWriteResGroup106 : SchedWriteRes<[HWPort1,HWPort4,HWPort5,HWPort237]> {
Gadi Haber2cf601f2017-12-08 09:48:44 +00003830 let Latency = 7;
Gadi Haberd76f7b82017-08-28 10:04:16 +00003831 let NumMicroOps = 4;
3832 let ResourceCycles = [1,1,1,1];
3833}
3834def: InstRW<[HWWriteResGroup106], (instregex "VCVTPS2PHYmr")>;
3835
3836def HWWriteResGroup107 : SchedWriteRes<[HWPort1,HWPort6,HWPort06,HWPort0156]> {
3837 let Latency = 6;
3838 let NumMicroOps = 4;
3839 let ResourceCycles = [1,1,1,1];
3840}
3841def: InstRW<[HWWriteResGroup107], (instregex "SLDT(16|32|64)r")>;
3842
3843def HWWriteResGroup108 : SchedWriteRes<[HWPort6,HWPort0156]> {
3844 let Latency = 6;
3845 let NumMicroOps = 6;
3846 let ResourceCycles = [1,5];
3847}
3848def: InstRW<[HWWriteResGroup108], (instregex "STD")>;
3849
3850def HWWriteResGroup109 : SchedWriteRes<[HWPort1,HWPort23,HWPort237,HWPort06,HWPort0156]> {
Gadi Haber2cf601f2017-12-08 09:48:44 +00003851 let Latency = 12;
Gadi Haberd76f7b82017-08-28 10:04:16 +00003852 let NumMicroOps = 6;
3853 let ResourceCycles = [1,1,1,1,2];
3854}
3855def: InstRW<[HWWriteResGroup109], (instregex "SHLD(16|32|64)mrCL")>;
3856def: InstRW<[HWWriteResGroup109], (instregex "SHRD(16|32|64)mrCL")>;
3857
3858def HWWriteResGroup110 : SchedWriteRes<[HWPort5]> {
3859 let Latency = 7;
3860 let NumMicroOps = 1;
3861 let ResourceCycles = [1];
3862}
3863def: InstRW<[HWWriteResGroup110], (instregex "AESDECLASTrr")>;
3864def: InstRW<[HWWriteResGroup110], (instregex "AESDECrr")>;
3865def: InstRW<[HWWriteResGroup110], (instregex "AESENCLASTrr")>;
3866def: InstRW<[HWWriteResGroup110], (instregex "AESENCrr")>;
3867def: InstRW<[HWWriteResGroup110], (instregex "VAESDECLASTrr")>;
3868def: InstRW<[HWWriteResGroup110], (instregex "VAESDECrr")>;
3869def: InstRW<[HWWriteResGroup110], (instregex "VAESENCLASTrr")>;
3870def: InstRW<[HWWriteResGroup110], (instregex "VAESENCrr")>;
3871
3872def HWWriteResGroup111 : SchedWriteRes<[HWPort5,HWPort23]> {
Gadi Haber2cf601f2017-12-08 09:48:44 +00003873 let Latency = 13;
Gadi Haberd76f7b82017-08-28 10:04:16 +00003874 let NumMicroOps = 2;
3875 let ResourceCycles = [1,1];
3876}
3877def: InstRW<[HWWriteResGroup111], (instregex "AESDECLASTrm")>;
3878def: InstRW<[HWWriteResGroup111], (instregex "AESDECrm")>;
3879def: InstRW<[HWWriteResGroup111], (instregex "AESENCLASTrm")>;
3880def: InstRW<[HWWriteResGroup111], (instregex "AESENCrm")>;
3881def: InstRW<[HWWriteResGroup111], (instregex "VAESDECLASTrm")>;
3882def: InstRW<[HWWriteResGroup111], (instregex "VAESDECrm")>;
3883def: InstRW<[HWWriteResGroup111], (instregex "VAESENCLASTrm")>;
3884def: InstRW<[HWWriteResGroup111], (instregex "VAESENCrm")>;
3885
3886def HWWriteResGroup112 : SchedWriteRes<[HWPort0,HWPort5]> {
3887 let Latency = 7;
3888 let NumMicroOps = 3;
3889 let ResourceCycles = [1,2];
3890}
3891def: InstRW<[HWWriteResGroup112], (instregex "MPSADBWrri")>;
3892def: InstRW<[HWWriteResGroup112], (instregex "VMPSADBWYrri")>;
3893def: InstRW<[HWWriteResGroup112], (instregex "VMPSADBWrri")>;
3894
3895def HWWriteResGroup113 : SchedWriteRes<[HWPort0,HWPort5,HWPort23]> {
Gadi Haber2cf601f2017-12-08 09:48:44 +00003896 let Latency = 13;
Michael Zuckermanf6684002017-06-28 11:23:31 +00003897 let NumMicroOps = 4;
Gadi Haberd76f7b82017-08-28 10:04:16 +00003898 let ResourceCycles = [1,2,1];
Michael Zuckermanf6684002017-06-28 11:23:31 +00003899}
Gadi Haberd76f7b82017-08-28 10:04:16 +00003900def: InstRW<[HWWriteResGroup113], (instregex "MPSADBWrmi")>;
Gadi Haberd76f7b82017-08-28 10:04:16 +00003901def: InstRW<[HWWriteResGroup113], (instregex "VMPSADBWrmi")>;
3902
Gadi Haber2cf601f2017-12-08 09:48:44 +00003903def HWWriteResGroup113_1 : SchedWriteRes<[HWPort0,HWPort5,HWPort23]> {
3904 let Latency = 14;
3905 let NumMicroOps = 4;
3906 let ResourceCycles = [1,2,1];
3907}
3908def: InstRW<[HWWriteResGroup113_1], (instregex "VMPSADBWYrmi")>;
3909
Gadi Haberd76f7b82017-08-28 10:04:16 +00003910def HWWriteResGroup114 : SchedWriteRes<[HWPort6,HWPort06,HWPort15,HWPort0156]> {
3911 let Latency = 7;
3912 let NumMicroOps = 7;
3913 let ResourceCycles = [2,2,1,2];
3914}
3915def: InstRW<[HWWriteResGroup114], (instregex "LOOP")>;
3916
3917def HWWriteResGroup115 : SchedWriteRes<[HWPort0,HWPort1,HWPort23]> {
Gadi Haber2cf601f2017-12-08 09:48:44 +00003918 let Latency = 15;
Gadi Haberd76f7b82017-08-28 10:04:16 +00003919 let NumMicroOps = 3;
3920 let ResourceCycles = [1,1,1];
3921}
3922def: InstRW<[HWWriteResGroup115], (instregex "MUL_FI16m")>;
3923def: InstRW<[HWWriteResGroup115], (instregex "MUL_FI32m")>;
3924
3925def HWWriteResGroup116 : SchedWriteRes<[HWPort0,HWPort1,HWPort5]> {
3926 let Latency = 9;
3927 let NumMicroOps = 3;
3928 let ResourceCycles = [1,1,1];
3929}
3930def: InstRW<[HWWriteResGroup116], (instregex "DPPDrri")>;
3931def: InstRW<[HWWriteResGroup116], (instregex "VDPPDrri")>;
3932
3933def HWWriteResGroup117 : SchedWriteRes<[HWPort0,HWPort1,HWPort5,HWPort23]> {
Gadi Haber2cf601f2017-12-08 09:48:44 +00003934 let Latency = 15;
Gadi Haberd76f7b82017-08-28 10:04:16 +00003935 let NumMicroOps = 4;
3936 let ResourceCycles = [1,1,1,1];
3937}
3938def: InstRW<[HWWriteResGroup117], (instregex "DPPDrmi")>;
3939def: InstRW<[HWWriteResGroup117], (instregex "VDPPDrmi")>;
3940
3941def HWWriteResGroup118 : SchedWriteRes<[HWPort0]> {
3942 let Latency = 10;
3943 let NumMicroOps = 2;
3944 let ResourceCycles = [2];
3945}
3946def: InstRW<[HWWriteResGroup118], (instregex "PMULLDrr")>;
3947def: InstRW<[HWWriteResGroup118], (instregex "VPMULLDYrr")>;
3948def: InstRW<[HWWriteResGroup118], (instregex "VPMULLDrr")>;
3949
3950def HWWriteResGroup119 : SchedWriteRes<[HWPort0,HWPort23]> {
Gadi Haber2cf601f2017-12-08 09:48:44 +00003951 let Latency = 16;
Gadi Haberd76f7b82017-08-28 10:04:16 +00003952 let NumMicroOps = 3;
3953 let ResourceCycles = [2,1];
3954}
3955def: InstRW<[HWWriteResGroup119], (instregex "PMULLDrm")>;
Gadi Haberd76f7b82017-08-28 10:04:16 +00003956def: InstRW<[HWWriteResGroup119], (instregex "VPMULLDrm")>;
3957
Gadi Haber2cf601f2017-12-08 09:48:44 +00003958def HWWriteResGroup119_1 : SchedWriteRes<[HWPort0,HWPort23]> {
3959 let Latency = 17;
3960 let NumMicroOps = 3;
3961 let ResourceCycles = [2,1];
3962}
3963def: InstRW<[HWWriteResGroup119_1], (instregex "VPMULLDYrm")>;
3964
Gadi Haberd76f7b82017-08-28 10:04:16 +00003965def HWWriteResGroup120 : SchedWriteRes<[HWPort1,HWPort23,HWPort237,HWPort06,HWPort15,HWPort0156]> {
Gadi Haber2cf601f2017-12-08 09:48:44 +00003966 let Latency = 16;
Gadi Haberd76f7b82017-08-28 10:04:16 +00003967 let NumMicroOps = 10;
3968 let ResourceCycles = [1,1,1,4,1,2];
3969}
3970def: InstRW<[HWWriteResGroup120], (instregex "RCL(16|32|64)mCL")>;
3971def: InstRW<[HWWriteResGroup120], (instregex "RCL8mCL")>;
3972
3973def HWWriteResGroup121 : SchedWriteRes<[HWPort0]> {
3974 let Latency = 11;
3975 let NumMicroOps = 1;
3976 let ResourceCycles = [1];
3977}
3978def: InstRW<[HWWriteResGroup121], (instregex "DIVPSrr")>;
3979def: InstRW<[HWWriteResGroup121], (instregex "DIVSSrr")>;
3980
3981def HWWriteResGroup122 : SchedWriteRes<[HWPort0,HWPort23]> {
Gadi Haber2cf601f2017-12-08 09:48:44 +00003982 let Latency = 17;
Gadi Haberd76f7b82017-08-28 10:04:16 +00003983 let NumMicroOps = 2;
3984 let ResourceCycles = [1,1];
3985}
3986def: InstRW<[HWWriteResGroup122], (instregex "DIVPSrm")>;
Gadi Haber2cf601f2017-12-08 09:48:44 +00003987
3988def HWWriteResGroup122_1 : SchedWriteRes<[HWPort0,HWPort23]> {
3989 let Latency = 16;
3990 let NumMicroOps = 2;
3991 let ResourceCycles = [1,1];
3992}
3993def: InstRW<[HWWriteResGroup122_1], (instregex "DIVSSrm")>;
Gadi Haberd76f7b82017-08-28 10:04:16 +00003994
3995def HWWriteResGroup123 : SchedWriteRes<[HWPort0]> {
3996 let Latency = 11;
3997 let NumMicroOps = 3;
3998 let ResourceCycles = [3];
3999}
4000def: InstRW<[HWWriteResGroup123], (instregex "PCMPISTRIrr")>;
4001def: InstRW<[HWWriteResGroup123], (instregex "PCMPISTRM128rr")>;
4002def: InstRW<[HWWriteResGroup123], (instregex "VPCMPISTRIrr")>;
4003def: InstRW<[HWWriteResGroup123], (instregex "VPCMPISTRM128rr")>;
4004
4005def HWWriteResGroup124 : SchedWriteRes<[HWPort0,HWPort5]> {
4006 let Latency = 11;
4007 let NumMicroOps = 3;
4008 let ResourceCycles = [2,1];
4009}
4010def: InstRW<[HWWriteResGroup124], (instregex "PCLMULQDQrr")>;
4011def: InstRW<[HWWriteResGroup124], (instregex "VPCLMULQDQrr")>;
4012
4013def HWWriteResGroup125 : SchedWriteRes<[HWPort0,HWPort015]> {
4014 let Latency = 11;
4015 let NumMicroOps = 3;
4016 let ResourceCycles = [2,1];
4017}
4018def: InstRW<[HWWriteResGroup125], (instregex "VRCPPSYr")>;
4019def: InstRW<[HWWriteResGroup125], (instregex "VRSQRTPSYr")>;
4020
4021def HWWriteResGroup126 : SchedWriteRes<[HWPort0,HWPort23]> {
Gadi Haber2cf601f2017-12-08 09:48:44 +00004022 let Latency = 17;
Gadi Haberd76f7b82017-08-28 10:04:16 +00004023 let NumMicroOps = 4;
4024 let ResourceCycles = [3,1];
4025}
4026def: InstRW<[HWWriteResGroup126], (instregex "PCMPISTRIrm")>;
4027def: InstRW<[HWWriteResGroup126], (instregex "PCMPISTRM128rm")>;
4028def: InstRW<[HWWriteResGroup126], (instregex "VPCMPISTRIrm")>;
4029def: InstRW<[HWWriteResGroup126], (instregex "VPCMPISTRM128rm")>;
4030
4031def HWWriteResGroup127 : SchedWriteRes<[HWPort0,HWPort5,HWPort23]> {
Gadi Haber2cf601f2017-12-08 09:48:44 +00004032 let Latency = 17;
Gadi Haberd76f7b82017-08-28 10:04:16 +00004033 let NumMicroOps = 4;
4034 let ResourceCycles = [2,1,1];
4035}
4036def: InstRW<[HWWriteResGroup127], (instregex "PCLMULQDQrm")>;
4037def: InstRW<[HWWriteResGroup127], (instregex "VPCLMULQDQrm")>;
4038
4039def HWWriteResGroup128 : SchedWriteRes<[HWPort0,HWPort23,HWPort015]> {
Gadi Haber2cf601f2017-12-08 09:48:44 +00004040 let Latency = 18;
Gadi Haberd76f7b82017-08-28 10:04:16 +00004041 let NumMicroOps = 4;
4042 let ResourceCycles = [2,1,1];
4043}
4044def: InstRW<[HWWriteResGroup128], (instregex "VRCPPSYm")>;
4045def: InstRW<[HWWriteResGroup128], (instregex "VRSQRTPSYm")>;
4046
4047def HWWriteResGroup129 : SchedWriteRes<[HWPort1,HWPort06,HWPort0156]> {
4048 let Latency = 11;
4049 let NumMicroOps = 7;
4050 let ResourceCycles = [2,2,3];
4051}
4052def: InstRW<[HWWriteResGroup129], (instregex "RCL(16|32|64)rCL")>;
4053def: InstRW<[HWWriteResGroup129], (instregex "RCR(16|32|64)rCL")>;
4054
4055def HWWriteResGroup130 : SchedWriteRes<[HWPort1,HWPort06,HWPort15,HWPort0156]> {
4056 let Latency = 11;
4057 let NumMicroOps = 9;
4058 let ResourceCycles = [1,4,1,3];
4059}
4060def: InstRW<[HWWriteResGroup130], (instregex "RCL8rCL")>;
4061
4062def HWWriteResGroup131 : SchedWriteRes<[HWPort06,HWPort0156]> {
4063 let Latency = 11;
4064 let NumMicroOps = 11;
4065 let ResourceCycles = [2,9];
4066}
4067def: InstRW<[HWWriteResGroup131], (instregex "LOOPE")>;
4068def: InstRW<[HWWriteResGroup131], (instregex "LOOPNE")>;
4069
4070def HWWriteResGroup132 : SchedWriteRes<[HWPort4,HWPort23,HWPort237,HWPort06,HWPort15,HWPort0156]> {
Gadi Haber2cf601f2017-12-08 09:48:44 +00004071 let Latency = 17;
Gadi Haberd76f7b82017-08-28 10:04:16 +00004072 let NumMicroOps = 14;
4073 let ResourceCycles = [1,1,1,4,2,5];
4074}
4075def: InstRW<[HWWriteResGroup132], (instregex "CMPXCHG8B")>;
4076
4077def HWWriteResGroup133 : SchedWriteRes<[HWPort0]> {
4078 let Latency = 13;
4079 let NumMicroOps = 1;
4080 let ResourceCycles = [1];
4081}
4082def: InstRW<[HWWriteResGroup133], (instregex "SQRTPSr")>;
4083def: InstRW<[HWWriteResGroup133], (instregex "SQRTSSr")>;
4084def: InstRW<[HWWriteResGroup133], (instregex "VDIVPSrr")>;
4085def: InstRW<[HWWriteResGroup133], (instregex "VDIVSSrr")>;
4086
4087def HWWriteResGroup134 : SchedWriteRes<[HWPort0,HWPort23]> {
Gadi Haber2cf601f2017-12-08 09:48:44 +00004088 let Latency = 19;
Gadi Haberd76f7b82017-08-28 10:04:16 +00004089 let NumMicroOps = 2;
4090 let ResourceCycles = [1,1];
4091}
Gadi Haber2cf601f2017-12-08 09:48:44 +00004092def: InstRW<[HWWriteResGroup134], (instregex "DIVSDrm")>;
Gadi Haberd76f7b82017-08-28 10:04:16 +00004093def: InstRW<[HWWriteResGroup134], (instregex "SQRTPSm")>;
Gadi Haberd76f7b82017-08-28 10:04:16 +00004094def: InstRW<[HWWriteResGroup134], (instregex "VDIVPSrm")>;
Gadi Haber2cf601f2017-12-08 09:48:44 +00004095def: InstRW<[HWWriteResGroup134], (instregex "VSQRTSSm")>;
Gadi Haberd76f7b82017-08-28 10:04:16 +00004096
4097def HWWriteResGroup135 : SchedWriteRes<[HWPort1,HWPort23,HWPort237,HWPort06,HWPort15,HWPort0156]> {
Gadi Haber2cf601f2017-12-08 09:48:44 +00004098 let Latency = 19;
Gadi Haberd76f7b82017-08-28 10:04:16 +00004099 let NumMicroOps = 11;
4100 let ResourceCycles = [2,1,1,3,1,3];
4101}
4102def: InstRW<[HWWriteResGroup135], (instregex "RCR(16|32|64)mCL")>;
4103def: InstRW<[HWWriteResGroup135], (instregex "RCR8mCL")>;
4104
4105def HWWriteResGroup136 : SchedWriteRes<[HWPort0]> {
4106 let Latency = 14;
4107 let NumMicroOps = 1;
4108 let ResourceCycles = [1];
4109}
4110def: InstRW<[HWWriteResGroup136], (instregex "DIVPDrr")>;
4111def: InstRW<[HWWriteResGroup136], (instregex "DIVSDrr")>;
4112def: InstRW<[HWWriteResGroup136], (instregex "VSQRTPSr")>;
4113def: InstRW<[HWWriteResGroup136], (instregex "VSQRTSSr")>;
4114
4115def HWWriteResGroup137 : SchedWriteRes<[HWPort5]> {
4116 let Latency = 14;
4117 let NumMicroOps = 2;
4118 let ResourceCycles = [2];
4119}
4120def: InstRW<[HWWriteResGroup137], (instregex "AESIMCrr")>;
4121def: InstRW<[HWWriteResGroup137], (instregex "VAESIMCrr")>;
4122
4123def HWWriteResGroup138 : SchedWriteRes<[HWPort0,HWPort23]> {
Gadi Haber2cf601f2017-12-08 09:48:44 +00004124 let Latency = 20;
Gadi Haberd76f7b82017-08-28 10:04:16 +00004125 let NumMicroOps = 2;
4126 let ResourceCycles = [1,1];
4127}
4128def: InstRW<[HWWriteResGroup138], (instregex "DIVPDrm")>;
Gadi Haberd76f7b82017-08-28 10:04:16 +00004129def: InstRW<[HWWriteResGroup138], (instregex "VSQRTPSm")>;
Gadi Haberd76f7b82017-08-28 10:04:16 +00004130
4131def HWWriteResGroup139 : SchedWriteRes<[HWPort5,HWPort23]> {
Gadi Haber2cf601f2017-12-08 09:48:44 +00004132 let Latency = 20;
Gadi Haberd76f7b82017-08-28 10:04:16 +00004133 let NumMicroOps = 3;
4134 let ResourceCycles = [2,1];
4135}
4136def: InstRW<[HWWriteResGroup139], (instregex "AESIMCrm")>;
4137def: InstRW<[HWWriteResGroup139], (instregex "VAESIMCrm")>;
4138
4139def HWWriteResGroup140 : SchedWriteRes<[HWPort0,HWPort1,HWPort5]> {
4140 let Latency = 14;
4141 let NumMicroOps = 4;
4142 let ResourceCycles = [2,1,1];
4143}
4144def: InstRW<[HWWriteResGroup140], (instregex "DPPSrri")>;
4145def: InstRW<[HWWriteResGroup140], (instregex "VDPPSYrri")>;
4146def: InstRW<[HWWriteResGroup140], (instregex "VDPPSrri")>;
4147
4148def HWWriteResGroup141 : SchedWriteRes<[HWPort0,HWPort1,HWPort5,HWPort23]> {
Gadi Haber2cf601f2017-12-08 09:48:44 +00004149 let Latency = 20;
Gadi Haberd76f7b82017-08-28 10:04:16 +00004150 let NumMicroOps = 5;
4151 let ResourceCycles = [2,1,1,1];
4152}
4153def: InstRW<[HWWriteResGroup141], (instregex "DPPSrmi")>;
Gadi Haberd76f7b82017-08-28 10:04:16 +00004154def: InstRW<[HWWriteResGroup141], (instregex "VDPPSrmi")>;
4155
Gadi Haber2cf601f2017-12-08 09:48:44 +00004156def HWWriteResGroup141_1 : SchedWriteRes<[HWPort0,HWPort1,HWPort5,HWPort23]> {
4157 let Latency = 21;
4158 let NumMicroOps = 5;
4159 let ResourceCycles = [2,1,1,1];
4160}
4161def: InstRW<[HWWriteResGroup141_1], (instregex "VDPPSYrmi")>;
4162
Gadi Haberd76f7b82017-08-28 10:04:16 +00004163def HWWriteResGroup142 : SchedWriteRes<[HWPort1,HWPort06,HWPort15,HWPort0156]> {
4164 let Latency = 14;
4165 let NumMicroOps = 10;
4166 let ResourceCycles = [2,3,1,4];
4167}
4168def: InstRW<[HWWriteResGroup142], (instregex "RCR8rCL")>;
4169
4170def HWWriteResGroup143 : SchedWriteRes<[HWPort23,HWPort0156]> {
Gadi Haber2cf601f2017-12-08 09:48:44 +00004171 let Latency = 19;
Gadi Haberd76f7b82017-08-28 10:04:16 +00004172 let NumMicroOps = 15;
4173 let ResourceCycles = [1,14];
4174}
4175def: InstRW<[HWWriteResGroup143], (instregex "POPF16")>;
4176
4177def HWWriteResGroup144 : SchedWriteRes<[HWPort4,HWPort5,HWPort6,HWPort23,HWPort237,HWPort06,HWPort0156]> {
Gadi Haber2cf601f2017-12-08 09:48:44 +00004178 let Latency = 21;
Gadi Haberd76f7b82017-08-28 10:04:16 +00004179 let NumMicroOps = 8;
4180 let ResourceCycles = [1,1,1,1,1,1,2];
4181}
4182def: InstRW<[HWWriteResGroup144], (instregex "INSB")>;
4183def: InstRW<[HWWriteResGroup144], (instregex "INSL")>;
4184def: InstRW<[HWWriteResGroup144], (instregex "INSW")>;
4185
4186def HWWriteResGroup145 : SchedWriteRes<[HWPort5]> {
4187 let Latency = 16;
4188 let NumMicroOps = 16;
4189 let ResourceCycles = [16];
4190}
4191def: InstRW<[HWWriteResGroup145], (instregex "VZEROALL")>;
4192
4193def HWWriteResGroup146 : SchedWriteRes<[HWPort0,HWPort4,HWPort5,HWPort23,HWPort237,HWPort06,HWPort0156]> {
Gadi Haber2cf601f2017-12-08 09:48:44 +00004194 let Latency = 22;
Gadi Haberd76f7b82017-08-28 10:04:16 +00004195 let NumMicroOps = 19;
4196 let ResourceCycles = [2,1,4,1,1,4,6];
4197}
4198def: InstRW<[HWWriteResGroup146], (instregex "CMPXCHG16B")>;
4199
4200def HWWriteResGroup147 : SchedWriteRes<[HWPort0,HWPort1,HWPort5,HWPort6,HWPort01,HWPort0156]> {
4201 let Latency = 17;
4202 let NumMicroOps = 15;
4203 let ResourceCycles = [2,1,2,4,2,4];
4204}
4205def: InstRW<[HWWriteResGroup147], (instregex "XCH_F")>;
4206
4207def HWWriteResGroup148 : SchedWriteRes<[HWPort0,HWPort5,HWPort0156]> {
4208 let Latency = 18;
4209 let NumMicroOps = 8;
4210 let ResourceCycles = [4,3,1];
4211}
4212def: InstRW<[HWWriteResGroup148], (instregex "PCMPESTRIrr")>;
4213def: InstRW<[HWWriteResGroup148], (instregex "VPCMPESTRIrr")>;
4214
4215def HWWriteResGroup149 : SchedWriteRes<[HWPort5,HWPort6,HWPort06,HWPort0156]> {
4216 let Latency = 18;
4217 let NumMicroOps = 8;
4218 let ResourceCycles = [1,1,1,5];
4219}
4220def: InstRW<[HWWriteResGroup149], (instregex "CPUID")>;
4221def: InstRW<[HWWriteResGroup149], (instregex "RDTSC")>;
4222
4223def HWWriteResGroup150 : SchedWriteRes<[HWPort0,HWPort5,HWPort23,HWPort0156]> {
Gadi Haber2cf601f2017-12-08 09:48:44 +00004224 let Latency = 24;
Gadi Haberd76f7b82017-08-28 10:04:16 +00004225 let NumMicroOps = 9;
4226 let ResourceCycles = [4,3,1,1];
4227}
4228def: InstRW<[HWWriteResGroup150], (instregex "PCMPESTRIrm")>;
4229def: InstRW<[HWWriteResGroup150], (instregex "VPCMPESTRIrm")>;
4230
4231def HWWriteResGroup151 : SchedWriteRes<[HWPort6,HWPort23,HWPort0156]> {
Gadi Haber2cf601f2017-12-08 09:48:44 +00004232 let Latency = 23;
Gadi Haberd76f7b82017-08-28 10:04:16 +00004233 let NumMicroOps = 19;
4234 let ResourceCycles = [3,1,15];
4235}
4236def: InstRW<[HWWriteResGroup151], (instregex "XRSTOR(64?)")>;
4237
4238def HWWriteResGroup152 : SchedWriteRes<[HWPort0,HWPort5,HWPort015,HWPort0156]> {
4239 let Latency = 19;
4240 let NumMicroOps = 9;
4241 let ResourceCycles = [4,3,1,1];
4242}
4243def: InstRW<[HWWriteResGroup152], (instregex "PCMPESTRM128rr")>;
4244def: InstRW<[HWWriteResGroup152], (instregex "VPCMPESTRM128rr")>;
4245
4246def HWWriteResGroup153 : SchedWriteRes<[HWPort0,HWPort5,HWPort23,HWPort015,HWPort0156]> {
Gadi Haber2cf601f2017-12-08 09:48:44 +00004247 let Latency = 25;
Gadi Haberd76f7b82017-08-28 10:04:16 +00004248 let NumMicroOps = 10;
4249 let ResourceCycles = [4,3,1,1,1];
4250}
4251def: InstRW<[HWWriteResGroup153], (instregex "PCMPESTRM128rm")>;
4252def: InstRW<[HWWriteResGroup153], (instregex "VPCMPESTRM128rm")>;
4253
4254def HWWriteResGroup154 : SchedWriteRes<[HWPort0]> {
4255 let Latency = 20;
4256 let NumMicroOps = 1;
4257 let ResourceCycles = [1];
4258}
4259def: InstRW<[HWWriteResGroup154], (instregex "DIV_FPrST0")>;
4260def: InstRW<[HWWriteResGroup154], (instregex "DIV_FST0r")>;
4261def: InstRW<[HWWriteResGroup154], (instregex "DIV_FrST0")>;
4262def: InstRW<[HWWriteResGroup154], (instregex "SQRTPDr")>;
4263def: InstRW<[HWWriteResGroup154], (instregex "SQRTSDr")>;
4264def: InstRW<[HWWriteResGroup154], (instregex "VDIVPDrr")>;
4265def: InstRW<[HWWriteResGroup154], (instregex "VDIVSDrr")>;
4266
4267def HWWriteResGroup155 : SchedWriteRes<[HWPort0,HWPort23]> {
Gadi Haber2cf601f2017-12-08 09:48:44 +00004268 let Latency = 27;
Gadi Haberd76f7b82017-08-28 10:04:16 +00004269 let NumMicroOps = 2;
4270 let ResourceCycles = [1,1];
4271}
4272def: InstRW<[HWWriteResGroup155], (instregex "DIVR_F32m")>;
4273def: InstRW<[HWWriteResGroup155], (instregex "DIVR_F64m")>;
Gadi Haber2cf601f2017-12-08 09:48:44 +00004274def: InstRW<[HWWriteResGroup155], (instregex "VSQRTPDm")>;
4275
4276def HWWriteResGroup155_1 : SchedWriteRes<[HWPort0,HWPort23]> {
4277 let Latency = 26;
4278 let NumMicroOps = 2;
4279 let ResourceCycles = [1,1];
4280}
4281def: InstRW<[HWWriteResGroup155_1], (instregex "SQRTPDm")>;
4282def: InstRW<[HWWriteResGroup155_1], (instregex "VDIVPDrm")>;
4283def: InstRW<[HWWriteResGroup155_1], (instregex "VSQRTSDm")>;
4284
4285def HWWriteResGroup155_2 : SchedWriteRes<[HWPort0,HWPort23]> {
4286 let Latency = 25;
4287 let NumMicroOps = 2;
4288 let ResourceCycles = [1,1];
4289}
4290def: InstRW<[HWWriteResGroup155_2], (instregex "SQRTSDm")>;
4291def: InstRW<[HWWriteResGroup155_2], (instregex "VDIVSDrm")>;
Gadi Haberd76f7b82017-08-28 10:04:16 +00004292
4293def HWWriteResGroup156 : SchedWriteRes<[HWPort5,HWPort6,HWPort0156]> {
4294 let Latency = 20;
4295 let NumMicroOps = 10;
4296 let ResourceCycles = [1,2,7];
4297}
4298def: InstRW<[HWWriteResGroup156], (instregex "MWAITrr")>;
4299
4300def HWWriteResGroup157 : SchedWriteRes<[HWPort0]> {
4301 let Latency = 21;
4302 let NumMicroOps = 1;
4303 let ResourceCycles = [1];
4304}
4305def: InstRW<[HWWriteResGroup157], (instregex "VSQRTPDr")>;
4306def: InstRW<[HWWriteResGroup157], (instregex "VSQRTSDr")>;
4307
Gadi Haberd76f7b82017-08-28 10:04:16 +00004308def HWWriteResGroup159 : SchedWriteRes<[HWPort0,HWPort015]> {
4309 let Latency = 21;
4310 let NumMicroOps = 3;
4311 let ResourceCycles = [2,1];
4312}
4313def: InstRW<[HWWriteResGroup159], (instregex "VDIVPSYrr")>;
4314def: InstRW<[HWWriteResGroup159], (instregex "VSQRTPSYr")>;
4315
4316def HWWriteResGroup160 : SchedWriteRes<[HWPort0,HWPort23,HWPort015]> {
Gadi Haber2cf601f2017-12-08 09:48:44 +00004317 let Latency = 28;
Gadi Haberd76f7b82017-08-28 10:04:16 +00004318 let NumMicroOps = 4;
4319 let ResourceCycles = [2,1,1];
4320}
4321def: InstRW<[HWWriteResGroup160], (instregex "VDIVPSYrm")>;
4322def: InstRW<[HWWriteResGroup160], (instregex "VSQRTPSYm")>;
4323
4324def HWWriteResGroup161 : SchedWriteRes<[HWPort0,HWPort1,HWPort23]> {
Gadi Haber2cf601f2017-12-08 09:48:44 +00004325 let Latency = 30;
Gadi Haberd76f7b82017-08-28 10:04:16 +00004326 let NumMicroOps = 3;
4327 let ResourceCycles = [1,1,1];
4328}
4329def: InstRW<[HWWriteResGroup161], (instregex "DIVR_FI16m")>;
4330def: InstRW<[HWWriteResGroup161], (instregex "DIVR_FI32m")>;
4331
4332def HWWriteResGroup162 : SchedWriteRes<[HWPort0]> {
4333 let Latency = 24;
4334 let NumMicroOps = 1;
4335 let ResourceCycles = [1];
4336}
4337def: InstRW<[HWWriteResGroup162], (instregex "DIVR_FPrST0")>;
4338def: InstRW<[HWWriteResGroup162], (instregex "DIVR_FST0r")>;
4339def: InstRW<[HWWriteResGroup162], (instregex "DIVR_FrST0")>;
4340
4341def HWWriteResGroup163 : SchedWriteRes<[HWPort0,HWPort23]> {
Gadi Haber2cf601f2017-12-08 09:48:44 +00004342 let Latency = 31;
Gadi Haberd76f7b82017-08-28 10:04:16 +00004343 let NumMicroOps = 2;
4344 let ResourceCycles = [1,1];
4345}
4346def: InstRW<[HWWriteResGroup163], (instregex "DIV_F32m")>;
4347def: InstRW<[HWWriteResGroup163], (instregex "DIV_F64m")>;
4348
4349def HWWriteResGroup164 : SchedWriteRes<[HWPort4,HWPort6,HWPort23,HWPort237,HWPort0156]> {
Gadi Haber2cf601f2017-12-08 09:48:44 +00004350 let Latency = 30;
Gadi Haberd76f7b82017-08-28 10:04:16 +00004351 let NumMicroOps = 27;
4352 let ResourceCycles = [1,5,1,1,19];
4353}
4354def: InstRW<[HWWriteResGroup164], (instregex "XSAVE64")>;
4355
4356def HWWriteResGroup165 : SchedWriteRes<[HWPort4,HWPort6,HWPort23,HWPort237,HWPort0156]> {
Gadi Haber2cf601f2017-12-08 09:48:44 +00004357 let Latency = 31;
Gadi Haberd76f7b82017-08-28 10:04:16 +00004358 let NumMicroOps = 28;
4359 let ResourceCycles = [1,6,1,1,19];
4360}
4361def: InstRW<[HWWriteResGroup165], (instregex "XSAVE(OPT?)")>;
4362
4363def HWWriteResGroup166 : SchedWriteRes<[HWPort0,HWPort1,HWPort23]> {
Gadi Haber2cf601f2017-12-08 09:48:44 +00004364 let Latency = 34;
Gadi Haberd76f7b82017-08-28 10:04:16 +00004365 let NumMicroOps = 3;
4366 let ResourceCycles = [1,1,1];
4367}
4368def: InstRW<[HWWriteResGroup166], (instregex "DIV_FI16m")>;
4369def: InstRW<[HWWriteResGroup166], (instregex "DIV_FI32m")>;
4370
4371def HWWriteResGroup167 : SchedWriteRes<[HWPort0,HWPort5,HWPort23,HWPort015]> {
Gadi Haber2cf601f2017-12-08 09:48:44 +00004372 let Latency = 34;
Gadi Haberd76f7b82017-08-28 10:04:16 +00004373 let NumMicroOps = 11;
4374 let ResourceCycles = [2,7,1,1];
4375}
4376def: InstRW<[HWWriteResGroup167], (instregex "AESKEYGENASSIST128rm")>;
4377def: InstRW<[HWWriteResGroup167], (instregex "VAESKEYGENASSIST128rm")>;
4378
4379def HWWriteResGroup168 : SchedWriteRes<[HWPort0,HWPort5,HWPort015]> {
4380 let Latency = 29;
4381 let NumMicroOps = 11;
4382 let ResourceCycles = [2,7,2];
4383}
4384def: InstRW<[HWWriteResGroup168], (instregex "AESKEYGENASSIST128rr")>;
4385def: InstRW<[HWWriteResGroup168], (instregex "VAESKEYGENASSIST128rr")>;
4386
4387def HWWriteResGroup170 : SchedWriteRes<[HWPort5,HWPort6,HWPort23,HWPort06,HWPort0156]> {
Gadi Haber2cf601f2017-12-08 09:48:44 +00004388 let Latency = 35;
Gadi Haberd76f7b82017-08-28 10:04:16 +00004389 let NumMicroOps = 23;
4390 let ResourceCycles = [1,5,3,4,10];
4391}
4392def: InstRW<[HWWriteResGroup170], (instregex "IN32ri")>;
4393def: InstRW<[HWWriteResGroup170], (instregex "IN32rr")>;
4394def: InstRW<[HWWriteResGroup170], (instregex "IN8ri")>;
4395def: InstRW<[HWWriteResGroup170], (instregex "IN8rr")>;
4396
4397def HWWriteResGroup171 : SchedWriteRes<[HWPort5,HWPort6,HWPort23,HWPort237,HWPort06,HWPort0156]> {
Gadi Haber2cf601f2017-12-08 09:48:44 +00004398 let Latency = 36;
Gadi Haberd76f7b82017-08-28 10:04:16 +00004399 let NumMicroOps = 23;
4400 let ResourceCycles = [1,5,2,1,4,10];
4401}
4402def: InstRW<[HWWriteResGroup171], (instregex "OUT32ir")>;
4403def: InstRW<[HWWriteResGroup171], (instregex "OUT32rr")>;
4404def: InstRW<[HWWriteResGroup171], (instregex "OUT8ir")>;
4405def: InstRW<[HWWriteResGroup171], (instregex "OUT8rr")>;
4406
4407def HWWriteResGroup172 : SchedWriteRes<[HWPort01,HWPort15,HWPort015,HWPort0156]> {
4408 let Latency = 31;
4409 let NumMicroOps = 31;
4410 let ResourceCycles = [8,1,21,1];
4411}
4412def: InstRW<[HWWriteResGroup172], (instregex "MMX_EMMS")>;
4413
4414def HWWriteResGroup173 : SchedWriteRes<[HWPort0,HWPort015]> {
4415 let Latency = 35;
4416 let NumMicroOps = 3;
4417 let ResourceCycles = [2,1];
4418}
4419def: InstRW<[HWWriteResGroup173], (instregex "VDIVPDYrr")>;
4420def: InstRW<[HWWriteResGroup173], (instregex "VSQRTPDYr")>;
4421
4422def HWWriteResGroup174 : SchedWriteRes<[HWPort0,HWPort23,HWPort015]> {
Gadi Haber2cf601f2017-12-08 09:48:44 +00004423 let Latency = 42;
Gadi Haberd76f7b82017-08-28 10:04:16 +00004424 let NumMicroOps = 4;
4425 let ResourceCycles = [2,1,1];
4426}
4427def: InstRW<[HWWriteResGroup174], (instregex "VDIVPDYrm")>;
4428def: InstRW<[HWWriteResGroup174], (instregex "VSQRTPDYm")>;
4429
4430def HWWriteResGroup175 : SchedWriteRes<[HWPort1,HWPort4,HWPort5,HWPort6,HWPort23,HWPort237,HWPort15,HWPort0156]> {
Gadi Haber2cf601f2017-12-08 09:48:44 +00004431 let Latency = 41;
Gadi Haberd76f7b82017-08-28 10:04:16 +00004432 let NumMicroOps = 18;
4433 let ResourceCycles = [1,1,2,3,1,1,1,8];
4434}
4435def: InstRW<[HWWriteResGroup175], (instregex "VMCLEARm")>;
4436
4437def HWWriteResGroup176 : SchedWriteRes<[HWPort5,HWPort0156]> {
4438 let Latency = 42;
4439 let NumMicroOps = 22;
4440 let ResourceCycles = [2,20];
4441}
4442def: InstRW<[HWWriteResGroup176], (instregex "RDTSCP")>;
4443
4444def HWWriteResGroup177 : SchedWriteRes<[HWPort0,HWPort01,HWPort23,HWPort05,HWPort06,HWPort015,HWPort0156]> {
Gadi Haber2cf601f2017-12-08 09:48:44 +00004445 let Latency = 61;
Gadi Haberd76f7b82017-08-28 10:04:16 +00004446 let NumMicroOps = 64;
4447 let ResourceCycles = [2,2,8,1,10,2,39];
4448}
4449def: InstRW<[HWWriteResGroup177], (instregex "FLDENVm")>;
4450def: InstRW<[HWWriteResGroup177], (instregex "FLDENVm")>;
4451
4452def HWWriteResGroup178 : SchedWriteRes<[HWPort0,HWPort6,HWPort23,HWPort05,HWPort06,HWPort15,HWPort0156]> {
Gadi Haber2cf601f2017-12-08 09:48:44 +00004453 let Latency = 64;
Gadi Haberd76f7b82017-08-28 10:04:16 +00004454 let NumMicroOps = 88;
4455 let ResourceCycles = [4,4,31,1,2,1,45];
4456}
4457def: InstRW<[HWWriteResGroup178], (instregex "FXRSTOR64")>;
4458
4459def HWWriteResGroup179 : SchedWriteRes<[HWPort0,HWPort6,HWPort23,HWPort05,HWPort06,HWPort15,HWPort0156]> {
Gadi Haber2cf601f2017-12-08 09:48:44 +00004460 let Latency = 64;
Gadi Haberd76f7b82017-08-28 10:04:16 +00004461 let NumMicroOps = 90;
4462 let ResourceCycles = [4,2,33,1,2,1,47];
4463}
4464def: InstRW<[HWWriteResGroup179], (instregex "FXRSTOR")>;
4465
4466def HWWriteResGroup180 : SchedWriteRes<[HWPort5,HWPort01,HWPort0156]> {
4467 let Latency = 75;
4468 let NumMicroOps = 15;
4469 let ResourceCycles = [6,3,6];
4470}
4471def: InstRW<[HWWriteResGroup180], (instregex "FNINIT")>;
4472
4473def HWWriteResGroup181 : SchedWriteRes<[HWPort0,HWPort1,HWPort5,HWPort6,HWPort01,HWPort0156]> {
4474 let Latency = 98;
4475 let NumMicroOps = 32;
4476 let ResourceCycles = [7,7,3,3,1,11];
4477}
4478def: InstRW<[HWWriteResGroup181], (instregex "DIV(16|32|64)r")>;
4479
4480def HWWriteResGroup182 : SchedWriteRes<[HWPort0,HWPort1,HWPort5,HWPort6,HWPort06,HWPort0156]> {
4481 let Latency = 112;
4482 let NumMicroOps = 66;
4483 let ResourceCycles = [4,2,4,8,14,34];
4484}
4485def: InstRW<[HWWriteResGroup182], (instregex "IDIV(16|32|64)r")>;
4486
4487def HWWriteResGroup183 : SchedWriteRes<[HWPort0,HWPort1,HWPort4,HWPort5,HWPort6,HWPort237,HWPort06,HWPort0156]> {
Gadi Haber2cf601f2017-12-08 09:48:44 +00004488 let Latency = 115;
Gadi Haberd76f7b82017-08-28 10:04:16 +00004489 let NumMicroOps = 100;
4490 let ResourceCycles = [9,9,11,8,1,11,21,30];
4491}
4492def: InstRW<[HWWriteResGroup183], (instregex "FSTENVm")>;
4493def: InstRW<[HWWriteResGroup183], (instregex "FSTENVm")>;
Quentin Colombet95e05312014-08-18 17:55:59 +00004494
Gadi Haber2cf601f2017-12-08 09:48:44 +00004495def HWWriteResGroup184 : SchedWriteRes<[HWPort0, HWPort5, HWPort15, HWPort015, HWPort06, HWPort23]> {
4496 let Latency = 26;
4497 let NumMicroOps = 12;
4498 let ResourceCycles = [2,2,1,3,2,2];
4499}
4500def: InstRW<[HWWriteResGroup184], (instregex "VGATHERDPDrm")>;
4501def: InstRW<[HWWriteResGroup184], (instregex "VPGATHERDQrm")>;
4502def: InstRW<[HWWriteResGroup184], (instregex "VPGATHERDDrm")>;
4503
4504def HWWriteResGroup185 : SchedWriteRes<[HWPort0, HWPort5, HWPort06, HWPort15, HWPort015, HWPort23]> {
4505 let Latency = 24;
4506 let NumMicroOps = 22;
4507 let ResourceCycles = [5,3,4,1,5,4];
4508}
4509def: InstRW<[HWWriteResGroup185], (instregex "VGATHERQPDYrm")>;
4510def: InstRW<[HWWriteResGroup185], (instregex "VPGATHERQQYrm")>;
4511
4512def HWWriteResGroup186 : SchedWriteRes<[HWPort0, HWPort5, HWPort06, HWPort15, HWPort015, HWPort23]> {
4513 let Latency = 28;
4514 let NumMicroOps = 22;
4515 let ResourceCycles = [5,3,4,1,5,4];
4516}
4517def: InstRW<[HWWriteResGroup186], (instregex "VPGATHERQDYrm")>;
4518
4519def HWWriteResGroup187 : SchedWriteRes<[HWPort0, HWPort5, HWPort06, HWPort15, HWPort015, HWPort23]> {
4520 let Latency = 25;
4521 let NumMicroOps = 22;
4522 let ResourceCycles = [5,3,4,1,5,4];
4523}
4524def: InstRW<[HWWriteResGroup187], (instregex "VPGATHERQDrm")>;
4525
4526def HWWriteResGroup188 : SchedWriteRes<[HWPort0, HWPort5, HWPort06, HWPort15, HWPort015, HWPort23]> {
4527 let Latency = 27;
4528 let NumMicroOps = 20;
4529 let ResourceCycles = [3,3,4,1,5,4];
4530}
4531def: InstRW<[HWWriteResGroup188], (instregex "VGATHERDPDYrm")>;
4532def: InstRW<[HWWriteResGroup188], (instregex "VPGATHERDQYrm")>;
4533
4534def HWWriteResGroup189 : SchedWriteRes<[HWPort0, HWPort5, HWPort06, HWPort15, HWPort015, HWPort23]> {
4535 let Latency = 27;
4536 let NumMicroOps = 34;
4537 let ResourceCycles = [5,3,8,1,9,8];
4538}
4539def: InstRW<[HWWriteResGroup189], (instregex "VGATHERDPSYrm")>;
4540def: InstRW<[HWWriteResGroup189], (instregex "VPGATHERDDYrm")>;
4541
4542def HWWriteResGroup190 : SchedWriteRes<[HWPort0, HWPort5, HWPort06, HWPort15, HWPort015, HWPort23]> {
4543 let Latency = 23;
4544 let NumMicroOps = 14;
4545 let ResourceCycles = [3,3,2,1,3,2];
4546}
4547def: InstRW<[HWWriteResGroup190], (instregex "VGATHERQPDrm")>;
4548def: InstRW<[HWWriteResGroup190], (instregex "VPGATHERQQrm")>;
4549
4550def HWWriteResGroup191 : SchedWriteRes<[HWPort0, HWPort5, HWPort06, HWPort15, HWPort015, HWPort23]> {
4551 let Latency = 28;
4552 let NumMicroOps = 15;
4553 let ResourceCycles = [3,3,2,1,4,2];
4554}
4555def: InstRW<[HWWriteResGroup191], (instregex "VGATHERQPSYrm")>;
4556
4557def HWWriteResGroup192 : SchedWriteRes<[HWPort0, HWPort5, HWPort06, HWPort15, HWPort015, HWPort23]> {
4558 let Latency = 25;
4559 let NumMicroOps = 15;
4560 let ResourceCycles = [3,3,2,1,4,2];
4561}
4562def: InstRW<[HWWriteResGroup192], (instregex "VGATHERQPSrm")>;
4563def: InstRW<[HWWriteResGroup192], (instregex "VGATHERDPSrm")>;
4564
Nadav Roteme7b6a8a2013-03-28 22:34:46 +00004565} // SchedModel