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Tom Stellard75aadc22012-12-11 21:25:42 +00001//===-- R600Intrinsics.td - R600 Instrinsic defs -------*- tablegen -*-----===//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// R600 Intrinsic Definitions
11//
12//===----------------------------------------------------------------------===//
13
Matt Arsenault59bd3012016-01-22 19:00:09 +000014// FIXME: Should migrate to using TargetPrefix that matches triple arch name.
Matt Arsenaultbee75752016-01-26 04:49:24 +000015let TargetPrefix = "AMDGPU", isTarget = 1 in {
16 def int_AMDGPU_dp4 : Intrinsic<[llvm_float_ty], [llvm_v4f32_ty, llvm_v4f32_ty], [IntrNoMem]>;
17 def int_AMDGPU_tex : Intrinsic<[llvm_v4f32_ty], [llvm_v4f32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>;
18 def int_AMDGPU_txb : Intrinsic<[llvm_v4f32_ty], [llvm_v4f32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>;
19 def int_AMDGPU_txf : Intrinsic<[llvm_v4f32_ty], [llvm_v4f32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>;
20 def int_AMDGPU_txq : Intrinsic<[llvm_v4f32_ty], [llvm_v4f32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>;
21 def int_AMDGPU_txd : Intrinsic<[llvm_v4f32_ty], [llvm_v4f32_ty, llvm_v4f32_ty, llvm_v4f32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>;
22 def int_AMDGPU_txl : Intrinsic<[llvm_v4f32_ty], [llvm_v4f32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>;
23 def int_AMDGPU_ddx : Intrinsic<[llvm_v4f32_ty], [llvm_v4f32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>;
24 def int_AMDGPU_ddy : Intrinsic<[llvm_v4f32_ty], [llvm_v4f32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>;
25}
26
Tom Stellard75aadc22012-12-11 21:25:42 +000027let TargetPrefix = "R600", isTarget = 1 in {
Matt Arsenault648e4222016-07-14 05:23:23 +000028 def int_R600_store_swizzle :
29 Intrinsic<[], [llvm_v4f32_ty, llvm_i32_ty, llvm_i32_ty], []>;
30 def int_R600_store_stream_output :
31 Intrinsic<[], [llvm_v4f32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], []>;
32} // End TargetPrefix = "R600", isTarget = 1
33
34let TargetPrefix = "r600", isTarget = 1 in {
Vincent Lejeuned3eed662013-05-17 16:50:20 +000035 class TextureIntrinsicFloatInput :
36 Intrinsic<[llvm_v4f32_ty], [
37 llvm_v4f32_ty, // Coord
38 llvm_i32_ty, // offset_x
39 llvm_i32_ty, // offset_y,
40 llvm_i32_ty, // offset_z,
41 llvm_i32_ty, // resource_id
42 llvm_i32_ty, // samplerid
43 llvm_i32_ty, // coord_type_x
44 llvm_i32_ty, // coord_type_y
45 llvm_i32_ty, // coord_type_z
46 llvm_i32_ty // coord_type_w
47 ], [IntrNoMem]>;
48 class TextureIntrinsicInt32Input :
49 Intrinsic<[llvm_v4i32_ty], [
50 llvm_v4i32_ty, // Coord
51 llvm_i32_ty, // offset_x
52 llvm_i32_ty, // offset_y,
53 llvm_i32_ty, // offset_z,
54 llvm_i32_ty, // resource_id
55 llvm_i32_ty, // samplerid
56 llvm_i32_ty, // coord_type_x
57 llvm_i32_ty, // coord_type_y
58 llvm_i32_ty, // coord_type_z
59 llvm_i32_ty // coord_type_w
60 ], [IntrNoMem]>;
61
Matt Arsenault59bd3012016-01-22 19:00:09 +000062
Matt Arsenault59bd3012016-01-22 19:00:09 +000063 def int_r600_tex : TextureIntrinsicFloatInput;
64 def int_r600_texc : TextureIntrinsicFloatInput;
65 def int_r600_txl : TextureIntrinsicFloatInput;
66 def int_r600_txlc : TextureIntrinsicFloatInput;
67 def int_r600_txb : TextureIntrinsicFloatInput;
68 def int_r600_txbc : TextureIntrinsicFloatInput;
69 def int_r600_txf : TextureIntrinsicInt32Input;
70 def int_r600_txq : TextureIntrinsicInt32Input;
71 def int_r600_ddx : TextureIntrinsicFloatInput;
72 def int_r600_ddy : TextureIntrinsicFloatInput;
Matt Arsenaultbee75752016-01-26 04:49:24 +000073} // End TargetPrefix = "r600", isTarget = 1