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Roman Lebedev7c423002018-06-15 14:01:35 +00001# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
Roman Lebedev680c43b2019-06-15 16:12:05 +00002# RUN: llvm-mca %s -mtriple=x86_64-unknown-unknown -mcpu=x86-64 -iterations=1 -all-stats=false -all-views=false -scheduler-stats < %s | FileCheck --check-prefixes=ALL,BARCELONA %s
Roman Lebedeva5baf862018-10-27 20:46:30 +00003# RUN: llvm-mca %s -mtriple=x86_64-unknown-unknown -mcpu=bdver2 -iterations=1 -all-stats=false -all-views=false -scheduler-stats < %s | FileCheck --check-prefixes=ALL,BDVER2 %s
Roman Lebedev7c423002018-06-15 14:01:35 +00004# RUN: llvm-mca %s -mtriple=x86_64-unknown-unknown -mcpu=btver2 -iterations=1 -all-stats=false -all-views=false -scheduler-stats < %s | FileCheck --check-prefixes=ALL,BTVER2 %s
5# RUN: llvm-mca %s -mtriple=x86_64-unknown-unknown -mcpu=znver1 -iterations=1 -all-stats=false -all-views=false -scheduler-stats < %s | FileCheck --check-prefixes=ALL,ZNVER1 %s
6# RUN: llvm-mca %s -mtriple=x86_64-unknown-unknown -mcpu=sandybridge -iterations=1 -all-stats=false -all-views=false -scheduler-stats < %s | FileCheck --check-prefixes=ALL,SNB %s
7# RUN: llvm-mca %s -mtriple=x86_64-unknown-unknown -mcpu=ivybridge -iterations=1 -all-stats=false -all-views=false -scheduler-stats < %s | FileCheck --check-prefixes=ALL,IVB %s
8# RUN: llvm-mca %s -mtriple=x86_64-unknown-unknown -mcpu=haswell -iterations=1 -all-stats=false -all-views=false -scheduler-stats < %s | FileCheck --check-prefixes=ALL,HSW %s
9# RUN: llvm-mca %s -mtriple=x86_64-unknown-unknown -mcpu=broadwell -iterations=1 -all-stats=false -all-views=false -scheduler-stats < %s | FileCheck --check-prefixes=ALL,BDW %s
10# RUN: llvm-mca %s -mtriple=x86_64-unknown-unknown -mcpu=knl -iterations=1 -all-stats=false -all-views=false -scheduler-stats < %s | FileCheck --check-prefixes=ALL,KNL %s
11# RUN: llvm-mca %s -mtriple=x86_64-unknown-unknown -mcpu=skylake -iterations=1 -all-stats=false -all-views=false -scheduler-stats < %s | FileCheck --check-prefixes=ALL,SKX %s
12# RUN: llvm-mca %s -mtriple=x86_64-unknown-unknown -mcpu=skylake-avx512 -iterations=1 -all-stats=false -all-views=false -scheduler-stats < %s | FileCheck --check-prefixes=ALL,SKX-AVX512 %s
13# RUN: llvm-mca %s -mtriple=x86_64-unknown-unknown -mcpu=slm -iterations=1 -all-stats=false -all-views=false -scheduler-stats < %s | FileCheck --check-prefixes=ALL,SLM %s
14
15xor %eax, %ebx
16
Andrea Di Biagiof6a60f12019-04-08 16:05:54 +000017# ALL: Schedulers - number of cycles where we saw N micro opcodes issued:
Roman Lebedev7c423002018-06-15 14:01:35 +000018# ALL-NEXT: [# issued], [# cycles]
19# ALL-NEXT: 0, 3 (75.0%)
20# ALL-NEXT: 1, 1 (25.0%)
21
Roman Lebedev680c43b2019-06-15 16:12:05 +000022# BARCELONA: Scheduler's queue usage:
23# BARCELONA-NEXT: [1] Resource name.
24# BARCELONA-NEXT: [2] Average number of used buffer entries.
25# BARCELONA-NEXT: [3] Maximum number of used buffer entries.
26# BARCELONA-NEXT: [4] Total number of buffer entries.
27
Roman Lebedeva5192182018-10-27 20:36:11 +000028# BDVER2: Scheduler's queue usage:
29# BDVER2-NEXT: [1] Resource name.
30# BDVER2-NEXT: [2] Average number of used buffer entries.
31# BDVER2-NEXT: [3] Maximum number of used buffer entries.
32# BDVER2-NEXT: [4] Total number of buffer entries.
33
Andrea Di Biagiob89b96c2018-08-27 14:52:52 +000034# BDW: Scheduler's queue usage:
35# BDW-NEXT: [1] Resource name.
36# BDW-NEXT: [2] Average number of used buffer entries.
37# BDW-NEXT: [3] Maximum number of used buffer entries.
38# BDW-NEXT: [4] Total number of buffer entries.
Roman Lebedev7c423002018-06-15 14:01:35 +000039
Andrea Di Biagiob89b96c2018-08-27 14:52:52 +000040# BTVER2: Scheduler's queue usage:
41# BTVER2-NEXT: [1] Resource name.
42# BTVER2-NEXT: [2] Average number of used buffer entries.
43# BTVER2-NEXT: [3] Maximum number of used buffer entries.
44# BTVER2-NEXT: [4] Total number of buffer entries.
45
46# HSW: Scheduler's queue usage:
47# HSW-NEXT: [1] Resource name.
48# HSW-NEXT: [2] Average number of used buffer entries.
49# HSW-NEXT: [3] Maximum number of used buffer entries.
50# HSW-NEXT: [4] Total number of buffer entries.
51
52# IVB: Scheduler's queue usage:
53# IVB-NEXT: [1] Resource name.
54# IVB-NEXT: [2] Average number of used buffer entries.
55# IVB-NEXT: [3] Maximum number of used buffer entries.
56# IVB-NEXT: [4] Total number of buffer entries.
57
58# KNL: Scheduler's queue usage:
59# KNL-NEXT: [1] Resource name.
60# KNL-NEXT: [2] Average number of used buffer entries.
61# KNL-NEXT: [3] Maximum number of used buffer entries.
62# KNL-NEXT: [4] Total number of buffer entries.
Roman Lebedev7c423002018-06-15 14:01:35 +000063
64# SKX: Scheduler's queue usage:
Andrea Di Biagiob89b96c2018-08-27 14:52:52 +000065# SKX-NEXT: [1] Resource name.
66# SKX-NEXT: [2] Average number of used buffer entries.
67# SKX-NEXT: [3] Maximum number of used buffer entries.
68# SKX-NEXT: [4] Total number of buffer entries.
Roman Lebedev7c423002018-06-15 14:01:35 +000069
70# SKX-AVX512: Scheduler's queue usage:
Andrea Di Biagiob89b96c2018-08-27 14:52:52 +000071# SKX-AVX512-NEXT: [1] Resource name.
72# SKX-AVX512-NEXT: [2] Average number of used buffer entries.
73# SKX-AVX512-NEXT: [3] Maximum number of used buffer entries.
74# SKX-AVX512-NEXT: [4] Total number of buffer entries.
75
Greg Bedwelldee7bfd2018-10-04 14:42:19 +000076# SLM: Scheduler's queue usage:
77# SLM-NEXT: No scheduler resources used.
78
Andrea Di Biagiob89b96c2018-08-27 14:52:52 +000079# SNB: Scheduler's queue usage:
80# SNB-NEXT: [1] Resource name.
81# SNB-NEXT: [2] Average number of used buffer entries.
82# SNB-NEXT: [3] Maximum number of used buffer entries.
83# SNB-NEXT: [4] Total number of buffer entries.
Roman Lebedev7c423002018-06-15 14:01:35 +000084
85# ZNVER1: Scheduler's queue usage:
Andrea Di Biagiob89b96c2018-08-27 14:52:52 +000086# ZNVER1-NEXT: [1] Resource name.
87# ZNVER1-NEXT: [2] Average number of used buffer entries.
88# ZNVER1-NEXT: [3] Maximum number of used buffer entries.
89# ZNVER1-NEXT: [4] Total number of buffer entries.
90
Roman Lebedev680c43b2019-06-15 16:12:05 +000091# BARCELONA: [1] [2] [3] [4]
92# BARCELONA-NEXT: SBPortAny 0 1 54
93
Roman Lebedeva5192182018-10-27 20:36:11 +000094# BDVER2: [1] [2] [3] [4]
Roman Lebedeva5baf862018-10-27 20:46:30 +000095# BDVER2-NEXT: PdEX 0 1 40
96# BDVER2-NEXT: PdFPU 0 0 64
97# BDVER2-NEXT: PdLoad 0 0 40
98# BDVER2-NEXT: PdStore 0 0 24
Roman Lebedeva5192182018-10-27 20:36:11 +000099
Andrea Di Biagiob89b96c2018-08-27 14:52:52 +0000100# BDW: [1] [2] [3] [4]
101# BDW-NEXT: BWPortAny 0 1 60
102
Andrea Di Biagiob89b96c2018-08-27 14:52:52 +0000103# BTVER2: [1] [2] [3] [4]
104# BTVER2-NEXT: JALU01 0 1 20
105# BTVER2-NEXT: JFPU01 0 0 18
106# BTVER2-NEXT: JLSAGU 0 0 12
107
Greg Bedwelldee7bfd2018-10-04 14:42:19 +0000108# HSW: [1] [2] [3] [4]
109# HSW-NEXT: HWPortAny 0 1 60
110
Andrea Di Biagiob89b96c2018-08-27 14:52:52 +0000111# IVB: [1] [2] [3] [4]
112# IVB-NEXT: SBPortAny 0 1 54
113
Greg Bedwelldee7bfd2018-10-04 14:42:19 +0000114# KNL: [1] [2] [3] [4]
115# KNL-NEXT: HWPortAny 0 1 60
Andrea Di Biagiob89b96c2018-08-27 14:52:52 +0000116
117# SKX: [1] [2] [3] [4]
118# SKX-NEXT: SKLPortAny 0 1 60
119
120# SKX-AVX512: [1] [2] [3] [4]
121# SKX-AVX512-NEXT: SKXPortAny 0 1 60
122
Greg Bedwelldee7bfd2018-10-04 14:42:19 +0000123# SNB: [1] [2] [3] [4]
124# SNB-NEXT: SBPortAny 0 1 54
125
Andrea Di Biagiob89b96c2018-08-27 14:52:52 +0000126# ZNVER1: [1] [2] [3] [4]
127# ZNVER1-NEXT: ZnAGU 0 0 28
128# ZNVER1-NEXT: ZnALU 0 1 56
129# ZNVER1-NEXT: ZnFPU 0 0 36