| Tom Stellard | 75aadc2 | 2012-12-11 21:25:42 +0000 | [diff] [blame] | 1 | //===-- AMDIL.td - AMDIL Tablegen files --*- tablegen -*-------------------===// |
| 2 | // |
| 3 | // The LLVM Compiler Infrastructure |
| 4 | // |
| 5 | // This file is distributed under the University of Illinois Open Source |
| 6 | // License. See LICENSE.TXT for details. |
| 7 | // |
| 8 | //==-----------------------------------------------------------------------===// |
| 9 | |
| 10 | // Include AMDIL TD files |
| 11 | include "AMDILBase.td" |
| 12 | |
| Tom Stellard | 9979277 | 2013-06-07 20:28:49 +0000 | [diff] [blame] | 13 | //===----------------------------------------------------------------------===// |
| 14 | // Subtarget Features |
| 15 | //===----------------------------------------------------------------------===// |
| 16 | |
| Tom Stellard | a6c6e1b | 2013-06-07 20:37:48 +0000 | [diff] [blame] | 17 | // Debugging Features |
| 18 | |
| 19 | def FeatureDumpCode : SubtargetFeature <"DumpCode", |
| 20 | "DumpCode", |
| 21 | "true", |
| 22 | "Dump MachineInstrs in the CodeEmitter">; |
| 23 | |
| Tom Stellard | ed0ceec | 2013-10-10 17:11:12 +0000 | [diff] [blame] | 24 | def FeatureIRStructurizer : SubtargetFeature <"EnableIRStructurizer", |
| 25 | "EnableIRStructurizer", |
| 26 | "true", |
| 27 | "Enable IR Structurizer">; |
| 28 | |
| Tom Stellard | a6c6e1b | 2013-06-07 20:37:48 +0000 | [diff] [blame] | 29 | // Target features |
| 30 | |
| Tom Stellard | 9979277 | 2013-06-07 20:28:49 +0000 | [diff] [blame] | 31 | def FeatureFP64 : SubtargetFeature<"fp64", |
| Tom Stellard | a6c6e1b | 2013-06-07 20:37:48 +0000 | [diff] [blame] | 32 | "FP64", |
| Tom Stellard | 9979277 | 2013-06-07 20:28:49 +0000 | [diff] [blame] | 33 | "true", |
| 34 | "Enable 64bit double precision operations">; |
| Tom Stellard | 9979277 | 2013-06-07 20:28:49 +0000 | [diff] [blame] | 35 | |
| 36 | def Feature64BitPtr : SubtargetFeature<"64BitPtr", |
| 37 | "Is64bit", |
| Tom Stellard | a6c6e1b | 2013-06-07 20:37:48 +0000 | [diff] [blame] | 38 | "true", |
| Tom Stellard | 9979277 | 2013-06-07 20:28:49 +0000 | [diff] [blame] | 39 | "Specify if 64bit addressing should be used.">; |
| 40 | |
| 41 | def Feature32on64BitPtr : SubtargetFeature<"64on32BitPtr", |
| 42 | "Is32on64bit", |
| 43 | "false", |
| 44 | "Specify if 64bit sized pointers with 32bit addressing should be used.">; |
| Tom Stellard | 9979277 | 2013-06-07 20:28:49 +0000 | [diff] [blame] | 45 | |
| 46 | def FeatureR600ALUInst : SubtargetFeature<"R600ALUInst", |
| 47 | "R600ALUInst", |
| 48 | "false", |
| 49 | "Older version of ALU instructions encoding.">; |
| 50 | |
| 51 | def FeatureVertexCache : SubtargetFeature<"HasVertexCache", |
| 52 | "HasVertexCache", |
| 53 | "true", |
| 54 | "Specify use of dedicated vertex cache.">; |
| 55 | |
| Tom Stellard | a6c6e1b | 2013-06-07 20:37:48 +0000 | [diff] [blame] | 56 | def FeatureCaymanISA : SubtargetFeature<"caymanISA", |
| 57 | "CaymanISA", |
| 58 | "true", |
| 59 | "Use Cayman ISA">; |
| 60 | |
| Tom Stellard | 3498e4f | 2013-06-07 20:28:55 +0000 | [diff] [blame] | 61 | class SubtargetFeatureFetchLimit <string Value> : |
| 62 | SubtargetFeature <"fetch"#Value, |
| 63 | "TexVTXClauseSize", |
| 64 | Value, |
| 65 | "Limit the maximum number of fetches in a clause to "#Value>; |
| Tom Stellard | 9979277 | 2013-06-07 20:28:49 +0000 | [diff] [blame] | 66 | |
| Tom Stellard | 3498e4f | 2013-06-07 20:28:55 +0000 | [diff] [blame] | 67 | def FeatureFetchLimit8 : SubtargetFeatureFetchLimit <"8">; |
| 68 | def FeatureFetchLimit16 : SubtargetFeatureFetchLimit <"16">; |
| 69 | |
| Tom Stellard | a6c6e1b | 2013-06-07 20:37:48 +0000 | [diff] [blame] | 70 | class SubtargetFeatureGeneration <string Value, |
| 71 | list<SubtargetFeature> Implies> : |
| 72 | SubtargetFeature <Value, "Gen", "AMDGPUSubtarget::"#Value, |
| 73 | Value#" GPU generation", Implies>; |
| 74 | |
| 75 | def FeatureR600 : SubtargetFeatureGeneration<"R600", |
| 76 | [FeatureR600ALUInst, FeatureFetchLimit8]>; |
| 77 | |
| 78 | def FeatureR700 : SubtargetFeatureGeneration<"R700", |
| 79 | [FeatureFetchLimit16]>; |
| 80 | |
| 81 | def FeatureEvergreen : SubtargetFeatureGeneration<"EVERGREEN", |
| 82 | [FeatureFetchLimit16]>; |
| 83 | |
| 84 | def FeatureNorthernIslands : SubtargetFeatureGeneration<"NORTHERN_ISLANDS", |
| 85 | [FeatureFetchLimit16]>; |
| 86 | |
| 87 | def FeatureSouthernIslands : SubtargetFeatureGeneration<"SOUTHERN_ISLANDS", |
| 88 | [Feature64BitPtr, FeatureFP64]>; |
| 89 | |
| Tom Stellard | 6e1ee47 | 2013-10-29 16:37:28 +0000 | [diff] [blame^] | 90 | def FeatureSeaIslands : SubtargetFeatureGeneration<"SEA_ISLANDS", |
| 91 | [Feature64BitPtr, FeatureFP64]>; |
| Tom Stellard | 3498e4f | 2013-06-07 20:28:55 +0000 | [diff] [blame] | 92 | //===----------------------------------------------------------------------===// |
| Tom Stellard | 75aadc2 | 2012-12-11 21:25:42 +0000 | [diff] [blame] | 93 | |
| 94 | def AMDGPUInstrInfo : InstrInfo { |
| 95 | let guessInstructionProperties = 1; |
| 96 | } |
| 97 | |
| 98 | //===----------------------------------------------------------------------===// |
| 99 | // Declare the target which we are implementing |
| 100 | //===----------------------------------------------------------------------===// |
| 101 | def AMDGPUAsmWriter : AsmWriter { |
| 102 | string AsmWriterClassName = "InstPrinter"; |
| 103 | int Variant = 0; |
| 104 | bit isMCAsmWriter = 1; |
| 105 | } |
| 106 | |
| 107 | def AMDGPU : Target { |
| 108 | // Pull in Instruction Info: |
| 109 | let InstructionSet = AMDGPUInstrInfo; |
| 110 | let AssemblyWriters = [AMDGPUAsmWriter]; |
| 111 | } |
| 112 | |
| 113 | // Include AMDGPU TD files |
| 114 | include "R600Schedule.td" |
| 115 | include "SISchedule.td" |
| 116 | include "Processors.td" |
| 117 | include "AMDGPUInstrInfo.td" |
| 118 | include "AMDGPUIntrinsics.td" |
| 119 | include "AMDGPURegisterInfo.td" |
| 120 | include "AMDGPUInstructions.td" |
| Christian Konig | 2c8f6d5 | 2013-03-07 09:03:52 +0000 | [diff] [blame] | 121 | include "AMDGPUCallingConv.td" |