blob: 1ba4160747be001f23ee563810d1d88d037f9e7d [file] [log] [blame]
Tom Stellard75aadc22012-12-11 21:25:42 +00001//===-- R600InstrInfo.h - R600 Instruction Info Interface -------*- C++ -*-===//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10/// \file
11/// \brief Interface definition for R600InstrInfo
12//
13//===----------------------------------------------------------------------===//
14
15#ifndef R600INSTRUCTIONINFO_H_
16#define R600INSTRUCTIONINFO_H_
17
Tom Stellard75aadc22012-12-11 21:25:42 +000018#include "AMDGPUInstrInfo.h"
19#include "R600Defines.h"
20#include "R600RegisterInfo.h"
Tom Stellard75aadc22012-12-11 21:25:42 +000021#include <map>
22
23namespace llvm {
24
25 class AMDGPUTargetMachine;
26 class DFAPacketizer;
27 class ScheduleDAG;
28 class MachineFunction;
29 class MachineInstr;
30 class MachineInstrBuilder;
31
32 class R600InstrInfo : public AMDGPUInstrInfo {
33 private:
34 const R600RegisterInfo RI;
Vincent Lejeunec2991642013-04-30 00:13:39 +000035 const AMDGPUSubtarget &ST;
Tom Stellard75aadc22012-12-11 21:25:42 +000036
37 int getBranchInstr(const MachineOperand &op) const;
Vincent Lejeune0fca91d2013-05-17 16:50:02 +000038 std::vector<std::pair<int, unsigned> >
Vincent Lejeunebb8a87212013-06-29 19:32:29 +000039 ExtractSrcs(MachineInstr *MI, const DenseMap<unsigned, unsigned> &PV, unsigned &ConstCount) const;
Tom Stellard75aadc22012-12-11 21:25:42 +000040
41 public:
Vincent Lejeune0fca91d2013-05-17 16:50:02 +000042 enum BankSwizzle {
Vincent Lejeunebb8a87212013-06-29 19:32:29 +000043 ALU_VEC_012_SCL_210 = 0,
44 ALU_VEC_021_SCL_122,
45 ALU_VEC_120_SCL_212,
46 ALU_VEC_102_SCL_221,
Vincent Lejeune0fca91d2013-05-17 16:50:02 +000047 ALU_VEC_201,
48 ALU_VEC_210
49 };
50
Tom Stellard75aadc22012-12-11 21:25:42 +000051 explicit R600InstrInfo(AMDGPUTargetMachine &tm);
52
53 const R600RegisterInfo &getRegisterInfo() const;
54 virtual void copyPhysReg(MachineBasicBlock &MBB,
55 MachineBasicBlock::iterator MI, DebugLoc DL,
56 unsigned DestReg, unsigned SrcReg,
57 bool KillSrc) const;
58
59 bool isTrig(const MachineInstr &MI) const;
60 bool isPlaceHolderOpcode(unsigned opcode) const;
61 bool isReductionOp(unsigned opcode) const;
62 bool isCubeOp(unsigned opcode) const;
63
64 /// \returns true if this \p Opcode represents an ALU instruction.
65 bool isALUInstr(unsigned Opcode) const;
Tom Stellardc026e8b2013-06-28 15:47:08 +000066 bool hasInstrModifiers(unsigned Opcode) const;
67 bool isLDSInstr(unsigned Opcode) const;
Tom Stellard75aadc22012-12-11 21:25:42 +000068
Vincent Lejeune076c0b22013-04-30 00:14:17 +000069 bool isTransOnly(unsigned Opcode) const;
70 bool isTransOnly(const MachineInstr *MI) const;
71
Vincent Lejeunec2991642013-04-30 00:13:39 +000072 bool usesVertexCache(unsigned Opcode) const;
73 bool usesVertexCache(const MachineInstr *MI) const;
74 bool usesTextureCache(unsigned Opcode) const;
75 bool usesTextureCache(const MachineInstr *MI) const;
76
Tom Stellardce540332013-06-28 15:46:59 +000077 bool mustBeLastInClause(unsigned Opcode) const;
78
Vincent Lejeune0fca91d2013-05-17 16:50:02 +000079 /// \returns a pair for each src of an ALU instructions.
80 /// The first member of a pair is the register id.
81 /// If register is ALU_CONST, second member is SEL.
82 /// If register is ALU_LITERAL, second member is IMM.
83 /// Otherwise, second member value is undefined.
84 SmallVector<std::pair<MachineOperand *, int64_t>, 3>
85 getSrcs(MachineInstr *MI) const;
86
Vincent Lejeune77a83522013-06-29 19:32:43 +000087 unsigned isLegalUpTo(
88 const std::vector<std::vector<std::pair<int, unsigned> > > &IGSrcs,
89 const std::vector<R600InstrInfo::BankSwizzle> &Swz,
90 const std::vector<std::pair<int, unsigned> > &TransSrcs,
91 R600InstrInfo::BankSwizzle TransSwz) const;
92
93 bool FindSwizzleForVectorSlot(
94 const std::vector<std::vector<std::pair<int, unsigned> > > &IGSrcs,
95 std::vector<R600InstrInfo::BankSwizzle> &SwzCandidate,
96 const std::vector<std::pair<int, unsigned> > &TransSrcs,
97 R600InstrInfo::BankSwizzle TransSwz) const;
Tom Stellardc026e8b2013-06-28 15:47:08 +000098
Vincent Lejeune0fca91d2013-05-17 16:50:02 +000099 /// Given the order VEC_012 < VEC_021 < VEC_120 < VEC_102 < VEC_201 < VEC_210
100 /// returns true and the first (in lexical order) BankSwizzle affectation
101 /// starting from the one already provided in the Instruction Group MIs that
102 /// fits Read Port limitations in BS if available. Otherwise returns false
103 /// and undefined content in BS.
Vincent Lejeune77a83522013-06-29 19:32:43 +0000104 /// isLastAluTrans should be set if the last Alu of MIs will be executed on
105 /// Trans ALU. In this case, ValidTSwizzle returns the BankSwizzle value to
106 /// apply to the last instruction.
Vincent Lejeune0fca91d2013-05-17 16:50:02 +0000107 /// PV holds GPR to PV registers in the Instruction Group MIs.
108 bool fitsReadPortLimitations(const std::vector<MachineInstr *> &MIs,
109 const DenseMap<unsigned, unsigned> &PV,
Vincent Lejeune77a83522013-06-29 19:32:43 +0000110 std::vector<BankSwizzle> &BS,
111 bool isLastAluTrans) const;
112
113 /// An instruction group can only access 2 channel pair (either [XY] or [ZW])
114 /// from KCache bank on R700+. This function check if MI set in input meet
115 /// this limitations
116 bool fitsConstReadLimitations(const std::vector<MachineInstr *> &) const;
117 /// Same but using const index set instead of MI set.
Vincent Lejeune0a22bc42013-03-14 15:50:45 +0000118 bool fitsConstReadLimitations(const std::vector<unsigned>&) const;
Vincent Lejeune0a22bc42013-03-14 15:50:45 +0000119
Tom Stellard75aadc22012-12-11 21:25:42 +0000120 /// \breif Vector instructions are instructions that must fill all
121 /// instruction slots within an instruction group.
122 bool isVector(const MachineInstr &MI) const;
123
124 virtual MachineInstr * getMovImmInstr(MachineFunction *MF, unsigned DstReg,
125 int64_t Imm) const;
126
127 virtual unsigned getIEQOpcode() const;
128 virtual bool isMov(unsigned Opcode) const;
129
130 DFAPacketizer *CreateTargetScheduleState(const TargetMachine *TM,
131 const ScheduleDAG *DAG) const;
132
133 bool ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const;
134
135 bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB,
136 SmallVectorImpl<MachineOperand> &Cond, bool AllowModify) const;
137
138 unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, const SmallVectorImpl<MachineOperand> &Cond, DebugLoc DL) const;
139
140 unsigned RemoveBranch(MachineBasicBlock &MBB) const;
141
142 bool isPredicated(const MachineInstr *MI) const;
143
144 bool isPredicable(MachineInstr *MI) const;
145
146 bool
147 isProfitableToDupForIfCvt(MachineBasicBlock &MBB, unsigned NumCyles,
148 const BranchProbability &Probability) const;
149
150 bool isProfitableToIfCvt(MachineBasicBlock &MBB, unsigned NumCyles,
151 unsigned ExtraPredCycles,
152 const BranchProbability &Probability) const ;
153
154 bool
155 isProfitableToIfCvt(MachineBasicBlock &TMBB,
156 unsigned NumTCycles, unsigned ExtraTCycles,
157 MachineBasicBlock &FMBB,
158 unsigned NumFCycles, unsigned ExtraFCycles,
159 const BranchProbability &Probability) const;
160
161 bool DefinesPredicate(MachineInstr *MI,
162 std::vector<MachineOperand> &Pred) const;
163
164 bool SubsumesPredicate(const SmallVectorImpl<MachineOperand> &Pred1,
165 const SmallVectorImpl<MachineOperand> &Pred2) const;
166
167 bool isProfitableToUnpredicate(MachineBasicBlock &TMBB,
168 MachineBasicBlock &FMBB) const;
169
170 bool PredicateInstruction(MachineInstr *MI,
171 const SmallVectorImpl<MachineOperand> &Pred) const;
172
173 unsigned int getInstrLatency(const InstrItineraryData *ItinData,
174 const MachineInstr *MI,
175 unsigned *PredCost = 0) const;
176
177 virtual int getInstrLatency(const InstrItineraryData *ItinData,
178 SDNode *Node) const { return 1;}
179
Tom Stellardf3b2a1e2013-02-06 17:32:29 +0000180 /// \returns a list of all the registers that may be accesed using indirect
181 /// addressing.
182 std::vector<unsigned> getIndirectReservedRegs(const MachineFunction &MF) const;
183
184 virtual int getIndirectIndexBegin(const MachineFunction &MF) const;
185
186 virtual int getIndirectIndexEnd(const MachineFunction &MF) const;
187
188
189 virtual unsigned calculateIndirectAddress(unsigned RegIndex,
190 unsigned Channel) const;
191
192 virtual const TargetRegisterClass *getIndirectAddrStoreRegClass(
193 unsigned SourceReg) const;
194
195 virtual const TargetRegisterClass *getIndirectAddrLoadRegClass() const;
196
197 virtual MachineInstrBuilder buildIndirectWrite(MachineBasicBlock *MBB,
198 MachineBasicBlock::iterator I,
199 unsigned ValueReg, unsigned Address,
200 unsigned OffsetReg) const;
201
202 virtual MachineInstrBuilder buildIndirectRead(MachineBasicBlock *MBB,
203 MachineBasicBlock::iterator I,
204 unsigned ValueReg, unsigned Address,
205 unsigned OffsetReg) const;
206
207 virtual const TargetRegisterClass *getSuperIndirectRegClass() const;
208
Vincent Lejeune80031d9f2013-04-03 16:49:34 +0000209 unsigned getMaxAlusPerClause() const;
Tom Stellardf3b2a1e2013-02-06 17:32:29 +0000210
211 ///buildDefaultInstruction - This function returns a MachineInstr with
212 /// all the instruction modifiers initialized to their default values.
Tom Stellard75aadc22012-12-11 21:25:42 +0000213 /// You can use this function to avoid manually specifying each instruction
214 /// modifier operand when building a new instruction.
215 ///
216 /// \returns a MachineInstr with all the instruction modifiers initialized
217 /// to their default values.
218 MachineInstrBuilder buildDefaultInstruction(MachineBasicBlock &MBB,
219 MachineBasicBlock::iterator I,
220 unsigned Opcode,
221 unsigned DstReg,
222 unsigned Src0Reg,
223 unsigned Src1Reg = 0) const;
224
Vincent Lejeune519f21e2013-05-17 16:50:32 +0000225 MachineInstr *buildSlotOfVectorInstruction(MachineBasicBlock &MBB,
226 MachineInstr *MI,
227 unsigned Slot,
228 unsigned DstReg) const;
229
Tom Stellard75aadc22012-12-11 21:25:42 +0000230 MachineInstr *buildMovImm(MachineBasicBlock &BB,
231 MachineBasicBlock::iterator I,
232 unsigned DstReg,
233 uint64_t Imm) const;
234
235 /// \brief Get the index of Op in the MachineInstr.
236 ///
237 /// \returns -1 if the Instruction does not contain the specified \p Op.
Tom Stellard02661d92013-06-25 21:22:18 +0000238 int getOperandIdx(const MachineInstr &MI, unsigned Op) const;
Tom Stellard75aadc22012-12-11 21:25:42 +0000239
240 /// \brief Get the index of \p Op for the given Opcode.
241 ///
242 /// \returns -1 if the Instruction does not contain the specified \p Op.
Tom Stellard02661d92013-06-25 21:22:18 +0000243 int getOperandIdx(unsigned Opcode, unsigned Op) const;
Tom Stellard75aadc22012-12-11 21:25:42 +0000244
245 /// \brief Helper function for setting instruction flag values.
Tom Stellard02661d92013-06-25 21:22:18 +0000246 void setImmOperand(MachineInstr *MI, unsigned Op, int64_t Imm) const;
Tom Stellard75aadc22012-12-11 21:25:42 +0000247
248 /// \returns true if this instruction has an operand for storing target flags.
249 bool hasFlagOperand(const MachineInstr &MI) const;
250
251 ///\brief Add one of the MO_FLAG* flags to the specified \p Operand.
252 void addFlag(MachineInstr *MI, unsigned Operand, unsigned Flag) const;
253
254 ///\brief Determine if the specified \p Flag is set on this \p Operand.
255 bool isFlagSet(const MachineInstr &MI, unsigned Operand, unsigned Flag) const;
256
257 /// \param SrcIdx The register source to set the flag on (e.g src0, src1, src2)
258 /// \param Flag The flag being set.
259 ///
260 /// \returns the operand containing the flags for this instruction.
261 MachineOperand &getFlagOp(MachineInstr *MI, unsigned SrcIdx = 0,
262 unsigned Flag = 0) const;
263
264 /// \brief Clear the specified flag on the instruction.
265 void clearFlag(MachineInstr *MI, unsigned Operand, unsigned Flag) const;
266};
267
268} // End llvm namespace
269
270#endif // R600INSTRINFO_H_