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gerrit-public.fairphone.software / toolchain / llvm-project / 79243d9664671d43eb2d688b3b1b30bf9a5a19b7 / . / llvm / test / CodeGen / R600 / add.ll
blob: 9bea9be8485f2d71d136d8cc0c959c5d4a4085b4 [file] [log] [blame]
Tom Stellard967bf582014-02-13 23:34:15 +0000[diff] [blame]1; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck --check-prefix=EG-CHECK --check-prefix=FUNC %s
2; RUN: llc < %s -march=r600 -mcpu=verde -verify-machineinstrs | FileCheck --check-prefix=SI-CHECK --check-prefix=FUNC %s
Tom Stellard75aadc22012-12-11 21:25:42 +0000[diff] [blame]3
Tom Stellard79243d92014-10-01 17:15:17 +0000[diff] [blame^]4;FUNC-LABEL: {{^}}test1:
Matt Arsenault44138782013-10-11 21:03:41 +0000[diff] [blame]5;EG-CHECK: ADD_INT {{[* ]*}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
6
Matt Arsenault72b31ee2013-11-12 02:35:51 +0000[diff] [blame]7;SI-CHECK: V_ADD_I32_e32 [[REG:v[0-9]+]], {{v[0-9]+, v[0-9]+}}
Matt Arsenault44138782013-10-11 21:03:41 +0000[diff] [blame]8;SI-CHECK-NOT: [[REG]]
9;SI-CHECK: BUFFER_STORE_DWORD [[REG]],
10define void @test1(i32 addrspace(1)* %out, i32 addrspace(1)* %in) {
11 %b_ptr = getelementptr i32 addrspace(1)* %in, i32 1
12 %a = load i32 addrspace(1)* %in
13 %b = load i32 addrspace(1)* %b_ptr
14 %result = add i32 %a, %b
15 store i32 %result, i32 addrspace(1)* %out
16 ret void
17}
18
Tom Stellard79243d92014-10-01 17:15:17 +0000[diff] [blame^]19;FUNC-LABEL: {{^}}test2:
Tom Stellard1e803092013-07-23 01:48:18 +0000[diff] [blame]20;EG-CHECK: ADD_INT {{[* ]*}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
21;EG-CHECK: ADD_INT {{[* ]*}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
Tom Stellard75aadc22012-12-11 21:25:42 +0000[diff] [blame]22
Matt Arsenault72b31ee2013-11-12 02:35:51 +0000[diff] [blame]23;SI-CHECK: V_ADD_I32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}}
24;SI-CHECK: V_ADD_I32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}}
Tom Stellard043795e2013-06-20 21:55:30 +0000[diff] [blame]25
26define void @test2(<2 x i32> addrspace(1)* %out, <2 x i32> addrspace(1)* %in) {
27 %b_ptr = getelementptr <2 x i32> addrspace(1)* %in, i32 1
Matt Arsenaultc15b8572013-10-11 21:03:39 +0000[diff] [blame]28 %a = load <2 x i32> addrspace(1)* %in
29 %b = load <2 x i32> addrspace(1)* %b_ptr
Tom Stellard043795e2013-06-20 21:55:30 +0000[diff] [blame]30 %result = add <2 x i32> %a, %b
31 store <2 x i32> %result, <2 x i32> addrspace(1)* %out
32 ret void
33}
34
Tom Stellard79243d92014-10-01 17:15:17 +0000[diff] [blame^]35;FUNC-LABEL: {{^}}test4:
Tom Stellard1e803092013-07-23 01:48:18 +0000[diff] [blame]36;EG-CHECK: ADD_INT {{[* ]*}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
37;EG-CHECK: ADD_INT {{[* ]*}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
38;EG-CHECK: ADD_INT {{[* ]*}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
39;EG-CHECK: ADD_INT {{[* ]*}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
Tom Stellard043795e2013-06-20 21:55:30 +0000[diff] [blame]40
Matt Arsenault72b31ee2013-11-12 02:35:51 +0000[diff] [blame]41;SI-CHECK: V_ADD_I32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}}
42;SI-CHECK: V_ADD_I32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}}
43;SI-CHECK: V_ADD_I32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}}
44;SI-CHECK: V_ADD_I32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}}
Tom Stellard043795e2013-06-20 21:55:30 +0000[diff] [blame]45
46define void @test4(<4 x i32> addrspace(1)* %out, <4 x i32> addrspace(1)* %in) {
Tom Stellard75aadc22012-12-11 21:25:42 +0000[diff] [blame]47 %b_ptr = getelementptr <4 x i32> addrspace(1)* %in, i32 1
Matt Arsenaultc15b8572013-10-11 21:03:39 +0000[diff] [blame]48 %a = load <4 x i32> addrspace(1)* %in
49 %b = load <4 x i32> addrspace(1)* %b_ptr
Tom Stellard75aadc22012-12-11 21:25:42 +0000[diff] [blame]50 %result = add <4 x i32> %a, %b
51 store <4 x i32> %result, <4 x i32> addrspace(1)* %out
52 ret void
53}
Tom Stellard967bf582014-02-13 23:34:15 +0000[diff] [blame]54
Tom Stellard79243d92014-10-01 17:15:17 +0000[diff] [blame^]55; FUNC-LABEL: {{^}}test8:
Tom Stellard967bf582014-02-13 23:34:15 +0000[diff] [blame]56; EG-CHECK: ADD_INT
57; EG-CHECK: ADD_INT
58; EG-CHECK: ADD_INT
59; EG-CHECK: ADD_INT
60; EG-CHECK: ADD_INT
61; EG-CHECK: ADD_INT
62; EG-CHECK: ADD_INT
63; EG-CHECK: ADD_INT
64; SI-CHECK: S_ADD_I32
65; SI-CHECK: S_ADD_I32
66; SI-CHECK: S_ADD_I32
67; SI-CHECK: S_ADD_I32
68; SI-CHECK: S_ADD_I32
69; SI-CHECK: S_ADD_I32
70; SI-CHECK: S_ADD_I32
71; SI-CHECK: S_ADD_I32
72define void @test8(<8 x i32> addrspace(1)* %out, <8 x i32> %a, <8 x i32> %b) {
73entry:
74 %0 = add <8 x i32> %a, %b
75 store <8 x i32> %0, <8 x i32> addrspace(1)* %out
76 ret void
77}
Tom Stellard1f15bff2014-02-25 21:36:18 +0000[diff] [blame]78
Tom Stellard79243d92014-10-01 17:15:17 +0000[diff] [blame^]79; FUNC-LABEL: {{^}}test16:
Tom Stellardd61a1c32014-02-28 21:36:37 +0000[diff] [blame]80; EG-CHECK: ADD_INT
81; EG-CHECK: ADD_INT
82; EG-CHECK: ADD_INT
83; EG-CHECK: ADD_INT
84; EG-CHECK: ADD_INT
85; EG-CHECK: ADD_INT
86; EG-CHECK: ADD_INT
87; EG-CHECK: ADD_INT
88; EG-CHECK: ADD_INT
89; EG-CHECK: ADD_INT
90; EG-CHECK: ADD_INT
91; EG-CHECK: ADD_INT
92; EG-CHECK: ADD_INT
93; EG-CHECK: ADD_INT
94; EG-CHECK: ADD_INT
95; EG-CHECK: ADD_INT
96; SI-CHECK: S_ADD_I32
97; SI-CHECK: S_ADD_I32
98; SI-CHECK: S_ADD_I32
99; SI-CHECK: S_ADD_I32
100; SI-CHECK: S_ADD_I32
101; SI-CHECK: S_ADD_I32
102; SI-CHECK: S_ADD_I32
103; SI-CHECK: S_ADD_I32
104; SI-CHECK: S_ADD_I32
105; SI-CHECK: S_ADD_I32
106; SI-CHECK: S_ADD_I32
107; SI-CHECK: S_ADD_I32
108; SI-CHECK: S_ADD_I32
109; SI-CHECK: S_ADD_I32
110; SI-CHECK: S_ADD_I32
111; SI-CHECK: S_ADD_I32
112define void @test16(<16 x i32> addrspace(1)* %out, <16 x i32> %a, <16 x i32> %b) {
113entry:
114 %0 = add <16 x i32> %a, %b
115 store <16 x i32> %0, <16 x i32> addrspace(1)* %out
116 ret void
117}
118
Tom Stellard79243d92014-10-01 17:15:17 +0000[diff] [blame^]119; FUNC-LABEL: {{^}}add64:
Tom Stellard80942a12014-09-05 14:07:59 +0000[diff] [blame]120; SI-CHECK: S_ADD_U32
Tom Stellard1f15bff2014-02-25 21:36:18 +0000[diff] [blame]121; SI-CHECK: S_ADDC_U32
122define void @add64(i64 addrspace(1)* %out, i64 %a, i64 %b) {
123entry:
124 %0 = add i64 %a, %b
125 store i64 %0, i64 addrspace(1)* %out
126 ret void
127}
Tom Stellarde28859f2014-03-07 20:12:39 +0000[diff] [blame]128
129; The V_ADDC_U32 and V_ADD_I32 instruction can't read SGPRs, because they
130; use VCC. The test is designed so that %a will be stored in an SGPR and
131; %0 will be stored in a VGPR, so the comiler will be forced to copy %a
132; to a VGPR before doing the add.
133
Tom Stellard79243d92014-10-01 17:15:17 +0000[diff] [blame^]134; FUNC-LABEL: {{^}}add64_sgpr_vgpr:
Tom Stellarde28859f2014-03-07 20:12:39 +0000[diff] [blame]135; SI-CHECK-NOT: V_ADDC_U32_e32 s
136define void @add64_sgpr_vgpr(i64 addrspace(1)* %out, i64 %a, i64 addrspace(1)* %in) {
137entry:
138 %0 = load i64 addrspace(1)* %in
139 %1 = add i64 %a, %0
140 store i64 %1, i64 addrspace(1)* %out
141 ret void
142}
Tom Stellard73b98ed2014-05-15 14:41:54 +0000[diff] [blame]143
Tom Stellard744b99b2014-09-24 01:33:28 +0000[diff] [blame]144; Test i64 add inside a branch.
Tom Stellard79243d92014-10-01 17:15:17 +0000[diff] [blame^]145; FUNC-LABEL: {{^}}add64_in_branch:
Tom Stellard744b99b2014-09-24 01:33:28 +0000[diff] [blame]146; SI-CHECK: S_ADD_U32
147; SI-CHECK: S_ADDC_U32
Tom Stellard73b98ed2014-05-15 14:41:54 +0000[diff] [blame]148define void @add64_in_branch(i64 addrspace(1)* %out, i64 addrspace(1)* %in, i64 %a, i64 %b, i64 %c) {
149entry:
150 %0 = icmp eq i64 %a, 0
151 br i1 %0, label %if, label %else
152
153if:
154 %1 = load i64 addrspace(1)* %in
155 br label %endif
156
157else:
158 %2 = add i64 %a, %b
159 br label %endif
160
161endif:
162 %3 = phi i64 [%1, %if], [%2, %else]
163 store i64 %3, i64 addrspace(1)* %out
164 ret void
165}