Blame - clang/lib/Headers/avx512vlintrin.h - toolchain/llvm-project

blob: 494e7be59109bc07ca1a205f4db559272a472e3f [file] [log] [blame]

Robert Khasanov	b9f3a91	2014-10-08 17:18:13 +0000	[diff] [blame]	1	/*===---- avx512vlintrin.h - AVX512VL intrinsics ---------------------------===
				2	*
				3	* Permission is hereby granted, free of charge, to any person obtaining a copy
				4	* of this software and associated documentation files (the "Software"), to deal
				5	* in the Software without restriction, including without limitation the rights
				6	* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
				7	* copies of the Software, and to permit persons to whom the Software is
				8	* furnished to do so, subject to the following conditions:
				9	*
				10	* The above copyright notice and this permission notice shall be included in
				11	* all copies or substantial portions of the Software.
				12	*
				13	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
				14	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
				15	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
				16	* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
				17	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
				18	* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
				19	* THE SOFTWARE.
				20	*
				21	*===-----------------------------------------------------------------------===
				22	*/
				23
				24	#ifndef __IMMINTRIN_H
				25	#error "Never use <avx512vlintrin.h> directly; include <immintrin.h> instead."
				26	#endif
				27
				28	#ifndef __AVX512VLINTRIN_H
				29	#define __AVX512VLINTRIN_H
				30
Michael Kuperstein	e45af54	2015-06-30 13:36:19 +0000	[diff] [blame]	31	#define __DEFAULT_FN_ATTRS __attribute__((__always_inline__, __nodebug__, __target__("avx512vl")))
Eric Christopher	99af5b2	2015-10-27 06:11:03 +0000	[diff] [blame]	32	#define __DEFAULT_FN_ATTRS_BOTH __attribute__((__always_inline__, __nodebug__, __target__("avx512vl, avx512bw")))
Eric Christopher	4d185168	2015-06-17 07:09:20 +0000	[diff] [blame]	33
Robert Khasanov	b9f3a91	2014-10-08 17:18:13 +0000	[diff] [blame]	34	/* Integer compare */
				35
Eric Christopher	99af5b2	2015-10-27 06:11:03 +0000	[diff] [blame]	36	static __inline__ __mmask8 __DEFAULT_FN_ATTRS_BOTH
Robert Khasanov	b9f3a91	2014-10-08 17:18:13 +0000	[diff] [blame]	37	_mm_cmpeq_epi32_mask(__m128i __a, __m128i __b) {
				38	return (__mmask8)__builtin_ia32_pcmpeqd128_mask((__v4si)__a, (__v4si)__b,
				39	(__mmask8)-1);
				40	}
				41
Eric Christopher	99af5b2	2015-10-27 06:11:03 +0000	[diff] [blame]	42	static __inline__ __mmask8 __DEFAULT_FN_ATTRS_BOTH
Robert Khasanov	b9f3a91	2014-10-08 17:18:13 +0000	[diff] [blame]	43	_mm_mask_cmpeq_epi32_mask(__mmask8 __u, __m128i __a, __m128i __b) {
				44	return (__mmask8)__builtin_ia32_pcmpeqd128_mask((__v4si)__a, (__v4si)__b,
				45	__u);
				46	}
				47
Michael Kuperstein	e45af54	2015-06-30 13:36:19 +0000	[diff] [blame]	48	static __inline__ __mmask8 __DEFAULT_FN_ATTRS
Craig Topper	2f25a5a	2015-01-26 08:11:49 +0000	[diff] [blame]	49	_mm_cmpeq_epu32_mask(__m128i __a, __m128i __b) {
				50	return (__mmask8)__builtin_ia32_ucmpd128_mask((__v4si)__a, (__v4si)__b, 0,
				51	(__mmask8)-1);
				52	}
				53
Michael Kuperstein	e45af54	2015-06-30 13:36:19 +0000	[diff] [blame]	54	static __inline__ __mmask8 __DEFAULT_FN_ATTRS
Craig Topper	2f25a5a	2015-01-26 08:11:49 +0000	[diff] [blame]	55	_mm_mask_cmpeq_epu32_mask(__mmask8 __u, __m128i __a, __m128i __b) {
				56	return (__mmask8)__builtin_ia32_ucmpd128_mask((__v4si)__a, (__v4si)__b, 0,
				57	__u);
				58	}
Robert Khasanov	b9f3a91	2014-10-08 17:18:13 +0000	[diff] [blame]	59
Eric Christopher	99af5b2	2015-10-27 06:11:03 +0000	[diff] [blame]	60	static __inline__ __mmask8 __DEFAULT_FN_ATTRS_BOTH
Robert Khasanov	b9f3a91	2014-10-08 17:18:13 +0000	[diff] [blame]	61	_mm256_cmpeq_epi32_mask(__m256i __a, __m256i __b) {
				62	return (__mmask8)__builtin_ia32_pcmpeqd256_mask((__v8si)__a, (__v8si)__b,
				63	(__mmask8)-1);
				64	}
				65
Eric Christopher	99af5b2	2015-10-27 06:11:03 +0000	[diff] [blame]	66	static __inline__ __mmask8 __DEFAULT_FN_ATTRS_BOTH
Robert Khasanov	b9f3a91	2014-10-08 17:18:13 +0000	[diff] [blame]	67	_mm256_mask_cmpeq_epi32_mask(__mmask8 __u, __m256i __a, __m256i __b) {
				68	return (__mmask8)__builtin_ia32_pcmpeqd256_mask((__v8si)__a, (__v8si)__b,
				69	__u);
				70	}
				71
Michael Kuperstein	e45af54	2015-06-30 13:36:19 +0000	[diff] [blame]	72	static __inline__ __mmask8 __DEFAULT_FN_ATTRS
Craig Topper	2f25a5a	2015-01-26 08:11:49 +0000	[diff] [blame]	73	_mm256_cmpeq_epu32_mask(__m256i __a, __m256i __b) {
				74	return (__mmask8)__builtin_ia32_ucmpd256_mask((__v8si)__a, (__v8si)__b, 0,
				75	(__mmask8)-1);
				76	}
				77
Michael Kuperstein	e45af54	2015-06-30 13:36:19 +0000	[diff] [blame]	78	static __inline__ __mmask8 __DEFAULT_FN_ATTRS
Craig Topper	2f25a5a	2015-01-26 08:11:49 +0000	[diff] [blame]	79	_mm256_mask_cmpeq_epu32_mask(__mmask8 __u, __m256i __a, __m256i __b) {
				80	return (__mmask8)__builtin_ia32_ucmpd256_mask((__v8si)__a, (__v8si)__b, 0,
				81	__u);
				82	}
				83
Eric Christopher	99af5b2	2015-10-27 06:11:03 +0000	[diff] [blame]	84	static __inline__ __mmask8 __DEFAULT_FN_ATTRS_BOTH
Robert Khasanov	b9f3a91	2014-10-08 17:18:13 +0000	[diff] [blame]	85	_mm_cmpeq_epi64_mask(__m128i __a, __m128i __b) {
				86	return (__mmask8)__builtin_ia32_pcmpeqq128_mask((__v2di)__a, (__v2di)__b,
				87	(__mmask8)-1);
				88	}
				89
Eric Christopher	99af5b2	2015-10-27 06:11:03 +0000	[diff] [blame]	90	static __inline__ __mmask8 __DEFAULT_FN_ATTRS_BOTH
Robert Khasanov	b9f3a91	2014-10-08 17:18:13 +0000	[diff] [blame]	91	_mm_mask_cmpeq_epi64_mask(__mmask8 __u, __m128i __a, __m128i __b) {
				92	return (__mmask8)__builtin_ia32_pcmpeqq128_mask((__v2di)__a, (__v2di)__b,
				93	__u);
				94	}
				95
Michael Kuperstein	e45af54	2015-06-30 13:36:19 +0000	[diff] [blame]	96	static __inline__ __mmask8 __DEFAULT_FN_ATTRS
Craig Topper	2f25a5a	2015-01-26 08:11:49 +0000	[diff] [blame]	97	_mm_cmpeq_epu64_mask(__m128i __a, __m128i __b) {
				98	return (__mmask8)__builtin_ia32_ucmpq128_mask((__v2di)__a, (__v2di)__b, 0,
				99	(__mmask8)-1);
				100	}
				101
Michael Kuperstein	e45af54	2015-06-30 13:36:19 +0000	[diff] [blame]	102	static __inline__ __mmask8 __DEFAULT_FN_ATTRS
Craig Topper	2f25a5a	2015-01-26 08:11:49 +0000	[diff] [blame]	103	_mm_mask_cmpeq_epu64_mask(__mmask8 __u, __m128i __a, __m128i __b) {
				104	return (__mmask8)__builtin_ia32_ucmpq128_mask((__v2di)__a, (__v2di)__b, 0,
				105	__u);
				106	}
Robert Khasanov	b9f3a91	2014-10-08 17:18:13 +0000	[diff] [blame]	107
Eric Christopher	99af5b2	2015-10-27 06:11:03 +0000	[diff] [blame]	108	static __inline__ __mmask8 __DEFAULT_FN_ATTRS_BOTH
Robert Khasanov	b9f3a91	2014-10-08 17:18:13 +0000	[diff] [blame]	109	_mm256_cmpeq_epi64_mask(__m256i __a, __m256i __b) {
				110	return (__mmask8)__builtin_ia32_pcmpeqq256_mask((__v4di)__a, (__v4di)__b,
				111	(__mmask8)-1);
				112	}
				113
Eric Christopher	99af5b2	2015-10-27 06:11:03 +0000	[diff] [blame]	114	static __inline__ __mmask8 __DEFAULT_FN_ATTRS_BOTH
Robert Khasanov	b9f3a91	2014-10-08 17:18:13 +0000	[diff] [blame]	115	_mm256_mask_cmpeq_epi64_mask(__mmask8 __u, __m256i __a, __m256i __b) {
				116	return (__mmask8)__builtin_ia32_pcmpeqq256_mask((__v4di)__a, (__v4di)__b,
				117	__u);
				118	}
				119
Michael Kuperstein	e45af54	2015-06-30 13:36:19 +0000	[diff] [blame]	120	static __inline__ __mmask8 __DEFAULT_FN_ATTRS
Craig Topper	2f25a5a	2015-01-26 08:11:49 +0000	[diff] [blame]	121	_mm256_cmpeq_epu64_mask(__m256i __a, __m256i __b) {
				122	return (__mmask8)__builtin_ia32_ucmpq256_mask((__v4di)__a, (__v4di)__b, 0,
				123	(__mmask8)-1);
				124	}
				125
Michael Kuperstein	e45af54	2015-06-30 13:36:19 +0000	[diff] [blame]	126	static __inline__ __mmask8 __DEFAULT_FN_ATTRS
Craig Topper	2f25a5a	2015-01-26 08:11:49 +0000	[diff] [blame]	127	_mm256_mask_cmpeq_epu64_mask(__mmask8 __u, __m256i __a, __m256i __b) {
				128	return (__mmask8)__builtin_ia32_ucmpq256_mask((__v4di)__a, (__v4di)__b, 0,
				129	__u);
				130	}
				131
				132
Michael Kuperstein	e45af54	2015-06-30 13:36:19 +0000	[diff] [blame]	133	static __inline__ __mmask8 __DEFAULT_FN_ATTRS
Craig Topper	2f25a5a	2015-01-26 08:11:49 +0000	[diff] [blame]	134	_mm_cmpge_epi32_mask(__m128i __a, __m128i __b) {
				135	return (__mmask8)__builtin_ia32_cmpd128_mask((__v4si)__a, (__v4si)__b, 5,
				136	(__mmask8)-1);
				137	}
				138
Michael Kuperstein	e45af54	2015-06-30 13:36:19 +0000	[diff] [blame]	139	static __inline__ __mmask8 __DEFAULT_FN_ATTRS
Craig Topper	2f25a5a	2015-01-26 08:11:49 +0000	[diff] [blame]	140	_mm_mask_cmpge_epi32_mask(__mmask8 __u, __m128i __a, __m128i __b) {
				141	return (__mmask8)__builtin_ia32_cmpd128_mask((__v4si)__a, (__v4si)__b, 5,
				142	__u);
				143	}
				144
Michael Kuperstein	e45af54	2015-06-30 13:36:19 +0000	[diff] [blame]	145	static __inline__ __mmask8 __DEFAULT_FN_ATTRS
Craig Topper	2f25a5a	2015-01-26 08:11:49 +0000	[diff] [blame]	146	_mm_cmpge_epu32_mask(__m128i __a, __m128i __b) {
				147	return (__mmask8)__builtin_ia32_ucmpd128_mask((__v4si)__a, (__v4si)__b, 5,
				148	(__mmask8)-1);
				149	}
				150
Michael Kuperstein	e45af54	2015-06-30 13:36:19 +0000	[diff] [blame]	151	static __inline__ __mmask8 __DEFAULT_FN_ATTRS
Craig Topper	2f25a5a	2015-01-26 08:11:49 +0000	[diff] [blame]	152	_mm_mask_cmpge_epu32_mask(__mmask8 __u, __m128i __a, __m128i __b) {
				153	return (__mmask8)__builtin_ia32_ucmpd128_mask((__v4si)__a, (__v4si)__b, 5,
				154	__u);
				155	}
				156
Michael Kuperstein	e45af54	2015-06-30 13:36:19 +0000	[diff] [blame]	157	static __inline__ __mmask8 __DEFAULT_FN_ATTRS
Craig Topper	2f25a5a	2015-01-26 08:11:49 +0000	[diff] [blame]	158	_mm256_cmpge_epi32_mask(__m256i __a, __m256i __b) {
				159	return (__mmask8)__builtin_ia32_cmpd256_mask((__v8si)__a, (__v8si)__b, 5,
				160	(__mmask8)-1);
				161	}
				162
Michael Kuperstein	e45af54	2015-06-30 13:36:19 +0000	[diff] [blame]	163	static __inline__ __mmask8 __DEFAULT_FN_ATTRS
Craig Topper	2f25a5a	2015-01-26 08:11:49 +0000	[diff] [blame]	164	_mm256_mask_cmpge_epi32_mask(__mmask8 __u, __m256i __a, __m256i __b) {
				165	return (__mmask8)__builtin_ia32_cmpd256_mask((__v8si)__a, (__v8si)__b, 5,
				166	__u);
				167	}
				168
Michael Kuperstein	e45af54	2015-06-30 13:36:19 +0000	[diff] [blame]	169	static __inline__ __mmask8 __DEFAULT_FN_ATTRS
Craig Topper	2f25a5a	2015-01-26 08:11:49 +0000	[diff] [blame]	170	_mm256_cmpge_epu32_mask(__m256i __a, __m256i __b) {
				171	return (__mmask8)__builtin_ia32_ucmpd256_mask((__v8si)__a, (__v8si)__b, 5,
				172	(__mmask8)-1);
				173	}
				174
Michael Kuperstein	e45af54	2015-06-30 13:36:19 +0000	[diff] [blame]	175	static __inline__ __mmask8 __DEFAULT_FN_ATTRS
Craig Topper	2f25a5a	2015-01-26 08:11:49 +0000	[diff] [blame]	176	_mm256_mask_cmpge_epu32_mask(__mmask8 __u, __m256i __a, __m256i __b) {
				177	return (__mmask8)__builtin_ia32_ucmpd256_mask((__v8si)__a, (__v8si)__b, 5,
				178	__u);
				179	}
				180
Michael Kuperstein	e45af54	2015-06-30 13:36:19 +0000	[diff] [blame]	181	static __inline__ __mmask8 __DEFAULT_FN_ATTRS
Craig Topper	2f25a5a	2015-01-26 08:11:49 +0000	[diff] [blame]	182	_mm_cmpge_epi64_mask(__m128i __a, __m128i __b) {
				183	return (__mmask8)__builtin_ia32_cmpq128_mask((__v2di)__a, (__v2di)__b, 5,
				184	(__mmask8)-1);
				185	}
				186
Michael Kuperstein	e45af54	2015-06-30 13:36:19 +0000	[diff] [blame]	187	static __inline__ __mmask8 __DEFAULT_FN_ATTRS
Craig Topper	2f25a5a	2015-01-26 08:11:49 +0000	[diff] [blame]	188	_mm_mask_cmpge_epi64_mask(__mmask8 __u, __m128i __a, __m128i __b) {
				189	return (__mmask8)__builtin_ia32_cmpq128_mask((__v2di)__a, (__v2di)__b, 5,
				190	__u);
				191	}
				192
Michael Kuperstein	e45af54	2015-06-30 13:36:19 +0000	[diff] [blame]	193	static __inline__ __mmask8 __DEFAULT_FN_ATTRS
Craig Topper	2f25a5a	2015-01-26 08:11:49 +0000	[diff] [blame]	194	_mm_cmpge_epu64_mask(__m128i __a, __m128i __b) {
				195	return (__mmask8)__builtin_ia32_ucmpq128_mask((__v2di)__a, (__v2di)__b, 5,
				196	(__mmask8)-1);
				197	}
				198
Michael Kuperstein	e45af54	2015-06-30 13:36:19 +0000	[diff] [blame]	199	static __inline__ __mmask8 __DEFAULT_FN_ATTRS
Craig Topper	2f25a5a	2015-01-26 08:11:49 +0000	[diff] [blame]	200	_mm_mask_cmpge_epu64_mask(__mmask8 __u, __m128i __a, __m128i __b) {
				201	return (__mmask8)__builtin_ia32_ucmpq128_mask((__v2di)__a, (__v2di)__b, 5,
				202	__u);
				203	}
				204
Michael Kuperstein	e45af54	2015-06-30 13:36:19 +0000	[diff] [blame]	205	static __inline__ __mmask8 __DEFAULT_FN_ATTRS
Craig Topper	2f25a5a	2015-01-26 08:11:49 +0000	[diff] [blame]	206	_mm256_cmpge_epi64_mask(__m256i __a, __m256i __b) {
				207	return (__mmask8)__builtin_ia32_cmpq256_mask((__v4di)__a, (__v4di)__b, 5,
				208	(__mmask8)-1);
				209	}
				210
Michael Kuperstein	e45af54	2015-06-30 13:36:19 +0000	[diff] [blame]	211	static __inline__ __mmask8 __DEFAULT_FN_ATTRS
Craig Topper	2f25a5a	2015-01-26 08:11:49 +0000	[diff] [blame]	212	_mm256_mask_cmpge_epi64_mask(__mmask8 __u, __m256i __a, __m256i __b) {
				213	return (__mmask8)__builtin_ia32_cmpq256_mask((__v4di)__a, (__v4di)__b, 5,
				214	__u);
				215	}
				216
Michael Kuperstein	e45af54	2015-06-30 13:36:19 +0000	[diff] [blame]	217	static __inline__ __mmask8 __DEFAULT_FN_ATTRS
Craig Topper	2f25a5a	2015-01-26 08:11:49 +0000	[diff] [blame]	218	_mm256_cmpge_epu64_mask(__m256i __a, __m256i __b) {
				219	return (__mmask8)__builtin_ia32_ucmpq256_mask((__v4di)__a, (__v4di)__b, 5,
				220	(__mmask8)-1);
				221	}
				222
Michael Kuperstein	e45af54	2015-06-30 13:36:19 +0000	[diff] [blame]	223	static __inline__ __mmask8 __DEFAULT_FN_ATTRS
Craig Topper	2f25a5a	2015-01-26 08:11:49 +0000	[diff] [blame]	224	_mm256_mask_cmpge_epu64_mask(__mmask8 __u, __m256i __a, __m256i __b) {
				225	return (__mmask8)__builtin_ia32_ucmpq256_mask((__v4di)__a, (__v4di)__b, 5,
				226	__u);
				227	}
				228
Eric Christopher	99af5b2	2015-10-27 06:11:03 +0000	[diff] [blame]	229	static __inline__ __mmask8 __DEFAULT_FN_ATTRS_BOTH
Craig Topper	2f25a5a	2015-01-26 08:11:49 +0000	[diff] [blame]	230	_mm_cmpgt_epi32_mask(__m128i __a, __m128i __b) {
				231	return (__mmask8)__builtin_ia32_pcmpgtd128_mask((__v4si)__a, (__v4si)__b,
				232	(__mmask8)-1);
				233	}
				234
Eric Christopher	99af5b2	2015-10-27 06:11:03 +0000	[diff] [blame]	235	static __inline__ __mmask8 __DEFAULT_FN_ATTRS_BOTH
Craig Topper	2f25a5a	2015-01-26 08:11:49 +0000	[diff] [blame]	236	_mm_mask_cmpgt_epi32_mask(__mmask8 __u, __m128i __a, __m128i __b) {
				237	return (__mmask8)__builtin_ia32_pcmpgtd128_mask((__v4si)__a, (__v4si)__b,
				238	__u);
				239	}
				240
Michael Kuperstein	e45af54	2015-06-30 13:36:19 +0000	[diff] [blame]	241	static __inline__ __mmask8 __DEFAULT_FN_ATTRS
Craig Topper	2f25a5a	2015-01-26 08:11:49 +0000	[diff] [blame]	242	_mm_cmpgt_epu32_mask(__m128i __a, __m128i __b) {
				243	return (__mmask8)__builtin_ia32_ucmpd128_mask((__v4si)__a, (__v4si)__b, 6,
				244	(__mmask8)-1);
				245	}
				246
Michael Kuperstein	e45af54	2015-06-30 13:36:19 +0000	[diff] [blame]	247	static __inline__ __mmask8 __DEFAULT_FN_ATTRS
Craig Topper	2f25a5a	2015-01-26 08:11:49 +0000	[diff] [blame]	248	_mm_mask_cmpgt_epu32_mask(__mmask8 __u, __m128i __a, __m128i __b) {
				249	return (__mmask8)__builtin_ia32_ucmpd128_mask((__v4si)__a, (__v4si)__b, 6,
				250	__u);
				251	}
				252
Eric Christopher	99af5b2	2015-10-27 06:11:03 +0000	[diff] [blame]	253	static __inline__ __mmask8 __DEFAULT_FN_ATTRS_BOTH
Craig Topper	2f25a5a	2015-01-26 08:11:49 +0000	[diff] [blame]	254	_mm256_cmpgt_epi32_mask(__m256i __a, __m256i __b) {
				255	return (__mmask8)__builtin_ia32_pcmpgtd256_mask((__v8si)__a, (__v8si)__b,
				256	(__mmask8)-1);
				257	}
				258
Eric Christopher	99af5b2	2015-10-27 06:11:03 +0000	[diff] [blame]	259	static __inline__ __mmask8 __DEFAULT_FN_ATTRS_BOTH
Craig Topper	2f25a5a	2015-01-26 08:11:49 +0000	[diff] [blame]	260	_mm256_mask_cmpgt_epi32_mask(__mmask8 __u, __m256i __a, __m256i __b) {
				261	return (__mmask8)__builtin_ia32_pcmpgtd256_mask((__v8si)__a, (__v8si)__b,
				262	__u);
				263	}
				264
Michael Kuperstein	e45af54	2015-06-30 13:36:19 +0000	[diff] [blame]	265	static __inline__ __mmask8 __DEFAULT_FN_ATTRS
Craig Topper	2f25a5a	2015-01-26 08:11:49 +0000	[diff] [blame]	266	_mm256_cmpgt_epu32_mask(__m256i __a, __m256i __b) {
				267	return (__mmask8)__builtin_ia32_ucmpd256_mask((__v8si)__a, (__v8si)__b, 6,
				268	(__mmask8)-1);
				269	}
				270
Michael Kuperstein	e45af54	2015-06-30 13:36:19 +0000	[diff] [blame]	271	static __inline__ __mmask8 __DEFAULT_FN_ATTRS
Craig Topper	2f25a5a	2015-01-26 08:11:49 +0000	[diff] [blame]	272	_mm256_mask_cmpgt_epu32_mask(__mmask8 __u, __m256i __a, __m256i __b) {
				273	return (__mmask8)__builtin_ia32_ucmpd256_mask((__v8si)__a, (__v8si)__b, 6,
				274	__u);
				275	}
				276
Eric Christopher	99af5b2	2015-10-27 06:11:03 +0000	[diff] [blame]	277	static __inline__ __mmask8 __DEFAULT_FN_ATTRS_BOTH
Craig Topper	2f25a5a	2015-01-26 08:11:49 +0000	[diff] [blame]	278	_mm_cmpgt_epi64_mask(__m128i __a, __m128i __b) {
				279	return (__mmask8)__builtin_ia32_pcmpgtq128_mask((__v2di)__a, (__v2di)__b,
				280	(__mmask8)-1);
				281	}
				282
Eric Christopher	99af5b2	2015-10-27 06:11:03 +0000	[diff] [blame]	283	static __inline__ __mmask8 __DEFAULT_FN_ATTRS_BOTH
Craig Topper	2f25a5a	2015-01-26 08:11:49 +0000	[diff] [blame]	284	_mm_mask_cmpgt_epi64_mask(__mmask8 __u, __m128i __a, __m128i __b) {
				285	return (__mmask8)__builtin_ia32_pcmpgtq128_mask((__v2di)__a, (__v2di)__b,
				286	__u);
				287	}
				288
Michael Kuperstein	e45af54	2015-06-30 13:36:19 +0000	[diff] [blame]	289	static __inline__ __mmask8 __DEFAULT_FN_ATTRS
Craig Topper	2f25a5a	2015-01-26 08:11:49 +0000	[diff] [blame]	290	_mm_cmpgt_epu64_mask(__m128i __a, __m128i __b) {
				291	return (__mmask8)__builtin_ia32_ucmpq128_mask((__v2di)__a, (__v2di)__b, 6,
				292	(__mmask8)-1);
				293	}
				294
Michael Kuperstein	e45af54	2015-06-30 13:36:19 +0000	[diff] [blame]	295	static __inline__ __mmask8 __DEFAULT_FN_ATTRS
Craig Topper	2f25a5a	2015-01-26 08:11:49 +0000	[diff] [blame]	296	_mm_mask_cmpgt_epu64_mask(__mmask8 __u, __m128i __a, __m128i __b) {
				297	return (__mmask8)__builtin_ia32_ucmpq128_mask((__v2di)__a, (__v2di)__b, 6,
				298	__u);
				299	}
				300
Eric Christopher	99af5b2	2015-10-27 06:11:03 +0000	[diff] [blame]	301	static __inline__ __mmask8 __DEFAULT_FN_ATTRS_BOTH
Craig Topper	2f25a5a	2015-01-26 08:11:49 +0000	[diff] [blame]	302	_mm256_cmpgt_epi64_mask(__m256i __a, __m256i __b) {
				303	return (__mmask8)__builtin_ia32_pcmpgtq256_mask((__v4di)__a, (__v4di)__b,
				304	(__mmask8)-1);
				305	}
				306
Eric Christopher	99af5b2	2015-10-27 06:11:03 +0000	[diff] [blame]	307	static __inline__ __mmask8 __DEFAULT_FN_ATTRS_BOTH
Craig Topper	2f25a5a	2015-01-26 08:11:49 +0000	[diff] [blame]	308	_mm256_mask_cmpgt_epi64_mask(__mmask8 __u, __m256i __a, __m256i __b) {
				309	return (__mmask8)__builtin_ia32_pcmpgtq256_mask((__v4di)__a, (__v4di)__b,
				310	__u);
				311	}
				312
Michael Kuperstein	e45af54	2015-06-30 13:36:19 +0000	[diff] [blame]	313	static __inline__ __mmask8 __DEFAULT_FN_ATTRS
Craig Topper	2f25a5a	2015-01-26 08:11:49 +0000	[diff] [blame]	314	_mm256_cmpgt_epu64_mask(__m256i __a, __m256i __b) {
				315	return (__mmask8)__builtin_ia32_ucmpq256_mask((__v4di)__a, (__v4di)__b, 6,
				316	(__mmask8)-1);
				317	}
				318
Michael Kuperstein	e45af54	2015-06-30 13:36:19 +0000	[diff] [blame]	319	static __inline__ __mmask8 __DEFAULT_FN_ATTRS
Craig Topper	2f25a5a	2015-01-26 08:11:49 +0000	[diff] [blame]	320	_mm256_mask_cmpgt_epu64_mask(__mmask8 __u, __m256i __a, __m256i __b) {
				321	return (__mmask8)__builtin_ia32_ucmpq256_mask((__v4di)__a, (__v4di)__b, 6,
				322	__u);
				323	}
				324
Michael Kuperstein	e45af54	2015-06-30 13:36:19 +0000	[diff] [blame]	325	static __inline__ __mmask8 __DEFAULT_FN_ATTRS
Craig Topper	2f25a5a	2015-01-26 08:11:49 +0000	[diff] [blame]	326	_mm_cmple_epi32_mask(__m128i __a, __m128i __b) {
				327	return (__mmask8)__builtin_ia32_cmpd128_mask((__v4si)__a, (__v4si)__b, 2,
				328	(__mmask8)-1);
				329	}
				330
Michael Kuperstein	e45af54	2015-06-30 13:36:19 +0000	[diff] [blame]	331	static __inline__ __mmask8 __DEFAULT_FN_ATTRS
Craig Topper	2f25a5a	2015-01-26 08:11:49 +0000	[diff] [blame]	332	_mm_mask_cmple_epi32_mask(__mmask8 __u, __m128i __a, __m128i __b) {
				333	return (__mmask8)__builtin_ia32_cmpd128_mask((__v4si)__a, (__v4si)__b, 2,
				334	__u);
				335	}
				336
Michael Kuperstein	e45af54	2015-06-30 13:36:19 +0000	[diff] [blame]	337	static __inline__ __mmask8 __DEFAULT_FN_ATTRS
Craig Topper	2f25a5a	2015-01-26 08:11:49 +0000	[diff] [blame]	338	_mm_cmple_epu32_mask(__m128i __a, __m128i __b) {
				339	return (__mmask8)__builtin_ia32_ucmpd128_mask((__v4si)__a, (__v4si)__b, 2,
				340	(__mmask8)-1);
				341	}
				342
Michael Kuperstein	e45af54	2015-06-30 13:36:19 +0000	[diff] [blame]	343	static __inline__ __mmask8 __DEFAULT_FN_ATTRS
Craig Topper	2f25a5a	2015-01-26 08:11:49 +0000	[diff] [blame]	344	_mm_mask_cmple_epu32_mask(__mmask8 __u, __m128i __a, __m128i __b) {
				345	return (__mmask8)__builtin_ia32_ucmpd128_mask((__v4si)__a, (__v4si)__b, 2,
				346	__u);
				347	}
				348
Michael Kuperstein	e45af54	2015-06-30 13:36:19 +0000	[diff] [blame]	349	static __inline__ __mmask8 __DEFAULT_FN_ATTRS
Craig Topper	2f25a5a	2015-01-26 08:11:49 +0000	[diff] [blame]	350	_mm256_cmple_epi32_mask(__m256i __a, __m256i __b) {
				351	return (__mmask8)__builtin_ia32_cmpd256_mask((__v8si)__a, (__v8si)__b, 2,
				352	(__mmask8)-1);
				353	}
				354
Michael Kuperstein	e45af54	2015-06-30 13:36:19 +0000	[diff] [blame]	355	static __inline__ __mmask8 __DEFAULT_FN_ATTRS
Craig Topper	2f25a5a	2015-01-26 08:11:49 +0000	[diff] [blame]	356	_mm256_mask_cmple_epi32_mask(__mmask8 __u, __m256i __a, __m256i __b) {
				357	return (__mmask8)__builtin_ia32_cmpd256_mask((__v8si)__a, (__v8si)__b, 2,
				358	__u);
				359	}
				360
Michael Kuperstein	e45af54	2015-06-30 13:36:19 +0000	[diff] [blame]	361	static __inline__ __mmask8 __DEFAULT_FN_ATTRS
Craig Topper	2f25a5a	2015-01-26 08:11:49 +0000	[diff] [blame]	362	_mm256_cmple_epu32_mask(__m256i __a, __m256i __b) {
				363	return (__mmask8)__builtin_ia32_ucmpd256_mask((__v8si)__a, (__v8si)__b, 2,
				364	(__mmask8)-1);
				365	}
				366
Michael Kuperstein	e45af54	2015-06-30 13:36:19 +0000	[diff] [blame]	367	static __inline__ __mmask8 __DEFAULT_FN_ATTRS
Craig Topper	2f25a5a	2015-01-26 08:11:49 +0000	[diff] [blame]	368	_mm256_mask_cmple_epu32_mask(__mmask8 __u, __m256i __a, __m256i __b) {
				369	return (__mmask8)__builtin_ia32_ucmpd256_mask((__v8si)__a, (__v8si)__b, 2,
				370	__u);
				371	}
				372
Michael Kuperstein	e45af54	2015-06-30 13:36:19 +0000	[diff] [blame]	373	static __inline__ __mmask8 __DEFAULT_FN_ATTRS
Craig Topper	2f25a5a	2015-01-26 08:11:49 +0000	[diff] [blame]	374	_mm_cmple_epi64_mask(__m128i __a, __m128i __b) {
				375	return (__mmask8)__builtin_ia32_cmpq128_mask((__v2di)__a, (__v2di)__b, 2,
				376	(__mmask8)-1);
				377	}
				378
Michael Kuperstein	e45af54	2015-06-30 13:36:19 +0000	[diff] [blame]	379	static __inline__ __mmask8 __DEFAULT_FN_ATTRS
Craig Topper	2f25a5a	2015-01-26 08:11:49 +0000	[diff] [blame]	380	_mm_mask_cmple_epi64_mask(__mmask8 __u, __m128i __a, __m128i __b) {
				381	return (__mmask8)__builtin_ia32_cmpq128_mask((__v2di)__a, (__v2di)__b, 2,
				382	__u);
				383	}
				384
Michael Kuperstein	e45af54	2015-06-30 13:36:19 +0000	[diff] [blame]	385	static __inline__ __mmask8 __DEFAULT_FN_ATTRS
Craig Topper	2f25a5a	2015-01-26 08:11:49 +0000	[diff] [blame]	386	_mm_cmple_epu64_mask(__m128i __a, __m128i __b) {
				387	return (__mmask8)__builtin_ia32_ucmpq128_mask((__v2di)__a, (__v2di)__b, 2,
				388	(__mmask8)-1);
				389	}
				390
Michael Kuperstein	e45af54	2015-06-30 13:36:19 +0000	[diff] [blame]	391	static __inline__ __mmask8 __DEFAULT_FN_ATTRS
Craig Topper	2f25a5a	2015-01-26 08:11:49 +0000	[diff] [blame]	392	_mm_mask_cmple_epu64_mask(__mmask8 __u, __m128i __a, __m128i __b) {
				393	return (__mmask8)__builtin_ia32_ucmpq128_mask((__v2di)__a, (__v2di)__b, 2,
				394	__u);
				395	}
				396
Michael Kuperstein	e45af54	2015-06-30 13:36:19 +0000	[diff] [blame]	397	static __inline__ __mmask8 __DEFAULT_FN_ATTRS
Craig Topper	2f25a5a	2015-01-26 08:11:49 +0000	[diff] [blame]	398	_mm256_cmple_epi64_mask(__m256i __a, __m256i __b) {
				399	return (__mmask8)__builtin_ia32_cmpq256_mask((__v4di)__a, (__v4di)__b, 2,
				400	(__mmask8)-1);
				401	}
				402
Michael Kuperstein	e45af54	2015-06-30 13:36:19 +0000	[diff] [blame]	403	static __inline__ __mmask8 __DEFAULT_FN_ATTRS
Craig Topper	2f25a5a	2015-01-26 08:11:49 +0000	[diff] [blame]	404	_mm256_mask_cmple_epi64_mask(__mmask8 __u, __m256i __a, __m256i __b) {
				405	return (__mmask8)__builtin_ia32_cmpq256_mask((__v4di)__a, (__v4di)__b, 2,
				406	__u);
				407	}
				408
Michael Kuperstein	e45af54	2015-06-30 13:36:19 +0000	[diff] [blame]	409	static __inline__ __mmask8 __DEFAULT_FN_ATTRS
Craig Topper	2f25a5a	2015-01-26 08:11:49 +0000	[diff] [blame]	410	_mm256_cmple_epu64_mask(__m256i __a, __m256i __b) {
				411	return (__mmask8)__builtin_ia32_ucmpq256_mask((__v4di)__a, (__v4di)__b, 2,
				412	(__mmask8)-1);
				413	}
				414
Michael Kuperstein	e45af54	2015-06-30 13:36:19 +0000	[diff] [blame]	415	static __inline__ __mmask8 __DEFAULT_FN_ATTRS
Craig Topper	2f25a5a	2015-01-26 08:11:49 +0000	[diff] [blame]	416	_mm256_mask_cmple_epu64_mask(__mmask8 __u, __m256i __a, __m256i __b) {
				417	return (__mmask8)__builtin_ia32_ucmpq256_mask((__v4di)__a, (__v4di)__b, 2,
				418	__u);
				419	}
				420
Michael Kuperstein	e45af54	2015-06-30 13:36:19 +0000	[diff] [blame]	421	static __inline__ __mmask8 __DEFAULT_FN_ATTRS
Craig Topper	2f25a5a	2015-01-26 08:11:49 +0000	[diff] [blame]	422	_mm_cmplt_epi32_mask(__m128i __a, __m128i __b) {
				423	return (__mmask8)__builtin_ia32_cmpd128_mask((__v4si)__a, (__v4si)__b, 1,
				424	(__mmask8)-1);
				425	}
				426
Michael Kuperstein	e45af54	2015-06-30 13:36:19 +0000	[diff] [blame]	427	static __inline__ __mmask8 __DEFAULT_FN_ATTRS
Craig Topper	2f25a5a	2015-01-26 08:11:49 +0000	[diff] [blame]	428	_mm_mask_cmplt_epi32_mask(__mmask8 __u, __m128i __a, __m128i __b) {
				429	return (__mmask8)__builtin_ia32_cmpd128_mask((__v4si)__a, (__v4si)__b, 1,
				430	__u);
				431	}
				432
Michael Kuperstein	e45af54	2015-06-30 13:36:19 +0000	[diff] [blame]	433	static __inline__ __mmask8 __DEFAULT_FN_ATTRS
Craig Topper	2f25a5a	2015-01-26 08:11:49 +0000	[diff] [blame]	434	_mm_cmplt_epu32_mask(__m128i __a, __m128i __b) {
				435	return (__mmask8)__builtin_ia32_ucmpd128_mask((__v4si)__a, (__v4si)__b, 1,
				436	(__mmask8)-1);
				437	}
				438
Michael Kuperstein	e45af54	2015-06-30 13:36:19 +0000	[diff] [blame]	439	static __inline__ __mmask8 __DEFAULT_FN_ATTRS
Craig Topper	2f25a5a	2015-01-26 08:11:49 +0000	[diff] [blame]	440	_mm_mask_cmplt_epu32_mask(__mmask8 __u, __m128i __a, __m128i __b) {
				441	return (__mmask8)__builtin_ia32_ucmpd128_mask((__v4si)__a, (__v4si)__b, 1,
				442	__u);
				443	}
				444
Michael Kuperstein	e45af54	2015-06-30 13:36:19 +0000	[diff] [blame]	445	static __inline__ __mmask8 __DEFAULT_FN_ATTRS
Craig Topper	2f25a5a	2015-01-26 08:11:49 +0000	[diff] [blame]	446	_mm256_cmplt_epi32_mask(__m256i __a, __m256i __b) {
				447	return (__mmask8)__builtin_ia32_cmpd256_mask((__v8si)__a, (__v8si)__b, 1,
				448	(__mmask8)-1);
				449	}
				450
Michael Kuperstein	e45af54	2015-06-30 13:36:19 +0000	[diff] [blame]	451	static __inline__ __mmask8 __DEFAULT_FN_ATTRS
Craig Topper	2f25a5a	2015-01-26 08:11:49 +0000	[diff] [blame]	452	_mm256_mask_cmplt_epi32_mask(__mmask8 __u, __m256i __a, __m256i __b) {
				453	return (__mmask8)__builtin_ia32_cmpd256_mask((__v8si)__a, (__v8si)__b, 1,
				454	__u);
				455	}
				456
Michael Kuperstein	e45af54	2015-06-30 13:36:19 +0000	[diff] [blame]	457	static __inline__ __mmask8 __DEFAULT_FN_ATTRS
Craig Topper	2f25a5a	2015-01-26 08:11:49 +0000	[diff] [blame]	458	_mm256_cmplt_epu32_mask(__m256i __a, __m256i __b) {
				459	return (__mmask8)__builtin_ia32_ucmpd256_mask((__v8si)__a, (__v8si)__b, 1,
				460	(__mmask8)-1);
				461	}
				462
Michael Kuperstein	e45af54	2015-06-30 13:36:19 +0000	[diff] [blame]	463	static __inline__ __mmask8 __DEFAULT_FN_ATTRS
Craig Topper	2f25a5a	2015-01-26 08:11:49 +0000	[diff] [blame]	464	_mm256_mask_cmplt_epu32_mask(__mmask8 __u, __m256i __a, __m256i __b) {
				465	return (__mmask8)__builtin_ia32_ucmpd256_mask((__v8si)__a, (__v8si)__b, 1,
				466	__u);
				467	}
				468
Michael Kuperstein	e45af54	2015-06-30 13:36:19 +0000	[diff] [blame]	469	static __inline__ __mmask8 __DEFAULT_FN_ATTRS
Craig Topper	2f25a5a	2015-01-26 08:11:49 +0000	[diff] [blame]	470	_mm_cmplt_epi64_mask(__m128i __a, __m128i __b) {
				471	return (__mmask8)__builtin_ia32_cmpq128_mask((__v2di)__a, (__v2di)__b, 1,
				472	(__mmask8)-1);
				473	}
				474
Michael Kuperstein	e45af54	2015-06-30 13:36:19 +0000	[diff] [blame]	475	static __inline__ __mmask8 __DEFAULT_FN_ATTRS
Craig Topper	2f25a5a	2015-01-26 08:11:49 +0000	[diff] [blame]	476	_mm_mask_cmplt_epi64_mask(__mmask8 __u, __m128i __a, __m128i __b) {
				477	return (__mmask8)__builtin_ia32_cmpq128_mask((__v2di)__a, (__v2di)__b, 1,
				478	__u);
				479	}
				480
Michael Kuperstein	e45af54	2015-06-30 13:36:19 +0000	[diff] [blame]	481	static __inline__ __mmask8 __DEFAULT_FN_ATTRS
Craig Topper	2f25a5a	2015-01-26 08:11:49 +0000	[diff] [blame]	482	_mm_cmplt_epu64_mask(__m128i __a, __m128i __b) {
				483	return (__mmask8)__builtin_ia32_ucmpq128_mask((__v2di)__a, (__v2di)__b, 1,
				484	(__mmask8)-1);
				485	}
				486
Michael Kuperstein	e45af54	2015-06-30 13:36:19 +0000	[diff] [blame]	487	static __inline__ __mmask8 __DEFAULT_FN_ATTRS
Craig Topper	2f25a5a	2015-01-26 08:11:49 +0000	[diff] [blame]	488	_mm_mask_cmplt_epu64_mask(__mmask8 __u, __m128i __a, __m128i __b) {
				489	return (__mmask8)__builtin_ia32_ucmpq128_mask((__v2di)__a, (__v2di)__b, 1,
				490	__u);
				491	}
				492
Michael Kuperstein	e45af54	2015-06-30 13:36:19 +0000	[diff] [blame]	493	static __inline__ __mmask8 __DEFAULT_FN_ATTRS
Craig Topper	2f25a5a	2015-01-26 08:11:49 +0000	[diff] [blame]	494	_mm256_cmplt_epi64_mask(__m256i __a, __m256i __b) {
				495	return (__mmask8)__builtin_ia32_cmpq256_mask((__v4di)__a, (__v4di)__b, 1,
				496	(__mmask8)-1);
				497	}
				498
Michael Kuperstein	e45af54	2015-06-30 13:36:19 +0000	[diff] [blame]	499	static __inline__ __mmask8 __DEFAULT_FN_ATTRS
Craig Topper	2f25a5a	2015-01-26 08:11:49 +0000	[diff] [blame]	500	_mm256_mask_cmplt_epi64_mask(__mmask8 __u, __m256i __a, __m256i __b) {
				501	return (__mmask8)__builtin_ia32_cmpq256_mask((__v4di)__a, (__v4di)__b, 1,
				502	__u);
				503	}
				504
Michael Kuperstein	e45af54	2015-06-30 13:36:19 +0000	[diff] [blame]	505	static __inline__ __mmask8 __DEFAULT_FN_ATTRS
Craig Topper	2f25a5a	2015-01-26 08:11:49 +0000	[diff] [blame]	506	_mm256_cmplt_epu64_mask(__m256i __a, __m256i __b) {
				507	return (__mmask8)__builtin_ia32_ucmpq256_mask((__v4di)__a, (__v4di)__b, 1,
				508	(__mmask8)-1);
				509	}
				510
Michael Kuperstein	e45af54	2015-06-30 13:36:19 +0000	[diff] [blame]	511	static __inline__ __mmask8 __DEFAULT_FN_ATTRS
Craig Topper	2f25a5a	2015-01-26 08:11:49 +0000	[diff] [blame]	512	_mm256_mask_cmplt_epu64_mask(__mmask8 __u, __m256i __a, __m256i __b) {
				513	return (__mmask8)__builtin_ia32_ucmpq256_mask((__v4di)__a, (__v4di)__b, 1,
				514	__u);
				515	}
				516
Michael Kuperstein	e45af54	2015-06-30 13:36:19 +0000	[diff] [blame]	517	static __inline__ __mmask8 __DEFAULT_FN_ATTRS
Craig Topper	2f25a5a	2015-01-26 08:11:49 +0000	[diff] [blame]	518	_mm_cmpneq_epi32_mask(__m128i __a, __m128i __b) {
				519	return (__mmask8)__builtin_ia32_cmpd128_mask((__v4si)__a, (__v4si)__b, 4,
				520	(__mmask8)-1);
				521	}
				522
Michael Kuperstein	e45af54	2015-06-30 13:36:19 +0000	[diff] [blame]	523	static __inline__ __mmask8 __DEFAULT_FN_ATTRS
Craig Topper	2f25a5a	2015-01-26 08:11:49 +0000	[diff] [blame]	524	_mm_mask_cmpneq_epi32_mask(__mmask8 __u, __m128i __a, __m128i __b) {
				525	return (__mmask8)__builtin_ia32_cmpd128_mask((__v4si)__a, (__v4si)__b, 4,
				526	__u);
				527	}
				528
Michael Kuperstein	e45af54	2015-06-30 13:36:19 +0000	[diff] [blame]	529	static __inline__ __mmask8 __DEFAULT_FN_ATTRS
Craig Topper	2f25a5a	2015-01-26 08:11:49 +0000	[diff] [blame]	530	_mm_cmpneq_epu32_mask(__m128i __a, __m128i __b) {
				531	return (__mmask8)__builtin_ia32_ucmpd128_mask((__v4si)__a, (__v4si)__b, 4,
				532	(__mmask8)-1);
				533	}
				534
Michael Kuperstein	e45af54	2015-06-30 13:36:19 +0000	[diff] [blame]	535	static __inline__ __mmask8 __DEFAULT_FN_ATTRS
Craig Topper	2f25a5a	2015-01-26 08:11:49 +0000	[diff] [blame]	536	_mm_mask_cmpneq_epu32_mask(__mmask8 __u, __m128i __a, __m128i __b) {
				537	return (__mmask8)__builtin_ia32_ucmpd128_mask((__v4si)__a, (__v4si)__b, 4,
				538	__u);
				539	}
				540
Michael Kuperstein	e45af54	2015-06-30 13:36:19 +0000	[diff] [blame]	541	static __inline__ __mmask8 __DEFAULT_FN_ATTRS
Craig Topper	2f25a5a	2015-01-26 08:11:49 +0000	[diff] [blame]	542	_mm256_cmpneq_epi32_mask(__m256i __a, __m256i __b) {
				543	return (__mmask8)__builtin_ia32_cmpd256_mask((__v8si)__a, (__v8si)__b, 4,
				544	(__mmask8)-1);
				545	}
				546
Michael Kuperstein	e45af54	2015-06-30 13:36:19 +0000	[diff] [blame]	547	static __inline__ __mmask8 __DEFAULT_FN_ATTRS
Craig Topper	2f25a5a	2015-01-26 08:11:49 +0000	[diff] [blame]	548	_mm256_mask_cmpneq_epi32_mask(__mmask8 __u, __m256i __a, __m256i __b) {
				549	return (__mmask8)__builtin_ia32_cmpd256_mask((__v8si)__a, (__v8si)__b, 4,
				550	__u);
				551	}
				552
Michael Kuperstein	e45af54	2015-06-30 13:36:19 +0000	[diff] [blame]	553	static __inline__ __mmask8 __DEFAULT_FN_ATTRS
Craig Topper	2f25a5a	2015-01-26 08:11:49 +0000	[diff] [blame]	554	_mm256_cmpneq_epu32_mask(__m256i __a, __m256i __b) {
				555	return (__mmask8)__builtin_ia32_ucmpd256_mask((__v8si)__a, (__v8si)__b, 4,
				556	(__mmask8)-1);
				557	}
				558
Michael Kuperstein	e45af54	2015-06-30 13:36:19 +0000	[diff] [blame]	559	static __inline__ __mmask8 __DEFAULT_FN_ATTRS
Craig Topper	2f25a5a	2015-01-26 08:11:49 +0000	[diff] [blame]	560	_mm256_mask_cmpneq_epu32_mask(__mmask8 __u, __m256i __a, __m256i __b) {
				561	return (__mmask8)__builtin_ia32_ucmpd256_mask((__v8si)__a, (__v8si)__b, 4,
				562	__u);
				563	}
				564
Michael Kuperstein	e45af54	2015-06-30 13:36:19 +0000	[diff] [blame]	565	static __inline__ __mmask8 __DEFAULT_FN_ATTRS
Craig Topper	2f25a5a	2015-01-26 08:11:49 +0000	[diff] [blame]	566	_mm_cmpneq_epi64_mask(__m128i __a, __m128i __b) {
				567	return (__mmask8)__builtin_ia32_cmpq128_mask((__v2di)__a, (__v2di)__b, 4,
				568	(__mmask8)-1);
				569	}
				570
Michael Kuperstein	e45af54	2015-06-30 13:36:19 +0000	[diff] [blame]	571	static __inline__ __mmask8 __DEFAULT_FN_ATTRS
Craig Topper	2f25a5a	2015-01-26 08:11:49 +0000	[diff] [blame]	572	_mm_mask_cmpneq_epi64_mask(__mmask8 __u, __m128i __a, __m128i __b) {
				573	return (__mmask8)__builtin_ia32_cmpq128_mask((__v2di)__a, (__v2di)__b, 4,
				574	__u);
				575	}
				576
Michael Kuperstein	e45af54	2015-06-30 13:36:19 +0000	[diff] [blame]	577	static __inline__ __mmask8 __DEFAULT_FN_ATTRS
Craig Topper	2f25a5a	2015-01-26 08:11:49 +0000	[diff] [blame]	578	_mm_cmpneq_epu64_mask(__m128i __a, __m128i __b) {
				579	return (__mmask8)__builtin_ia32_ucmpq128_mask((__v2di)__a, (__v2di)__b, 4,
				580	(__mmask8)-1);
				581	}
				582
Michael Kuperstein	e45af54	2015-06-30 13:36:19 +0000	[diff] [blame]	583	static __inline__ __mmask8 __DEFAULT_FN_ATTRS
Craig Topper	2f25a5a	2015-01-26 08:11:49 +0000	[diff] [blame]	584	_mm_mask_cmpneq_epu64_mask(__mmask8 __u, __m128i __a, __m128i __b) {
				585	return (__mmask8)__builtin_ia32_ucmpq128_mask((__v2di)__a, (__v2di)__b, 4,
				586	__u);
				587	}
				588
Michael Kuperstein	e45af54	2015-06-30 13:36:19 +0000	[diff] [blame]	589	static __inline__ __mmask8 __DEFAULT_FN_ATTRS
Craig Topper	2f25a5a	2015-01-26 08:11:49 +0000	[diff] [blame]	590	_mm256_cmpneq_epi64_mask(__m256i __a, __m256i __b) {
				591	return (__mmask8)__builtin_ia32_cmpq256_mask((__v4di)__a, (__v4di)__b, 4,
				592	(__mmask8)-1);
				593	}
				594
Michael Kuperstein	e45af54	2015-06-30 13:36:19 +0000	[diff] [blame]	595	static __inline__ __mmask8 __DEFAULT_FN_ATTRS
Craig Topper	2f25a5a	2015-01-26 08:11:49 +0000	[diff] [blame]	596	_mm256_mask_cmpneq_epi64_mask(__mmask8 __u, __m256i __a, __m256i __b) {
				597	return (__mmask8)__builtin_ia32_cmpq256_mask((__v4di)__a, (__v4di)__b, 4,
				598	__u);
				599	}
				600
Michael Kuperstein	e45af54	2015-06-30 13:36:19 +0000	[diff] [blame]	601	static __inline__ __mmask8 __DEFAULT_FN_ATTRS
Craig Topper	2f25a5a	2015-01-26 08:11:49 +0000	[diff] [blame]	602	_mm256_cmpneq_epu64_mask(__m256i __a, __m256i __b) {
				603	return (__mmask8)__builtin_ia32_ucmpq256_mask((__v4di)__a, (__v4di)__b, 4,
				604	(__mmask8)-1);
				605	}
				606
Michael Kuperstein	e45af54	2015-06-30 13:36:19 +0000	[diff] [blame]	607	static __inline__ __mmask8 __DEFAULT_FN_ATTRS
Craig Topper	2f25a5a	2015-01-26 08:11:49 +0000	[diff] [blame]	608	_mm256_mask_cmpneq_epu64_mask(__mmask8 __u, __m256i __a, __m256i __b) {
				609	return (__mmask8)__builtin_ia32_ucmpq256_mask((__v4di)__a, (__v4di)__b, 4,
				610	__u);
				611	}
				612
Michael Kuperstein	e45af54	2015-06-30 13:36:19 +0000	[diff] [blame]	613	static __inline__ __m256i __DEFAULT_FN_ATTRS
Elena Demikhovsky	35dc8c0	2015-04-28 13:28:01 +0000	[diff] [blame]	614	_mm256_mask_add_epi32 (__m256i __W, __mmask8 __U, __m256i __A,
				615	__m256i __B)
				616	{
				617	return (__m256i) __builtin_ia32_paddd256_mask ((__v8si) __A,
				618	(__v8si) __B,
				619	(__v8si) __W,
				620	(__mmask8) __U);
				621	}
				622
Michael Kuperstein	e45af54	2015-06-30 13:36:19 +0000	[diff] [blame]	623	static __inline__ __m256i __DEFAULT_FN_ATTRS
Elena Demikhovsky	35dc8c0	2015-04-28 13:28:01 +0000	[diff] [blame]	624	_mm256_maskz_add_epi32 (__mmask8 __U, __m256i __A, __m256i __B)
				625	{
				626	return (__m256i) __builtin_ia32_paddd256_mask ((__v8si) __A,
				627	(__v8si) __B,
				628	(__v8si)
				629	_mm256_setzero_si256 (),
				630	(__mmask8) __U);
				631	}
				632
Michael Kuperstein	e45af54	2015-06-30 13:36:19 +0000	[diff] [blame]	633	static __inline__ __m256i __DEFAULT_FN_ATTRS
Elena Demikhovsky	35dc8c0	2015-04-28 13:28:01 +0000	[diff] [blame]	634	_mm256_mask_add_epi64 (__m256i __W, __mmask8 __U, __m256i __A,
				635	__m256i __B)
				636	{
				637	return (__m256i) __builtin_ia32_paddq256_mask ((__v4di) __A,
				638	(__v4di) __B,
				639	(__v4di) __W,
				640	(__mmask8) __U);
				641	}
				642
Michael Kuperstein	e45af54	2015-06-30 13:36:19 +0000	[diff] [blame]	643	static __inline__ __m256i __DEFAULT_FN_ATTRS
Elena Demikhovsky	35dc8c0	2015-04-28 13:28:01 +0000	[diff] [blame]	644	_mm256_maskz_add_epi64 (__mmask8 __U, __m256i __A, __m256i __B)
				645	{
				646	return (__m256i) __builtin_ia32_paddq256_mask ((__v4di) __A,
				647	(__v4di) __B,
				648	(__v4di)
				649	_mm256_setzero_si256 (),
				650	(__mmask8) __U);
				651	}
				652
Michael Kuperstein	e45af54	2015-06-30 13:36:19 +0000	[diff] [blame]	653	static __inline__ __m256i __DEFAULT_FN_ATTRS
Elena Demikhovsky	35dc8c0	2015-04-28 13:28:01 +0000	[diff] [blame]	654	_mm256_mask_sub_epi32 (__m256i __W, __mmask8 __U, __m256i __A,
				655	__m256i __B)
				656	{
				657	return (__m256i) __builtin_ia32_psubd256_mask ((__v8si) __A,
				658	(__v8si) __B,
				659	(__v8si) __W,
				660	(__mmask8) __U);
				661	}
				662
Michael Kuperstein	e45af54	2015-06-30 13:36:19 +0000	[diff] [blame]	663	static __inline__ __m256i __DEFAULT_FN_ATTRS
Elena Demikhovsky	35dc8c0	2015-04-28 13:28:01 +0000	[diff] [blame]	664	_mm256_maskz_sub_epi32 (__mmask8 __U, __m256i __A, __m256i __B)
				665	{
				666	return (__m256i) __builtin_ia32_psubd256_mask ((__v8si) __A,
				667	(__v8si) __B,
				668	(__v8si)
				669	_mm256_setzero_si256 (),
				670	(__mmask8) __U);
				671	}
				672
Michael Kuperstein	e45af54	2015-06-30 13:36:19 +0000	[diff] [blame]	673	static __inline__ __m256i __DEFAULT_FN_ATTRS
Elena Demikhovsky	35dc8c0	2015-04-28 13:28:01 +0000	[diff] [blame]	674	_mm256_mask_sub_epi64 (__m256i __W, __mmask8 __U, __m256i __A,
				675	__m256i __B)
				676	{
				677	return (__m256i) __builtin_ia32_psubq256_mask ((__v4di) __A,
				678	(__v4di) __B,
				679	(__v4di) __W,
				680	(__mmask8) __U);
				681	}
				682
Michael Kuperstein	e45af54	2015-06-30 13:36:19 +0000	[diff] [blame]	683	static __inline__ __m256i __DEFAULT_FN_ATTRS
Elena Demikhovsky	35dc8c0	2015-04-28 13:28:01 +0000	[diff] [blame]	684	_mm256_maskz_sub_epi64 (__mmask8 __U, __m256i __A, __m256i __B)
				685	{
				686	return (__m256i) __builtin_ia32_psubq256_mask ((__v4di) __A,
				687	(__v4di) __B,
				688	(__v4di)
				689	_mm256_setzero_si256 (),
				690	(__mmask8) __U);
				691	}
				692
Michael Kuperstein	e45af54	2015-06-30 13:36:19 +0000	[diff] [blame]	693	static __inline__ __m128i __DEFAULT_FN_ATTRS
Elena Demikhovsky	35dc8c0	2015-04-28 13:28:01 +0000	[diff] [blame]	694	_mm_mask_add_epi32 (__m128i __W, __mmask8 __U, __m128i __A,
				695	__m128i __B)
				696	{
				697	return (__m128i) __builtin_ia32_paddd128_mask ((__v4si) __A,
				698	(__v4si) __B,
				699	(__v4si) __W,
				700	(__mmask8) __U);
				701	}
				702
Michael Kuperstein	e45af54	2015-06-30 13:36:19 +0000	[diff] [blame]	703	static __inline__ __m128i __DEFAULT_FN_ATTRS
Elena Demikhovsky	35dc8c0	2015-04-28 13:28:01 +0000	[diff] [blame]	704	_mm_maskz_add_epi32 (__mmask8 __U, __m128i __A, __m128i __B)
				705	{
				706	return (__m128i) __builtin_ia32_paddd128_mask ((__v4si) __A,
				707	(__v4si) __B,
				708	(__v4si)
				709	_mm_setzero_si128 (),
				710	(__mmask8) __U);
				711	}
				712
Michael Kuperstein	e45af54	2015-06-30 13:36:19 +0000	[diff] [blame]	713	static __inline__ __m128i __DEFAULT_FN_ATTRS
Elena Demikhovsky	35dc8c0	2015-04-28 13:28:01 +0000	[diff] [blame]	714	_mm_mask_add_epi64 (__m128i __W, __mmask8 __U, __m128i __A,
				715	__m128i __B)
				716	{
				717	return (__m128i) __builtin_ia32_paddq128_mask ((__v2di) __A,
				718	(__v2di) __B,
				719	(__v2di) __W,
				720	(__mmask8) __U);
				721	}
				722
Michael Kuperstein	e45af54	2015-06-30 13:36:19 +0000	[diff] [blame]	723	static __inline__ __m128i __DEFAULT_FN_ATTRS
Elena Demikhovsky	35dc8c0	2015-04-28 13:28:01 +0000	[diff] [blame]	724	_mm_maskz_add_epi64 (__mmask8 __U, __m128i __A, __m128i __B)
				725	{
				726	return (__m128i) __builtin_ia32_paddq128_mask ((__v2di) __A,
				727	(__v2di) __B,
				728	(__v2di)
				729	_mm_setzero_si128 (),
				730	(__mmask8) __U);
				731	}
				732
Michael Kuperstein	e45af54	2015-06-30 13:36:19 +0000	[diff] [blame]	733	static __inline__ __m128i __DEFAULT_FN_ATTRS
Elena Demikhovsky	35dc8c0	2015-04-28 13:28:01 +0000	[diff] [blame]	734	_mm_mask_sub_epi32 (__m128i __W, __mmask8 __U, __m128i __A,
				735	__m128i __B)
				736	{
				737	return (__m128i) __builtin_ia32_psubd128_mask ((__v4si) __A,
				738	(__v4si) __B,
				739	(__v4si) __W,
				740	(__mmask8) __U);
				741	}
				742
Michael Kuperstein	e45af54	2015-06-30 13:36:19 +0000	[diff] [blame]	743	static __inline__ __m128i __DEFAULT_FN_ATTRS
Elena Demikhovsky	35dc8c0	2015-04-28 13:28:01 +0000	[diff] [blame]	744	_mm_maskz_sub_epi32 (__mmask8 __U, __m128i __A, __m128i __B)
				745	{
				746	return (__m128i) __builtin_ia32_psubd128_mask ((__v4si) __A,
				747	(__v4si) __B,
				748	(__v4si)
				749	_mm_setzero_si128 (),
				750	(__mmask8) __U);
				751	}
				752
Michael Kuperstein	e45af54	2015-06-30 13:36:19 +0000	[diff] [blame]	753	static __inline__ __m128i __DEFAULT_FN_ATTRS
Elena Demikhovsky	35dc8c0	2015-04-28 13:28:01 +0000	[diff] [blame]	754	_mm_mask_sub_epi64 (__m128i __W, __mmask8 __U, __m128i __A,
				755	__m128i __B)
				756	{
				757	return (__m128i) __builtin_ia32_psubq128_mask ((__v2di) __A,
				758	(__v2di) __B,
				759	(__v2di) __W,
				760	(__mmask8) __U);
				761	}
				762
Michael Kuperstein	e45af54	2015-06-30 13:36:19 +0000	[diff] [blame]	763	static __inline__ __m128i __DEFAULT_FN_ATTRS
Elena Demikhovsky	35dc8c0	2015-04-28 13:28:01 +0000	[diff] [blame]	764	_mm_maskz_sub_epi64 (__mmask8 __U, __m128i __A, __m128i __B)
				765	{
				766	return (__m128i) __builtin_ia32_psubq128_mask ((__v2di) __A,
				767	(__v2di) __B,
				768	(__v2di)
				769	_mm_setzero_si128 (),
				770	(__mmask8) __U);
				771	}
				772
Michael Kuperstein	e45af54	2015-06-30 13:36:19 +0000	[diff] [blame]	773	static __inline__ __m256i __DEFAULT_FN_ATTRS
Elena Demikhovsky	35dc8c0	2015-04-28 13:28:01 +0000	[diff] [blame]	774	_mm256_mask_mul_epi32 (__m256i __W, __mmask8 __M, __m256i __X,
				775	__m256i __Y)
				776	{
				777	return (__m256i) __builtin_ia32_pmuldq256_mask ((__v8si) __X,
				778	(__v8si) __Y,
				779	(__v4di) __W, __M);
				780	}
				781
Michael Kuperstein	e45af54	2015-06-30 13:36:19 +0000	[diff] [blame]	782	static __inline__ __m256i __DEFAULT_FN_ATTRS
Elena Demikhovsky	35dc8c0	2015-04-28 13:28:01 +0000	[diff] [blame]	783	_mm256_maskz_mul_epi32 (__mmask8 __M, __m256i __X, __m256i __Y)
				784	{
				785	return (__m256i) __builtin_ia32_pmuldq256_mask ((__v8si) __X,
				786	(__v8si) __Y,
				787	(__v4di)
				788	_mm256_setzero_si256 (),
				789	__M);
				790	}
				791
Michael Kuperstein	e45af54	2015-06-30 13:36:19 +0000	[diff] [blame]	792	static __inline__ __m128i __DEFAULT_FN_ATTRS
Elena Demikhovsky	35dc8c0	2015-04-28 13:28:01 +0000	[diff] [blame]	793	_mm_mask_mul_epi32 (__m128i __W, __mmask8 __M, __m128i __X,
				794	__m128i __Y)
				795	{
				796	return (__m128i) __builtin_ia32_pmuldq128_mask ((__v4si) __X,
				797	(__v4si) __Y,
				798	(__v2di) __W, __M);
				799	}
				800
Michael Kuperstein	e45af54	2015-06-30 13:36:19 +0000	[diff] [blame]	801	static __inline__ __m128i __DEFAULT_FN_ATTRS
Elena Demikhovsky	35dc8c0	2015-04-28 13:28:01 +0000	[diff] [blame]	802	_mm_maskz_mul_epi32 (__mmask8 __M, __m128i __X, __m128i __Y)
				803	{
				804	return (__m128i) __builtin_ia32_pmuldq128_mask ((__v4si) __X,
				805	(__v4si) __Y,
				806	(__v2di)
				807	_mm_setzero_si128 (),
				808	__M);
				809	}
				810
Michael Kuperstein	e45af54	2015-06-30 13:36:19 +0000	[diff] [blame]	811	static __inline__ __m256i __DEFAULT_FN_ATTRS
Elena Demikhovsky	35dc8c0	2015-04-28 13:28:01 +0000	[diff] [blame]	812	_mm256_mask_mul_epu32 (__m256i __W, __mmask8 __M, __m256i __X,
				813	__m256i __Y)
				814	{
				815	return (__m256i) __builtin_ia32_pmuludq256_mask ((__v8si) __X,
				816	(__v8si) __Y,
				817	(__v4di) __W, __M);
				818	}
				819
Michael Kuperstein	e45af54	2015-06-30 13:36:19 +0000	[diff] [blame]	820	static __inline__ __m256i __DEFAULT_FN_ATTRS
Elena Demikhovsky	35dc8c0	2015-04-28 13:28:01 +0000	[diff] [blame]	821	_mm256_maskz_mul_epu32 (__mmask8 __M, __m256i __X, __m256i __Y)
				822	{
				823	return (__m256i) __builtin_ia32_pmuludq256_mask ((__v8si) __X,
				824	(__v8si) __Y,
				825	(__v4di)
				826	_mm256_setzero_si256 (),
				827	__M);
				828	}
				829
Michael Kuperstein	e45af54	2015-06-30 13:36:19 +0000	[diff] [blame]	830	static __inline__ __m128i __DEFAULT_FN_ATTRS
Elena Demikhovsky	35dc8c0	2015-04-28 13:28:01 +0000	[diff] [blame]	831	_mm_mask_mul_epu32 (__m128i __W, __mmask8 __M, __m128i __X,
				832	__m128i __Y)
				833	{
				834	return (__m128i) __builtin_ia32_pmuludq128_mask ((__v4si) __X,
				835	(__v4si) __Y,
				836	(__v2di) __W, __M);
				837	}
				838
Michael Kuperstein	e45af54	2015-06-30 13:36:19 +0000	[diff] [blame]	839	static __inline__ __m128i __DEFAULT_FN_ATTRS
Elena Demikhovsky	35dc8c0	2015-04-28 13:28:01 +0000	[diff] [blame]	840	_mm_maskz_mul_epu32 (__mmask8 __M, __m128i __X, __m128i __Y)
				841	{
				842	return (__m128i) __builtin_ia32_pmuludq128_mask ((__v4si) __X,
				843	(__v4si) __Y,
				844	(__v2di)
				845	_mm_setzero_si128 (),
				846	__M);
				847	}
				848
Michael Kuperstein	e45af54	2015-06-30 13:36:19 +0000	[diff] [blame]	849	static __inline__ __m256i __DEFAULT_FN_ATTRS
Elena Demikhovsky	35dc8c0	2015-04-28 13:28:01 +0000	[diff] [blame]	850	_mm256_maskz_mullo_epi32 (__mmask8 __M, __m256i __A, __m256i __B)
				851	{
				852	return (__m256i) __builtin_ia32_pmulld256_mask ((__v8si) __A,
				853	(__v8si) __B,
				854	(__v8si)
				855	_mm256_setzero_si256 (),
				856	__M);
				857	}
				858
Michael Kuperstein	e45af54	2015-06-30 13:36:19 +0000	[diff] [blame]	859	static __inline__ __m256i __DEFAULT_FN_ATTRS
Elena Demikhovsky	35dc8c0	2015-04-28 13:28:01 +0000	[diff] [blame]	860	_mm256_mask_mullo_epi32 (__m256i __W, __mmask8 __M, __m256i __A,
				861	__m256i __B)
				862	{
				863	return (__m256i) __builtin_ia32_pmulld256_mask ((__v8si) __A,
				864	(__v8si) __B,
				865	(__v8si) __W, __M);
				866	}
				867
Michael Kuperstein	e45af54	2015-06-30 13:36:19 +0000	[diff] [blame]	868	static __inline__ __m128i __DEFAULT_FN_ATTRS
Elena Demikhovsky	35dc8c0	2015-04-28 13:28:01 +0000	[diff] [blame]	869	_mm_maskz_mullo_epi32 (__mmask8 __M, __m128i __A, __m128i __B)
				870	{
				871	return (__m128i) __builtin_ia32_pmulld128_mask ((__v4si) __A,
				872	(__v4si) __B,
				873	(__v4si)
				874	_mm_setzero_si128 (),
				875	__M);
				876	}
				877
Michael Kuperstein	e45af54	2015-06-30 13:36:19 +0000	[diff] [blame]	878	static __inline__ __m128i __DEFAULT_FN_ATTRS
Elena Demikhovsky	35dc8c0	2015-04-28 13:28:01 +0000	[diff] [blame]	879	_mm_mask_mullo_epi32 (__m128i __W, __mmask16 __M, __m128i __A,
				880	__m128i __B)
				881	{
				882	return (__m128i) __builtin_ia32_pmulld128_mask ((__v4si) __A,
				883	(__v4si) __B,
				884	(__v4si) __W, __M);
				885	}
				886
Michael Kuperstein	e45af54	2015-06-30 13:36:19 +0000	[diff] [blame]	887	static __inline__ __m256i __DEFAULT_FN_ATTRS
Elena Demikhovsky	35dc8c0	2015-04-28 13:28:01 +0000	[diff] [blame]	888	_mm256_mask_and_epi32 (__m256i __W, __mmask8 __U, __m256i __A,
				889	__m256i __B)
				890	{
				891	return (__m256i) __builtin_ia32_pandd256_mask ((__v8si) __A,
				892	(__v8si) __B,
				893	(__v8si) __W,
				894	(__mmask8) __U);
				895	}
				896
Michael Kuperstein	e45af54	2015-06-30 13:36:19 +0000	[diff] [blame]	897	static __inline__ __m256i __DEFAULT_FN_ATTRS
Elena Demikhovsky	35dc8c0	2015-04-28 13:28:01 +0000	[diff] [blame]	898	_mm256_maskz_and_epi32 (__mmask8 __U, __m256i __A, __m256i __B)
				899	{
				900	return (__m256i) __builtin_ia32_pandd256_mask ((__v8si) __A,
				901	(__v8si) __B,
				902	(__v8si)
				903	_mm256_setzero_si256 (),
				904	(__mmask8) __U);
				905	}
				906
Michael Kuperstein	e45af54	2015-06-30 13:36:19 +0000	[diff] [blame]	907	static __inline__ __m128i __DEFAULT_FN_ATTRS
Elena Demikhovsky	35dc8c0	2015-04-28 13:28:01 +0000	[diff] [blame]	908	_mm_mask_and_epi32 (__m128i __W, __mmask8 __U, __m128i __A, __m128i __B)
				909	{
				910	return (__m128i) __builtin_ia32_pandd128_mask ((__v4si) __A,
				911	(__v4si) __B,
				912	(__v4si) __W,
				913	(__mmask8) __U);
				914	}
				915
Michael Kuperstein	e45af54	2015-06-30 13:36:19 +0000	[diff] [blame]	916	static __inline__ __m128i __DEFAULT_FN_ATTRS
Elena Demikhovsky	35dc8c0	2015-04-28 13:28:01 +0000	[diff] [blame]	917	_mm_maskz_and_epi32 (__mmask8 __U, __m128i __A, __m128i __B)
				918	{
				919	return (__m128i) __builtin_ia32_pandd128_mask ((__v4si) __A,
				920	(__v4si) __B,
				921	(__v4si)
				922	_mm_setzero_si128 (),
				923	(__mmask8) __U);
				924	}
				925
Michael Kuperstein	e45af54	2015-06-30 13:36:19 +0000	[diff] [blame]	926	static __inline__ __m256i __DEFAULT_FN_ATTRS
Elena Demikhovsky	35dc8c0	2015-04-28 13:28:01 +0000	[diff] [blame]	927	_mm256_mask_andnot_epi32 (__m256i __W, __mmask8 __U, __m256i __A,
				928	__m256i __B)
				929	{
				930	return (__m256i) __builtin_ia32_pandnd256_mask ((__v8si) __A,
				931	(__v8si) __B,
				932	(__v8si) __W,
				933	(__mmask8) __U);
				934	}
				935
Michael Kuperstein	e45af54	2015-06-30 13:36:19 +0000	[diff] [blame]	936	static __inline__ __m256i __DEFAULT_FN_ATTRS
Elena Demikhovsky	35dc8c0	2015-04-28 13:28:01 +0000	[diff] [blame]	937	_mm256_maskz_andnot_epi32 (__mmask8 __U, __m256i __A, __m256i __B)
				938	{
				939	return (__m256i) __builtin_ia32_pandnd256_mask ((__v8si) __A,
				940	(__v8si) __B,
				941	(__v8si)
				942	_mm256_setzero_si256 (),
				943	(__mmask8) __U);
				944	}
				945
Michael Kuperstein	e45af54	2015-06-30 13:36:19 +0000	[diff] [blame]	946	static __inline__ __m128i __DEFAULT_FN_ATTRS
Elena Demikhovsky	35dc8c0	2015-04-28 13:28:01 +0000	[diff] [blame]	947	_mm_mask_andnot_epi32 (__m128i __W, __mmask8 __U, __m128i __A,
				948	__m128i __B)
				949	{
				950	return (__m128i) __builtin_ia32_pandnd128_mask ((__v4si) __A,
				951	(__v4si) __B,
				952	(__v4si) __W,
				953	(__mmask8) __U);
				954	}
				955
Michael Kuperstein	e45af54	2015-06-30 13:36:19 +0000	[diff] [blame]	956	static __inline__ __m128i __DEFAULT_FN_ATTRS
Elena Demikhovsky	35dc8c0	2015-04-28 13:28:01 +0000	[diff] [blame]	957	_mm_maskz_andnot_epi32 (__mmask8 __U, __m128i __A, __m128i __B)
				958	{
				959	return (__m128i) __builtin_ia32_pandnd128_mask ((__v4si) __A,
				960	(__v4si) __B,
				961	(__v4si)
				962	_mm_setzero_si128 (),
				963	(__mmask8) __U);
				964	}
				965
Michael Kuperstein	e45af54	2015-06-30 13:36:19 +0000	[diff] [blame]	966	static __inline__ __m256i __DEFAULT_FN_ATTRS
Elena Demikhovsky	35dc8c0	2015-04-28 13:28:01 +0000	[diff] [blame]	967	_mm256_mask_or_epi32 (__m256i __W, __mmask8 __U, __m256i __A,
				968	__m256i __B)
				969	{
				970	return (__m256i) __builtin_ia32_pord256_mask ((__v8si) __A,
				971	(__v8si) __B,
				972	(__v8si) __W,
				973	(__mmask8) __U);
				974	}
				975
Michael Kuperstein	e45af54	2015-06-30 13:36:19 +0000	[diff] [blame]	976	static __inline__ __m256i __DEFAULT_FN_ATTRS
Elena Demikhovsky	35dc8c0	2015-04-28 13:28:01 +0000	[diff] [blame]	977	_mm256_maskz_or_epi32 (__mmask8 __U, __m256i __A, __m256i __B)
				978	{
				979	return (__m256i) __builtin_ia32_pord256_mask ((__v8si) __A,
				980	(__v8si) __B,
				981	(__v8si)
				982	_mm256_setzero_si256 (),
				983	(__mmask8) __U);
				984	}
				985
Michael Kuperstein	e45af54	2015-06-30 13:36:19 +0000	[diff] [blame]	986	static __inline__ __m128i __DEFAULT_FN_ATTRS
Elena Demikhovsky	35dc8c0	2015-04-28 13:28:01 +0000	[diff] [blame]	987	_mm_mask_or_epi32 (__m128i __W, __mmask8 __U, __m128i __A, __m128i __B)
				988	{
				989	return (__m128i) __builtin_ia32_pord128_mask ((__v4si) __A,
				990	(__v4si) __B,
				991	(__v4si) __W,
				992	(__mmask8) __U);
				993	}
				994
Michael Kuperstein	e45af54	2015-06-30 13:36:19 +0000	[diff] [blame]	995	static __inline__ __m128i __DEFAULT_FN_ATTRS
Elena Demikhovsky	35dc8c0	2015-04-28 13:28:01 +0000	[diff] [blame]	996	_mm_maskz_or_epi32 (__mmask8 __U, __m128i __A, __m128i __B)
				997	{
				998	return (__m128i) __builtin_ia32_pord128_mask ((__v4si) __A,
				999	(__v4si) __B,
				1000	(__v4si)
				1001	_mm_setzero_si128 (),
				1002	(__mmask8) __U);
				1003	}
				1004
Michael Kuperstein	e45af54	2015-06-30 13:36:19 +0000	[diff] [blame]	1005	static __inline__ __m256i __DEFAULT_FN_ATTRS
Elena Demikhovsky	35dc8c0	2015-04-28 13:28:01 +0000	[diff] [blame]	1006	_mm256_mask_xor_epi32 (__m256i __W, __mmask8 __U, __m256i __A,
				1007	__m256i __B)
				1008	{
				1009	return (__m256i) __builtin_ia32_pxord256_mask ((__v8si) __A,
				1010	(__v8si) __B,
				1011	(__v8si) __W,
				1012	(__mmask8) __U);
				1013	}
				1014
Michael Kuperstein	e45af54	2015-06-30 13:36:19 +0000	[diff] [blame]	1015	static __inline__ __m256i __DEFAULT_FN_ATTRS
Elena Demikhovsky	35dc8c0	2015-04-28 13:28:01 +0000	[diff] [blame]	1016	_mm256_maskz_xor_epi32 (__mmask8 __U, __m256i __A, __m256i __B)
				1017	{
				1018	return (__m256i) __builtin_ia32_pxord256_mask ((__v8si) __A,
				1019	(__v8si) __B,
				1020	(__v8si)
				1021	_mm256_setzero_si256 (),
				1022	(__mmask8) __U);
				1023	}
				1024
Michael Kuperstein	e45af54	2015-06-30 13:36:19 +0000	[diff] [blame]	1025	static __inline__ __m128i __DEFAULT_FN_ATTRS
Elena Demikhovsky	35dc8c0	2015-04-28 13:28:01 +0000	[diff] [blame]	1026	_mm_mask_xor_epi32 (__m128i __W, __mmask8 __U, __m128i __A,
				1027	__m128i __B)
				1028	{
				1029	return (__m128i) __builtin_ia32_pxord128_mask ((__v4si) __A,
				1030	(__v4si) __B,
				1031	(__v4si) __W,
				1032	(__mmask8) __U);
				1033	}
				1034
Michael Kuperstein	e45af54	2015-06-30 13:36:19 +0000	[diff] [blame]	1035	static __inline__ __m128i __DEFAULT_FN_ATTRS
Elena Demikhovsky	35dc8c0	2015-04-28 13:28:01 +0000	[diff] [blame]	1036	_mm_maskz_xor_epi32 (__mmask8 __U, __m128i __A, __m128i __B)
				1037	{
				1038	return (__m128i) __builtin_ia32_pxord128_mask ((__v4si) __A,
				1039	(__v4si) __B,
				1040	(__v4si)
				1041	_mm_setzero_si128 (),
				1042	(__mmask8) __U);
				1043	}
				1044
Michael Kuperstein	e45af54	2015-06-30 13:36:19 +0000	[diff] [blame]	1045	static __inline__ __m256i __DEFAULT_FN_ATTRS
Elena Demikhovsky	35dc8c0	2015-04-28 13:28:01 +0000	[diff] [blame]	1046	_mm256_mask_and_epi64 (__m256i __W, __mmask8 __U, __m256i __A,
				1047	__m256i __B)
				1048	{
				1049	return (__m256i) __builtin_ia32_pandq256_mask ((__v4di) __A,
				1050	(__v4di) __B,
				1051	(__v4di) __W, __U);
				1052	}
				1053
Michael Kuperstein	e45af54	2015-06-30 13:36:19 +0000	[diff] [blame]	1054	static __inline__ __m256i __DEFAULT_FN_ATTRS
Elena Demikhovsky	35dc8c0	2015-04-28 13:28:01 +0000	[diff] [blame]	1055	_mm256_maskz_and_epi64 (__mmask8 __U, __m256i __A, __m256i __B)
				1056	{
				1057	return (__m256i) __builtin_ia32_pandq256_mask ((__v4di) __A,
				1058	(__v4di) __B,
				1059	(__v4di)
				1060	_mm256_setzero_pd (),
				1061	__U);
				1062	}
				1063
Michael Kuperstein	e45af54	2015-06-30 13:36:19 +0000	[diff] [blame]	1064	static __inline__ __m128i __DEFAULT_FN_ATTRS
Elena Demikhovsky	35dc8c0	2015-04-28 13:28:01 +0000	[diff] [blame]	1065	_mm_mask_and_epi64 (__m128i __W, __mmask8 __U, __m128i __A,
				1066	__m128i __B)
				1067	{
				1068	return (__m128i) __builtin_ia32_pandq128_mask ((__v2di) __A,
				1069	(__v2di) __B,
				1070	(__v2di) __W, __U);
				1071	}
				1072
Michael Kuperstein	e45af54	2015-06-30 13:36:19 +0000	[diff] [blame]	1073	static __inline__ __m128i __DEFAULT_FN_ATTRS
Elena Demikhovsky	35dc8c0	2015-04-28 13:28:01 +0000	[diff] [blame]	1074	_mm_maskz_and_epi64 (__mmask8 __U, __m128i __A, __m128i __B)
				1075	{
				1076	return (__m128i) __builtin_ia32_pandq128_mask ((__v2di) __A,
				1077	(__v2di) __B,
				1078	(__v2di)
				1079	_mm_setzero_pd (),
				1080	__U);
				1081	}
				1082
Michael Kuperstein	e45af54	2015-06-30 13:36:19 +0000	[diff] [blame]	1083	static __inline__ __m256i __DEFAULT_FN_ATTRS
Elena Demikhovsky	35dc8c0	2015-04-28 13:28:01 +0000	[diff] [blame]	1084	_mm256_mask_andnot_epi64 (__m256i __W, __mmask8 __U, __m256i __A,
				1085	__m256i __B)
				1086	{
				1087	return (__m256i) __builtin_ia32_pandnq256_mask ((__v4di) __A,
				1088	(__v4di) __B,
				1089	(__v4di) __W, __U);
				1090	}
				1091
Michael Kuperstein	e45af54	2015-06-30 13:36:19 +0000	[diff] [blame]	1092	static __inline__ __m256i __DEFAULT_FN_ATTRS
Elena Demikhovsky	35dc8c0	2015-04-28 13:28:01 +0000	[diff] [blame]	1093	_mm256_maskz_andnot_epi64 (__mmask8 __U, __m256i __A, __m256i __B)
				1094	{
				1095	return (__m256i) __builtin_ia32_pandnq256_mask ((__v4di) __A,
				1096	(__v4di) __B,
				1097	(__v4di)
				1098	_mm256_setzero_pd (),
				1099	__U);
				1100	}
				1101
Michael Kuperstein	e45af54	2015-06-30 13:36:19 +0000	[diff] [blame]	1102	static __inline__ __m128i __DEFAULT_FN_ATTRS
Elena Demikhovsky	35dc8c0	2015-04-28 13:28:01 +0000	[diff] [blame]	1103	_mm_mask_andnot_epi64 (__m128i __W, __mmask8 __U, __m128i __A,
				1104	__m128i __B)
				1105	{
				1106	return (__m128i) __builtin_ia32_pandnq128_mask ((__v2di) __A,
				1107	(__v2di) __B,
				1108	(__v2di) __W, __U);
				1109	}
				1110
Michael Kuperstein	e45af54	2015-06-30 13:36:19 +0000	[diff] [blame]	1111	static __inline__ __m128i __DEFAULT_FN_ATTRS
Elena Demikhovsky	35dc8c0	2015-04-28 13:28:01 +0000	[diff] [blame]	1112	_mm_maskz_andnot_epi64 (__mmask8 __U, __m128i __A, __m128i __B)
				1113	{
				1114	return (__m128i) __builtin_ia32_pandnq128_mask ((__v2di) __A,
				1115	(__v2di) __B,
				1116	(__v2di)
				1117	_mm_setzero_pd (),
				1118	__U);
				1119	}
				1120
Michael Kuperstein	e45af54	2015-06-30 13:36:19 +0000	[diff] [blame]	1121	static __inline__ __m256i __DEFAULT_FN_ATTRS
Elena Demikhovsky	35dc8c0	2015-04-28 13:28:01 +0000	[diff] [blame]	1122	_mm256_mask_or_epi64 (__m256i __W, __mmask8 __U, __m256i __A,
				1123	__m256i __B)
				1124	{
				1125	return (__m256i) __builtin_ia32_porq256_mask ((__v4di) __A,
				1126	(__v4di) __B,
				1127	(__v4di) __W,
				1128	(__mmask8) __U);
				1129	}
				1130
Michael Kuperstein	e45af54	2015-06-30 13:36:19 +0000	[diff] [blame]	1131	static __inline__ __m256i __DEFAULT_FN_ATTRS
Elena Demikhovsky	35dc8c0	2015-04-28 13:28:01 +0000	[diff] [blame]	1132	_mm256_maskz_or_epi64 (__mmask8 __U, __m256i __A, __m256i __B)
				1133	{
				1134	return (__m256i) __builtin_ia32_porq256_mask ((__v4di) __A,
				1135	(__v4di) __B,
				1136	(__v4di)
				1137	_mm256_setzero_si256 (),
				1138	(__mmask8) __U);
				1139	}
				1140
Michael Kuperstein	e45af54	2015-06-30 13:36:19 +0000	[diff] [blame]	1141	static __inline__ __m128i __DEFAULT_FN_ATTRS
Elena Demikhovsky	35dc8c0	2015-04-28 13:28:01 +0000	[diff] [blame]	1142	_mm_mask_or_epi64 (__m128i __W, __mmask8 __U, __m128i __A, __m128i __B)
				1143	{
				1144	return (__m128i) __builtin_ia32_porq128_mask ((__v2di) __A,
				1145	(__v2di) __B,
				1146	(__v2di) __W,
				1147	(__mmask8) __U);
				1148	}
				1149
Michael Kuperstein	e45af54	2015-06-30 13:36:19 +0000	[diff] [blame]	1150	static __inline__ __m128i __DEFAULT_FN_ATTRS
Elena Demikhovsky	35dc8c0	2015-04-28 13:28:01 +0000	[diff] [blame]	1151	_mm_maskz_or_epi64 (__mmask8 __U, __m128i __A, __m128i __B)
				1152	{
				1153	return (__m128i) __builtin_ia32_porq128_mask ((__v2di) __A,
				1154	(__v2di) __B,
				1155	(__v2di)
				1156	_mm_setzero_si128 (),
				1157	(__mmask8) __U);
				1158	}
				1159
Michael Kuperstein	e45af54	2015-06-30 13:36:19 +0000	[diff] [blame]	1160	static __inline__ __m256i __DEFAULT_FN_ATTRS
Elena Demikhovsky	35dc8c0	2015-04-28 13:28:01 +0000	[diff] [blame]	1161	_mm256_mask_xor_epi64 (__m256i __W, __mmask8 __U, __m256i __A,
				1162	__m256i __B)
				1163	{
				1164	return (__m256i) __builtin_ia32_pxorq256_mask ((__v4di) __A,
				1165	(__v4di) __B,
				1166	(__v4di) __W,
				1167	(__mmask8) __U);
				1168	}
				1169
Michael Kuperstein	e45af54	2015-06-30 13:36:19 +0000	[diff] [blame]	1170	static __inline__ __m256i __DEFAULT_FN_ATTRS
Elena Demikhovsky	35dc8c0	2015-04-28 13:28:01 +0000	[diff] [blame]	1171	_mm256_maskz_xor_epi64 (__mmask8 __U, __m256i __A, __m256i __B)
				1172	{
				1173	return (__m256i) __builtin_ia32_pxorq256_mask ((__v4di) __A,
				1174	(__v4di) __B,
				1175	(__v4di)
				1176	_mm256_setzero_si256 (),
				1177	(__mmask8) __U);
				1178	}
				1179
Michael Kuperstein	e45af54	2015-06-30 13:36:19 +0000	[diff] [blame]	1180	static __inline__ __m128i __DEFAULT_FN_ATTRS
Elena Demikhovsky	35dc8c0	2015-04-28 13:28:01 +0000	[diff] [blame]	1181	_mm_mask_xor_epi64 (__m128i __W, __mmask8 __U, __m128i __A,
				1182	__m128i __B)
				1183	{
				1184	return (__m128i) __builtin_ia32_pxorq128_mask ((__v2di) __A,
				1185	(__v2di) __B,
				1186	(__v2di) __W,
				1187	(__mmask8) __U);
				1188	}
				1189
Michael Kuperstein	e45af54	2015-06-30 13:36:19 +0000	[diff] [blame]	1190	static __inline__ __m128i __DEFAULT_FN_ATTRS
Elena Demikhovsky	35dc8c0	2015-04-28 13:28:01 +0000	[diff] [blame]	1191	_mm_maskz_xor_epi64 (__mmask8 __U, __m128i __A, __m128i __B)
				1192	{
				1193	return (__m128i) __builtin_ia32_pxorq128_mask ((__v2di) __A,
				1194	(__v2di) __B,
				1195	(__v2di)
				1196	_mm_setzero_si128 (),
				1197	(__mmask8) __U);
				1198	}
				1199
Craig Topper	2f25a5a	2015-01-26 08:11:49 +0000	[diff] [blame]	1200	#define _mm_cmp_epi32_mask(a, b, p) __extension__ ({ \
				1201	(__mmask8)__builtin_ia32_cmpd128_mask((__v4si)(__m128i)(a), \
				1202	(__v4si)(__m128i)(b), \
				1203	(p), (__mmask8)-1); })
				1204
				1205	#define _mm_mask_cmp_epi32_mask(m, a, b, p) __extension__ ({ \
				1206	(__mmask8)__builtin_ia32_cmpd128_mask((__v4si)(__m128i)(a), \
				1207	(__v4si)(__m128i)(b), \
				1208	(p), (__mmask8)(m)); })
				1209
				1210	#define _mm_cmp_epu32_mask(a, b, p) __extension__ ({ \
				1211	(__mmask8)__builtin_ia32_ucmpd128_mask((__v4si)(__m128i)(a), \
				1212	(__v4si)(__m128i)(b), \
				1213	(p), (__mmask8)-1); })
				1214
				1215	#define _mm_mask_cmp_epu32_mask(m, a, b, p) __extension__ ({ \
				1216	(__mmask8)__builtin_ia32_ucmpd128_mask((__v4si)(__m128i)(a), \
				1217	(__v4si)(__m128i)(b), \
				1218	(p), (__mmask8)(m)); })
				1219
				1220	#define _mm256_cmp_epi32_mask(a, b, p) __extension__ ({ \
				1221	(__mmask8)__builtin_ia32_cmpd256_mask((__v8si)(__m256i)(a), \
				1222	(__v8si)(__m256i)(b), \
				1223	(p), (__mmask8)-1); })
				1224
				1225	#define _mm256_mask_cmp_epi32_mask(m, a, b, p) __extension__ ({ \
				1226	(__mmask8)__builtin_ia32_cmpd256_mask((__v8si)(__m256i)(a), \
				1227	(__v8si)(__m256i)(b), \
				1228	(p), (__mmask8)(m)); })
				1229
				1230	#define _mm256_cmp_epu32_mask(a, b, p) __extension__ ({ \
				1231	(__mmask8)__builtin_ia32_ucmpd256_mask((__v8si)(__m256i)(a), \
				1232	(__v8si)(__m256i)(b), \
				1233	(p), (__mmask8)-1); })
				1234
				1235	#define _mm256_mask_cmp_epu32_mask(m, a, b, p) __extension__ ({ \
				1236	(__mmask8)__builtin_ia32_ucmpd256_mask((__v8si)(__m256i)(a), \
				1237	(__v8si)(__m256i)(b), \
				1238	(p), (__mmask8)(m)); })
				1239
				1240	#define _mm_cmp_epi64_mask(a, b, p) __extension__ ({ \
				1241	(__mmask8)__builtin_ia32_cmpq128_mask((__v2di)(__m128i)(a), \
				1242	(__v2di)(__m128i)(b), \
				1243	(p), (__mmask8)-1); })
				1244
				1245	#define _mm_mask_cmp_epi64_mask(m, a, b, p) __extension__ ({ \
				1246	(__mmask8)__builtin_ia32_cmpq128_mask((__v2di)(__m128i)(a), \
				1247	(__v2di)(__m128i)(b), \
				1248	(p), (__mmask8)(m)); })
				1249
				1250	#define _mm_cmp_epu64_mask(a, b, p) __extension__ ({ \
				1251	(__mmask8)__builtin_ia32_ucmpq128_mask((__v2di)(__m128i)(a), \
				1252	(__v2di)(__m128i)(b), \
				1253	(p), (__mmask8)-1); })
				1254
				1255	#define _mm_mask_cmp_epu64_mask(m, a, b, p) __extension__ ({ \
				1256	(__mmask8)__builtin_ia32_ucmpq128_mask((__v2di)(__m128i)(a), \
				1257	(__v2di)(__m128i)(b), \
				1258	(p), (__mmask8)(m)); })
				1259
				1260	#define _mm256_cmp_epi64_mask(a, b, p) __extension__ ({ \
				1261	(__mmask8)__builtin_ia32_cmpq256_mask((__v4di)(__m256i)(a), \
				1262	(__v4di)(__m256i)(b), \
				1263	(p), (__mmask8)-1); })
				1264
				1265	#define _mm256_mask_cmp_epi64_mask(m, a, b, p) __extension__ ({ \
				1266	(__mmask8)__builtin_ia32_cmpq256_mask((__v4di)(__m256i)(a), \
				1267	(__v4di)(__m256i)(b), \
				1268	(p), (__mmask8)(m)); })
				1269
				1270	#define _mm256_cmp_epu64_mask(a, b, p) __extension__ ({ \
				1271	(__mmask8)__builtin_ia32_ucmpq256_mask((__v4di)(__m256i)(a), \
				1272	(__v4di)(__m256i)(b), \
				1273	(p), (__mmask8)-1); })
				1274
				1275	#define _mm256_mask_cmp_epu64_mask(m, a, b, p) __extension__ ({ \
				1276	(__mmask8)__builtin_ia32_ucmpq256_mask((__v4di)(__m256i)(a), \
				1277	(__v4di)(__m256i)(b), \
				1278	(p), (__mmask8)(m)); })
				1279
Elena Demikhovsky	bd5c8b9	2015-05-07 11:26:36 +0000	[diff] [blame]	1280	#define _mm256_cmp_ps_mask(a, b, p) __extension__ ({ \
				1281	(__mmask8)__builtin_ia32_cmpps256_mask((__v8sf)(__m256)(a), \
				1282	(__v8sf)(__m256)(b), \
				1283	(p), (__mmask8)-1); })
				1284
				1285	#define _mm256_mask_cmp_ps_mask(m, a, b, p) __extension__ ({ \
				1286	(__mmask8)__builtin_ia32_cmpps256_mask((__v8sf)(__m256)(a), \
				1287	(__v8sf)(__m256)(b), \
				1288	(p), (__mmask8)(m)); })
				1289
				1290	#define _mm256_cmp_pd_mask(a, b, p) __extension__ ({ \
				1291	(__mmask8)__builtin_ia32_cmppd256_mask((__v4df)(__m256)(a), \
				1292	(__v4df)(__m256)(b), \
				1293	(p), (__mmask8)-1); })
				1294
				1295	#define _mm256_mask_cmp_pd_mask(m, a, b, p) __extension__ ({ \
				1296	(__mmask8)__builtin_ia32_cmppd256_mask((__v4df)(__m256)(a), \
				1297	(__v4df)(__m256)(b), \
				1298	(p), (__mmask8)(m)); })
				1299
				1300	#define _mm128_cmp_ps_mask(a, b, p) __extension__ ({ \
				1301	(__mmask8)__builtin_ia32_cmpps128_mask((__v4sf)(__m128)(a), \
				1302	(__v4sf)(__m128)(b), \
				1303	(p), (__mmask8)-1); })
				1304
				1305	#define _mm128_mask_cmp_ps_mask(m, a, b, p) __extension__ ({ \
				1306	(__mmask8)__builtin_ia32_cmpps128_mask((__v4sf)(__m128)(a), \
				1307	(__v4sf)(__m128)(b), \
				1308	(p), (__mmask8)(m)); })
				1309
				1310	#define _mm128_cmp_pd_mask(a, b, p) __extension__ ({ \
				1311	(__mmask8)__builtin_ia32_cmppd128_mask((__v2df)(__m128)(a), \
				1312	(__v2df)(__m128)(b), \
				1313	(p), (__mmask8)-1); })
				1314
				1315	#define _mm128_mask_cmp_pd_mask(m, a, b, p) __extension__ ({ \
				1316	(__mmask8)__builtin_ia32_cmppd128_mask((__v2df)(__m128)(a), \
				1317	(__v2df)(__m128)(b), \
				1318	(p), (__mmask8)(m)); })
Eric Christopher	4d185168	2015-06-17 07:09:20 +0000	[diff] [blame]	1319
Michael Kuperstein	e45af54	2015-06-30 13:36:19 +0000	[diff] [blame]	1320	static __inline__ __m128d __DEFAULT_FN_ATTRS
Elena Demikhovsky	c563c2c	2015-06-29 09:20:57 +0000	[diff] [blame]	1321	_mm_mask_fmadd_pd(__m128d __A, __mmask8 __U, __m128d __B, __m128d __C)
				1322	{
				1323	return (__m128d) __builtin_ia32_vfmaddpd128_mask ((__v2df) __A,
				1324	(__v2df) __B,
				1325	(__v2df) __C,
				1326	(__mmask8) __U);
				1327	}
				1328
Michael Kuperstein	e45af54	2015-06-30 13:36:19 +0000	[diff] [blame]	1329	static __inline__ __m128d __DEFAULT_FN_ATTRS
Elena Demikhovsky	c563c2c	2015-06-29 09:20:57 +0000	[diff] [blame]	1330	_mm_mask3_fmadd_pd(__m128d __A, __m128d __B, __m128d __C, __mmask8 __U)
				1331	{
				1332	return (__m128d) __builtin_ia32_vfmaddpd128_mask3 ((__v2df) __A,
				1333	(__v2df) __B,
				1334	(__v2df) __C,
				1335	(__mmask8) __U);
				1336	}
				1337
Michael Kuperstein	e45af54	2015-06-30 13:36:19 +0000	[diff] [blame]	1338	static __inline__ __m128d __DEFAULT_FN_ATTRS
Elena Demikhovsky	c563c2c	2015-06-29 09:20:57 +0000	[diff] [blame]	1339	_mm_maskz_fmadd_pd(__mmask8 __U, __m128d __A, __m128d __B, __m128d __C)
				1340	{
				1341	return (__m128d) __builtin_ia32_vfmaddpd128_maskz ((__v2df) __A,
				1342	(__v2df) __B,
				1343	(__v2df) __C,
				1344	(__mmask8) __U);
				1345	}
				1346
Michael Kuperstein	e45af54	2015-06-30 13:36:19 +0000	[diff] [blame]	1347	static __inline__ __m128d __DEFAULT_FN_ATTRS
Elena Demikhovsky	c563c2c	2015-06-29 09:20:57 +0000	[diff] [blame]	1348	_mm_mask_fmsub_pd(__m128d __A, __mmask8 __U, __m128d __B, __m128d __C)
				1349	{
				1350	return (__m128d) __builtin_ia32_vfmaddpd128_mask ((__v2df) __A,
				1351	(__v2df) __B,
				1352	-(__v2df) __C,
				1353	(__mmask8) __U);
				1354	}
				1355
Michael Kuperstein	e45af54	2015-06-30 13:36:19 +0000	[diff] [blame]	1356	static __inline__ __m128d __DEFAULT_FN_ATTRS
Elena Demikhovsky	c563c2c	2015-06-29 09:20:57 +0000	[diff] [blame]	1357	_mm_maskz_fmsub_pd(__mmask8 __U, __m128d __A, __m128d __B, __m128d __C)
				1358	{
				1359	return (__m128d) __builtin_ia32_vfmaddpd128_maskz ((__v2df) __A,
				1360	(__v2df) __B,
				1361	-(__v2df) __C,
				1362	(__mmask8) __U);
				1363	}
				1364
Michael Kuperstein	e45af54	2015-06-30 13:36:19 +0000	[diff] [blame]	1365	static __inline__ __m128d __DEFAULT_FN_ATTRS
Elena Demikhovsky	c563c2c	2015-06-29 09:20:57 +0000	[diff] [blame]	1366	_mm_mask3_fnmadd_pd(__m128d __A, __m128d __B, __m128d __C, __mmask8 __U)
				1367	{
				1368	return (__m128d) __builtin_ia32_vfmaddpd128_mask3 (-(__v2df) __A,
				1369	(__v2df) __B,
				1370	(__v2df) __C,
				1371	(__mmask8) __U);
				1372	}
				1373
Michael Kuperstein	e45af54	2015-06-30 13:36:19 +0000	[diff] [blame]	1374	static __inline__ __m128d __DEFAULT_FN_ATTRS
Elena Demikhovsky	c563c2c	2015-06-29 09:20:57 +0000	[diff] [blame]	1375	_mm_maskz_fnmadd_pd(__mmask8 __U, __m128d __A, __m128d __B, __m128d __C)
				1376	{
				1377	return (__m128d) __builtin_ia32_vfmaddpd128_maskz (-(__v2df) __A,
				1378	(__v2df) __B,
				1379	(__v2df) __C,
				1380	(__mmask8) __U);
				1381	}
				1382
Michael Kuperstein	e45af54	2015-06-30 13:36:19 +0000	[diff] [blame]	1383	static __inline__ __m128d __DEFAULT_FN_ATTRS
Elena Demikhovsky	c563c2c	2015-06-29 09:20:57 +0000	[diff] [blame]	1384	_mm_maskz_fnmsub_pd(__mmask8 __U, __m128d __A, __m128d __B, __m128d __C)
				1385	{
				1386	return (__m128d) __builtin_ia32_vfmaddpd128_maskz (-(__v2df) __A,
				1387	(__v2df) __B,
				1388	-(__v2df) __C,
				1389	(__mmask8) __U);
				1390	}
				1391
Michael Kuperstein	e45af54	2015-06-30 13:36:19 +0000	[diff] [blame]	1392	static __inline__ __m256d __DEFAULT_FN_ATTRS
Elena Demikhovsky	c563c2c	2015-06-29 09:20:57 +0000	[diff] [blame]	1393	_mm256_mask_fmadd_pd(__m256d __A, __mmask8 __U, __m256d __B, __m256d __C)
				1394	{
				1395	return (__m256d) __builtin_ia32_vfmaddpd256_mask ((__v4df) __A,
				1396	(__v4df) __B,
				1397	(__v4df) __C,
				1398	(__mmask8) __U);
				1399	}
				1400
Michael Kuperstein	e45af54	2015-06-30 13:36:19 +0000	[diff] [blame]	1401	static __inline__ __m256d __DEFAULT_FN_ATTRS
Elena Demikhovsky	c563c2c	2015-06-29 09:20:57 +0000	[diff] [blame]	1402	_mm256_mask3_fmadd_pd(__m256d __A, __m256d __B, __m256d __C, __mmask8 __U)
				1403	{
				1404	return (__m256d) __builtin_ia32_vfmaddpd256_mask3 ((__v4df) __A,
				1405	(__v4df) __B,
				1406	(__v4df) __C,
				1407	(__mmask8) __U);
				1408	}
				1409
Michael Kuperstein	e45af54	2015-06-30 13:36:19 +0000	[diff] [blame]	1410	static __inline__ __m256d __DEFAULT_FN_ATTRS
Elena Demikhovsky	c563c2c	2015-06-29 09:20:57 +0000	[diff] [blame]	1411	_mm256_maskz_fmadd_pd(__mmask8 __U, __m256d __A, __m256d __B, __m256d __C)
				1412	{
				1413	return (__m256d) __builtin_ia32_vfmaddpd256_maskz ((__v4df) __A,
				1414	(__v4df) __B,
				1415	(__v4df) __C,
				1416	(__mmask8) __U);
				1417	}
				1418
Michael Kuperstein	e45af54	2015-06-30 13:36:19 +0000	[diff] [blame]	1419	static __inline__ __m256d __DEFAULT_FN_ATTRS
Elena Demikhovsky	c563c2c	2015-06-29 09:20:57 +0000	[diff] [blame]	1420	_mm256_mask_fmsub_pd(__m256d __A, __mmask8 __U, __m256d __B, __m256d __C)
				1421	{
				1422	return (__m256d) __builtin_ia32_vfmaddpd256_mask ((__v4df) __A,
				1423	(__v4df) __B,
				1424	-(__v4df) __C,
				1425	(__mmask8) __U);
				1426	}
				1427
Michael Kuperstein	e45af54	2015-06-30 13:36:19 +0000	[diff] [blame]	1428	static __inline__ __m256d __DEFAULT_FN_ATTRS
Elena Demikhovsky	c563c2c	2015-06-29 09:20:57 +0000	[diff] [blame]	1429	_mm256_maskz_fmsub_pd(__mmask8 __U, __m256d __A, __m256d __B, __m256d __C)
				1430	{
				1431	return (__m256d) __builtin_ia32_vfmaddpd256_maskz ((__v4df) __A,
				1432	(__v4df) __B,
				1433	-(__v4df) __C,
				1434	(__mmask8) __U);
				1435	}
				1436
Michael Kuperstein	e45af54	2015-06-30 13:36:19 +0000	[diff] [blame]	1437	static __inline__ __m256d __DEFAULT_FN_ATTRS
Elena Demikhovsky	c563c2c	2015-06-29 09:20:57 +0000	[diff] [blame]	1438	_mm256_mask3_fnmadd_pd(__m256d __A, __m256d __B, __m256d __C, __mmask8 __U)
				1439	{
				1440	return (__m256d) __builtin_ia32_vfmaddpd256_mask3 (-(__v4df) __A,
				1441	(__v4df) __B,
				1442	(__v4df) __C,
				1443	(__mmask8) __U);
				1444	}
				1445
Michael Kuperstein	e45af54	2015-06-30 13:36:19 +0000	[diff] [blame]	1446	static __inline__ __m256d __DEFAULT_FN_ATTRS
Elena Demikhovsky	c563c2c	2015-06-29 09:20:57 +0000	[diff] [blame]	1447	_mm256_maskz_fnmadd_pd(__mmask8 __U, __m256d __A, __m256d __B, __m256d __C)
				1448	{
				1449	return (__m256d) __builtin_ia32_vfmaddpd256_maskz (-(__v4df) __A,
				1450	(__v4df) __B,
				1451	(__v4df) __C,
				1452	(__mmask8) __U);
				1453	}
				1454
Michael Kuperstein	e45af54	2015-06-30 13:36:19 +0000	[diff] [blame]	1455	static __inline__ __m256d __DEFAULT_FN_ATTRS
Elena Demikhovsky	c563c2c	2015-06-29 09:20:57 +0000	[diff] [blame]	1456	_mm256_maskz_fnmsub_pd(__mmask8 __U, __m256d __A, __m256d __B, __m256d __C)
				1457	{
				1458	return (__m256d) __builtin_ia32_vfmaddpd256_maskz (-(__v4df) __A,
				1459	(__v4df) __B,
				1460	-(__v4df) __C,
				1461	(__mmask8) __U);
				1462	}
				1463
Michael Kuperstein	e45af54	2015-06-30 13:36:19 +0000	[diff] [blame]	1464	static __inline__ __m128 __DEFAULT_FN_ATTRS
Elena Demikhovsky	c563c2c	2015-06-29 09:20:57 +0000	[diff] [blame]	1465	_mm_mask_fmadd_ps(__m128 __A, __mmask8 __U, __m128 __B, __m128 __C)
				1466	{
				1467	return (__m128) __builtin_ia32_vfmaddps128_mask ((__v4sf) __A,
				1468	(__v4sf) __B,
				1469	(__v4sf) __C,
				1470	(__mmask8) __U);
				1471	}
				1472
Michael Kuperstein	e45af54	2015-06-30 13:36:19 +0000	[diff] [blame]	1473	static __inline__ __m128 __DEFAULT_FN_ATTRS
Elena Demikhovsky	c563c2c	2015-06-29 09:20:57 +0000	[diff] [blame]	1474	_mm_mask3_fmadd_ps(__m128 __A, __m128 __B, __m128 __C, __mmask8 __U)
				1475	{
				1476	return (__m128) __builtin_ia32_vfmaddps128_mask3 ((__v4sf) __A,
				1477	(__v4sf) __B,
				1478	(__v4sf) __C,
				1479	(__mmask8) __U);
				1480	}
				1481
Michael Kuperstein	e45af54	2015-06-30 13:36:19 +0000	[diff] [blame]	1482	static __inline__ __m128 __DEFAULT_FN_ATTRS
Elena Demikhovsky	c563c2c	2015-06-29 09:20:57 +0000	[diff] [blame]	1483	_mm_maskz_fmadd_ps(__mmask8 __U, __m128 __A, __m128 __B, __m128 __C)
				1484	{
				1485	return (__m128) __builtin_ia32_vfmaddps128_maskz ((__v4sf) __A,
				1486	(__v4sf) __B,
				1487	(__v4sf) __C,
				1488	(__mmask8) __U);
				1489	}
				1490
Michael Kuperstein	e45af54	2015-06-30 13:36:19 +0000	[diff] [blame]	1491	static __inline__ __m128 __DEFAULT_FN_ATTRS
Elena Demikhovsky	c563c2c	2015-06-29 09:20:57 +0000	[diff] [blame]	1492	_mm_mask_fmsub_ps(__m128 __A, __mmask8 __U, __m128 __B, __m128 __C)
				1493	{
				1494	return (__m128) __builtin_ia32_vfmaddps128_mask ((__v4sf) __A,
				1495	(__v4sf) __B,
				1496	-(__v4sf) __C,
				1497	(__mmask8) __U);
				1498	}
				1499
Michael Kuperstein	e45af54	2015-06-30 13:36:19 +0000	[diff] [blame]	1500	static __inline__ __m128 __DEFAULT_FN_ATTRS
Elena Demikhovsky	c563c2c	2015-06-29 09:20:57 +0000	[diff] [blame]	1501	_mm_maskz_fmsub_ps(__mmask8 __U, __m128 __A, __m128 __B, __m128 __C)
				1502	{
				1503	return (__m128) __builtin_ia32_vfmaddps128_maskz ((__v4sf) __A,
				1504	(__v4sf) __B,
				1505	-(__v4sf) __C,
				1506	(__mmask8) __U);
				1507	}
				1508
Michael Kuperstein	e45af54	2015-06-30 13:36:19 +0000	[diff] [blame]	1509	static __inline__ __m128 __DEFAULT_FN_ATTRS
Elena Demikhovsky	c563c2c	2015-06-29 09:20:57 +0000	[diff] [blame]	1510	_mm_mask3_fnmadd_ps(__m128 __A, __m128 __B, __m128 __C, __mmask8 __U)
				1511	{
				1512	return (__m128) __builtin_ia32_vfmaddps128_mask3 (-(__v4sf) __A,
				1513	(__v4sf) __B,
				1514	(__v4sf) __C,
				1515	(__mmask8) __U);
				1516	}
				1517
Michael Kuperstein	e45af54	2015-06-30 13:36:19 +0000	[diff] [blame]	1518	static __inline__ __m128 __DEFAULT_FN_ATTRS
Elena Demikhovsky	c563c2c	2015-06-29 09:20:57 +0000	[diff] [blame]	1519	_mm_maskz_fnmadd_ps(__mmask8 __U, __m128 __A, __m128 __B, __m128 __C)
				1520	{
				1521	return (__m128) __builtin_ia32_vfmaddps128_maskz (-(__v4sf) __A,
				1522	(__v4sf) __B,
				1523	(__v4sf) __C,
				1524	(__mmask8) __U);
				1525	}
				1526
Michael Kuperstein	e45af54	2015-06-30 13:36:19 +0000	[diff] [blame]	1527	static __inline__ __m128 __DEFAULT_FN_ATTRS
Elena Demikhovsky	c563c2c	2015-06-29 09:20:57 +0000	[diff] [blame]	1528	_mm_maskz_fnmsub_ps(__mmask8 __U, __m128 __A, __m128 __B, __m128 __C)
				1529	{
				1530	return (__m128) __builtin_ia32_vfmaddps128_maskz (-(__v4sf) __A,
				1531	(__v4sf) __B,
				1532	-(__v4sf) __C,
				1533	(__mmask8) __U);
				1534	}
				1535
Michael Kuperstein	e45af54	2015-06-30 13:36:19 +0000	[diff] [blame]	1536	static __inline__ __m256 __DEFAULT_FN_ATTRS
Elena Demikhovsky	c563c2c	2015-06-29 09:20:57 +0000	[diff] [blame]	1537	_mm256_mask_fmadd_ps(__m256 __A, __mmask8 __U, __m256 __B, __m256 __C)
				1538	{
				1539	return (__m256) __builtin_ia32_vfmaddps256_mask ((__v8sf) __A,
				1540	(__v8sf) __B,
				1541	(__v8sf) __C,
				1542	(__mmask8) __U);
				1543	}
				1544
Michael Kuperstein	e45af54	2015-06-30 13:36:19 +0000	[diff] [blame]	1545	static __inline__ __m256 __DEFAULT_FN_ATTRS
Elena Demikhovsky	c563c2c	2015-06-29 09:20:57 +0000	[diff] [blame]	1546	_mm256_mask3_fmadd_ps(__m256 __A, __m256 __B, __m256 __C, __mmask8 __U)
				1547	{
				1548	return (__m256) __builtin_ia32_vfmaddps256_mask3 ((__v8sf) __A,
				1549	(__v8sf) __B,
				1550	(__v8sf) __C,
				1551	(__mmask8) __U);
				1552	}
				1553
Michael Kuperstein	e45af54	2015-06-30 13:36:19 +0000	[diff] [blame]	1554	static __inline__ __m256 __DEFAULT_FN_ATTRS
Elena Demikhovsky	c563c2c	2015-06-29 09:20:57 +0000	[diff] [blame]	1555	_mm256_maskz_fmadd_ps(__mmask8 __U, __m256 __A, __m256 __B, __m256 __C)
				1556	{
				1557	return (__m256) __builtin_ia32_vfmaddps256_maskz ((__v8sf) __A,
				1558	(__v8sf) __B,
				1559	(__v8sf) __C,
				1560	(__mmask8) __U);
				1561	}
				1562
Michael Kuperstein	e45af54	2015-06-30 13:36:19 +0000	[diff] [blame]	1563	static __inline__ __m256 __DEFAULT_FN_ATTRS
Elena Demikhovsky	c563c2c	2015-06-29 09:20:57 +0000	[diff] [blame]	1564	_mm256_mask_fmsub_ps(__m256 __A, __mmask8 __U, __m256 __B, __m256 __C)
				1565	{
				1566	return (__m256) __builtin_ia32_vfmaddps256_mask ((__v8sf) __A,
				1567	(__v8sf) __B,
				1568	-(__v8sf) __C,
				1569	(__mmask8) __U);
				1570	}
				1571
Michael Kuperstein	e45af54	2015-06-30 13:36:19 +0000	[diff] [blame]	1572	static __inline__ __m256 __DEFAULT_FN_ATTRS
Elena Demikhovsky	c563c2c	2015-06-29 09:20:57 +0000	[diff] [blame]	1573	_mm256_maskz_fmsub_ps(__mmask8 __U, __m256 __A, __m256 __B, __m256 __C)
				1574	{
				1575	return (__m256) __builtin_ia32_vfmaddps256_maskz ((__v8sf) __A,
				1576	(__v8sf) __B,
				1577	-(__v8sf) __C,
				1578	(__mmask8) __U);
				1579	}
				1580
Michael Kuperstein	e45af54	2015-06-30 13:36:19 +0000	[diff] [blame]	1581	static __inline__ __m256 __DEFAULT_FN_ATTRS
Elena Demikhovsky	c563c2c	2015-06-29 09:20:57 +0000	[diff] [blame]	1582	_mm256_mask3_fnmadd_ps(__m256 __A, __m256 __B, __m256 __C, __mmask8 __U)
				1583	{
				1584	return (__m256) __builtin_ia32_vfmaddps256_mask3 (-(__v8sf) __A,
				1585	(__v8sf) __B,
				1586	(__v8sf) __C,
				1587	(__mmask8) __U);
				1588	}
				1589
Michael Kuperstein	e45af54	2015-06-30 13:36:19 +0000	[diff] [blame]	1590	static __inline__ __m256 __DEFAULT_FN_ATTRS
Elena Demikhovsky	c563c2c	2015-06-29 09:20:57 +0000	[diff] [blame]	1591	_mm256_maskz_fnmadd_ps(__mmask8 __U, __m256 __A, __m256 __B, __m256 __C)
				1592	{
				1593	return (__m256) __builtin_ia32_vfmaddps256_maskz (-(__v8sf) __A,
				1594	(__v8sf) __B,
				1595	(__v8sf) __C,
				1596	(__mmask8) __U);
				1597	}
				1598
Michael Kuperstein	e45af54	2015-06-30 13:36:19 +0000	[diff] [blame]	1599	static __inline__ __m256 __DEFAULT_FN_ATTRS
Elena Demikhovsky	c563c2c	2015-06-29 09:20:57 +0000	[diff] [blame]	1600	_mm256_maskz_fnmsub_ps(__mmask8 __U, __m256 __A, __m256 __B, __m256 __C)
				1601	{
				1602	return (__m256) __builtin_ia32_vfmaddps256_maskz (-(__v8sf) __A,
				1603	(__v8sf) __B,
				1604	-(__v8sf) __C,
				1605	(__mmask8) __U);
				1606	}
				1607
Michael Kuperstein	e45af54	2015-06-30 13:36:19 +0000	[diff] [blame]	1608	static __inline__ __m128d __DEFAULT_FN_ATTRS
Elena Demikhovsky	c563c2c	2015-06-29 09:20:57 +0000	[diff] [blame]	1609	_mm_mask_fmaddsub_pd(__m128d __A, __mmask8 __U, __m128d __B, __m128d __C)
				1610	{
				1611	return (__m128d) __builtin_ia32_vfmaddsubpd128_mask ((__v2df) __A,
				1612	(__v2df) __B,
				1613	(__v2df) __C,
				1614	(__mmask8) __U);
				1615	}
				1616
Michael Kuperstein	e45af54	2015-06-30 13:36:19 +0000	[diff] [blame]	1617	static __inline__ __m128d __DEFAULT_FN_ATTRS
Elena Demikhovsky	c563c2c	2015-06-29 09:20:57 +0000	[diff] [blame]	1618	_mm_mask3_fmaddsub_pd(__m128d __A, __m128d __B, __m128d __C, __mmask8 __U)
				1619	{
				1620	return (__m128d) __builtin_ia32_vfmaddsubpd128_mask3 ((__v2df) __A,
				1621	(__v2df) __B,
				1622	(__v2df) __C,
				1623	(__mmask8)
				1624	__U);
				1625	}
				1626
Michael Kuperstein	e45af54	2015-06-30 13:36:19 +0000	[diff] [blame]	1627	static __inline__ __m128d __DEFAULT_FN_ATTRS
Elena Demikhovsky	c563c2c	2015-06-29 09:20:57 +0000	[diff] [blame]	1628	_mm_maskz_fmaddsub_pd(__mmask8 __U, __m128d __A, __m128d __B, __m128d __C)
				1629	{
				1630	return (__m128d) __builtin_ia32_vfmaddsubpd128_maskz ((__v2df) __A,
				1631	(__v2df) __B,
				1632	(__v2df) __C,
				1633	(__mmask8)
				1634	__U);
				1635	}
				1636
Michael Kuperstein	e45af54	2015-06-30 13:36:19 +0000	[diff] [blame]	1637	static __inline__ __m128d __DEFAULT_FN_ATTRS
Elena Demikhovsky	c563c2c	2015-06-29 09:20:57 +0000	[diff] [blame]	1638	_mm_mask_fmsubadd_pd(__m128d __A, __mmask8 __U, __m128d __B, __m128d __C)
				1639	{
				1640	return (__m128d) __builtin_ia32_vfmaddsubpd128_mask ((__v2df) __A,
				1641	(__v2df) __B,
				1642	-(__v2df) __C,
				1643	(__mmask8) __U);
				1644	}
				1645
Michael Kuperstein	e45af54	2015-06-30 13:36:19 +0000	[diff] [blame]	1646	static __inline__ __m128d __DEFAULT_FN_ATTRS
Elena Demikhovsky	c563c2c	2015-06-29 09:20:57 +0000	[diff] [blame]	1647	_mm_maskz_fmsubadd_pd(__mmask8 __U, __m128d __A, __m128d __B, __m128d __C)
				1648	{
				1649	return (__m128d) __builtin_ia32_vfmaddsubpd128_maskz ((__v2df) __A,
				1650	(__v2df) __B,
				1651	-(__v2df) __C,
				1652	(__mmask8)
				1653	__U);
				1654	}
				1655
Michael Kuperstein	e45af54	2015-06-30 13:36:19 +0000	[diff] [blame]	1656	static __inline__ __m256d __DEFAULT_FN_ATTRS
Elena Demikhovsky	c563c2c	2015-06-29 09:20:57 +0000	[diff] [blame]	1657	_mm256_mask_fmaddsub_pd(__m256d __A, __mmask8 __U, __m256d __B, __m256d __C)
				1658	{
				1659	return (__m256d) __builtin_ia32_vfmaddsubpd256_mask ((__v4df) __A,
				1660	(__v4df) __B,
				1661	(__v4df) __C,
				1662	(__mmask8) __U);
				1663	}
				1664
Michael Kuperstein	e45af54	2015-06-30 13:36:19 +0000	[diff] [blame]	1665	static __inline__ __m256d __DEFAULT_FN_ATTRS
Elena Demikhovsky	c563c2c	2015-06-29 09:20:57 +0000	[diff] [blame]	1666	_mm256_mask3_fmaddsub_pd(__m256d __A, __m256d __B, __m256d __C, __mmask8 __U)
				1667	{
				1668	return (__m256d) __builtin_ia32_vfmaddsubpd256_mask3 ((__v4df) __A,
				1669	(__v4df) __B,
				1670	(__v4df) __C,
				1671	(__mmask8)
				1672	__U);
				1673	}
				1674
Michael Kuperstein	e45af54	2015-06-30 13:36:19 +0000	[diff] [blame]	1675	static __inline__ __m256d __DEFAULT_FN_ATTRS
Elena Demikhovsky	c563c2c	2015-06-29 09:20:57 +0000	[diff] [blame]	1676	_mm256_maskz_fmaddsub_pd(__mmask8 __U, __m256d __A, __m256d __B, __m256d __C)
				1677	{
				1678	return (__m256d) __builtin_ia32_vfmaddsubpd256_maskz ((__v4df) __A,
				1679	(__v4df) __B,
				1680	(__v4df) __C,
				1681	(__mmask8)
				1682	__U);
				1683	}
				1684
Michael Kuperstein	e45af54	2015-06-30 13:36:19 +0000	[diff] [blame]	1685	static __inline__ __m256d __DEFAULT_FN_ATTRS
Elena Demikhovsky	c563c2c	2015-06-29 09:20:57 +0000	[diff] [blame]	1686	_mm256_mask_fmsubadd_pd(__m256d __A, __mmask8 __U, __m256d __B, __m256d __C)
				1687	{
				1688	return (__m256d) __builtin_ia32_vfmaddsubpd256_mask ((__v4df) __A,
				1689	(__v4df) __B,
				1690	-(__v4df) __C,
				1691	(__mmask8) __U);
				1692	}
				1693
Michael Kuperstein	e45af54	2015-06-30 13:36:19 +0000	[diff] [blame]	1694	static __inline__ __m256d __DEFAULT_FN_ATTRS
Elena Demikhovsky	c563c2c	2015-06-29 09:20:57 +0000	[diff] [blame]	1695	_mm256_maskz_fmsubadd_pd(__mmask8 __U, __m256d __A, __m256d __B, __m256d __C)
				1696	{
				1697	return (__m256d) __builtin_ia32_vfmaddsubpd256_maskz ((__v4df) __A,
				1698	(__v4df) __B,
				1699	-(__v4df) __C,
				1700	(__mmask8)
				1701	__U);
				1702	}
				1703
Michael Kuperstein	e45af54	2015-06-30 13:36:19 +0000	[diff] [blame]	1704	static __inline__ __m128 __DEFAULT_FN_ATTRS
Elena Demikhovsky	c563c2c	2015-06-29 09:20:57 +0000	[diff] [blame]	1705	_mm_mask_fmaddsub_ps(__m128 __A, __mmask8 __U, __m128 __B, __m128 __C)
				1706	{
				1707	return (__m128) __builtin_ia32_vfmaddsubps128_mask ((__v4sf) __A,
				1708	(__v4sf) __B,
				1709	(__v4sf) __C,
				1710	(__mmask8) __U);
				1711	}
				1712
Michael Kuperstein	e45af54	2015-06-30 13:36:19 +0000	[diff] [blame]	1713	static __inline__ __m128 __DEFAULT_FN_ATTRS
Elena Demikhovsky	c563c2c	2015-06-29 09:20:57 +0000	[diff] [blame]	1714	_mm_mask3_fmaddsub_ps(__m128 __A, __m128 __B, __m128 __C, __mmask8 __U)
				1715	{
				1716	return (__m128) __builtin_ia32_vfmaddsubps128_mask3 ((__v4sf) __A,
				1717	(__v4sf) __B,
				1718	(__v4sf) __C,
				1719	(__mmask8) __U);
				1720	}
				1721
Michael Kuperstein	e45af54	2015-06-30 13:36:19 +0000	[diff] [blame]	1722	static __inline__ __m128 __DEFAULT_FN_ATTRS
Elena Demikhovsky	c563c2c	2015-06-29 09:20:57 +0000	[diff] [blame]	1723	_mm_maskz_fmaddsub_ps(__mmask8 __U, __m128 __A, __m128 __B, __m128 __C)
				1724	{
				1725	return (__m128) __builtin_ia32_vfmaddsubps128_maskz ((__v4sf) __A,
				1726	(__v4sf) __B,
				1727	(__v4sf) __C,
				1728	(__mmask8) __U);
				1729	}
				1730
Michael Kuperstein	e45af54	2015-06-30 13:36:19 +0000	[diff] [blame]	1731	static __inline__ __m128 __DEFAULT_FN_ATTRS
Elena Demikhovsky	c563c2c	2015-06-29 09:20:57 +0000	[diff] [blame]	1732	_mm_mask_fmsubadd_ps(__m128 __A, __mmask8 __U, __m128 __B, __m128 __C)
				1733	{
				1734	return (__m128) __builtin_ia32_vfmaddsubps128_mask ((__v4sf) __A,
				1735	(__v4sf) __B,
				1736	-(__v4sf) __C,
				1737	(__mmask8) __U);
				1738	}
				1739
Michael Kuperstein	e45af54	2015-06-30 13:36:19 +0000	[diff] [blame]	1740	static __inline__ __m128 __DEFAULT_FN_ATTRS
Elena Demikhovsky	c563c2c	2015-06-29 09:20:57 +0000	[diff] [blame]	1741	_mm_maskz_fmsubadd_ps(__mmask8 __U, __m128 __A, __m128 __B, __m128 __C)
				1742	{
				1743	return (__m128) __builtin_ia32_vfmaddsubps128_maskz ((__v4sf) __A,
				1744	(__v4sf) __B,
				1745	-(__v4sf) __C,
				1746	(__mmask8) __U);
				1747	}
				1748
Michael Kuperstein	e45af54	2015-06-30 13:36:19 +0000	[diff] [blame]	1749	static __inline__ __m256 __DEFAULT_FN_ATTRS
Elena Demikhovsky	c563c2c	2015-06-29 09:20:57 +0000	[diff] [blame]	1750	_mm256_mask_fmaddsub_ps(__m256 __A, __mmask8 __U, __m256 __B,
				1751	__m256 __C)
				1752	{
				1753	return (__m256) __builtin_ia32_vfmaddsubps256_mask ((__v8sf) __A,
				1754	(__v8sf) __B,
				1755	(__v8sf) __C,
				1756	(__mmask8) __U);
				1757	}
				1758
Michael Kuperstein	e45af54	2015-06-30 13:36:19 +0000	[diff] [blame]	1759	static __inline__ __m256 __DEFAULT_FN_ATTRS
Elena Demikhovsky	c563c2c	2015-06-29 09:20:57 +0000	[diff] [blame]	1760	_mm256_mask3_fmaddsub_ps(__m256 __A, __m256 __B, __m256 __C, __mmask8 __U)
				1761	{
				1762	return (__m256) __builtin_ia32_vfmaddsubps256_mask3 ((__v8sf) __A,
				1763	(__v8sf) __B,
				1764	(__v8sf) __C,
				1765	(__mmask8) __U);
				1766	}
				1767
Michael Kuperstein	e45af54	2015-06-30 13:36:19 +0000	[diff] [blame]	1768	static __inline__ __m256 __DEFAULT_FN_ATTRS
Elena Demikhovsky	c563c2c	2015-06-29 09:20:57 +0000	[diff] [blame]	1769	_mm256_maskz_fmaddsub_ps(__mmask8 __U, __m256 __A, __m256 __B, __m256 __C)
				1770	{
				1771	return (__m256) __builtin_ia32_vfmaddsubps256_maskz ((__v8sf) __A,
				1772	(__v8sf) __B,
				1773	(__v8sf) __C,
				1774	(__mmask8) __U);
				1775	}
				1776
Michael Kuperstein	e45af54	2015-06-30 13:36:19 +0000	[diff] [blame]	1777	static __inline__ __m256 __DEFAULT_FN_ATTRS
Elena Demikhovsky	c563c2c	2015-06-29 09:20:57 +0000	[diff] [blame]	1778	_mm256_mask_fmsubadd_ps(__m256 __A, __mmask8 __U, __m256 __B, __m256 __C)
				1779	{
				1780	return (__m256) __builtin_ia32_vfmaddsubps256_mask ((__v8sf) __A,
				1781	(__v8sf) __B,
				1782	-(__v8sf) __C,
				1783	(__mmask8) __U);
				1784	}
				1785
Michael Kuperstein	e45af54	2015-06-30 13:36:19 +0000	[diff] [blame]	1786	static __inline__ __m256 __DEFAULT_FN_ATTRS
Elena Demikhovsky	c563c2c	2015-06-29 09:20:57 +0000	[diff] [blame]	1787	_mm256_maskz_fmsubadd_ps(__mmask8 __U, __m256 __A, __m256 __B, __m256 __C)
				1788	{
				1789	return (__m256) __builtin_ia32_vfmaddsubps256_maskz ((__v8sf) __A,
				1790	(__v8sf) __B,
				1791	-(__v8sf) __C,
				1792	(__mmask8) __U);
				1793	}
				1794
Michael Kuperstein	e45af54	2015-06-30 13:36:19 +0000	[diff] [blame]	1795	static __inline__ __m128d __DEFAULT_FN_ATTRS
Elena Demikhovsky	c563c2c	2015-06-29 09:20:57 +0000	[diff] [blame]	1796	_mm_mask3_fmsub_pd(__m128d __A, __m128d __B, __m128d __C, __mmask8 __U)
				1797	{
				1798	return (__m128d) __builtin_ia32_vfmsubpd128_mask3 ((__v2df) __A,
				1799	(__v2df) __B,
				1800	(__v2df) __C,
				1801	(__mmask8) __U);
				1802	}
				1803
Michael Kuperstein	e45af54	2015-06-30 13:36:19 +0000	[diff] [blame]	1804	static __inline__ __m256d __DEFAULT_FN_ATTRS
Elena Demikhovsky	c563c2c	2015-06-29 09:20:57 +0000	[diff] [blame]	1805	_mm256_mask3_fmsub_pd(__m256d __A, __m256d __B, __m256d __C, __mmask8 __U)
				1806	{
				1807	return (__m256d) __builtin_ia32_vfmsubpd256_mask3 ((__v4df) __A,
				1808	(__v4df) __B,
				1809	(__v4df) __C,
				1810	(__mmask8) __U);
				1811	}
				1812
Michael Kuperstein	e45af54	2015-06-30 13:36:19 +0000	[diff] [blame]	1813	static __inline__ __m128 __DEFAULT_FN_ATTRS
Elena Demikhovsky	c563c2c	2015-06-29 09:20:57 +0000	[diff] [blame]	1814	_mm_mask3_fmsub_ps(__m128 __A, __m128 __B, __m128 __C, __mmask8 __U)
				1815	{
				1816	return (__m128) __builtin_ia32_vfmsubps128_mask3 ((__v4sf) __A,
				1817	(__v4sf) __B,
				1818	(__v4sf) __C,
				1819	(__mmask8) __U);
				1820	}
				1821
Michael Kuperstein	e45af54	2015-06-30 13:36:19 +0000	[diff] [blame]	1822	static __inline__ __m256 __DEFAULT_FN_ATTRS
Elena Demikhovsky	c563c2c	2015-06-29 09:20:57 +0000	[diff] [blame]	1823	_mm256_mask3_fmsub_ps(__m256 __A, __m256 __B, __m256 __C, __mmask8 __U)
				1824	{
				1825	return (__m256) __builtin_ia32_vfmsubps256_mask3 ((__v8sf) __A,
				1826	(__v8sf) __B,
				1827	(__v8sf) __C,
				1828	(__mmask8) __U);
				1829	}
				1830
Michael Kuperstein	e45af54	2015-06-30 13:36:19 +0000	[diff] [blame]	1831	static __inline__ __m128d __DEFAULT_FN_ATTRS
Elena Demikhovsky	c563c2c	2015-06-29 09:20:57 +0000	[diff] [blame]	1832	_mm_mask3_fmsubadd_pd(__m128d __A, __m128d __B, __m128d __C, __mmask8 __U)
				1833	{
				1834	return (__m128d) __builtin_ia32_vfmsubaddpd128_mask3 ((__v2df) __A,
				1835	(__v2df) __B,
				1836	(__v2df) __C,
				1837	(__mmask8)
				1838	__U);
				1839	}
				1840
Michael Kuperstein	e45af54	2015-06-30 13:36:19 +0000	[diff] [blame]	1841	static __inline__ __m256d __DEFAULT_FN_ATTRS
Elena Demikhovsky	c563c2c	2015-06-29 09:20:57 +0000	[diff] [blame]	1842	_mm256_mask3_fmsubadd_pd(__m256d __A, __m256d __B, __m256d __C, __mmask8 __U)
				1843	{
				1844	return (__m256d) __builtin_ia32_vfmsubaddpd256_mask3 ((__v4df) __A,
				1845	(__v4df) __B,
				1846	(__v4df) __C,
				1847	(__mmask8)
				1848	__U);
				1849	}
				1850
Michael Kuperstein	e45af54	2015-06-30 13:36:19 +0000	[diff] [blame]	1851	static __inline__ __m128 __DEFAULT_FN_ATTRS
Elena Demikhovsky	c563c2c	2015-06-29 09:20:57 +0000	[diff] [blame]	1852	_mm_mask3_fmsubadd_ps(__m128 __A, __m128 __B, __m128 __C, __mmask8 __U)
				1853	{
				1854	return (__m128) __builtin_ia32_vfmsubaddps128_mask3 ((__v4sf) __A,
				1855	(__v4sf) __B,
				1856	(__v4sf) __C,
				1857	(__mmask8) __U);
				1858	}
				1859
Michael Kuperstein	e45af54	2015-06-30 13:36:19 +0000	[diff] [blame]	1860	static __inline__ __m256 __DEFAULT_FN_ATTRS
Elena Demikhovsky	c563c2c	2015-06-29 09:20:57 +0000	[diff] [blame]	1861	_mm256_mask3_fmsubadd_ps(__m256 __A, __m256 __B, __m256 __C, __mmask8 __U)
				1862	{
				1863	return (__m256) __builtin_ia32_vfmsubaddps256_mask3 ((__v8sf) __A,
				1864	(__v8sf) __B,
				1865	(__v8sf) __C,
				1866	(__mmask8) __U);
				1867	}
				1868
Michael Kuperstein	e45af54	2015-06-30 13:36:19 +0000	[diff] [blame]	1869	static __inline__ __m128d __DEFAULT_FN_ATTRS
Elena Demikhovsky	c563c2c	2015-06-29 09:20:57 +0000	[diff] [blame]	1870	_mm_mask_fnmadd_pd(__m128d __A, __mmask8 __U, __m128d __B, __m128d __C)
				1871	{
				1872	return (__m128d) __builtin_ia32_vfnmaddpd128_mask ((__v2df) __A,
				1873	(__v2df) __B,
				1874	(__v2df) __C,
				1875	(__mmask8) __U);
				1876	}
				1877
Michael Kuperstein	e45af54	2015-06-30 13:36:19 +0000	[diff] [blame]	1878	static __inline__ __m256d __DEFAULT_FN_ATTRS
Elena Demikhovsky	c563c2c	2015-06-29 09:20:57 +0000	[diff] [blame]	1879	_mm256_mask_fnmadd_pd(__m256d __A, __mmask8 __U, __m256d __B, __m256d __C)
				1880	{
				1881	return (__m256d) __builtin_ia32_vfnmaddpd256_mask ((__v4df) __A,
				1882	(__v4df) __B,
				1883	(__v4df) __C,
				1884	(__mmask8) __U);
				1885	}
				1886
Michael Kuperstein	e45af54	2015-06-30 13:36:19 +0000	[diff] [blame]	1887	static __inline__ __m128 __DEFAULT_FN_ATTRS
Elena Demikhovsky	c563c2c	2015-06-29 09:20:57 +0000	[diff] [blame]	1888	_mm_mask_fnmadd_ps(__m128 __A, __mmask8 __U, __m128 __B, __m128 __C)
				1889	{
				1890	return (__m128) __builtin_ia32_vfnmaddps128_mask ((__v4sf) __A,
				1891	(__v4sf) __B,
				1892	(__v4sf) __C,
				1893	(__mmask8) __U);
				1894	}
				1895
Michael Kuperstein	e45af54	2015-06-30 13:36:19 +0000	[diff] [blame]	1896	static __inline__ __m256 __DEFAULT_FN_ATTRS
Elena Demikhovsky	c563c2c	2015-06-29 09:20:57 +0000	[diff] [blame]	1897	_mm256_mask_fnmadd_ps(__m256 __A, __mmask8 __U, __m256 __B, __m256 __C)
				1898	{
				1899	return (__m256) __builtin_ia32_vfnmaddps256_mask ((__v8sf) __A,
				1900	(__v8sf) __B,
				1901	(__v8sf) __C,
				1902	(__mmask8) __U);
				1903	}
				1904
Michael Kuperstein	e45af54	2015-06-30 13:36:19 +0000	[diff] [blame]	1905	static __inline__ __m128d __DEFAULT_FN_ATTRS
Elena Demikhovsky	c563c2c	2015-06-29 09:20:57 +0000	[diff] [blame]	1906	_mm_mask_fnmsub_pd(__m128d __A, __mmask8 __U, __m128d __B, __m128d __C)
				1907	{
				1908	return (__m128d) __builtin_ia32_vfnmsubpd128_mask ((__v2df) __A,
				1909	(__v2df) __B,
				1910	(__v2df) __C,
				1911	(__mmask8) __U);
				1912	}
				1913
Michael Kuperstein	e45af54	2015-06-30 13:36:19 +0000	[diff] [blame]	1914	static __inline__ __m128d __DEFAULT_FN_ATTRS
Elena Demikhovsky	c563c2c	2015-06-29 09:20:57 +0000	[diff] [blame]	1915	_mm_mask3_fnmsub_pd(__m128d __A, __m128d __B, __m128d __C, __mmask8 __U)
				1916	{
				1917	return (__m128d) __builtin_ia32_vfnmsubpd128_mask3 ((__v2df) __A,
				1918	(__v2df) __B,
				1919	(__v2df) __C,
				1920	(__mmask8) __U);
				1921	}
				1922
Michael Kuperstein	e45af54	2015-06-30 13:36:19 +0000	[diff] [blame]	1923	static __inline__ __m256d __DEFAULT_FN_ATTRS
Elena Demikhovsky	c563c2c	2015-06-29 09:20:57 +0000	[diff] [blame]	1924	_mm256_mask_fnmsub_pd(__m256d __A, __mmask8 __U, __m256d __B, __m256d __C)
				1925	{
				1926	return (__m256d) __builtin_ia32_vfnmsubpd256_mask ((__v4df) __A,
				1927	(__v4df) __B,
				1928	(__v4df) __C,
				1929	(__mmask8) __U);
				1930	}
				1931
Michael Kuperstein	e45af54	2015-06-30 13:36:19 +0000	[diff] [blame]	1932	static __inline__ __m256d __DEFAULT_FN_ATTRS
Elena Demikhovsky	c563c2c	2015-06-29 09:20:57 +0000	[diff] [blame]	1933	_mm256_mask3_fnmsub_pd(__m256d __A, __m256d __B, __m256d __C, __mmask8 __U)
				1934	{
				1935	return (__m256d) __builtin_ia32_vfnmsubpd256_mask3 ((__v4df) __A,
				1936	(__v4df) __B,
				1937	(__v4df) __C,
				1938	(__mmask8) __U);
				1939	}
				1940
Michael Kuperstein	e45af54	2015-06-30 13:36:19 +0000	[diff] [blame]	1941	static __inline__ __m128 __DEFAULT_FN_ATTRS
Elena Demikhovsky	c563c2c	2015-06-29 09:20:57 +0000	[diff] [blame]	1942	_mm_mask_fnmsub_ps(__m128 __A, __mmask8 __U, __m128 __B, __m128 __C)
				1943	{
				1944	return (__m128) __builtin_ia32_vfnmsubps128_mask ((__v4sf) __A,
				1945	(__v4sf) __B,
				1946	(__v4sf) __C,
				1947	(__mmask8) __U);
				1948	}
				1949
Michael Kuperstein	e45af54	2015-06-30 13:36:19 +0000	[diff] [blame]	1950	static __inline__ __m128 __DEFAULT_FN_ATTRS
Elena Demikhovsky	c563c2c	2015-06-29 09:20:57 +0000	[diff] [blame]	1951	_mm_mask3_fnmsub_ps(__m128 __A, __m128 __B, __m128 __C, __mmask8 __U)
				1952	{
				1953	return (__m128) __builtin_ia32_vfnmsubps128_mask3 ((__v4sf) __A,
				1954	(__v4sf) __B,
				1955	(__v4sf) __C,
				1956	(__mmask8) __U);
				1957	}
				1958
Michael Kuperstein	e45af54	2015-06-30 13:36:19 +0000	[diff] [blame]	1959	static __inline__ __m256 __DEFAULT_FN_ATTRS
Elena Demikhovsky	c563c2c	2015-06-29 09:20:57 +0000	[diff] [blame]	1960	_mm256_mask_fnmsub_ps(__m256 __A, __mmask8 __U, __m256 __B, __m256 __C)
				1961	{
				1962	return (__m256) __builtin_ia32_vfnmsubps256_mask ((__v8sf) __A,
				1963	(__v8sf) __B,
				1964	(__v8sf) __C,
				1965	(__mmask8) __U);
				1966	}
				1967
Michael Kuperstein	e45af54	2015-06-30 13:36:19 +0000	[diff] [blame]	1968	static __inline__ __m256 __DEFAULT_FN_ATTRS
Elena Demikhovsky	c563c2c	2015-06-29 09:20:57 +0000	[diff] [blame]	1969	_mm256_mask3_fnmsub_ps(__m256 __A, __m256 __B, __m256 __C, __mmask8 __U)
				1970	{
				1971	return (__m256) __builtin_ia32_vfnmsubps256_mask3 ((__v8sf) __A,
				1972	(__v8sf) __B,
				1973	(__v8sf) __C,
				1974	(__mmask8) __U);
				1975	}
				1976
Asaf Badouh	74da387	2015-07-28 08:26:14 +0000	[diff] [blame]	1977	static __inline__ __m128d __DEFAULT_FN_ATTRS
				1978	_mm_mask_add_pd (__m128d __W, __mmask8 __U, __m128d __A, __m128d __B) {
				1979	return (__m128d) __builtin_ia32_addpd128_mask ((__v2df) __A,
				1980	(__v2df) __B,
				1981	(__v2df) __W,
				1982	(__mmask8) __U);
				1983	}
				1984
				1985	static __inline__ __m128d __DEFAULT_FN_ATTRS
				1986	_mm_maskz_add_pd (__mmask8 __U, __m128d __A, __m128d __B) {
				1987	return (__m128d) __builtin_ia32_addpd128_mask ((__v2df) __A,
				1988	(__v2df) __B,
				1989	(__v2df)
				1990	_mm_setzero_pd (),
				1991	(__mmask8) __U);
				1992	}
				1993
				1994	static __inline__ __m256d __DEFAULT_FN_ATTRS
				1995	_mm256_mask_add_pd (__m256d __W, __mmask8 __U, __m256d __A, __m256d __B) {
				1996	return (__m256d) __builtin_ia32_addpd256_mask ((__v4df) __A,
				1997	(__v4df) __B,
				1998	(__v4df) __W,
				1999	(__mmask8) __U);
				2000	}
				2001
				2002	static __inline__ __m256d __DEFAULT_FN_ATTRS
				2003	_mm256_maskz_add_pd (__mmask8 __U, __m256d __A, __m256d __B) {
				2004	return (__m256d) __builtin_ia32_addpd256_mask ((__v4df) __A,
				2005	(__v4df) __B,
				2006	(__v4df)
				2007	_mm256_setzero_pd (),
				2008	(__mmask8) __U);
				2009	}
				2010
				2011	static __inline__ __m128 __DEFAULT_FN_ATTRS
				2012	_mm_mask_add_ps (__m128 __W, __mmask16 __U, __m128 __A, __m128 __B) {
				2013	return (__m128) __builtin_ia32_addps128_mask ((__v4sf) __A,
				2014	(__v4sf) __B,
				2015	(__v4sf) __W,
				2016	(__mmask8) __U);
				2017	}
				2018
				2019	static __inline__ __m128 __DEFAULT_FN_ATTRS
				2020	_mm_maskz_add_ps (__mmask16 __U, __m128 __A, __m128 __B) {
				2021	return (__m128) __builtin_ia32_addps128_mask ((__v4sf) __A,
				2022	(__v4sf) __B,
				2023	(__v4sf)
				2024	_mm_setzero_ps (),
				2025	(__mmask8) __U);
				2026	}
				2027
				2028	static __inline__ __m256 __DEFAULT_FN_ATTRS
				2029	_mm256_mask_add_ps (__m256 __W, __mmask16 __U, __m256 __A, __m256 __B) {
				2030	return (__m256) __builtin_ia32_addps256_mask ((__v8sf) __A,
				2031	(__v8sf) __B,
				2032	(__v8sf) __W,
				2033	(__mmask8) __U);
				2034	}
				2035
				2036	static __inline__ __m256 __DEFAULT_FN_ATTRS
				2037	_mm256_maskz_add_ps (__mmask16 __U, __m256 __A, __m256 __B) {
				2038	return (__m256) __builtin_ia32_addps256_mask ((__v8sf) __A,
				2039	(__v8sf) __B,
				2040	(__v8sf)
				2041	_mm256_setzero_ps (),
				2042	(__mmask8) __U);
				2043	}
				2044
				2045	static __inline__ __m128i __DEFAULT_FN_ATTRS
				2046	_mm_mask_blend_epi32 (__mmask8 __U, __m128i __A, __m128i __W) {
				2047	return (__m128i) __builtin_ia32_blendmd_128_mask ((__v4si) __A,
				2048	(__v4si) __W,
				2049	(__mmask8) __U);
				2050	}
				2051
				2052	static __inline__ __m256i __DEFAULT_FN_ATTRS
				2053	_mm256_mask_blend_epi32 (__mmask8 __U, __m256i __A, __m256i __W) {
				2054	return (__m256i) __builtin_ia32_blendmd_256_mask ((__v8si) __A,
				2055	(__v8si) __W,
				2056	(__mmask8) __U);
				2057	}
				2058
				2059	static __inline__ __m128d __DEFAULT_FN_ATTRS
				2060	_mm_mask_blend_pd (__mmask8 __U, __m128d __A, __m128d __W) {
				2061	return (__m128d) __builtin_ia32_blendmpd_128_mask ((__v2df) __A,
				2062	(__v2df) __W,
				2063	(__mmask8) __U);
				2064	}
				2065
				2066	static __inline__ __m256d __DEFAULT_FN_ATTRS
				2067	_mm256_mask_blend_pd (__mmask8 __U, __m256d __A, __m256d __W) {
				2068	return (__m256d) __builtin_ia32_blendmpd_256_mask ((__v4df) __A,
				2069	(__v4df) __W,
				2070	(__mmask8) __U);
				2071	}
				2072
				2073	static __inline__ __m128 __DEFAULT_FN_ATTRS
				2074	_mm_mask_blend_ps (__mmask8 __U, __m128 __A, __m128 __W) {
				2075	return (__m128) __builtin_ia32_blendmps_128_mask ((__v4sf) __A,
				2076	(__v4sf) __W,
				2077	(__mmask8) __U);
				2078	}
				2079
				2080	static __inline__ __m256 __DEFAULT_FN_ATTRS
				2081	_mm256_mask_blend_ps (__mmask8 __U, __m256 __A, __m256 __W) {
				2082	return (__m256) __builtin_ia32_blendmps_256_mask ((__v8sf) __A,
				2083	(__v8sf) __W,
				2084	(__mmask8) __U);
				2085	}
				2086
				2087	static __inline__ __m128i __DEFAULT_FN_ATTRS
				2088	_mm_mask_blend_epi64 (__mmask8 __U, __m128i __A, __m128i __W) {
				2089	return (__m128i) __builtin_ia32_blendmq_128_mask ((__v2di) __A,
				2090	(__v2di) __W,
				2091	(__mmask8) __U);
				2092	}
				2093
				2094	static __inline__ __m256i __DEFAULT_FN_ATTRS
				2095	_mm256_mask_blend_epi64 (__mmask8 __U, __m256i __A, __m256i __W) {
				2096	return (__m256i) __builtin_ia32_blendmq_256_mask ((__v4di) __A,
				2097	(__v4di) __W,
				2098	(__mmask8) __U);
				2099	}
				2100
				2101	static __inline__ __m128d __DEFAULT_FN_ATTRS
				2102	_mm_mask_compress_pd (__m128d __W, __mmask8 __U, __m128d __A) {
				2103	return (__m128d) __builtin_ia32_compressdf128_mask ((__v2df) __A,
				2104	(__v2df) __W,
				2105	(__mmask8) __U);
				2106	}
				2107
				2108	static __inline__ __m128d __DEFAULT_FN_ATTRS
				2109	_mm_maskz_compress_pd (__mmask8 __U, __m128d __A) {
				2110	return (__m128d) __builtin_ia32_compressdf128_mask ((__v2df) __A,
				2111	(__v2df)
				2112	_mm_setzero_pd (),
				2113	(__mmask8) __U);
				2114	}
				2115
				2116	static __inline__ __m256d __DEFAULT_FN_ATTRS
				2117	_mm256_mask_compress_pd (__m256d __W, __mmask8 __U, __m256d __A) {
				2118	return (__m256d) __builtin_ia32_compressdf256_mask ((__v4df) __A,
				2119	(__v4df) __W,
				2120	(__mmask8) __U);
				2121	}
				2122
				2123	static __inline__ __m256d __DEFAULT_FN_ATTRS
				2124	_mm256_maskz_compress_pd (__mmask8 __U, __m256d __A) {
				2125	return (__m256d) __builtin_ia32_compressdf256_mask ((__v4df) __A,
				2126	(__v4df)
				2127	_mm256_setzero_pd (),
				2128	(__mmask8) __U);
				2129	}
				2130
				2131	static __inline__ __m128i __DEFAULT_FN_ATTRS
				2132	_mm_mask_compress_epi64 (__m128i __W, __mmask8 __U, __m128i __A) {
				2133	return (__m128i) __builtin_ia32_compressdi128_mask ((__v2di) __A,
				2134	(__v2di) __W,
				2135	(__mmask8) __U);
				2136	}
				2137
				2138	static __inline__ __m128i __DEFAULT_FN_ATTRS
				2139	_mm_maskz_compress_epi64 (__mmask8 __U, __m128i __A) {
				2140	return (__m128i) __builtin_ia32_compressdi128_mask ((__v2di) __A,
				2141	(__v2di)
				2142	_mm_setzero_si128 (),
				2143	(__mmask8) __U);
				2144	}
				2145
				2146	static __inline__ __m256i __DEFAULT_FN_ATTRS
				2147	_mm256_mask_compress_epi64 (__m256i __W, __mmask8 __U, __m256i __A) {
				2148	return (__m256i) __builtin_ia32_compressdi256_mask ((__v4di) __A,
				2149	(__v4di) __W,
				2150	(__mmask8) __U);
				2151	}
				2152
				2153	static __inline__ __m256i __DEFAULT_FN_ATTRS
				2154	_mm256_maskz_compress_epi64 (__mmask8 __U, __m256i __A) {
				2155	return (__m256i) __builtin_ia32_compressdi256_mask ((__v4di) __A,
				2156	(__v4di)
				2157	_mm256_setzero_si256 (),
				2158	(__mmask8) __U);
				2159	}
				2160
				2161	static __inline__ __m128 __DEFAULT_FN_ATTRS
				2162	_mm_mask_compress_ps (__m128 __W, __mmask8 __U, __m128 __A) {
				2163	return (__m128) __builtin_ia32_compresssf128_mask ((__v4sf) __A,
				2164	(__v4sf) __W,
				2165	(__mmask8) __U);
				2166	}
				2167
				2168	static __inline__ __m128 __DEFAULT_FN_ATTRS
				2169	_mm_maskz_compress_ps (__mmask8 __U, __m128 __A) {
				2170	return (__m128) __builtin_ia32_compresssf128_mask ((__v4sf) __A,
				2171	(__v4sf)
				2172	_mm_setzero_ps (),
				2173	(__mmask8) __U);
				2174	}
				2175
				2176	static __inline__ __m256 __DEFAULT_FN_ATTRS
				2177	_mm256_mask_compress_ps (__m256 __W, __mmask8 __U, __m256 __A) {
				2178	return (__m256) __builtin_ia32_compresssf256_mask ((__v8sf) __A,
				2179	(__v8sf) __W,
				2180	(__mmask8) __U);
				2181	}
				2182
				2183	static __inline__ __m256 __DEFAULT_FN_ATTRS
				2184	_mm256_maskz_compress_ps (__mmask8 __U, __m256 __A) {
				2185	return (__m256) __builtin_ia32_compresssf256_mask ((__v8sf) __A,
				2186	(__v8sf)
				2187	_mm256_setzero_ps (),
				2188	(__mmask8) __U);
				2189	}
				2190
				2191	static __inline__ __m128i __DEFAULT_FN_ATTRS
				2192	_mm_mask_compress_epi32 (__m128i __W, __mmask8 __U, __m128i __A) {
				2193	return (__m128i) __builtin_ia32_compresssi128_mask ((__v4si) __A,
				2194	(__v4si) __W,
				2195	(__mmask8) __U);
				2196	}
				2197
				2198	static __inline__ __m128i __DEFAULT_FN_ATTRS
				2199	_mm_maskz_compress_epi32 (__mmask8 __U, __m128i __A) {
				2200	return (__m128i) __builtin_ia32_compresssi128_mask ((__v4si) __A,
				2201	(__v4si)
				2202	_mm_setzero_si128 (),
				2203	(__mmask8) __U);
				2204	}
				2205
				2206	static __inline__ __m256i __DEFAULT_FN_ATTRS
				2207	_mm256_mask_compress_epi32 (__m256i __W, __mmask8 __U, __m256i __A) {
				2208	return (__m256i) __builtin_ia32_compresssi256_mask ((__v8si) __A,
				2209	(__v8si) __W,
				2210	(__mmask8) __U);
				2211	}
				2212
				2213	static __inline__ __m256i __DEFAULT_FN_ATTRS
				2214	_mm256_maskz_compress_epi32 (__mmask8 __U, __m256i __A) {
				2215	return (__m256i) __builtin_ia32_compresssi256_mask ((__v8si) __A,
				2216	(__v8si)
				2217	_mm256_setzero_si256 (),
				2218	(__mmask8) __U);
				2219	}
				2220
				2221	static __inline__ void __DEFAULT_FN_ATTRS
				2222	_mm_mask_compressstoreu_pd (void *__P, __mmask8 __U, __m128d __A) {
				2223	__builtin_ia32_compressstoredf128_mask ((__v2df *) __P,
				2224	(__v2df) __A,
				2225	(__mmask8) __U);
				2226	}
				2227
				2228	static __inline__ void __DEFAULT_FN_ATTRS
				2229	_mm256_mask_compressstoreu_pd (void *__P, __mmask8 __U, __m256d __A) {
				2230	__builtin_ia32_compressstoredf256_mask ((__v4df *) __P,
				2231	(__v4df) __A,
				2232	(__mmask8) __U);
				2233	}
				2234
				2235	static __inline__ void __DEFAULT_FN_ATTRS
				2236	_mm_mask_compressstoreu_epi64 (void *__P, __mmask8 __U, __m128i __A) {
				2237	__builtin_ia32_compressstoredi128_mask ((__v2di *) __P,
				2238	(__v2di) __A,
				2239	(__mmask8) __U);
				2240	}
				2241
				2242	static __inline__ void __DEFAULT_FN_ATTRS
				2243	_mm256_mask_compressstoreu_epi64 (void *__P, __mmask8 __U, __m256i __A) {
				2244	__builtin_ia32_compressstoredi256_mask ((__v4di *) __P,
				2245	(__v4di) __A,
				2246	(__mmask8) __U);
				2247	}
				2248
				2249	static __inline__ void __DEFAULT_FN_ATTRS
				2250	_mm_mask_compressstoreu_ps (void *__P, __mmask8 __U, __m128 __A) {
				2251	__builtin_ia32_compressstoresf128_mask ((__v4sf *) __P,
				2252	(__v4sf) __A,
				2253	(__mmask8) __U);
				2254	}
				2255
				2256	static __inline__ void __DEFAULT_FN_ATTRS
				2257	_mm256_mask_compressstoreu_ps (void *__P, __mmask8 __U, __m256 __A) {
				2258	__builtin_ia32_compressstoresf256_mask ((__v8sf *) __P,
				2259	(__v8sf) __A,
				2260	(__mmask8) __U);
				2261	}
				2262
				2263	static __inline__ void __DEFAULT_FN_ATTRS
				2264	_mm_mask_compressstoreu_epi32 (void *__P, __mmask8 __U, __m128i __A) {
				2265	__builtin_ia32_compressstoresi128_mask ((__v4si *) __P,
				2266	(__v4si) __A,
				2267	(__mmask8) __U);
				2268	}
				2269
				2270	static __inline__ void __DEFAULT_FN_ATTRS
				2271	_mm256_mask_compressstoreu_epi32 (void *__P, __mmask8 __U, __m256i __A) {
				2272	__builtin_ia32_compressstoresi256_mask ((__v8si *) __P,
				2273	(__v8si) __A,
				2274	(__mmask8) __U);
				2275	}
				2276
				2277	static __inline__ __m128d __DEFAULT_FN_ATTRS
				2278	_mm_mask_cvtepi32_pd (__m128d __W, __mmask8 __U, __m128i __A) {
				2279	return (__m128d) __builtin_ia32_cvtdq2pd128_mask ((__v4si) __A,
				2280	(__v2df) __W,
				2281	(__mmask8) __U);
				2282	}
				2283
				2284	static __inline__ __m128d __DEFAULT_FN_ATTRS
				2285	_mm_maskz_cvtepi32_pd (__mmask8 __U, __m128i __A) {
				2286	return (__m128d) __builtin_ia32_cvtdq2pd128_mask ((__v4si) __A,
				2287	(__v2df)
				2288	_mm_setzero_pd (),
				2289	(__mmask8) __U);
				2290	}
				2291
				2292	static __inline__ __m256d __DEFAULT_FN_ATTRS
				2293	_mm256_mask_cvtepi32_pd (__m256d __W, __mmask8 __U, __m128i __A) {
				2294	return (__m256d) __builtin_ia32_cvtdq2pd256_mask ((__v4si) __A,
				2295	(__v4df) __W,
				2296	(__mmask8) __U);
				2297	}
				2298
				2299	static __inline__ __m256d __DEFAULT_FN_ATTRS
				2300	_mm256_maskz_cvtepi32_pd (__mmask8 __U, __m128i __A) {
				2301	return (__m256d) __builtin_ia32_cvtdq2pd256_mask ((__v4si) __A,
				2302	(__v4df)
				2303	_mm256_setzero_pd (),
				2304	(__mmask8) __U);
				2305	}
				2306
				2307	static __inline__ __m128 __DEFAULT_FN_ATTRS
				2308	_mm_mask_cvtepi32_ps (__m128 __W, __mmask8 __U, __m128i __A) {
				2309	return (__m128) __builtin_ia32_cvtdq2ps128_mask ((__v4si) __A,
				2310	(__v4sf) __W,
				2311	(__mmask8) __U);
				2312	}
				2313
				2314	static __inline__ __m128 __DEFAULT_FN_ATTRS
				2315	_mm_maskz_cvtepi32_ps (__mmask16 __U, __m128i __A) {
				2316	return (__m128) __builtin_ia32_cvtdq2ps128_mask ((__v4si) __A,
				2317	(__v4sf)
				2318	_mm_setzero_ps (),
				2319	(__mmask8) __U);
				2320	}
				2321
				2322	static __inline__ __m256 __DEFAULT_FN_ATTRS
				2323	_mm256_mask_cvtepi32_ps (__m256 __W, __mmask8 __U, __m256i __A) {
				2324	return (__m256) __builtin_ia32_cvtdq2ps256_mask ((__v8si) __A,
				2325	(__v8sf) __W,
				2326	(__mmask8) __U);
				2327	}
				2328
				2329	static __inline__ __m256 __DEFAULT_FN_ATTRS
				2330	_mm256_maskz_cvtepi32_ps (__mmask16 __U, __m256i __A) {
				2331	return (__m256) __builtin_ia32_cvtdq2ps256_mask ((__v8si) __A,
				2332	(__v8sf)
				2333	_mm256_setzero_ps (),
				2334	(__mmask8) __U);
				2335	}
				2336
				2337	static __inline__ __m128i __DEFAULT_FN_ATTRS
				2338	_mm_mask_cvtpd_epi32 (__m128i __W, __mmask8 __U, __m128d __A) {
				2339	return (__m128i) __builtin_ia32_cvtpd2dq128_mask ((__v2df) __A,
				2340	(__v4si) __W,
				2341	(__mmask8) __U);
				2342	}
				2343
				2344	static __inline__ __m128i __DEFAULT_FN_ATTRS
				2345	_mm_maskz_cvtpd_epi32 (__mmask8 __U, __m128d __A) {
				2346	return (__m128i) __builtin_ia32_cvtpd2dq128_mask ((__v2df) __A,
				2347	(__v4si)
				2348	_mm_setzero_si128 (),
				2349	(__mmask8) __U);
				2350	}
				2351
				2352	static __inline__ __m128i __DEFAULT_FN_ATTRS
				2353	_mm256_mask_cvtpd_epi32 (__m128i __W, __mmask8 __U, __m256d __A) {
				2354	return (__m128i) __builtin_ia32_cvtpd2dq256_mask ((__v4df) __A,
				2355	(__v4si) __W,
				2356	(__mmask8) __U);
				2357	}
				2358
				2359	static __inline__ __m128i __DEFAULT_FN_ATTRS
				2360	_mm256_maskz_cvtpd_epi32 (__mmask8 __U, __m256d __A) {
				2361	return (__m128i) __builtin_ia32_cvtpd2dq256_mask ((__v4df) __A,
				2362	(__v4si)
				2363	_mm_setzero_si128 (),
				2364	(__mmask8) __U);
				2365	}
				2366
				2367	static __inline__ __m128 __DEFAULT_FN_ATTRS
				2368	_mm_mask_cvtpd_ps (__m128 __W, __mmask8 __U, __m128d __A) {
				2369	return (__m128) __builtin_ia32_cvtpd2ps_mask ((__v2df) __A,
				2370	(__v4sf) __W,
				2371	(__mmask8) __U);
				2372	}
				2373
				2374	static __inline__ __m128 __DEFAULT_FN_ATTRS
				2375	_mm_maskz_cvtpd_ps (__mmask8 __U, __m128d __A) {
				2376	return (__m128) __builtin_ia32_cvtpd2ps_mask ((__v2df) __A,
				2377	(__v4sf)
				2378	_mm_setzero_ps (),
				2379	(__mmask8) __U);
				2380	}
				2381
				2382	static __inline__ __m128 __DEFAULT_FN_ATTRS
				2383	_mm256_mask_cvtpd_ps (__m128 __W, __mmask8 __U, __m256d __A) {
				2384	return (__m128) __builtin_ia32_cvtpd2ps256_mask ((__v4df) __A,
				2385	(__v4sf) __W,
				2386	(__mmask8) __U);
				2387	}
				2388
				2389	static __inline__ __m128 __DEFAULT_FN_ATTRS
				2390	_mm256_maskz_cvtpd_ps (__mmask8 __U, __m256d __A) {
				2391	return (__m128) __builtin_ia32_cvtpd2ps256_mask ((__v4df) __A,
				2392	(__v4sf)
				2393	_mm_setzero_ps (),
				2394	(__mmask8) __U);
				2395	}
				2396
				2397	static __inline__ __m128i __DEFAULT_FN_ATTRS
				2398	_mm_cvtpd_epu32 (__m128d __A) {
				2399	return (__m128i) __builtin_ia32_cvtpd2udq128_mask ((__v2df) __A,
				2400	(__v4si)
				2401	_mm_setzero_si128 (),
				2402	(__mmask8) -1);
				2403	}
				2404
				2405	static __inline__ __m128i __DEFAULT_FN_ATTRS
				2406	_mm_mask_cvtpd_epu32 (__m128i __W, __mmask8 __U, __m128d __A) {
				2407	return (__m128i) __builtin_ia32_cvtpd2udq128_mask ((__v2df) __A,
				2408	(__v4si) __W,
				2409	(__mmask8) __U);
				2410	}
				2411
				2412	static __inline__ __m128i __DEFAULT_FN_ATTRS
				2413	_mm_maskz_cvtpd_epu32 (__mmask8 __U, __m128d __A) {
				2414	return (__m128i) __builtin_ia32_cvtpd2udq128_mask ((__v2df) __A,
				2415	(__v4si)
				2416	_mm_setzero_si128 (),
				2417	(__mmask8) __U);
				2418	}
				2419
				2420	static __inline__ __m128i __DEFAULT_FN_ATTRS
				2421	_mm256_cvtpd_epu32 (__m256d __A) {
				2422	return (__m128i) __builtin_ia32_cvtpd2udq256_mask ((__v4df) __A,
				2423	(__v4si)
				2424	_mm_setzero_si128 (),
				2425	(__mmask8) -1);
				2426	}
				2427
				2428	static __inline__ __m128i __DEFAULT_FN_ATTRS
				2429	_mm256_mask_cvtpd_epu32 (__m128i __W, __mmask8 __U, __m256d __A) {
				2430	return (__m128i) __builtin_ia32_cvtpd2udq256_mask ((__v4df) __A,
				2431	(__v4si) __W,
				2432	(__mmask8) __U);
				2433	}
				2434
				2435	static __inline__ __m128i __DEFAULT_FN_ATTRS
				2436	_mm256_maskz_cvtpd_epu32 (__mmask8 __U, __m256d __A) {
				2437	return (__m128i) __builtin_ia32_cvtpd2udq256_mask ((__v4df) __A,
				2438	(__v4si)
				2439	_mm_setzero_si128 (),
				2440	(__mmask8) __U);
				2441	}
				2442
				2443	static __inline__ __m128i __DEFAULT_FN_ATTRS
				2444	_mm_mask_cvtps_epi32 (__m128i __W, __mmask8 __U, __m128 __A) {
				2445	return (__m128i) __builtin_ia32_cvtps2dq128_mask ((__v4sf) __A,
				2446	(__v4si) __W,
				2447	(__mmask8) __U);
				2448	}
				2449
				2450	static __inline__ __m128i __DEFAULT_FN_ATTRS
				2451	_mm_maskz_cvtps_epi32 (__mmask8 __U, __m128 __A) {
				2452	return (__m128i) __builtin_ia32_cvtps2dq128_mask ((__v4sf) __A,
				2453	(__v4si)
				2454	_mm_setzero_si128 (),
				2455	(__mmask8) __U);
				2456	}
				2457
				2458	static __inline__ __m256i __DEFAULT_FN_ATTRS
				2459	_mm256_mask_cvtps_epi32 (__m256i __W, __mmask8 __U, __m256 __A) {
				2460	return (__m256i) __builtin_ia32_cvtps2dq256_mask ((__v8sf) __A,
				2461	(__v8si) __W,
				2462	(__mmask8) __U);
				2463	}
				2464
				2465	static __inline__ __m256i __DEFAULT_FN_ATTRS
				2466	_mm256_maskz_cvtps_epi32 (__mmask8 __U, __m256 __A) {
				2467	return (__m256i) __builtin_ia32_cvtps2dq256_mask ((__v8sf) __A,
				2468	(__v8si)
				2469	_mm256_setzero_si256 (),
				2470	(__mmask8) __U);
				2471	}
				2472
				2473	static __inline__ __m128d __DEFAULT_FN_ATTRS
				2474	_mm_mask_cvtps_pd (__m128d __W, __mmask8 __U, __m128 __A) {
				2475	return (__m128d) __builtin_ia32_cvtps2pd128_mask ((__v4sf) __A,
				2476	(__v2df) __W,
				2477	(__mmask8) __U);
				2478	}
				2479
				2480	static __inline__ __m128d __DEFAULT_FN_ATTRS
				2481	_mm_maskz_cvtps_pd (__mmask8 __U, __m128 __A) {
				2482	return (__m128d) __builtin_ia32_cvtps2pd128_mask ((__v4sf) __A,
				2483	(__v2df)
				2484	_mm_setzero_pd (),
				2485	(__mmask8) __U);
				2486	}
				2487
				2488	static __inline__ __m256d __DEFAULT_FN_ATTRS
				2489	_mm256_mask_cvtps_pd (__m256d __W, __mmask8 __U, __m128 __A) {
				2490	return (__m256d) __builtin_ia32_cvtps2pd256_mask ((__v4sf) __A,
				2491	(__v4df) __W,
				2492	(__mmask8) __U);
				2493	}
				2494
				2495	static __inline__ __m256d __DEFAULT_FN_ATTRS
				2496	_mm256_maskz_cvtps_pd (__mmask8 __U, __m128 __A) {
				2497	return (__m256d) __builtin_ia32_cvtps2pd256_mask ((__v4sf) __A,
				2498	(__v4df)
				2499	_mm256_setzero_pd (),
				2500	(__mmask8) __U);
				2501	}
				2502
				2503	static __inline__ __m128i __DEFAULT_FN_ATTRS
				2504	_mm_cvtps_epu32 (__m128 __A) {
				2505	return (__m128i) __builtin_ia32_cvtps2udq128_mask ((__v4sf) __A,
				2506	(__v4si)
				2507	_mm_setzero_si128 (),
				2508	(__mmask8) -1);
				2509	}
				2510
				2511	static __inline__ __m128i __DEFAULT_FN_ATTRS
				2512	_mm_mask_cvtps_epu32 (__m128i __W, __mmask8 __U, __m128 __A) {
				2513	return (__m128i) __builtin_ia32_cvtps2udq128_mask ((__v4sf) __A,
				2514	(__v4si) __W,
				2515	(__mmask8) __U);
				2516	}
				2517
				2518	static __inline__ __m128i __DEFAULT_FN_ATTRS
				2519	_mm_maskz_cvtps_epu32 (__mmask8 __U, __m128 __A) {
				2520	return (__m128i) __builtin_ia32_cvtps2udq128_mask ((__v4sf) __A,
				2521	(__v4si)
				2522	_mm_setzero_si128 (),
				2523	(__mmask8) __U);
				2524	}
				2525
				2526	static __inline__ __m256i __DEFAULT_FN_ATTRS
				2527	_mm256_cvtps_epu32 (__m256 __A) {
				2528	return (__m256i) __builtin_ia32_cvtps2udq256_mask ((__v8sf) __A,
				2529	(__v8si)
				2530	_mm256_setzero_si256 (),
				2531	(__mmask8) -1);
				2532	}
				2533
				2534	static __inline__ __m256i __DEFAULT_FN_ATTRS
				2535	_mm256_mask_cvtps_epu32 (__m256i __W, __mmask8 __U, __m256 __A) {
				2536	return (__m256i) __builtin_ia32_cvtps2udq256_mask ((__v8sf) __A,
				2537	(__v8si) __W,
				2538	(__mmask8) __U);
				2539	}
				2540
				2541	static __inline__ __m256i __DEFAULT_FN_ATTRS
				2542	_mm256_maskz_cvtps_epu32 (__mmask8 __U, __m256 __A) {
				2543	return (__m256i) __builtin_ia32_cvtps2udq256_mask ((__v8sf) __A,
				2544	(__v8si)
				2545	_mm256_setzero_si256 (),
				2546	(__mmask8) __U);
				2547	}
				2548
				2549	static __inline__ __m128i __DEFAULT_FN_ATTRS
				2550	_mm_mask_cvttpd_epi32 (__m128i __W, __mmask8 __U, __m128d __A) {
				2551	return (__m128i) __builtin_ia32_cvttpd2dq128_mask ((__v2df) __A,
				2552	(__v4si) __W,
				2553	(__mmask8) __U);
				2554	}
				2555
				2556	static __inline__ __m128i __DEFAULT_FN_ATTRS
				2557	_mm_maskz_cvttpd_epi32 (__mmask8 __U, __m128d __A) {
				2558	return (__m128i) __builtin_ia32_cvttpd2dq128_mask ((__v2df) __A,
				2559	(__v4si)
				2560	_mm_setzero_si128 (),
				2561	(__mmask8) __U);
				2562	}
				2563
				2564	static __inline__ __m128i __DEFAULT_FN_ATTRS
				2565	_mm256_mask_cvttpd_epi32 (__m128i __W, __mmask8 __U, __m256d __A) {
				2566	return (__m128i) __builtin_ia32_cvttpd2dq256_mask ((__v4df) __A,
				2567	(__v4si) __W,
				2568	(__mmask8) __U);
				2569	}
				2570
				2571	static __inline__ __m128i __DEFAULT_FN_ATTRS
				2572	_mm256_maskz_cvttpd_epi32 (__mmask8 __U, __m256d __A) {
				2573	return (__m128i) __builtin_ia32_cvttpd2dq256_mask ((__v4df) __A,
				2574	(__v4si)
				2575	_mm_setzero_si128 (),
				2576	(__mmask8) __U);
				2577	}
				2578
				2579	static __inline__ __m128i __DEFAULT_FN_ATTRS
				2580	_mm_cvttpd_epu32 (__m128d __A) {
				2581	return (__m128i) __builtin_ia32_cvttpd2udq128_mask ((__v2df) __A,
				2582	(__v4si)
				2583	_mm_setzero_si128 (),
				2584	(__mmask8) -1);
				2585	}
				2586
				2587	static __inline__ __m128i __DEFAULT_FN_ATTRS
				2588	_mm_mask_cvttpd_epu32 (__m128i __W, __mmask8 __U, __m128d __A) {
				2589	return (__m128i) __builtin_ia32_cvttpd2udq128_mask ((__v2df) __A,
				2590	(__v4si) __W,
				2591	(__mmask8) __U);
				2592	}
				2593
				2594	static __inline__ __m128i __DEFAULT_FN_ATTRS
				2595	_mm_maskz_cvttpd_epu32 (__mmask8 __U, __m128d __A) {
				2596	return (__m128i) __builtin_ia32_cvttpd2udq128_mask ((__v2df) __A,
				2597	(__v4si)
				2598	_mm_setzero_si128 (),
				2599	(__mmask8) __U);
				2600	}
				2601
				2602	static __inline__ __m128i __DEFAULT_FN_ATTRS
				2603	_mm256_cvttpd_epu32 (__m256d __A) {
				2604	return (__m128i) __builtin_ia32_cvttpd2udq256_mask ((__v4df) __A,
				2605	(__v4si)
				2606	_mm_setzero_si128 (),
				2607	(__mmask8) -1);
				2608	}
				2609
				2610	static __inline__ __m128i __DEFAULT_FN_ATTRS
				2611	_mm256_mask_cvttpd_epu32 (__m128i __W, __mmask8 __U, __m256d __A) {
				2612	return (__m128i) __builtin_ia32_cvttpd2udq256_mask ((__v4df) __A,
				2613	(__v4si) __W,
				2614	(__mmask8) __U);
				2615	}
				2616
				2617	static __inline__ __m128i __DEFAULT_FN_ATTRS
				2618	_mm256_maskz_cvttpd_epu32 (__mmask8 __U, __m256d __A) {
				2619	return (__m128i) __builtin_ia32_cvttpd2udq256_mask ((__v4df) __A,
				2620	(__v4si)
				2621	_mm_setzero_si128 (),
				2622	(__mmask8) __U);
				2623	}
				2624
				2625	static __inline__ __m128i __DEFAULT_FN_ATTRS
				2626	_mm_mask_cvttps_epi32 (__m128i __W, __mmask8 __U, __m128 __A) {
				2627	return (__m128i) __builtin_ia32_cvttps2dq128_mask ((__v4sf) __A,
				2628	(__v4si) __W,
				2629	(__mmask8) __U);
				2630	}
				2631
				2632	static __inline__ __m128i __DEFAULT_FN_ATTRS
				2633	_mm_maskz_cvttps_epi32 (__mmask8 __U, __m128 __A) {
				2634	return (__m128i) __builtin_ia32_cvttps2dq128_mask ((__v4sf) __A,
				2635	(__v4si)
				2636	_mm_setzero_si128 (),
				2637	(__mmask8) __U);
				2638	}
				2639
				2640	static __inline__ __m256i __DEFAULT_FN_ATTRS
				2641	_mm256_mask_cvttps_epi32 (__m256i __W, __mmask8 __U, __m256 __A) {
				2642	return (__m256i) __builtin_ia32_cvttps2dq256_mask ((__v8sf) __A,
				2643	(__v8si) __W,
				2644	(__mmask8) __U);
				2645	}
				2646
				2647	static __inline__ __m256i __DEFAULT_FN_ATTRS
				2648	_mm256_maskz_cvttps_epi32 (__mmask8 __U, __m256 __A) {
				2649	return (__m256i) __builtin_ia32_cvttps2dq256_mask ((__v8sf) __A,
				2650	(__v8si)
				2651	_mm256_setzero_si256 (),
				2652	(__mmask8) __U);
				2653	}
				2654
				2655	static __inline__ __m128i __DEFAULT_FN_ATTRS
				2656	_mm_cvttps_epu32 (__m128 __A) {
				2657	return (__m128i) __builtin_ia32_cvttps2udq128_mask ((__v4sf) __A,
				2658	(__v4si)
				2659	_mm_setzero_si128 (),
				2660	(__mmask8) -1);
				2661	}
				2662
				2663	static __inline__ __m128i __DEFAULT_FN_ATTRS
				2664	_mm_mask_cvttps_epu32 (__m128i __W, __mmask8 __U, __m128 __A) {
				2665	return (__m128i) __builtin_ia32_cvttps2udq128_mask ((__v4sf) __A,
				2666	(__v4si) __W,
				2667	(__mmask8) __U);
				2668	}
				2669
				2670	static __inline__ __m128i __DEFAULT_FN_ATTRS
				2671	_mm_maskz_cvttps_epu32 (__mmask8 __U, __m128 __A) {
				2672	return (__m128i) __builtin_ia32_cvttps2udq128_mask ((__v4sf) __A,
				2673	(__v4si)
				2674	_mm_setzero_si128 (),
				2675	(__mmask8) __U);
				2676	}
				2677
				2678	static __inline__ __m256i __DEFAULT_FN_ATTRS
				2679	_mm256_cvttps_epu32 (__m256 __A) {
				2680	return (__m256i) __builtin_ia32_cvttps2udq256_mask ((__v8sf) __A,
				2681	(__v8si)
				2682	_mm256_setzero_si256 (),
				2683	(__mmask8) -1);
				2684	}
				2685
				2686	static __inline__ __m256i __DEFAULT_FN_ATTRS
				2687	_mm256_mask_cvttps_epu32 (__m256i __W, __mmask8 __U, __m256 __A) {
				2688	return (__m256i) __builtin_ia32_cvttps2udq256_mask ((__v8sf) __A,
				2689	(__v8si) __W,
				2690	(__mmask8) __U);
				2691	}
				2692
				2693	static __inline__ __m256i __DEFAULT_FN_ATTRS
				2694	_mm256_maskz_cvttps_epu32 (__mmask8 __U, __m256 __A) {
				2695	return (__m256i) __builtin_ia32_cvttps2udq256_mask ((__v8sf) __A,
				2696	(__v8si)
				2697	_mm256_setzero_si256 (),
				2698	(__mmask8) __U);
				2699	}
				2700
				2701	static __inline__ __m128d __DEFAULT_FN_ATTRS
				2702	_mm_cvtepu32_pd (__m128i __A) {
				2703	return (__m128d) __builtin_ia32_cvtudq2pd128_mask ((__v4si) __A,
				2704	(__v2df)
				2705	_mm_setzero_pd (),
				2706	(__mmask8) -1);
				2707	}
				2708
				2709	static __inline__ __m128d __DEFAULT_FN_ATTRS
				2710	_mm_mask_cvtepu32_pd (__m128d __W, __mmask8 __U, __m128i __A) {
				2711	return (__m128d) __builtin_ia32_cvtudq2pd128_mask ((__v4si) __A,
				2712	(__v2df) __W,
				2713	(__mmask8) __U);
				2714	}
				2715
				2716	static __inline__ __m128d __DEFAULT_FN_ATTRS
				2717	_mm_maskz_cvtepu32_pd (__mmask8 __U, __m128i __A) {
				2718	return (__m128d) __builtin_ia32_cvtudq2pd128_mask ((__v4si) __A,
				2719	(__v2df)
				2720	_mm_setzero_pd (),
				2721	(__mmask8) __U);
				2722	}
				2723
				2724	static __inline__ __m256d __DEFAULT_FN_ATTRS
				2725	_mm256_cvtepu32_pd (__m128i __A) {
				2726	return (__m256d) __builtin_ia32_cvtudq2pd256_mask ((__v4si) __A,
				2727	(__v4df)
				2728	_mm256_setzero_pd (),
				2729	(__mmask8) -1);
				2730	}
				2731
				2732	static __inline__ __m256d __DEFAULT_FN_ATTRS
				2733	_mm256_mask_cvtepu32_pd (__m256d __W, __mmask8 __U, __m128i __A) {
				2734	return (__m256d) __builtin_ia32_cvtudq2pd256_mask ((__v4si) __A,
				2735	(__v4df) __W,
				2736	(__mmask8) __U);
				2737	}
				2738
				2739	static __inline__ __m256d __DEFAULT_FN_ATTRS
				2740	_mm256_maskz_cvtepu32_pd (__mmask8 __U, __m128i __A) {
				2741	return (__m256d) __builtin_ia32_cvtudq2pd256_mask ((__v4si) __A,
				2742	(__v4df)
				2743	_mm256_setzero_pd (),
				2744	(__mmask8) __U);
				2745	}
				2746
				2747	static __inline__ __m128 __DEFAULT_FN_ATTRS
				2748	_mm_cvtepu32_ps (__m128i __A) {
				2749	return (__m128) __builtin_ia32_cvtudq2ps128_mask ((__v4si) __A,
				2750	(__v4sf)
				2751	_mm_setzero_ps (),
				2752	(__mmask8) -1);
				2753	}
				2754
				2755	static __inline__ __m128 __DEFAULT_FN_ATTRS
				2756	_mm_mask_cvtepu32_ps (__m128 __W, __mmask8 __U, __m128i __A) {
				2757	return (__m128) __builtin_ia32_cvtudq2ps128_mask ((__v4si) __A,
				2758	(__v4sf) __W,
				2759	(__mmask8) __U);
				2760	}
				2761
				2762	static __inline__ __m128 __DEFAULT_FN_ATTRS
				2763	_mm_maskz_cvtepu32_ps (__mmask8 __U, __m128i __A) {
				2764	return (__m128) __builtin_ia32_cvtudq2ps128_mask ((__v4si) __A,
				2765	(__v4sf)
				2766	_mm_setzero_ps (),
				2767	(__mmask8) __U);
				2768	}
				2769
				2770	static __inline__ __m256 __DEFAULT_FN_ATTRS
				2771	_mm256_cvtepu32_ps (__m256i __A) {
				2772	return (__m256) __builtin_ia32_cvtudq2ps256_mask ((__v8si) __A,
				2773	(__v8sf)
				2774	_mm256_setzero_ps (),
				2775	(__mmask8) -1);
				2776	}
				2777
				2778	static __inline__ __m256 __DEFAULT_FN_ATTRS
				2779	_mm256_mask_cvtepu32_ps (__m256 __W, __mmask8 __U, __m256i __A) {
				2780	return (__m256) __builtin_ia32_cvtudq2ps256_mask ((__v8si) __A,
				2781	(__v8sf) __W,
				2782	(__mmask8) __U);
				2783	}
				2784
				2785	static __inline__ __m256 __DEFAULT_FN_ATTRS
				2786	_mm256_maskz_cvtepu32_ps (__mmask8 __U, __m256i __A) {
				2787	return (__m256) __builtin_ia32_cvtudq2ps256_mask ((__v8si) __A,
				2788	(__v8sf)
				2789	_mm256_setzero_ps (),
				2790	(__mmask8) __U);
				2791	}
				2792
Asaf Badouh	78ee5cc	2015-07-28 10:30:56 +0000	[diff] [blame]	2793	static __inline__ __m128d __DEFAULT_FN_ATTRS
				2794	_mm_mask_div_pd (__m128d __W, __mmask8 __U, __m128d __A, __m128d __B) {
				2795	return (__m128d) __builtin_ia32_divpd_mask ((__v2df) __A,
				2796	(__v2df) __B,
				2797	(__v2df) __W,
				2798	(__mmask8) __U);
				2799	}
				2800
				2801	static __inline__ __m128d __DEFAULT_FN_ATTRS
				2802	_mm_maskz_div_pd (__mmask8 __U, __m128d __A, __m128d __B) {
				2803	return (__m128d) __builtin_ia32_divpd_mask ((__v2df) __A,
				2804	(__v2df) __B,
				2805	(__v2df)
				2806	_mm_setzero_pd (),
				2807	(__mmask8) __U);
				2808	}
				2809
				2810	static __inline__ __m256d __DEFAULT_FN_ATTRS
				2811	_mm256_mask_div_pd (__m256d __W, __mmask8 __U, __m256d __A,
				2812	__m256d __B) {
				2813	return (__m256d) __builtin_ia32_divpd256_mask ((__v4df) __A,
				2814	(__v4df) __B,
				2815	(__v4df) __W,
				2816	(__mmask8) __U);
				2817	}
				2818
				2819	static __inline__ __m256d __DEFAULT_FN_ATTRS
				2820	_mm256_maskz_div_pd (__mmask8 __U, __m256d __A, __m256d __B) {
				2821	return (__m256d) __builtin_ia32_divpd256_mask ((__v4df) __A,
				2822	(__v4df) __B,
				2823	(__v4df)
				2824	_mm256_setzero_pd (),
				2825	(__mmask8) __U);
				2826	}
				2827
				2828	static __inline__ __m128 __DEFAULT_FN_ATTRS
				2829	_mm_mask_div_ps (__m128 __W, __mmask8 __U, __m128 __A, __m128 __B) {
				2830	return (__m128) __builtin_ia32_divps_mask ((__v4sf) __A,
				2831	(__v4sf) __B,
				2832	(__v4sf) __W,
				2833	(__mmask8) __U);
				2834	}
				2835
				2836	static __inline__ __m128 __DEFAULT_FN_ATTRS
				2837	_mm_maskz_div_ps (__mmask8 __U, __m128 __A, __m128 __B) {
				2838	return (__m128) __builtin_ia32_divps_mask ((__v4sf) __A,
				2839	(__v4sf) __B,
				2840	(__v4sf)
				2841	_mm_setzero_ps (),
				2842	(__mmask8) __U);
				2843	}
				2844
				2845	static __inline__ __m256 __DEFAULT_FN_ATTRS
				2846	_mm256_mask_div_ps (__m256 __W, __mmask8 __U, __m256 __A, __m256 __B) {
				2847	return (__m256) __builtin_ia32_divps256_mask ((__v8sf) __A,
				2848	(__v8sf) __B,
				2849	(__v8sf) __W,
				2850	(__mmask8) __U);
				2851	}
				2852
				2853	static __inline__ __m256 __DEFAULT_FN_ATTRS
				2854	_mm256_maskz_div_ps (__mmask8 __U, __m256 __A, __m256 __B) {
				2855	return (__m256) __builtin_ia32_divps256_mask ((__v8sf) __A,
				2856	(__v8sf) __B,
				2857	(__v8sf)
				2858	_mm256_setzero_ps (),
				2859	(__mmask8) __U);
				2860	}
				2861
				2862	static __inline__ __m128d __DEFAULT_FN_ATTRS
				2863	_mm_mask_expand_pd (__m128d __W, __mmask8 __U, __m128d __A) {
				2864	return (__m128d) __builtin_ia32_expanddf128_mask ((__v2df) __A,
				2865	(__v2df) __W,
				2866	(__mmask8) __U);
				2867	}
				2868
				2869	static __inline__ __m128d __DEFAULT_FN_ATTRS
				2870	_mm_maskz_expand_pd (__mmask8 __U, __m128d __A) {
				2871	return (__m128d) __builtin_ia32_expanddf128_mask ((__v2df) __A,
				2872	(__v2df)
				2873	_mm_setzero_pd (),
				2874	(__mmask8) __U);
				2875	}
				2876
				2877	static __inline__ __m256d __DEFAULT_FN_ATTRS
				2878	_mm256_mask_expand_pd (__m256d __W, __mmask8 __U, __m256d __A) {
				2879	return (__m256d) __builtin_ia32_expanddf256_mask ((__v4df) __A,
				2880	(__v4df) __W,
				2881	(__mmask8) __U);
				2882	}
				2883
				2884	static __inline__ __m256d __DEFAULT_FN_ATTRS
				2885	_mm256_maskz_expand_pd (__mmask8 __U, __m256d __A) {
				2886	return (__m256d) __builtin_ia32_expanddf256_mask ((__v4df) __A,
				2887	(__v4df)
				2888	_mm256_setzero_pd (),
				2889	(__mmask8) __U);
				2890	}
				2891
				2892	static __inline__ __m128i __DEFAULT_FN_ATTRS
				2893	_mm_mask_expand_epi64 (__m128i __W, __mmask8 __U, __m128i __A) {
				2894	return (__m128i) __builtin_ia32_expanddi128_mask ((__v2di) __A,
				2895	(__v2di) __W,
				2896	(__mmask8) __U);
				2897	}
				2898
				2899	static __inline__ __m128i __DEFAULT_FN_ATTRS
				2900	_mm_maskz_expand_epi64 (__mmask8 __U, __m128i __A) {
				2901	return (__m128i) __builtin_ia32_expanddi128_mask ((__v2di) __A,
				2902	(__v2di)
				2903	_mm_setzero_si128 (),
				2904	(__mmask8) __U);
				2905	}
				2906
				2907	static __inline__ __m256i __DEFAULT_FN_ATTRS
				2908	_mm256_mask_expand_epi64 (__m256i __W, __mmask8 __U, __m256i __A) {
				2909	return (__m256i) __builtin_ia32_expanddi256_mask ((__v4di) __A,
				2910	(__v4di) __W,
				2911	(__mmask8) __U);
				2912	}
				2913
				2914	static __inline__ __m256i __DEFAULT_FN_ATTRS
				2915	_mm256_maskz_expand_epi64 (__mmask8 __U, __m256i __A) {
				2916	return (__m256i) __builtin_ia32_expanddi256_mask ((__v4di) __A,
				2917	(__v4di)
				2918	_mm256_setzero_si256 (),
				2919	(__mmask8) __U);
				2920	}
				2921
				2922	static __inline__ __m128d __DEFAULT_FN_ATTRS
				2923	_mm_mask_expandloadu_pd (__m128d __W, __mmask8 __U, void const *__P) {
				2924	return (__m128d) __builtin_ia32_expandloaddf128_mask ((__v2df *) __P,
				2925	(__v2df) __W,
				2926	(__mmask8)
				2927	__U);
				2928	}
				2929
				2930	static __inline__ __m128d __DEFAULT_FN_ATTRS
				2931	_mm_maskz_expandloadu_pd (__mmask8 __U, void const *__P) {
				2932	return (__m128d) __builtin_ia32_expandloaddf128_mask ((__v2df *) __P,
				2933	(__v2df)
				2934	_mm_setzero_pd (),
				2935	(__mmask8)
				2936	__U);
				2937	}
				2938
				2939	static __inline__ __m256d __DEFAULT_FN_ATTRS
				2940	_mm256_mask_expandloadu_pd (__m256d __W, __mmask8 __U, void const *__P) {
				2941	return (__m256d) __builtin_ia32_expandloaddf256_mask ((__v4df *) __P,
				2942	(__v4df) __W,
				2943	(__mmask8)
				2944	__U);
				2945	}
				2946
				2947	static __inline__ __m256d __DEFAULT_FN_ATTRS
				2948	_mm256_maskz_expandloadu_pd (__mmask8 __U, void const *__P) {
				2949	return (__m256d) __builtin_ia32_expandloaddf256_mask ((__v4df *) __P,
				2950	(__v4df)
				2951	_mm256_setzero_pd (),
				2952	(__mmask8)
				2953	__U);
				2954	}
				2955
				2956	static __inline__ __m128i __DEFAULT_FN_ATTRS
				2957	_mm_mask_expandloadu_epi64 (__m128i __W, __mmask8 __U, void const *__P) {
				2958	return (__m128i) __builtin_ia32_expandloaddi128_mask ((__v2di *) __P,
				2959	(__v2di) __W,
				2960	(__mmask8)
				2961	__U);
				2962	}
				2963
				2964	static __inline__ __m128i __DEFAULT_FN_ATTRS
				2965	_mm_maskz_expandloadu_epi64 (__mmask8 __U, void const *__P) {
				2966	return (__m128i) __builtin_ia32_expandloaddi128_mask ((__v2di *) __P,
				2967	(__v2di)
				2968	_mm_setzero_si128 (),
				2969	(__mmask8)
				2970	__U);
				2971	}
				2972
				2973	static __inline__ __m256i __DEFAULT_FN_ATTRS
				2974	_mm256_mask_expandloadu_epi64 (__m256i __W, __mmask8 __U,
				2975	void const *__P) {
				2976	return (__m256i) __builtin_ia32_expandloaddi256_mask ((__v4di *) __P,
				2977	(__v4di) __W,
				2978	(__mmask8)
				2979	__U);
				2980	}
				2981
				2982	static __inline__ __m256i __DEFAULT_FN_ATTRS
				2983	_mm256_maskz_expandloadu_epi64 (__mmask8 __U, void const *__P) {
				2984	return (__m256i) __builtin_ia32_expandloaddi256_mask ((__v4di *) __P,
				2985	(__v4di)
				2986	_mm256_setzero_si256 (),
				2987	(__mmask8)
				2988	__U);
				2989	}
				2990
				2991	static __inline__ __m128 __DEFAULT_FN_ATTRS
				2992	_mm_mask_expandloadu_ps (__m128 __W, __mmask8 __U, void const *__P) {
				2993	return (__m128) __builtin_ia32_expandloadsf128_mask ((__v4sf *) __P,
				2994	(__v4sf) __W,
				2995	(__mmask8) __U);
				2996	}
				2997
				2998	static __inline__ __m128 __DEFAULT_FN_ATTRS
				2999	_mm_maskz_expandloadu_ps (__mmask8 __U, void const *__P) {
				3000	return (__m128) __builtin_ia32_expandloadsf128_mask ((__v4sf *) __P,
				3001	(__v4sf)
				3002	_mm_setzero_ps (),
				3003	(__mmask8)
				3004	__U);
				3005	}
				3006
				3007	static __inline__ __m256 __DEFAULT_FN_ATTRS
				3008	_mm256_mask_expandloadu_ps (__m256 __W, __mmask8 __U, void const *__P) {
				3009	return (__m256) __builtin_ia32_expandloadsf256_mask ((__v8sf *) __P,
				3010	(__v8sf) __W,
				3011	(__mmask8) __U);
				3012	}
				3013
				3014	static __inline__ __m256 __DEFAULT_FN_ATTRS
				3015	_mm256_maskz_expandloadu_ps (__mmask8 __U, void const *__P) {
				3016	return (__m256) __builtin_ia32_expandloadsf256_mask ((__v8sf *) __P,
				3017	(__v8sf)
				3018	_mm256_setzero_ps (),
				3019	(__mmask8)
				3020	__U);
				3021	}
				3022
				3023	static __inline__ __m128i __DEFAULT_FN_ATTRS
				3024	_mm_mask_expandloadu_epi32 (__m128i __W, __mmask8 __U, void const *__P) {
				3025	return (__m128i) __builtin_ia32_expandloadsi128_mask ((__v4si *) __P,
				3026	(__v4si) __W,
				3027	(__mmask8)
				3028	__U);
				3029	}
				3030
				3031	static __inline__ __m128i __DEFAULT_FN_ATTRS
				3032	_mm_maskz_expandloadu_epi32 (__mmask8 __U, void const *__P) {
				3033	return (__m128i) __builtin_ia32_expandloadsi128_mask ((__v4si *) __P,
				3034	(__v4si)
				3035	_mm_setzero_si128 (),
				3036	(__mmask8) __U);
				3037	}
				3038
				3039	static __inline__ __m256i __DEFAULT_FN_ATTRS
				3040	_mm256_mask_expandloadu_epi32 (__m256i __W, __mmask8 __U,
				3041	void const *__P) {
				3042	return (__m256i) __builtin_ia32_expandloadsi256_mask ((__v8si *) __P,
				3043	(__v8si) __W,
				3044	(__mmask8)
				3045	__U);
				3046	}
				3047
				3048	static __inline__ __m256i __DEFAULT_FN_ATTRS
				3049	_mm256_maskz_expandloadu_epi32 (__mmask8 __U, void const *__P) {
				3050	return (__m256i) __builtin_ia32_expandloadsi256_mask ((__v8si *) __P,
				3051	(__v8si)
				3052	_mm256_setzero_si256 (),
				3053	(__mmask8)
				3054	__U);
				3055	}
				3056
				3057	static __inline__ __m128 __DEFAULT_FN_ATTRS
				3058	_mm_mask_expand_ps (__m128 __W, __mmask8 __U, __m128 __A) {
				3059	return (__m128) __builtin_ia32_expandsf128_mask ((__v4sf) __A,
				3060	(__v4sf) __W,
				3061	(__mmask8) __U);
				3062	}
				3063
				3064	static __inline__ __m128 __DEFAULT_FN_ATTRS
				3065	_mm_maskz_expand_ps (__mmask8 __U, __m128 __A) {
				3066	return (__m128) __builtin_ia32_expandsf128_mask ((__v4sf) __A,
				3067	(__v4sf)
				3068	_mm_setzero_ps (),
				3069	(__mmask8) __U);
				3070	}
				3071
				3072	static __inline__ __m256 __DEFAULT_FN_ATTRS
				3073	_mm256_mask_expand_ps (__m256 __W, __mmask8 __U, __m256 __A) {
				3074	return (__m256) __builtin_ia32_expandsf256_mask ((__v8sf) __A,
				3075	(__v8sf) __W,
				3076	(__mmask8) __U);
				3077	}
				3078
				3079	static __inline__ __m256 __DEFAULT_FN_ATTRS
				3080	_mm256_maskz_expand_ps (__mmask8 __U, __m256 __A) {
				3081	return (__m256) __builtin_ia32_expandsf256_mask ((__v8sf) __A,
				3082	(__v8sf)
				3083	_mm256_setzero_ps (),
				3084	(__mmask8) __U);
				3085	}
				3086
				3087	static __inline__ __m128i __DEFAULT_FN_ATTRS
				3088	_mm_mask_expand_epi32 (__m128i __W, __mmask8 __U, __m128i __A) {
				3089	return (__m128i) __builtin_ia32_expandsi128_mask ((__v4si) __A,
				3090	(__v4si) __W,
				3091	(__mmask8) __U);
				3092	}
				3093
				3094	static __inline__ __m128i __DEFAULT_FN_ATTRS
				3095	_mm_maskz_expand_epi32 (__mmask8 __U, __m128i __A) {
				3096	return (__m128i) __builtin_ia32_expandsi128_mask ((__v4si) __A,
				3097	(__v4si)
				3098	_mm_setzero_si128 (),
				3099	(__mmask8) __U);
				3100	}
				3101
				3102	static __inline__ __m256i __DEFAULT_FN_ATTRS
				3103	_mm256_mask_expand_epi32 (__m256i __W, __mmask8 __U, __m256i __A) {
				3104	return (__m256i) __builtin_ia32_expandsi256_mask ((__v8si) __A,
				3105	(__v8si) __W,
				3106	(__mmask8) __U);
				3107	}
				3108
				3109	static __inline__ __m256i __DEFAULT_FN_ATTRS
				3110	_mm256_maskz_expand_epi32 (__mmask8 __U, __m256i __A) {
				3111	return (__m256i) __builtin_ia32_expandsi256_mask ((__v8si) __A,
				3112	(__v8si)
				3113	_mm256_setzero_si256 (),
				3114	(__mmask8) __U);
				3115	}
				3116
				3117	static __inline__ __m128d __DEFAULT_FN_ATTRS
				3118	_mm_getexp_pd (__m128d __A) {
				3119	return (__m128d) __builtin_ia32_getexppd128_mask ((__v2df) __A,
				3120	(__v2df)
				3121	_mm_setzero_pd (),
				3122	(__mmask8) -1);
				3123	}
				3124
				3125	static __inline__ __m128d __DEFAULT_FN_ATTRS
				3126	_mm_mask_getexp_pd (__m128d __W, __mmask8 __U, __m128d __A) {
				3127	return (__m128d) __builtin_ia32_getexppd128_mask ((__v2df) __A,
				3128	(__v2df) __W,
				3129	(__mmask8) __U);
				3130	}
				3131
				3132	static __inline__ __m128d __DEFAULT_FN_ATTRS
				3133	_mm_maskz_getexp_pd (__mmask8 __U, __m128d __A) {
				3134	return (__m128d) __builtin_ia32_getexppd128_mask ((__v2df) __A,
				3135	(__v2df)
				3136	_mm_setzero_pd (),
				3137	(__mmask8) __U);
				3138	}
				3139
				3140	static __inline__ __m256d __DEFAULT_FN_ATTRS
				3141	_mm256_getexp_pd (__m256d __A) {
				3142	return (__m256d) __builtin_ia32_getexppd256_mask ((__v4df) __A,
				3143	(__v4df)
				3144	_mm256_setzero_pd (),
				3145	(__mmask8) -1);
				3146	}
				3147
				3148	static __inline__ __m256d __DEFAULT_FN_ATTRS
				3149	_mm256_mask_getexp_pd (__m256d __W, __mmask8 __U, __m256d __A) {
				3150	return (__m256d) __builtin_ia32_getexppd256_mask ((__v4df) __A,
				3151	(__v4df) __W,
				3152	(__mmask8) __U);
				3153	}
				3154
				3155	static __inline__ __m256d __DEFAULT_FN_ATTRS
				3156	_mm256_maskz_getexp_pd (__mmask8 __U, __m256d __A) {
				3157	return (__m256d) __builtin_ia32_getexppd256_mask ((__v4df) __A,
				3158	(__v4df)
				3159	_mm256_setzero_pd (),
				3160	(__mmask8) __U);
				3161	}
				3162
				3163	static __inline__ __m128 __DEFAULT_FN_ATTRS
				3164	_mm_getexp_ps (__m128 __A) {
				3165	return (__m128) __builtin_ia32_getexpps128_mask ((__v4sf) __A,
				3166	(__v4sf)
				3167	_mm_setzero_ps (),
				3168	(__mmask8) -1);
				3169	}
				3170
				3171	static __inline__ __m128 __DEFAULT_FN_ATTRS
				3172	_mm_mask_getexp_ps (__m128 __W, __mmask8 __U, __m128 __A) {
				3173	return (__m128) __builtin_ia32_getexpps128_mask ((__v4sf) __A,
				3174	(__v4sf) __W,
				3175	(__mmask8) __U);
				3176	}
				3177
				3178	static __inline__ __m128 __DEFAULT_FN_ATTRS
				3179	_mm_maskz_getexp_ps (__mmask8 __U, __m128 __A) {
				3180	return (__m128) __builtin_ia32_getexpps128_mask ((__v4sf) __A,
				3181	(__v4sf)
				3182	_mm_setzero_ps (),
				3183	(__mmask8) __U);
				3184	}
				3185
				3186	static __inline__ __m256 __DEFAULT_FN_ATTRS
				3187	_mm256_getexp_ps (__m256 __A) {
				3188	return (__m256) __builtin_ia32_getexpps256_mask ((__v8sf) __A,
				3189	(__v8sf)
				3190	_mm256_setzero_ps (),
				3191	(__mmask8) -1);
				3192	}
				3193
				3194	static __inline__ __m256 __DEFAULT_FN_ATTRS
				3195	_mm256_mask_getexp_ps (__m256 __W, __mmask8 __U, __m256 __A) {
				3196	return (__m256) __builtin_ia32_getexpps256_mask ((__v8sf) __A,
				3197	(__v8sf) __W,
				3198	(__mmask8) __U);
				3199	}
				3200
				3201	static __inline__ __m256 __DEFAULT_FN_ATTRS
				3202	_mm256_maskz_getexp_ps (__mmask8 __U, __m256 __A) {
				3203	return (__m256) __builtin_ia32_getexpps256_mask ((__v8sf) __A,
				3204	(__v8sf)
				3205	_mm256_setzero_ps (),
				3206	(__mmask8) __U);
				3207	}
				3208
				3209	static __inline__ __m128d __DEFAULT_FN_ATTRS
				3210	_mm_mask_max_pd (__m128d __W, __mmask8 __U, __m128d __A, __m128d __B) {
				3211	return (__m128d) __builtin_ia32_maxpd_mask ((__v2df) __A,
				3212	(__v2df) __B,
				3213	(__v2df) __W,
				3214	(__mmask8) __U);
				3215	}
				3216
				3217	static __inline__ __m128d __DEFAULT_FN_ATTRS
				3218	_mm_maskz_max_pd (__mmask8 __U, __m128d __A, __m128d __B) {
				3219	return (__m128d) __builtin_ia32_maxpd_mask ((__v2df) __A,
				3220	(__v2df) __B,
				3221	(__v2df)
				3222	_mm_setzero_pd (),
				3223	(__mmask8) __U);
				3224	}
				3225
				3226	static __inline__ __m256d __DEFAULT_FN_ATTRS
				3227	_mm256_mask_max_pd (__m256d __W, __mmask8 __U, __m256d __A,
				3228	__m256d __B) {
				3229	return (__m256d) __builtin_ia32_maxpd256_mask ((__v4df) __A,
				3230	(__v4df) __B,
				3231	(__v4df) __W,
				3232	(__mmask8) __U);
				3233	}
				3234
				3235	static __inline__ __m256d __DEFAULT_FN_ATTRS
				3236	_mm256_maskz_max_pd (__mmask8 __U, __m256d __A, __m256d __B) {
				3237	return (__m256d) __builtin_ia32_maxpd256_mask ((__v4df) __A,
				3238	(__v4df) __B,
				3239	(__v4df)
				3240	_mm256_setzero_pd (),
				3241	(__mmask8) __U);
				3242	}
				3243
				3244	static __inline__ __m128 __DEFAULT_FN_ATTRS
				3245	_mm_mask_max_ps (__m128 __W, __mmask8 __U, __m128 __A, __m128 __B) {
				3246	return (__m128) __builtin_ia32_maxps_mask ((__v4sf) __A,
				3247	(__v4sf) __B,
				3248	(__v4sf) __W,
				3249	(__mmask8) __U);
				3250	}
				3251
				3252	static __inline__ __m128 __DEFAULT_FN_ATTRS
				3253	_mm_maskz_max_ps (__mmask8 __U, __m128 __A, __m128 __B) {
				3254	return (__m128) __builtin_ia32_maxps_mask ((__v4sf) __A,
				3255	(__v4sf) __B,
				3256	(__v4sf)
				3257	_mm_setzero_ps (),
				3258	(__mmask8) __U);
				3259	}
				3260
				3261	static __inline__ __m256 __DEFAULT_FN_ATTRS
				3262	_mm256_mask_max_ps (__m256 __W, __mmask8 __U, __m256 __A, __m256 __B) {
				3263	return (__m256) __builtin_ia32_maxps256_mask ((__v8sf) __A,
				3264	(__v8sf) __B,
				3265	(__v8sf) __W,
				3266	(__mmask8) __U);
				3267	}
				3268
				3269	static __inline__ __m256 __DEFAULT_FN_ATTRS
				3270	_mm256_maskz_max_ps (__mmask8 __U, __m256 __A, __m256 __B) {
				3271	return (__m256) __builtin_ia32_maxps256_mask ((__v8sf) __A,
				3272	(__v8sf) __B,
				3273	(__v8sf)
				3274	_mm256_setzero_ps (),
				3275	(__mmask8) __U);
				3276	}
				3277
				3278	static __inline__ __m128d __DEFAULT_FN_ATTRS
				3279	_mm_mask_min_pd (__m128d __W, __mmask8 __U, __m128d __A, __m128d __B) {
				3280	return (__m128d) __builtin_ia32_minpd_mask ((__v2df) __A,
				3281	(__v2df) __B,
				3282	(__v2df) __W,
				3283	(__mmask8) __U);
				3284	}
				3285
				3286	static __inline__ __m128d __DEFAULT_FN_ATTRS
				3287	_mm_maskz_min_pd (__mmask8 __U, __m128d __A, __m128d __B) {
				3288	return (__m128d) __builtin_ia32_minpd_mask ((__v2df) __A,
				3289	(__v2df) __B,
				3290	(__v2df)
				3291	_mm_setzero_pd (),
				3292	(__mmask8) __U);
				3293	}
				3294
				3295	static __inline__ __m256d __DEFAULT_FN_ATTRS
				3296	_mm256_mask_min_pd (__m256d __W, __mmask8 __U, __m256d __A,
				3297	__m256d __B) {
				3298	return (__m256d) __builtin_ia32_minpd256_mask ((__v4df) __A,
				3299	(__v4df) __B,
				3300	(__v4df) __W,
				3301	(__mmask8) __U);
				3302	}
				3303
				3304	static __inline__ __m256d __DEFAULT_FN_ATTRS
				3305	_mm256_maskz_min_pd (__mmask8 __U, __m256d __A, __m256d __B) {
				3306	return (__m256d) __builtin_ia32_minpd256_mask ((__v4df) __A,
				3307	(__v4df) __B,
				3308	(__v4df)
				3309	_mm256_setzero_pd (),
				3310	(__mmask8) __U);
				3311	}
				3312
				3313	static __inline__ __m128 __DEFAULT_FN_ATTRS
				3314	_mm_mask_min_ps (__m128 __W, __mmask8 __U, __m128 __A, __m128 __B) {
				3315	return (__m128) __builtin_ia32_minps_mask ((__v4sf) __A,
				3316	(__v4sf) __B,
				3317	(__v4sf) __W,
				3318	(__mmask8) __U);
				3319	}
				3320
				3321	static __inline__ __m128 __DEFAULT_FN_ATTRS
				3322	_mm_maskz_min_ps (__mmask8 __U, __m128 __A, __m128 __B) {
				3323	return (__m128) __builtin_ia32_minps_mask ((__v4sf) __A,
				3324	(__v4sf) __B,
				3325	(__v4sf)
				3326	_mm_setzero_ps (),
				3327	(__mmask8) __U);
				3328	}
				3329
				3330	static __inline__ __m256 __DEFAULT_FN_ATTRS
				3331	_mm256_mask_min_ps (__m256 __W, __mmask8 __U, __m256 __A, __m256 __B) {
				3332	return (__m256) __builtin_ia32_minps256_mask ((__v8sf) __A,
				3333	(__v8sf) __B,
				3334	(__v8sf) __W,
				3335	(__mmask8) __U);
				3336	}
				3337
				3338	static __inline__ __m256 __DEFAULT_FN_ATTRS
				3339	_mm256_maskz_min_ps (__mmask8 __U, __m256 __A, __m256 __B) {
				3340	return (__m256) __builtin_ia32_minps256_mask ((__v8sf) __A,
				3341	(__v8sf) __B,
				3342	(__v8sf)
				3343	_mm256_setzero_ps (),
				3344	(__mmask8) __U);
				3345	}
				3346
				3347	static __inline__ __m128d __DEFAULT_FN_ATTRS
				3348	_mm_mask_mul_pd (__m128d __W, __mmask8 __U, __m128d __A, __m128d __B) {
				3349	return (__m128d) __builtin_ia32_mulpd_mask ((__v2df) __A,
				3350	(__v2df) __B,
				3351	(__v2df) __W,
				3352	(__mmask8) __U);
				3353	}
				3354
				3355	static __inline__ __m128d __DEFAULT_FN_ATTRS
				3356	_mm_maskz_mul_pd (__mmask8 __U, __m128d __A, __m128d __B) {
				3357	return (__m128d) __builtin_ia32_mulpd_mask ((__v2df) __A,
				3358	(__v2df) __B,
				3359	(__v2df)
				3360	_mm_setzero_pd (),
				3361	(__mmask8) __U);
				3362	}
				3363
				3364	static __inline__ __m256d __DEFAULT_FN_ATTRS
				3365	_mm256_mask_mul_pd (__m256d __W, __mmask8 __U, __m256d __A,
				3366	__m256d __B) {
				3367	return (__m256d) __builtin_ia32_mulpd256_mask ((__v4df) __A,
				3368	(__v4df) __B,
				3369	(__v4df) __W,
				3370	(__mmask8) __U);
				3371	}
				3372
				3373	static __inline__ __m256d __DEFAULT_FN_ATTRS
				3374	_mm256_maskz_mul_pd (__mmask8 __U, __m256d __A, __m256d __B) {
				3375	return (__m256d) __builtin_ia32_mulpd256_mask ((__v4df) __A,
				3376	(__v4df) __B,
				3377	(__v4df)
				3378	_mm256_setzero_pd (),
				3379	(__mmask8) __U);
				3380	}
				3381
				3382	static __inline__ __m128 __DEFAULT_FN_ATTRS
				3383	_mm_mask_mul_ps (__m128 __W, __mmask8 __U, __m128 __A, __m128 __B) {
				3384	return (__m128) __builtin_ia32_mulps_mask ((__v4sf) __A,
				3385	(__v4sf) __B,
				3386	(__v4sf) __W,
				3387	(__mmask8) __U);
				3388	}
				3389
				3390	static __inline__ __m128 __DEFAULT_FN_ATTRS
				3391	_mm_maskz_mul_ps (__mmask8 __U, __m128 __A, __m128 __B) {
				3392	return (__m128) __builtin_ia32_mulps_mask ((__v4sf) __A,
				3393	(__v4sf) __B,
				3394	(__v4sf)
				3395	_mm_setzero_ps (),
				3396	(__mmask8) __U);
				3397	}
				3398
				3399	static __inline__ __m256 __DEFAULT_FN_ATTRS
				3400	_mm256_mask_mul_ps (__m256 __W, __mmask8 __U, __m256 __A, __m256 __B) {
				3401	return (__m256) __builtin_ia32_mulps256_mask ((__v8sf) __A,
				3402	(__v8sf) __B,
				3403	(__v8sf) __W,
				3404	(__mmask8) __U);
				3405	}
				3406
				3407	static __inline__ __m256 __DEFAULT_FN_ATTRS
				3408	_mm256_maskz_mul_ps (__mmask8 __U, __m256 __A, __m256 __B) {
				3409	return (__m256) __builtin_ia32_mulps256_mask ((__v8sf) __A,
				3410	(__v8sf) __B,
				3411	(__v8sf)
				3412	_mm256_setzero_ps (),
				3413	(__mmask8) __U);
				3414	}
				3415
				3416	static __inline__ __m128i __DEFAULT_FN_ATTRS
				3417	_mm_mask_abs_epi32 (__m128i __W, __mmask8 __U, __m128i __A) {
				3418	return (__m128i) __builtin_ia32_pabsd128_mask ((__v4si) __A,
				3419	(__v4si) __W,
				3420	(__mmask8) __U);
				3421	}
				3422
				3423	static __inline__ __m128i __DEFAULT_FN_ATTRS
				3424	_mm_maskz_abs_epi32 (__mmask8 __U, __m128i __A) {
				3425	return (__m128i) __builtin_ia32_pabsd128_mask ((__v4si) __A,
				3426	(__v4si)
				3427	_mm_setzero_si128 (),
				3428	(__mmask8) __U);
				3429	}
				3430
				3431	static __inline__ __m256i __DEFAULT_FN_ATTRS
				3432	_mm256_mask_abs_epi32 (__m256i __W, __mmask8 __U, __m256i __A) {
				3433	return (__m256i) __builtin_ia32_pabsd256_mask ((__v8si) __A,
				3434	(__v8si) __W,
				3435	(__mmask8) __U);
				3436	}
				3437
				3438	static __inline__ __m256i __DEFAULT_FN_ATTRS
				3439	_mm256_maskz_abs_epi32 (__mmask8 __U, __m256i __A) {
				3440	return (__m256i) __builtin_ia32_pabsd256_mask ((__v8si) __A,
				3441	(__v8si)
				3442	_mm256_setzero_si256 (),
				3443	(__mmask8) __U);
				3444	}
				3445
				3446	static __inline__ __m128i __DEFAULT_FN_ATTRS
				3447	_mm_abs_epi64 (__m128i __A) {
				3448	return (__m128i) __builtin_ia32_pabsq128_mask ((__v2di) __A,
				3449	(__v2di)
				3450	_mm_setzero_si128 (),
				3451	(__mmask8) -1);
				3452	}
				3453
				3454	static __inline__ __m128i __DEFAULT_FN_ATTRS
				3455	_mm_mask_abs_epi64 (__m128i __W, __mmask8 __U, __m128i __A) {
				3456	return (__m128i) __builtin_ia32_pabsq128_mask ((__v2di) __A,
				3457	(__v2di) __W,
				3458	(__mmask8) __U);
				3459	}
				3460
				3461	static __inline__ __m128i __DEFAULT_FN_ATTRS
				3462	_mm_maskz_abs_epi64 (__mmask8 __U, __m128i __A) {
				3463	return (__m128i) __builtin_ia32_pabsq128_mask ((__v2di) __A,
				3464	(__v2di)
				3465	_mm_setzero_si128 (),
				3466	(__mmask8) __U);
				3467	}
				3468
				3469	static __inline__ __m256i __DEFAULT_FN_ATTRS
				3470	_mm256_abs_epi64 (__m256i __A) {
				3471	return (__m256i) __builtin_ia32_pabsq256_mask ((__v4di) __A,
				3472	(__v4di)
				3473	_mm256_setzero_si256 (),
				3474	(__mmask8) -1);
				3475	}
				3476
				3477	static __inline__ __m256i __DEFAULT_FN_ATTRS
				3478	_mm256_mask_abs_epi64 (__m256i __W, __mmask8 __U, __m256i __A) {
				3479	return (__m256i) __builtin_ia32_pabsq256_mask ((__v4di) __A,
				3480	(__v4di) __W,
				3481	(__mmask8) __U);
				3482	}
				3483
				3484	static __inline__ __m256i __DEFAULT_FN_ATTRS
				3485	_mm256_maskz_abs_epi64 (__mmask8 __U, __m256i __A) {
				3486	return (__m256i) __builtin_ia32_pabsq256_mask ((__v4di) __A,
				3487	(__v4di)
				3488	_mm256_setzero_si256 (),
				3489	(__mmask8) __U);
				3490	}
				3491
Asaf Badouh	b7cf71b	2015-07-28 11:14:09 +0000	[diff] [blame]	3492	static __inline__ __m128i __DEFAULT_FN_ATTRS
				3493	_mm_maskz_max_epi32 (__mmask8 __M, __m128i __A, __m128i __B) {
				3494	return (__m128i) __builtin_ia32_pmaxsd128_mask ((__v4si) __A,
				3495	(__v4si) __B,
				3496	(__v4si)
				3497	_mm_setzero_si128 (),
				3498	__M);
				3499	}
				3500
				3501	static __inline__ __m128i __DEFAULT_FN_ATTRS
				3502	_mm_mask_max_epi32 (__m128i __W, __mmask8 __M, __m128i __A,
				3503	__m128i __B) {
				3504	return (__m128i) __builtin_ia32_pmaxsd128_mask ((__v4si) __A,
				3505	(__v4si) __B,
				3506	(__v4si) __W, __M);
				3507	}
				3508
				3509	static __inline__ __m256i __DEFAULT_FN_ATTRS
				3510	_mm256_maskz_max_epi32 (__mmask8 __M, __m256i __A, __m256i __B) {
				3511	return (__m256i) __builtin_ia32_pmaxsd256_mask ((__v8si) __A,
				3512	(__v8si) __B,
				3513	(__v8si)
				3514	_mm256_setzero_si256 (),
				3515	__M);
				3516	}
				3517
				3518	static __inline__ __m256i __DEFAULT_FN_ATTRS
				3519	_mm256_mask_max_epi32 (__m256i __W, __mmask8 __M, __m256i __A,
				3520	__m256i __B) {
				3521	return (__m256i) __builtin_ia32_pmaxsd256_mask ((__v8si) __A,
				3522	(__v8si) __B,
				3523	(__v8si) __W, __M);
				3524	}
				3525
				3526	static __inline__ __m128i __DEFAULT_FN_ATTRS
				3527	_mm_maskz_max_epi64 (__mmask8 __M, __m128i __A, __m128i __B) {
				3528	return (__m128i) __builtin_ia32_pmaxsq128_mask ((__v2di) __A,
				3529	(__v2di) __B,
				3530	(__v2di)
				3531	_mm_setzero_si128 (),
				3532	__M);
				3533	}
				3534
				3535	static __inline__ __m128i __DEFAULT_FN_ATTRS
				3536	_mm_mask_max_epi64 (__m128i __W, __mmask8 __M, __m128i __A,
				3537	__m128i __B) {
				3538	return (__m128i) __builtin_ia32_pmaxsq128_mask ((__v2di) __A,
				3539	(__v2di) __B,
				3540	(__v2di) __W, __M);
				3541	}
				3542
				3543	static __inline__ __m128i __DEFAULT_FN_ATTRS
				3544	_mm_max_epi64 (__m128i __A, __m128i __B) {
				3545	return (__m128i) __builtin_ia32_pmaxsq128_mask ((__v2di) __A,
				3546	(__v2di) __B,
				3547	(__v2di)
				3548	_mm_setzero_si128 (),
				3549	(__mmask8) -1);
				3550	}
				3551
				3552	static __inline__ __m256i __DEFAULT_FN_ATTRS
				3553	_mm256_maskz_max_epi64 (__mmask8 __M, __m256i __A, __m256i __B) {
				3554	return (__m256i) __builtin_ia32_pmaxsq256_mask ((__v4di) __A,
				3555	(__v4di) __B,
				3556	(__v4di)
				3557	_mm256_setzero_si256 (),
				3558	__M);
				3559	}
				3560
				3561	static __inline__ __m256i __DEFAULT_FN_ATTRS
				3562	_mm256_mask_max_epi64 (__m256i __W, __mmask8 __M, __m256i __A,
				3563	__m256i __B) {
				3564	return (__m256i) __builtin_ia32_pmaxsq256_mask ((__v4di) __A,
				3565	(__v4di) __B,
				3566	(__v4di) __W, __M);
				3567	}
				3568
				3569	static __inline__ __m256i __DEFAULT_FN_ATTRS
				3570	_mm256_max_epi64 (__m256i __A, __m256i __B) {
				3571	return (__m256i) __builtin_ia32_pmaxsq256_mask ((__v4di) __A,
				3572	(__v4di) __B,
				3573	(__v4di)
				3574	_mm256_setzero_si256 (),
				3575	(__mmask8) -1);
				3576	}
				3577
				3578	static __inline__ __m128i __DEFAULT_FN_ATTRS
				3579	_mm_maskz_max_epu32 (__mmask8 __M, __m128i __A, __m128i __B) {
				3580	return (__m128i) __builtin_ia32_pmaxud128_mask ((__v4si) __A,
				3581	(__v4si) __B,
				3582	(__v4si)
				3583	_mm_setzero_si128 (),
				3584	__M);
				3585	}
				3586
				3587	static __inline__ __m128i __DEFAULT_FN_ATTRS
				3588	_mm_mask_max_epu32 (__m128i __W, __mmask8 __M, __m128i __A,
				3589	__m128i __B) {
				3590	return (__m128i) __builtin_ia32_pmaxud128_mask ((__v4si) __A,
				3591	(__v4si) __B,
				3592	(__v4si) __W, __M);
				3593	}
				3594
				3595	static __inline__ __m256i __DEFAULT_FN_ATTRS
				3596	_mm256_maskz_max_epu32 (__mmask8 __M, __m256i __A, __m256i __B) {
				3597	return (__m256i) __builtin_ia32_pmaxud256_mask ((__v8si) __A,
				3598	(__v8si) __B,
				3599	(__v8si)
				3600	_mm256_setzero_si256 (),
				3601	__M);
				3602	}
				3603
				3604	static __inline__ __m256i __DEFAULT_FN_ATTRS
				3605	_mm256_mask_max_epu32 (__m256i __W, __mmask8 __M, __m256i __A,
				3606	__m256i __B) {
				3607	return (__m256i) __builtin_ia32_pmaxud256_mask ((__v8si) __A,
				3608	(__v8si) __B,
				3609	(__v8si) __W, __M);
				3610	}
				3611
				3612	static __inline__ __m128i __DEFAULT_FN_ATTRS
				3613	_mm_maskz_max_epu64 (__mmask8 __M, __m128i __A, __m128i __B) {
				3614	return (__m128i) __builtin_ia32_pmaxuq128_mask ((__v2di) __A,
				3615	(__v2di) __B,
				3616	(__v2di)
				3617	_mm_setzero_si128 (),
				3618	__M);
				3619	}
				3620
				3621	static __inline__ __m128i __DEFAULT_FN_ATTRS
				3622	_mm_max_epu64 (__m128i __A, __m128i __B) {
				3623	return (__m128i) __builtin_ia32_pmaxuq128_mask ((__v2di) __A,
				3624	(__v2di) __B,
				3625	(__v2di)
				3626	_mm_setzero_si128 (),
				3627	(__mmask8) -1);
				3628	}
				3629
				3630	static __inline__ __m128i __DEFAULT_FN_ATTRS
				3631	_mm_mask_max_epu64 (__m128i __W, __mmask8 __M, __m128i __A,
				3632	__m128i __B) {
				3633	return (__m128i) __builtin_ia32_pmaxuq128_mask ((__v2di) __A,
				3634	(__v2di) __B,
				3635	(__v2di) __W, __M);
				3636	}
				3637
				3638	static __inline__ __m256i __DEFAULT_FN_ATTRS
				3639	_mm256_maskz_max_epu64 (__mmask8 __M, __m256i __A, __m256i __B) {
				3640	return (__m256i) __builtin_ia32_pmaxuq256_mask ((__v4di) __A,
				3641	(__v4di) __B,
				3642	(__v4di)
				3643	_mm256_setzero_si256 (),
				3644	__M);
				3645	}
				3646
				3647	static __inline__ __m256i __DEFAULT_FN_ATTRS
				3648	_mm256_max_epu64 (__m256i __A, __m256i __B) {
				3649	return (__m256i) __builtin_ia32_pmaxuq256_mask ((__v4di) __A,
				3650	(__v4di) __B,
				3651	(__v4di)
				3652	_mm256_setzero_si256 (),
				3653	(__mmask8) -1);
				3654	}
				3655
				3656	static __inline__ __m256i __DEFAULT_FN_ATTRS
				3657	_mm256_mask_max_epu64 (__m256i __W, __mmask8 __M, __m256i __A,
				3658	__m256i __B) {
				3659	return (__m256i) __builtin_ia32_pmaxuq256_mask ((__v4di) __A,
				3660	(__v4di) __B,
				3661	(__v4di) __W, __M);
				3662	}
				3663
				3664	static __inline__ __m128i __DEFAULT_FN_ATTRS
				3665	_mm_maskz_min_epi32 (__mmask8 __M, __m128i __A, __m128i __B) {
				3666	return (__m128i) __builtin_ia32_pminsd128_mask ((__v4si) __A,
				3667	(__v4si) __B,
				3668	(__v4si)
				3669	_mm_setzero_si128 (),
				3670	__M);
				3671	}
				3672
				3673	static __inline__ __m128i __DEFAULT_FN_ATTRS
				3674	_mm_mask_min_epi32 (__m128i __W, __mmask8 __M, __m128i __A,
				3675	__m128i __B) {
				3676	return (__m128i) __builtin_ia32_pminsd128_mask ((__v4si) __A,
				3677	(__v4si) __B,
				3678	(__v4si) __W, __M);
				3679	}
				3680
				3681	static __inline__ __m256i __DEFAULT_FN_ATTRS
				3682	_mm256_maskz_min_epi32 (__mmask8 __M, __m256i __A, __m256i __B) {
				3683	return (__m256i) __builtin_ia32_pminsd256_mask ((__v8si) __A,
				3684	(__v8si) __B,
				3685	(__v8si)
				3686	_mm256_setzero_si256 (),
				3687	__M);
				3688	}
				3689
				3690	static __inline__ __m256i __DEFAULT_FN_ATTRS
				3691	_mm256_mask_min_epi32 (__m256i __W, __mmask8 __M, __m256i __A,
				3692	__m256i __B) {
				3693	return (__m256i) __builtin_ia32_pminsd256_mask ((__v8si) __A,
				3694	(__v8si) __B,
				3695	(__v8si) __W, __M);
				3696	}
				3697
				3698	static __inline__ __m128i __DEFAULT_FN_ATTRS
				3699	_mm_min_epi64 (__m128i __A, __m128i __B) {
				3700	return (__m128i) __builtin_ia32_pminsq128_mask ((__v2di) __A,
				3701	(__v2di) __B,
				3702	(__v2di)
				3703	_mm_setzero_si128 (),
				3704	(__mmask8) -1);
				3705	}
				3706
				3707	static __inline__ __m128i __DEFAULT_FN_ATTRS
				3708	_mm_mask_min_epi64 (__m128i __W, __mmask8 __M, __m128i __A,
				3709	__m128i __B) {
				3710	return (__m128i) __builtin_ia32_pminsq128_mask ((__v2di) __A,
				3711	(__v2di) __B,
				3712	(__v2di) __W, __M);
				3713	}
				3714
				3715	static __inline__ __m128i __DEFAULT_FN_ATTRS
				3716	_mm_maskz_min_epi64 (__mmask8 __M, __m128i __A, __m128i __B) {
				3717	return (__m128i) __builtin_ia32_pminsq128_mask ((__v2di) __A,
				3718	(__v2di) __B,
				3719	(__v2di)
				3720	_mm_setzero_si128 (),
				3721	__M);
				3722	}
				3723
				3724	static __inline__ __m256i __DEFAULT_FN_ATTRS
				3725	_mm256_min_epi64 (__m256i __A, __m256i __B) {
				3726	return (__m256i) __builtin_ia32_pminsq256_mask ((__v4di) __A,
				3727	(__v4di) __B,
				3728	(__v4di)
				3729	_mm256_setzero_si256 (),
				3730	(__mmask8) -1);
				3731	}
				3732
				3733	static __inline__ __m256i __DEFAULT_FN_ATTRS
				3734	_mm256_mask_min_epi64 (__m256i __W, __mmask8 __M, __m256i __A,
				3735	__m256i __B) {
				3736	return (__m256i) __builtin_ia32_pminsq256_mask ((__v4di) __A,
				3737	(__v4di) __B,
				3738	(__v4di) __W, __M);
				3739	}
				3740
				3741	static __inline__ __m256i __DEFAULT_FN_ATTRS
				3742	_mm256_maskz_min_epi64 (__mmask8 __M, __m256i __A, __m256i __B) {
				3743	return (__m256i) __builtin_ia32_pminsq256_mask ((__v4di) __A,
				3744	(__v4di) __B,
				3745	(__v4di)
				3746	_mm256_setzero_si256 (),
				3747	__M);
				3748	}
				3749
				3750	static __inline__ __m128i __DEFAULT_FN_ATTRS
				3751	_mm_maskz_min_epu32 (__mmask8 __M, __m128i __A, __m128i __B) {
				3752	return (__m128i) __builtin_ia32_pminud128_mask ((__v4si) __A,
				3753	(__v4si) __B,
				3754	(__v4si)
				3755	_mm_setzero_si128 (),
				3756	__M);
				3757	}
				3758
				3759	static __inline__ __m128i __DEFAULT_FN_ATTRS
				3760	_mm_mask_min_epu32 (__m128i __W, __mmask8 __M, __m128i __A,
				3761	__m128i __B) {
				3762	return (__m128i) __builtin_ia32_pminud128_mask ((__v4si) __A,
				3763	(__v4si) __B,
				3764	(__v4si) __W, __M);
				3765	}
				3766
				3767	static __inline__ __m256i __DEFAULT_FN_ATTRS
				3768	_mm256_maskz_min_epu32 (__mmask8 __M, __m256i __A, __m256i __B) {
				3769	return (__m256i) __builtin_ia32_pminud256_mask ((__v8si) __A,
				3770	(__v8si) __B,
				3771	(__v8si)
				3772	_mm256_setzero_si256 (),
				3773	__M);
				3774	}
				3775
				3776	static __inline__ __m256i __DEFAULT_FN_ATTRS
				3777	_mm256_mask_min_epu32 (__m256i __W, __mmask8 __M, __m256i __A,
				3778	__m256i __B) {
				3779	return (__m256i) __builtin_ia32_pminud256_mask ((__v8si) __A,
				3780	(__v8si) __B,
				3781	(__v8si) __W, __M);
				3782	}
				3783
				3784	static __inline__ __m128i __DEFAULT_FN_ATTRS
				3785	_mm_min_epu64 (__m128i __A, __m128i __B) {
				3786	return (__m128i) __builtin_ia32_pminuq128_mask ((__v2di) __A,
				3787	(__v2di) __B,
				3788	(__v2di)
				3789	_mm_setzero_si128 (),
				3790	(__mmask8) -1);
				3791	}
				3792
				3793	static __inline__ __m128i __DEFAULT_FN_ATTRS
				3794	_mm_mask_min_epu64 (__m128i __W, __mmask8 __M, __m128i __A,
				3795	__m128i __B) {
				3796	return (__m128i) __builtin_ia32_pminuq128_mask ((__v2di) __A,
				3797	(__v2di) __B,
				3798	(__v2di) __W, __M);
				3799	}
				3800
				3801	static __inline__ __m128i __DEFAULT_FN_ATTRS
				3802	_mm_maskz_min_epu64 (__mmask8 __M, __m128i __A, __m128i __B) {
				3803	return (__m128i) __builtin_ia32_pminuq128_mask ((__v2di) __A,
				3804	(__v2di) __B,
				3805	(__v2di)
				3806	_mm_setzero_si128 (),
				3807	__M);
				3808	}
				3809
				3810	static __inline__ __m256i __DEFAULT_FN_ATTRS
				3811	_mm256_min_epu64 (__m256i __A, __m256i __B) {
				3812	return (__m256i) __builtin_ia32_pminuq256_mask ((__v4di) __A,
				3813	(__v4di) __B,
				3814	(__v4di)
				3815	_mm256_setzero_si256 (),
				3816	(__mmask8) -1);
				3817	}
				3818
				3819	static __inline__ __m256i __DEFAULT_FN_ATTRS
				3820	_mm256_mask_min_epu64 (__m256i __W, __mmask8 __M, __m256i __A,
				3821	__m256i __B) {
				3822	return (__m256i) __builtin_ia32_pminuq256_mask ((__v4di) __A,
				3823	(__v4di) __B,
				3824	(__v4di) __W, __M);
				3825	}
				3826
				3827	static __inline__ __m256i __DEFAULT_FN_ATTRS
				3828	_mm256_maskz_min_epu64 (__mmask8 __M, __m256i __A, __m256i __B) {
				3829	return (__m256i) __builtin_ia32_pminuq256_mask ((__v4di) __A,
				3830	(__v4di) __B,
				3831	(__v4di)
				3832	_mm256_setzero_si256 (),
				3833	__M);
				3834	}
				3835
				3836	#define _mm_roundscale_pd(__A, __imm) __extension__ ({ \
				3837	(__m128d) __builtin_ia32_rndscalepd_128_mask ((__v2df) __A, \
				3838	__imm, (__v2df) _mm_setzero_pd (), (__mmask8) -1); })
				3839
				3840
				3841	#define _mm_mask_roundscale_pd(__W, __U, __A, __imm) __extension__ ({ \
				3842	(__m128d) __builtin_ia32_rndscalepd_128_mask ((__v2df) __A, __imm, \
				3843	(__v2df) __W, (__mmask8) __U); })
				3844
				3845
				3846	#define _mm_maskz_roundscale_pd(__U, __A, __imm) __extension__ ({ \
				3847	(__m128d) __builtin_ia32_rndscalepd_128_mask ((__v2df) __A, __imm, \
				3848	(__v2df) _mm_setzero_pd (), (__mmask8) __U); })
				3849
				3850
				3851	#define _mm256_roundscale_pd(__A, __imm) __extension__ ({ \
				3852	(__m256d) __builtin_ia32_rndscalepd_256_mask ((__v4df) __A, __imm, \
				3853	(__v4df) _mm256_setzero_pd (), (__mmask8) -1); })
				3854
				3855
				3856	#define _mm256_mask_roundscale_pd(__W, __U, __A, __imm) __extension__ ({ \
				3857	(__m256d) __builtin_ia32_rndscalepd_256_mask ((__v4df) __A, __imm, \
				3858	(__v4df) __W, (__mmask8) __U); })
				3859
				3860
				3861	#define _mm256_maskz_roundscale_pd(__U, __A, __imm) __extension__ ({ \
				3862	(__m256d) __builtin_ia32_rndscalepd_256_mask ((__v4df) __A, __imm, \
				3863	(__v4df) _mm256_setzero_pd(), (__mmask8) __U); })
				3864
				3865	#define _mm_roundscale_ps(__A, __imm) __extension__ ({ \
				3866	(__m128) __builtin_ia32_rndscaleps_128_mask ((__v4sf) __A, __imm, \
				3867	(__v4sf) _mm_setzero_ps(), (__mmask8) -1); })
				3868
				3869
				3870	#define _mm_mask_roundscale_ps(__W, __U, __A, __imm) __extension__ ({ \
				3871	(__m128) __builtin_ia32_rndscaleps_128_mask ((__v4sf) __A, __imm, \
				3872	(__v4sf) __W, (__mmask8) __U); })
				3873
				3874
				3875	#define _mm_maskz_roundscale_ps(__U, __A, __imm) __extension__ ({ \
				3876	(__m128) __builtin_ia32_rndscaleps_128_mask ((__v4sf) __A, __imm, \
				3877	(__v4sf) _mm_setzero_ps(), (__mmask8) __U); })
				3878
				3879	#define _mm256_roundscale_ps(__A, __imm) __extension__ ({ \
				3880	(__m256) __builtin_ia32_rndscaleps_256_mask ((__v8sf) __A,__imm, \
				3881	(__v8sf) _mm256_setzero_ps(), (__mmask8) -1); })
				3882
				3883	#define _mm256_mask_roundscale_ps(__W, __U, __A,__imm) __extension__ ({ \
				3884	(__m256) __builtin_ia32_rndscaleps_256_mask ((__v8sf) __A, __imm, \
				3885	(__v8sf) __W, (__mmask8) __U); })
				3886
				3887
				3888	#define _mm256_maskz_roundscale_ps(__U, __A, __imm) __extension__ ({ \
				3889	(__m256) __builtin_ia32_rndscaleps_256_mask ((__v8sf) __A, __imm, \
				3890	(__v8sf) _mm256_setzero_ps(), (__mmask8) __U); })
				3891
				3892	static __inline__ __m128d __DEFAULT_FN_ATTRS
				3893	_mm_scalef_pd (__m128d __A, __m128d __B) {
				3894	return (__m128d) __builtin_ia32_scalefpd128_mask ((__v2df) __A,
				3895	(__v2df) __B,
				3896	(__v2df)
				3897	_mm_setzero_pd (),
				3898	(__mmask8) -1);
				3899	}
				3900
				3901	static __inline__ __m128d __DEFAULT_FN_ATTRS
				3902	_mm_mask_scalef_pd (__m128d __W, __mmask8 __U, __m128d __A,
				3903	__m128d __B) {
				3904	return (__m128d) __builtin_ia32_scalefpd128_mask ((__v2df) __A,
				3905	(__v2df) __B,
				3906	(__v2df) __W,
				3907	(__mmask8) __U);
				3908	}
				3909
				3910	static __inline__ __m128d __DEFAULT_FN_ATTRS
				3911	_mm_maskz_scalef_pd (__mmask8 __U, __m128d __A, __m128d __B) {
				3912	return (__m128d) __builtin_ia32_scalefpd128_mask ((__v2df) __A,
				3913	(__v2df) __B,
				3914	(__v2df)
				3915	_mm_setzero_pd (),
				3916	(__mmask8) __U);
				3917	}
				3918
				3919	static __inline__ __m256d __DEFAULT_FN_ATTRS
				3920	_mm256_scalef_pd (__m256d __A, __m256d __B) {
				3921	return (__m256d) __builtin_ia32_scalefpd256_mask ((__v4df) __A,
				3922	(__v4df) __B,
				3923	(__v4df)
				3924	_mm256_setzero_pd (),
				3925	(__mmask8) -1);
				3926	}
				3927
				3928	static __inline__ __m256d __DEFAULT_FN_ATTRS
				3929	_mm256_mask_scalef_pd (__m256d __W, __mmask8 __U, __m256d __A,
				3930	__m256d __B) {
				3931	return (__m256d) __builtin_ia32_scalefpd256_mask ((__v4df) __A,
				3932	(__v4df) __B,
				3933	(__v4df) __W,
				3934	(__mmask8) __U);
				3935	}
				3936
				3937	static __inline__ __m256d __DEFAULT_FN_ATTRS
				3938	_mm256_maskz_scalef_pd (__mmask8 __U, __m256d __A, __m256d __B) {
				3939	return (__m256d) __builtin_ia32_scalefpd256_mask ((__v4df) __A,
				3940	(__v4df) __B,
				3941	(__v4df)
				3942	_mm256_setzero_pd (),
				3943	(__mmask8) __U);
				3944	}
				3945
				3946	static __inline__ __m128 __DEFAULT_FN_ATTRS
				3947	_mm_scalef_ps (__m128 __A, __m128 __B) {
				3948	return (__m128) __builtin_ia32_scalefps128_mask ((__v4sf) __A,
				3949	(__v4sf) __B,
				3950	(__v4sf)
				3951	_mm_setzero_ps (),
				3952	(__mmask8) -1);
				3953	}
				3954
				3955	static __inline__ __m128 __DEFAULT_FN_ATTRS
				3956	_mm_mask_scalef_ps (__m128 __W, __mmask8 __U, __m128 __A, __m128 __B) {
				3957	return (__m128) __builtin_ia32_scalefps128_mask ((__v4sf) __A,
				3958	(__v4sf) __B,
				3959	(__v4sf) __W,
				3960	(__mmask8) __U);
				3961	}
				3962
				3963	static __inline__ __m128 __DEFAULT_FN_ATTRS
				3964	_mm_maskz_scalef_ps (__mmask8 __U, __m128 __A, __m128 __B) {
				3965	return (__m128) __builtin_ia32_scalefps128_mask ((__v4sf) __A,
				3966	(__v4sf) __B,
				3967	(__v4sf)
				3968	_mm_setzero_ps (),
				3969	(__mmask8) __U);
				3970	}
				3971
				3972	static __inline__ __m256 __DEFAULT_FN_ATTRS
				3973	_mm256_scalef_ps (__m256 __A, __m256 __B) {
				3974	return (__m256) __builtin_ia32_scalefps256_mask ((__v8sf) __A,
				3975	(__v8sf) __B,
				3976	(__v8sf)
				3977	_mm256_setzero_ps (),
				3978	(__mmask8) -1);
				3979	}
				3980
				3981	static __inline__ __m256 __DEFAULT_FN_ATTRS
				3982	_mm256_mask_scalef_ps (__m256 __W, __mmask8 __U, __m256 __A,
				3983	__m256 __B) {
				3984	return (__m256) __builtin_ia32_scalefps256_mask ((__v8sf) __A,
				3985	(__v8sf) __B,
				3986	(__v8sf) __W,
				3987	(__mmask8) __U);
				3988	}
				3989
				3990	static __inline__ __m256 __DEFAULT_FN_ATTRS
				3991	_mm256_maskz_scalef_ps (__mmask8 __U, __m256 __A, __m256 __B) {
				3992	return (__m256) __builtin_ia32_scalefps256_mask ((__v8sf) __A,
				3993	(__v8sf) __B,
				3994	(__v8sf)
				3995	_mm256_setzero_ps (),
				3996	(__mmask8) __U);
				3997	}
				3998
				3999	#define _mm_i64scatter_pd(__addr,__index, __v1, __scale) __extension__ ({ \
				4000	__builtin_ia32_scatterdiv2df(__addr, (__mmask8) 0xFF, (__v2di) __index, \
				4001	(__v2df) __v1, __scale); })
				4002
				4003	#define _mm_mask_i64scatter_pd(__addr, __mask, __index, __v1, \
				4004	__scale) __extension__ ({ \
				4005	__builtin_ia32_scatterdiv2df (__addr, __mask, (__v2di) __index, \
				4006	(__v2df) __v1, __scale); })
				4007
				4008
				4009	#define _mm_i64scatter_epi64(__addr, __index, __v1, __scale) __extension__ ({ \
				4010	__builtin_ia32_scatterdiv2di (__addr, (__mmask8) 0xFF, \
				4011	(__v2di) __index, (__v2di) __v1, __scale); })
				4012
				4013	#define _mm_mask_i64scatter_epi64(__addr, __mask, __index, __v1,\
				4014	__scale) __extension__ ({ \
				4015	__builtin_ia32_scatterdiv2di (__addr, __mask, (__v2di) __index,\
				4016	(__v2di) __v1, __scale); })
				4017
				4018	#define _mm256_i64scatter_pd(__addr, __index, __v1, __scale) __extension__ ({ \
				4019	__builtin_ia32_scatterdiv4df (__addr, (__mmask8) 0xFF,\
				4020	(__v4di) __index, (__v4df) __v1, __scale); })
				4021
				4022	#define _mm256_mask_i64scatter_pd(__addr, __mask, __index, __v1,\
				4023	__scale) __extension__ ({ \
				4024	__builtin_ia32_scatterdiv4df (__addr, __mask, (__v4di) __index,\
				4025	(__v4df) __v1, __scale); })
				4026
				4027	#define _mm256_i64scatter_epi64(__addr, __index, __v1, __scale) __extension__ ({ \
				4028	__builtin_ia32_scatterdiv4di (__addr, (__mmask8) 0xFF, (__v4di) __index,\
				4029	(__v4di) __v1, __scale); })
				4030
				4031	#define _mm256_mask_i64scatter_epi64(__addr, __mask, __index, __v1,\
				4032	__scale) __extension__ ({ \
				4033	__builtin_ia32_scatterdiv4di (__addr, __mask, (__v4di) __index,\
				4034	(__v4di) __v1, __scale); })
				4035
				4036	#define _mm_i64scatter_ps(__addr, __index, __v1, __scale) __extension__ ({ \
				4037	__builtin_ia32_scatterdiv4sf (__addr, (__mmask8) 0xFF,\
				4038	(__v2di) __index, (__v4sf) __v1, __scale); })
				4039
				4040	#define _mm_mask_i64scatter_ps(__addr, __mask, __index, __v1, \
				4041	__scale) __extension__ ({ \
				4042	__builtin_ia32_scatterdiv4sf (__addr, __mask, (__v2di) __index,\
				4043	(__v4sf) __v1, __scale); })
				4044
				4045	#define _mm_i64scatter_epi32(__addr, __index, __v1, \
				4046	__scale) __extension__ ({ \
				4047	__builtin_ia32_scatterdiv4si (__addr, (__mmask8) 0xFF,\
				4048	(__v2di) __index, (__v4si) __v1, __scale); })
				4049
				4050	#define _mm_mask_i64scatter_epi32(__addr, __mask, __index, __v1,\
				4051	__scale) __extension__ ({ \
				4052	__builtin_ia32_scatterdiv4si (__addr, __mask, (__v2di) __index,\
				4053	(__v4si) __v1, __scale); })
				4054
				4055	#define _mm256_i64scatter_ps(__addr, __index, __v1, __scale) __extension__ ({ \
				4056	__builtin_ia32_scatterdiv8sf (__addr, (__mmask8) 0xFF, (__v4di) __index, \
				4057	(__v4sf) __v1, __scale); })
				4058
				4059	#define _mm256_mask_i64scatter_ps(__addr, __mask, __index, __v1, \
				4060	__scale) __extension__ ({ \
				4061	__builtin_ia32_scatterdiv8sf (__addr, __mask, (__v4di) __index, \
				4062	(__v4sf) __v1, __scale); })
				4063
				4064	#define _mm256_i64scatter_epi32(__addr, __index, __v1, __scale) __extension__ ({ \
				4065	__builtin_ia32_scatterdiv8si (__addr, (__mmask8) 0xFF, \
				4066	(__v4di) __index, (__v4si) __v1, __scale); })
				4067
				4068	#define _mm256_mask_i64scatter_epi32(__addr, __mask, __index, __v1, \
				4069	__scale) __extension__ ({ \
				4070	__builtin_ia32_scatterdiv8si(__addr, __mask, (__v4di) __index, \
				4071	(__v4si) __v1, __scale); })
				4072
				4073	#define _mm_i32scatter_pd(__addr, __index, __v1, \
				4074	__scale) __extension__ ({ \
				4075	__builtin_ia32_scattersiv2df (__addr, (__mmask8) 0xFF, \
				4076	(__v4si) __index, (__v2df) __v1, __scale); })
				4077
				4078	#define _mm_mask_i32scatter_pd(__addr, __mask, __index, __v1, \
				4079	__scale) __extension__ ({ \
				4080	__builtin_ia32_scattersiv2df (__addr, __mask, (__v4si) __index,\
				4081	(__v2df) __v1, __scale); })
				4082
				4083	#define _mm_i32scatter_epi64(__addr, __index, __v1, __scale) __extension__ ({ \
				4084	__builtin_ia32_scattersiv2di (__addr, (__mmask8) 0xFF, \
				4085	(__v4si) __index, (__v2di) __v1, __scale); })
				4086
				4087	#define _mm_mask_i32scatter_epi64(__addr, __mask, __index, __v1, \
				4088	__scale) __extension__ ({ \
				4089	__builtin_ia32_scattersiv2di (__addr, __mask, (__v4si) __index, \
				4090	(__v2di) __v1, __scale); })
				4091
				4092	#define _mm256_i32scatter_pd(__addr, __index, __v1, __scale) __extension__ ({ \
				4093	__builtin_ia32_scattersiv4df (__addr, (__mmask8) 0xFF, \
				4094	(__v4si) __index, (__v4df) __v1, __scale); })
				4095
				4096	#define _mm256_mask_i32scatter_pd(__addr, __mask, __index, __v1, \
				4097	__scale) __extension__ ({ \
				4098	__builtin_ia32_scattersiv4df (__addr, __mask, (__v4si) __index, \
				4099	(__v4df) __v1, __scale); })
				4100
				4101	#define _mm256_i32scatter_epi64(__addr, __index, __v1, \
				4102	__scale) __extension__ ({ \
				4103	__builtin_ia32_scattersiv4di (__addr, (__mmask8) 0xFF, \
				4104	(__v4si) __index, (__v4di) __v1, __scale); })
				4105
				4106	#define _mm256_mask_i32scatter_epi64(__addr, __mask, __index, __v1, \
				4107	__scale) __extension__ ({ \
				4108	__builtin_ia32_scattersiv4di (__addr, __mask, (__v4si) __index, \
				4109	(__v4di) __v1, __scale); })
				4110
				4111	#define _mm_i32scatter_ps(__addr, __index, __v1, __scale) __extension__ ({ \
				4112	__builtin_ia32_scattersiv4sf (__addr, (__mmask8) 0xFF, \
				4113	(__v4si) __index, (__v4sf) __v1, __scale); })
				4114
				4115	#define _mm_mask_i32scatter_ps(__addr, __mask, __index, __v1, \
				4116	__scale) __extension__ ({ \
				4117	__builtin_ia32_scattersiv4sf (__addr, __mask, (__v4si) __index, \
				4118	(__v4sf) __v1, __scale); })
				4119
				4120	#define _mm_i32scatter_epi32(__addr, __index, __v1, __scale) __extension__ ({ \
				4121	__builtin_ia32_scattersiv4si (__addr, (__mmask8) 0xFF, \
				4122	(__v4si) __index, (__v4si) __v1, __scale); })
				4123
				4124	#define _mm_mask_i32scatter_epi32(__addr, __mask, __index, __v1, \
				4125	__scale) __extension__ ({ \
				4126	__builtin_ia32_scattersiv4si (__addr, __mask, (__v4si) __index,\
				4127	(__v4si) __v1, __scale); })
				4128
				4129	#define _mm256_i32scatter_ps(__addr, __index, __v1, __scale) __extension__ ({ \
				4130	__builtin_ia32_scattersiv8sf (__addr, (__mmask8) 0xFF, \
				4131	(__v8si) __index, (__v8sf) __v1, __scale); })
				4132
				4133	#define _mm256_mask_i32scatter_ps(__addr, __mask, __index, __v1, \
				4134	__scale) __extension__ ({ \
				4135	__builtin_ia32_scattersiv8sf (__addr, __mask, (__v8si) __index,\
				4136	(__v8sf) __v1, __scale); })
				4137
				4138	#define _mm256_i32scatter_epi32(__addr, __index, __v1, __scale) __extension__ ({ \
				4139	__builtin_ia32_scattersiv8si (__addr, (__mmask8) 0xFF, \
				4140	(__v8si) __index, (__v8si) __v1, __scale); })
				4141
				4142	#define _mm256_mask_i32scatter_epi32(__addr, __mask, __index, __v1, \
				4143	__scale) __extension__ ({ \
				4144	__builtin_ia32_scattersiv8si (__addr, __mask, (__v8si) __index, \
				4145	(__v8si) __v1, __scale); })
				4146
Asaf Badouh	93aa4c8	2015-07-28 12:04:40 +0000	[diff] [blame]	4147	static __inline__ __m128d __DEFAULT_FN_ATTRS
				4148	_mm_mask_sqrt_pd (__m128d __W, __mmask8 __U, __m128d __A) {
				4149	return (__m128d) __builtin_ia32_sqrtpd128_mask ((__v2df) __A,
				4150	(__v2df) __W,
				4151	(__mmask8) __U);
				4152	}
				4153
				4154	static __inline__ __m128d __DEFAULT_FN_ATTRS
				4155	_mm_maskz_sqrt_pd (__mmask8 __U, __m128d __A) {
				4156	return (__m128d) __builtin_ia32_sqrtpd128_mask ((__v2df) __A,
				4157	(__v2df)
				4158	_mm_setzero_pd (),
				4159	(__mmask8) __U);
				4160	}
				4161
				4162	static __inline__ __m256d __DEFAULT_FN_ATTRS
				4163	_mm256_mask_sqrt_pd (__m256d __W, __mmask8 __U, __m256d __A) {
				4164	return (__m256d) __builtin_ia32_sqrtpd256_mask ((__v4df) __A,
				4165	(__v4df) __W,
				4166	(__mmask8) __U);
				4167	}
				4168
				4169	static __inline__ __m256d __DEFAULT_FN_ATTRS
				4170	_mm256_maskz_sqrt_pd (__mmask8 __U, __m256d __A) {
				4171	return (__m256d) __builtin_ia32_sqrtpd256_mask ((__v4df) __A,
				4172	(__v4df)
				4173	_mm256_setzero_pd (),
				4174	(__mmask8) __U);
				4175	}
				4176
				4177	static __inline__ __m128 __DEFAULT_FN_ATTRS
				4178	_mm_mask_sqrt_ps (__m128 __W, __mmask8 __U, __m128 __A) {
				4179	return (__m128) __builtin_ia32_sqrtps128_mask ((__v4sf) __A,
				4180	(__v4sf) __W,
				4181	(__mmask8) __U);
				4182	}
				4183
				4184	static __inline__ __m128 __DEFAULT_FN_ATTRS
				4185	_mm_maskz_sqrt_ps (__mmask8 __U, __m128 __A) {
				4186	return (__m128) __builtin_ia32_sqrtps128_mask ((__v4sf) __A,
				4187	(__v4sf)
				4188	_mm_setzero_ps (),
				4189	(__mmask8) __U);
				4190	}
				4191
				4192	static __inline__ __m256 __DEFAULT_FN_ATTRS
				4193	_mm256_mask_sqrt_ps (__m256 __W, __mmask8 __U, __m256 __A) {
				4194	return (__m256) __builtin_ia32_sqrtps256_mask ((__v8sf) __A,
				4195	(__v8sf) __W,
				4196	(__mmask8) __U);
				4197	}
				4198
				4199	static __inline__ __m256 __DEFAULT_FN_ATTRS
				4200	_mm256_maskz_sqrt_ps (__mmask8 __U, __m256 __A) {
				4201	return (__m256) __builtin_ia32_sqrtps256_mask ((__v8sf) __A,
				4202	(__v8sf)
				4203	_mm256_setzero_ps (),
				4204	(__mmask8) __U);
				4205	}
				4206
				4207	static __inline__ __m128d __DEFAULT_FN_ATTRS
				4208	_mm_mask_sub_pd (__m128d __W, __mmask8 __U, __m128d __A, __m128d __B) {
				4209	return (__m128d) __builtin_ia32_subpd128_mask ((__v2df) __A,
				4210	(__v2df) __B,
				4211	(__v2df) __W,
				4212	(__mmask8) __U);
				4213	}
				4214
				4215	static __inline__ __m128d __DEFAULT_FN_ATTRS
				4216	_mm_maskz_sub_pd (__mmask8 __U, __m128d __A, __m128d __B) {
				4217	return (__m128d) __builtin_ia32_subpd128_mask ((__v2df) __A,
				4218	(__v2df) __B,
				4219	(__v2df)
				4220	_mm_setzero_pd (),
				4221	(__mmask8) __U);
				4222	}
				4223
				4224	static __inline__ __m256d __DEFAULT_FN_ATTRS
				4225	_mm256_mask_sub_pd (__m256d __W, __mmask8 __U, __m256d __A,
				4226	__m256d __B) {
				4227	return (__m256d) __builtin_ia32_subpd256_mask ((__v4df) __A,
				4228	(__v4df) __B,
				4229	(__v4df) __W,
				4230	(__mmask8) __U);
				4231	}
				4232
				4233	static __inline__ __m256d __DEFAULT_FN_ATTRS
				4234	_mm256_maskz_sub_pd (__mmask8 __U, __m256d __A, __m256d __B) {
				4235	return (__m256d) __builtin_ia32_subpd256_mask ((__v4df) __A,
				4236	(__v4df) __B,
				4237	(__v4df)
				4238	_mm256_setzero_pd (),
				4239	(__mmask8) __U);
				4240	}
				4241
				4242	static __inline__ __m128 __DEFAULT_FN_ATTRS
				4243	_mm_mask_sub_ps (__m128 __W, __mmask16 __U, __m128 __A, __m128 __B) {
				4244	return (__m128) __builtin_ia32_subps128_mask ((__v4sf) __A,
				4245	(__v4sf) __B,
				4246	(__v4sf) __W,
				4247	(__mmask8) __U);
				4248	}
				4249
				4250	static __inline__ __m128 __DEFAULT_FN_ATTRS
				4251	_mm_maskz_sub_ps (__mmask16 __U, __m128 __A, __m128 __B) {
				4252	return (__m128) __builtin_ia32_subps128_mask ((__v4sf) __A,
				4253	(__v4sf) __B,
				4254	(__v4sf)
				4255	_mm_setzero_ps (),
				4256	(__mmask8) __U);
				4257	}
				4258
				4259	static __inline__ __m256 __DEFAULT_FN_ATTRS
				4260	_mm256_mask_sub_ps (__m256 __W, __mmask16 __U, __m256 __A, __m256 __B) {
				4261	return (__m256) __builtin_ia32_subps256_mask ((__v8sf) __A,
				4262	(__v8sf) __B,
				4263	(__v8sf) __W,
				4264	(__mmask8) __U);
				4265	}
				4266
				4267	static __inline__ __m256 __DEFAULT_FN_ATTRS
				4268	_mm256_maskz_sub_ps (__mmask16 __U, __m256 __A, __m256 __B) {
				4269	return (__m256) __builtin_ia32_subps256_mask ((__v8sf) __A,
				4270	(__v8sf) __B,
				4271	(__v8sf)
				4272	_mm256_setzero_ps (),
				4273	(__mmask8) __U);
				4274	}
				4275
				4276	static __inline__ __m128i __DEFAULT_FN_ATTRS
				4277	_mm_mask2_permutex2var_epi32 (__m128i __A, __m128i __I, __mmask8 __U,
				4278	__m128i __B) {
				4279	return (__m128i) __builtin_ia32_vpermi2vard128_mask ((__v4si) __A,
				4280	(__v4si) __I
				4281	/* idx */ ,
				4282	(__v4si) __B,
				4283	(__mmask8) __U);
				4284	}
				4285
				4286	static __inline__ __m256i __DEFAULT_FN_ATTRS
				4287	_mm256_mask2_permutex2var_epi32 (__m256i __A, __m256i __I,
				4288	__mmask8 __U, __m256i __B) {
				4289	return (__m256i) __builtin_ia32_vpermi2vard256_mask ((__v8si) __A,
				4290	(__v8si) __I
				4291	/* idx */ ,
				4292	(__v8si) __B,
				4293	(__mmask8) __U);
				4294	}
				4295
				4296	static __inline__ __m128d __DEFAULT_FN_ATTRS
				4297	_mm_mask2_permutex2var_pd (__m128d __A, __m128i __I, __mmask8 __U,
				4298	__m128d __B) {
				4299	return (__m128d) __builtin_ia32_vpermi2varpd128_mask ((__v2df) __A,
				4300	(__v2di) __I
				4301	/* idx */ ,
				4302	(__v2df) __B,
				4303	(__mmask8)
				4304	__U);
				4305	}
				4306
				4307	static __inline__ __m256d __DEFAULT_FN_ATTRS
				4308	_mm256_mask2_permutex2var_pd (__m256d __A, __m256i __I, __mmask8 __U,
				4309	__m256d __B) {
				4310	return (__m256d) __builtin_ia32_vpermi2varpd256_mask ((__v4df) __A,
				4311	(__v4di) __I
				4312	/* idx */ ,
				4313	(__v4df) __B,
				4314	(__mmask8)
				4315	__U);
				4316	}
				4317
				4318	static __inline__ __m128 __DEFAULT_FN_ATTRS
				4319	_mm_mask2_permutex2var_ps (__m128 __A, __m128i __I, __mmask8 __U,
				4320	__m128 __B) {
				4321	return (__m128) __builtin_ia32_vpermi2varps128_mask ((__v4sf) __A,
				4322	(__v4si) __I
				4323	/* idx */ ,
				4324	(__v4sf) __B,
				4325	(__mmask8) __U);
				4326	}
				4327
				4328	static __inline__ __m256 __DEFAULT_FN_ATTRS
				4329	_mm256_mask2_permutex2var_ps (__m256 __A, __m256i __I, __mmask8 __U,
				4330	__m256 __B) {
				4331	return (__m256) __builtin_ia32_vpermi2varps256_mask ((__v8sf) __A,
				4332	(__v8si) __I
				4333	/* idx */ ,
				4334	(__v8sf) __B,
				4335	(__mmask8) __U);
				4336	}
				4337
				4338	static __inline__ __m128i __DEFAULT_FN_ATTRS
				4339	_mm_mask2_permutex2var_epi64 (__m128i __A, __m128i __I, __mmask8 __U,
				4340	__m128i __B) {
				4341	return (__m128i) __builtin_ia32_vpermi2varq128_mask ((__v2di) __A,
				4342	(__v2di) __I
				4343	/* idx */ ,
				4344	(__v2di) __B,
				4345	(__mmask8) __U);
				4346	}
				4347
				4348	static __inline__ __m256i __DEFAULT_FN_ATTRS
				4349	_mm256_mask2_permutex2var_epi64 (__m256i __A, __m256i __I,
				4350	__mmask8 __U, __m256i __B) {
				4351	return (__m256i) __builtin_ia32_vpermi2varq256_mask ((__v4di) __A,
				4352	(__v4di) __I
				4353	/* idx */ ,
				4354	(__v4di) __B,
				4355	(__mmask8) __U);
				4356	}
				4357
				4358	static __inline__ __m128i __DEFAULT_FN_ATTRS
				4359	_mm_permutex2var_epi32 (__m128i __A, __m128i __I, __m128i __B) {
				4360	return (__m128i) __builtin_ia32_vpermt2vard128_mask ((__v4si) __I
				4361	/* idx */ ,
				4362	(__v4si) __A,
				4363	(__v4si) __B,
				4364	(__mmask8) -1);
				4365	}
				4366
				4367	static __inline__ __m128i __DEFAULT_FN_ATTRS
				4368	_mm_mask_permutex2var_epi32 (__m128i __A, __mmask8 __U, __m128i __I,
				4369	__m128i __B) {
				4370	return (__m128i) __builtin_ia32_vpermt2vard128_mask ((__v4si) __I
				4371	/* idx */ ,
				4372	(__v4si) __A,
				4373	(__v4si) __B,
				4374	(__mmask8) __U);
				4375	}
				4376
				4377	static __inline__ __m128i __DEFAULT_FN_ATTRS
				4378	_mm_maskz_permutex2var_epi32 (__mmask8 __U, __m128i __A, __m128i __I,
				4379	__m128i __B) {
				4380	return (__m128i) __builtin_ia32_vpermt2vard128_maskz ((__v4si) __I
				4381	/* idx */ ,
				4382	(__v4si) __A,
				4383	(__v4si) __B,
				4384	(__mmask8)
				4385	__U);
				4386	}
				4387
				4388	static __inline__ __m256i __DEFAULT_FN_ATTRS
				4389	_mm256_permutex2var_epi32 (__m256i __A, __m256i __I, __m256i __B) {
				4390	return (__m256i) __builtin_ia32_vpermt2vard256_mask ((__v8si) __I
				4391	/* idx */ ,
				4392	(__v8si) __A,
				4393	(__v8si) __B,
				4394	(__mmask8) -1);
				4395	}
				4396
				4397	static __inline__ __m256i __DEFAULT_FN_ATTRS
				4398	_mm256_mask_permutex2var_epi32 (__m256i __A, __mmask8 __U, __m256i __I,
				4399	__m256i __B) {
				4400	return (__m256i) __builtin_ia32_vpermt2vard256_mask ((__v8si) __I
				4401	/* idx */ ,
				4402	(__v8si) __A,
				4403	(__v8si) __B,
				4404	(__mmask8) __U);
				4405	}
				4406
				4407	static __inline__ __m256i __DEFAULT_FN_ATTRS
				4408	_mm256_maskz_permutex2var_epi32 (__mmask8 __U, __m256i __A,
				4409	__m256i __I, __m256i __B) {
				4410	return (__m256i) __builtin_ia32_vpermt2vard256_maskz ((__v8si) __I
				4411	/* idx */ ,
				4412	(__v8si) __A,
				4413	(__v8si) __B,
				4414	(__mmask8)
				4415	__U);
				4416	}
				4417
				4418	static __inline__ __m128d __DEFAULT_FN_ATTRS
				4419	_mm_permutex2var_pd (__m128d __A, __m128i __I, __m128d __B) {
				4420	return (__m128d) __builtin_ia32_vpermt2varpd128_mask ((__v2di) __I
				4421	/* idx */ ,
				4422	(__v2df) __A,
				4423	(__v2df) __B,
				4424	(__mmask8) -
				4425	1);
				4426	}
				4427
				4428	static __inline__ __m128d __DEFAULT_FN_ATTRS
				4429	_mm_mask_permutex2var_pd (__m128d __A, __mmask8 __U, __m128i __I,
				4430	__m128d __B) {
				4431	return (__m128d) __builtin_ia32_vpermt2varpd128_mask ((__v2di) __I
				4432	/* idx */ ,
				4433	(__v2df) __A,
				4434	(__v2df) __B,
				4435	(__mmask8)
				4436	__U);
				4437	}
				4438
				4439	static __inline__ __m128d __DEFAULT_FN_ATTRS
				4440	_mm_maskz_permutex2var_pd (__mmask8 __U, __m128d __A, __m128i __I,
				4441	__m128d __B) {
				4442	return (__m128d) __builtin_ia32_vpermt2varpd128_maskz ((__v2di) __I
				4443	/* idx */ ,
				4444	(__v2df) __A,
				4445	(__v2df) __B,
				4446	(__mmask8)
				4447	__U);
				4448	}
				4449
				4450	static __inline__ __m256d __DEFAULT_FN_ATTRS
				4451	_mm256_permutex2var_pd (__m256d __A, __m256i __I, __m256d __B) {
				4452	return (__m256d) __builtin_ia32_vpermt2varpd256_mask ((__v4di) __I
				4453	/* idx */ ,
				4454	(__v4df) __A,
				4455	(__v4df) __B,
				4456	(__mmask8) -
				4457	1);
				4458	}
				4459
				4460	static __inline__ __m256d __DEFAULT_FN_ATTRS
				4461	_mm256_mask_permutex2var_pd (__m256d __A, __mmask8 __U, __m256i __I,
				4462	__m256d __B) {
				4463	return (__m256d) __builtin_ia32_vpermt2varpd256_mask ((__v4di) __I
				4464	/* idx */ ,
				4465	(__v4df) __A,
				4466	(__v4df) __B,
				4467	(__mmask8)
				4468	__U);
				4469	}
				4470
				4471	static __inline__ __m256d __DEFAULT_FN_ATTRS
				4472	_mm256_maskz_permutex2var_pd (__mmask8 __U, __m256d __A, __m256i __I,
				4473	__m256d __B) {
				4474	return (__m256d) __builtin_ia32_vpermt2varpd256_maskz ((__v4di) __I
				4475	/* idx */ ,
				4476	(__v4df) __A,
				4477	(__v4df) __B,
				4478	(__mmask8)
				4479	__U);
				4480	}
				4481
				4482	static __inline__ __m128 __DEFAULT_FN_ATTRS
				4483	_mm_permutex2var_ps (__m128 __A, __m128i __I, __m128 __B) {
				4484	return (__m128) __builtin_ia32_vpermt2varps128_mask ((__v4si) __I
				4485	/* idx */ ,
				4486	(__v4sf) __A,
				4487	(__v4sf) __B,
				4488	(__mmask8) -1);
				4489	}
				4490
				4491	static __inline__ __m128 __DEFAULT_FN_ATTRS
				4492	_mm_mask_permutex2var_ps (__m128 __A, __mmask8 __U, __m128i __I,
				4493	__m128 __B) {
				4494	return (__m128) __builtin_ia32_vpermt2varps128_mask ((__v4si) __I
				4495	/* idx */ ,
				4496	(__v4sf) __A,
				4497	(__v4sf) __B,
				4498	(__mmask8) __U);
				4499	}
				4500
				4501	static __inline__ __m128 __DEFAULT_FN_ATTRS
				4502	_mm_maskz_permutex2var_ps (__mmask8 __U, __m128 __A, __m128i __I,
				4503	__m128 __B) {
				4504	return (__m128) __builtin_ia32_vpermt2varps128_maskz ((__v4si) __I
				4505	/* idx */ ,
				4506	(__v4sf) __A,
				4507	(__v4sf) __B,
				4508	(__mmask8)
				4509	__U);
				4510	}
				4511
				4512	static __inline__ __m256 __DEFAULT_FN_ATTRS
				4513	_mm256_permutex2var_ps (__m256 __A, __m256i __I, __m256 __B) {
				4514	return (__m256) __builtin_ia32_vpermt2varps256_mask ((__v8si) __I
				4515	/* idx */ ,
				4516	(__v8sf) __A,
				4517	(__v8sf) __B,
				4518	(__mmask8) -1);
				4519	}
				4520
				4521	static __inline__ __m256 __DEFAULT_FN_ATTRS
				4522	_mm256_mask_permutex2var_ps (__m256 __A, __mmask8 __U, __m256i __I,
				4523	__m256 __B) {
				4524	return (__m256) __builtin_ia32_vpermt2varps256_mask ((__v8si) __I
				4525	/* idx */ ,
				4526	(__v8sf) __A,
				4527	(__v8sf) __B,
				4528	(__mmask8) __U);
				4529	}
				4530
				4531	static __inline__ __m256 __DEFAULT_FN_ATTRS
				4532	_mm256_maskz_permutex2var_ps (__mmask8 __U, __m256 __A, __m256i __I,
				4533	__m256 __B) {
				4534	return (__m256) __builtin_ia32_vpermt2varps256_maskz ((__v8si) __I
				4535	/* idx */ ,
				4536	(__v8sf) __A,
				4537	(__v8sf) __B,
				4538	(__mmask8)
				4539	__U);
				4540	}
				4541
				4542	static __inline__ __m128i __DEFAULT_FN_ATTRS
				4543	_mm_permutex2var_epi64 (__m128i __A, __m128i __I, __m128i __B) {
				4544	return (__m128i) __builtin_ia32_vpermt2varq128_mask ((__v2di) __I
				4545	/* idx */ ,
				4546	(__v2di) __A,
				4547	(__v2di) __B,
				4548	(__mmask8) -1);
				4549	}
				4550
				4551	static __inline__ __m128i __DEFAULT_FN_ATTRS
				4552	_mm_mask_permutex2var_epi64 (__m128i __A, __mmask8 __U, __m128i __I,
				4553	__m128i __B) {
				4554	return (__m128i) __builtin_ia32_vpermt2varq128_mask ((__v2di) __I
				4555	/* idx */ ,
				4556	(__v2di) __A,
				4557	(__v2di) __B,
				4558	(__mmask8) __U);
				4559	}
				4560
				4561	static __inline__ __m128i __DEFAULT_FN_ATTRS
				4562	_mm_maskz_permutex2var_epi64 (__mmask8 __U, __m128i __A, __m128i __I,
				4563	__m128i __B) {
				4564	return (__m128i) __builtin_ia32_vpermt2varq128_maskz ((__v2di) __I
				4565	/* idx */ ,
				4566	(__v2di) __A,
				4567	(__v2di) __B,
				4568	(__mmask8)
				4569	__U);
				4570	}
				4571
				4572
				4573	static __inline__ __m256i __DEFAULT_FN_ATTRS
				4574	_mm256_permutex2var_epi64 (__m256i __A, __m256i __I, __m256i __B) {
				4575	return (__m256i) __builtin_ia32_vpermt2varq256_mask ((__v4di) __I
				4576	/* idx */ ,
				4577	(__v4di) __A,
				4578	(__v4di) __B,
				4579	(__mmask8) -1);
				4580	}
				4581
				4582	static __inline__ __m256i __DEFAULT_FN_ATTRS
				4583	_mm256_mask_permutex2var_epi64 (__m256i __A, __mmask8 __U, __m256i __I,
				4584	__m256i __B) {
				4585	return (__m256i) __builtin_ia32_vpermt2varq256_mask ((__v4di) __I
				4586	/* idx */ ,
				4587	(__v4di) __A,
				4588	(__v4di) __B,
				4589	(__mmask8) __U);
				4590	}
				4591
				4592	static __inline__ __m256i __DEFAULT_FN_ATTRS
				4593	_mm256_maskz_permutex2var_epi64 (__mmask8 __U, __m256i __A,
				4594	__m256i __I, __m256i __B) {
				4595	return (__m256i) __builtin_ia32_vpermt2varq256_maskz ((__v4di) __I
				4596	/* idx */ ,
				4597	(__v4di) __A,
				4598	(__v4di) __B,
				4599	(__mmask8)
				4600	__U);
				4601	}
				4602
Michael Zuckerman	7cdb72f	2016-02-18 09:09:34 +0000	[diff] [blame^]	4603	static __inline__ __m128i __DEFAULT_FN_ATTRS
				4604	_mm_mask_cvtepi8_epi32 (__m128i __W, __mmask8 __U, __m128i __A)
				4605	{
				4606	return (__m128i) __builtin_ia32_pmovsxbd128_mask ((__v16qi) __A,
				4607	(__v4si) __W,
				4608	(__mmask8) __U);
				4609	}
				4610
				4611	static __inline__ __m128i __DEFAULT_FN_ATTRS
				4612	_mm_maskz_cvtepi8_epi32 (__mmask8 __U, __m128i __A)
				4613	{
				4614	return (__m128i) __builtin_ia32_pmovsxbd128_mask ((__v16qi) __A,
				4615	(__v4si)
				4616	_mm_setzero_si128 (),
				4617	(__mmask8) __U);
				4618	}
				4619
				4620	static __inline__ __m256i __DEFAULT_FN_ATTRS
				4621	_mm256_mask_cvtepi8_epi32 (__m256i __W, __mmask8 __U, __m128i __A)
				4622	{
				4623	return (__m256i) __builtin_ia32_pmovsxbd256_mask ((__v16qi) __A,
				4624	(__v8si) __W,
				4625	(__mmask8) __U);
				4626	}
				4627
				4628	static __inline__ __m256i __DEFAULT_FN_ATTRS
				4629	_mm256_maskz_cvtepi8_epi32 (__mmask8 __U, __m128i __A)
				4630	{
				4631	return (__m256i) __builtin_ia32_pmovsxbd256_mask ((__v16qi) __A,
				4632	(__v8si)
				4633	_mm256_setzero_si256 (),
				4634	(__mmask8) __U);
				4635	}
				4636
				4637	static __inline__ __m128i __DEFAULT_FN_ATTRS
				4638	_mm_mask_cvtepi8_epi64 (__m128i __W, __mmask8 __U, __m128i __A)
				4639	{
				4640	return (__m128i) __builtin_ia32_pmovsxbq128_mask ((__v16qi) __A,
				4641	(__v2di) __W,
				4642	(__mmask8) __U);
				4643	}
				4644
				4645	static __inline__ __m128i __DEFAULT_FN_ATTRS
				4646	_mm_maskz_cvtepi8_epi64 (__mmask8 __U, __m128i __A)
				4647	{
				4648	return (__m128i) __builtin_ia32_pmovsxbq128_mask ((__v16qi) __A,
				4649	(__v2di)
				4650	_mm_setzero_si128 (),
				4651	(__mmask8) __U);
				4652	}
				4653
				4654	static __inline__ __m256i __DEFAULT_FN_ATTRS
				4655	_mm256_mask_cvtepi8_epi64 (__m256i __W, __mmask8 __U, __m128i __A)
				4656	{
				4657	return (__m256i) __builtin_ia32_pmovsxbq256_mask ((__v16qi) __A,
				4658	(__v4di) __W,
				4659	(__mmask8) __U);
				4660	}
				4661
				4662	static __inline__ __m256i __DEFAULT_FN_ATTRS
				4663	_mm256_maskz_cvtepi8_epi64 (__mmask8 __U, __m128i __A)
				4664	{
				4665	return (__m256i) __builtin_ia32_pmovsxbq256_mask ((__v16qi) __A,
				4666	(__v4di)
				4667	_mm256_setzero_si256 (),
				4668	(__mmask8) __U);
				4669	}
				4670
				4671	static __inline__ __m128i __DEFAULT_FN_ATTRS
				4672	_mm_mask_cvtepi32_epi64 (__m128i __W, __mmask8 __U, __m128i __X)
				4673	{
				4674	return (__m128i) __builtin_ia32_pmovsxdq128_mask ((__v4si) __X,
				4675	(__v2di) __W,
				4676	(__mmask8) __U);
				4677	}
				4678
				4679	static __inline__ __m128i __DEFAULT_FN_ATTRS
				4680	_mm_maskz_cvtepi32_epi64 (__mmask8 __U, __m128i __X)
				4681	{
				4682	return (__m128i) __builtin_ia32_pmovsxdq128_mask ((__v4si) __X,
				4683	(__v2di)
				4684	_mm_setzero_si128 (),
				4685	(__mmask8) __U);
				4686	}
				4687
				4688	static __inline__ __m256i __DEFAULT_FN_ATTRS
				4689	_mm256_mask_cvtepi32_epi64 (__m256i __W, __mmask8 __U, __m128i __X)
				4690	{
				4691	return (__m256i) __builtin_ia32_pmovsxdq256_mask ((__v4si) __X,
				4692	(__v4di) __W,
				4693	(__mmask8) __U);
				4694	}
				4695
				4696	static __inline__ __m256i __DEFAULT_FN_ATTRS
				4697	_mm256_maskz_cvtepi32_epi64 (__mmask8 __U, __m128i __X)
				4698	{
				4699	return (__m256i) __builtin_ia32_pmovsxdq256_mask ((__v4si) __X,
				4700	(__v4di)
				4701	_mm256_setzero_si256 (),
				4702	(__mmask8) __U);
				4703	}
				4704
				4705	static __inline__ __m128i __DEFAULT_FN_ATTRS
				4706	_mm_mask_cvtepi16_epi32 (__m128i __W, __mmask8 __U, __m128i __A)
				4707	{
				4708	return (__m128i) __builtin_ia32_pmovsxwd128_mask ((__v8hi) __A,
				4709	(__v4si) __W,
				4710	(__mmask8) __U);
				4711	}
				4712
				4713	static __inline__ __m128i __DEFAULT_FN_ATTRS
				4714	_mm_maskz_cvtepi16_epi32 (__mmask8 __U, __m128i __A)
				4715	{
				4716	return (__m128i) __builtin_ia32_pmovsxwd128_mask ((__v8hi) __A,
				4717	(__v4si)
				4718	_mm_setzero_si128 (),
				4719	(__mmask8) __U);
				4720	}
				4721
				4722	static __inline__ __m256i __DEFAULT_FN_ATTRS
				4723	_mm256_mask_cvtepi16_epi32 (__m256i __W, __mmask8 __U, __m128i __A)
				4724	{
				4725	return (__m256i) __builtin_ia32_pmovsxwd256_mask ((__v8hi) __A,
				4726	(__v8si) __W,
				4727	(__mmask8) __U);
				4728	}
				4729
				4730	static __inline__ __m256i __DEFAULT_FN_ATTRS
				4731	_mm256_maskz_cvtepi16_epi32 (__mmask8 __U, __m128i __A)
				4732	{
				4733	return (__m256i) __builtin_ia32_pmovsxwd256_mask ((__v8hi) __A,
				4734	(__v8si)
				4735	_mm256_setzero_si256 (),
				4736	(__mmask8) __U);
				4737	}
				4738
				4739	static __inline__ __m128i __DEFAULT_FN_ATTRS
				4740	_mm_mask_cvtepi16_epi64 (__m128i __W, __mmask8 __U, __m128i __A)
				4741	{
				4742	return (__m128i) __builtin_ia32_pmovsxwq128_mask ((__v8hi) __A,
				4743	(__v2di) __W,
				4744	(__mmask8) __U);
				4745	}
				4746
				4747	static __inline__ __m128i __DEFAULT_FN_ATTRS
				4748	_mm_maskz_cvtepi16_epi64 (__mmask8 __U, __m128i __A)
				4749	{
				4750	return (__m128i) __builtin_ia32_pmovsxwq128_mask ((__v8hi) __A,
				4751	(__v2di)
				4752	_mm_setzero_si128 (),
				4753	(__mmask8) __U);
				4754	}
				4755
				4756	static __inline__ __m256i __DEFAULT_FN_ATTRS
				4757	_mm256_mask_cvtepi16_epi64 (__m256i __W, __mmask8 __U, __m128i __A)
				4758	{
				4759	return (__m256i) __builtin_ia32_pmovsxwq256_mask ((__v8hi) __A,
				4760	(__v4di) __W,
				4761	(__mmask8) __U);
				4762	}
				4763
				4764	static __inline__ __m256i __DEFAULT_FN_ATTRS
				4765	_mm256_maskz_cvtepi16_epi64 (__mmask8 __U, __m128i __A)
				4766	{
				4767	return (__m256i) __builtin_ia32_pmovsxwq256_mask ((__v8hi) __A,
				4768	(__v4di)
				4769	_mm256_setzero_si256 (),
				4770	(__mmask8) __U);
				4771	}
				4772
				4773
Michael Kuperstein	e45af54	2015-06-30 13:36:19 +0000	[diff] [blame]	4774	#undef __DEFAULT_FN_ATTRS
Eric Christopher	99af5b2	2015-10-27 06:11:03 +0000	[diff] [blame]	4775	#undef __DEFAULT_FN_ATTRS_BOTH
Eric Christopher	4d185168	2015-06-17 07:09:20 +0000	[diff] [blame]	4776
Robert Khasanov	b9f3a91	2014-10-08 17:18:13 +0000	[diff] [blame]	4777	#endif /* __AVX512VLINTRIN_H */