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gerrit-public.fairphone.software / toolchain / llvm-project / 81fcf865be23275a1421df5cdeeed8651259817c / . / llvm / lib / Target / AArch64 / Disassembler / AArch64Disassembler.cpp
blob: b4a554e0658de0bf6c78c5914d352b5e3929ff9b [file] [log] [blame]
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]1//===- AArch64Disassembler.cpp - Disassembler for AArch64 -----------------===//
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]2//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10//
11//===----------------------------------------------------------------------===//
12
13#include "AArch64Disassembler.h"
14#include "AArch64ExternalSymbolizer.h"
15#include "AArch64Subtarget.h"
16#include "MCTargetDesc/AArch64AddressingModes.h"
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]17#include "MCTargetDesc/AArch64MCTargetDesc.h"
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]18#include "Utils/AArch64BaseInfo.h"
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]19#include "llvm-c/Disassembler.h"
20#include "llvm/MC/MCDisassembler/MCRelocationInfo.h"
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]21#include "llvm/MC/MCFixedLenDisassembler.h"
Benjamin Kramer1f8930e2014-07-25 11:42:14 +0000[diff] [blame]22#include "llvm/MC/MCInst.h"
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]23#include "llvm/Support/Compiler.h"
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]24#include "llvm/Support/Debug.h"
Benjamin Kramer1f8930e2014-07-25 11:42:14 +0000[diff] [blame]25#include "llvm/Support/ErrorHandling.h"
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]26#include "llvm/Support/TargetRegistry.h"
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]27#include <algorithm>
28#include <memory>
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]29
30using namespace llvm;
31
32#define DEBUG_TYPE "aarch64-disassembler"
33
34// Pull DecodeStatus and its enum values into the global namespace.
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]35using DecodeStatus = MCDisassembler::DecodeStatus;
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]36
37// Forward declare these because the autogenerated code will reference them.
38// Definitions are further down.
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]39static DecodeStatus DecodeFPR128RegisterClass(MCInst &Inst,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]40 unsigned RegNo, uint64_t Address,
41 const void *Decoder);
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]42static DecodeStatus DecodeFPR128_loRegisterClass(MCInst &Inst,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]43 unsigned RegNo,
44 uint64_t Address,
45 const void *Decoder);
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]46static DecodeStatus DecodeFPR64RegisterClass(MCInst &Inst, unsigned RegNo,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]47 uint64_t Address,
48 const void *Decoder);
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]49static DecodeStatus DecodeFPR32RegisterClass(MCInst &Inst, unsigned RegNo,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]50 uint64_t Address,
51 const void *Decoder);
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]52static DecodeStatus DecodeFPR16RegisterClass(MCInst &Inst, unsigned RegNo,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]53 uint64_t Address,
54 const void *Decoder);
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]55static DecodeStatus DecodeFPR8RegisterClass(MCInst &Inst, unsigned RegNo,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]56 uint64_t Address,
57 const void *Decoder);
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]58static DecodeStatus DecodeGPR64RegisterClass(MCInst &Inst, unsigned RegNo,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]59 uint64_t Address,
60 const void *Decoder);
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]61static DecodeStatus DecodeGPR64spRegisterClass(MCInst &Inst,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]62 unsigned RegNo, uint64_t Address,
63 const void *Decoder);
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]64static DecodeStatus DecodeGPR32RegisterClass(MCInst &Inst, unsigned RegNo,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]65 uint64_t Address,
66 const void *Decoder);
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]67static DecodeStatus DecodeGPR32spRegisterClass(MCInst &Inst,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]68 unsigned RegNo, uint64_t Address,
69 const void *Decoder);
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]70static DecodeStatus DecodeQQRegisterClass(MCInst &Inst, unsigned RegNo,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]71 uint64_t Address,
72 const void *Decoder);
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]73static DecodeStatus DecodeQQQRegisterClass(MCInst &Inst, unsigned RegNo,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]74 uint64_t Address,
75 const void *Decoder);
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]76static DecodeStatus DecodeQQQQRegisterClass(MCInst &Inst, unsigned RegNo,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]77 uint64_t Address,
78 const void *Decoder);
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]79static DecodeStatus DecodeDDRegisterClass(MCInst &Inst, unsigned RegNo,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]80 uint64_t Address,
81 const void *Decoder);
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]82static DecodeStatus DecodeDDDRegisterClass(MCInst &Inst, unsigned RegNo,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]83 uint64_t Address,
84 const void *Decoder);
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]85static DecodeStatus DecodeDDDDRegisterClass(MCInst &Inst, unsigned RegNo,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]86 uint64_t Address,
87 const void *Decoder);
Florian Hahn91f11e52017-11-07 16:45:48 +0000[diff] [blame]88static DecodeStatus DecodeZPRRegisterClass(MCInst &Inst, unsigned RegNo,
89 uint64_t Address,
90 const void *Decode);
Sander de Smalencd6be962017-12-20 11:02:42 +0000[diff] [blame]91static DecodeStatus DecodePPRRegisterClass(MCInst &Inst, unsigned RegNo,
92 uint64_t Address,
93 const void *Decode);
Sander de Smalen906a5de2018-01-09 17:01:27 +0000[diff] [blame]94static DecodeStatus DecodePPR_3bRegisterClass(MCInst &Inst, unsigned RegNo,
95 uint64_t Address,
96 const void *Decode);
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]97
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]98static DecodeStatus DecodeFixedPointScaleImm32(MCInst &Inst, unsigned Imm,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]99 uint64_t Address,
100 const void *Decoder);
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]101static DecodeStatus DecodeFixedPointScaleImm64(MCInst &Inst, unsigned Imm,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]102 uint64_t Address,
103 const void *Decoder);
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]104static DecodeStatus DecodePCRelLabel19(MCInst &Inst, unsigned Imm,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]105 uint64_t Address, const void *Decoder);
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]106static DecodeStatus DecodeMemExtend(MCInst &Inst, unsigned Imm,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]107 uint64_t Address, const void *Decoder);
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]108static DecodeStatus DecodeMRSSystemRegister(MCInst &Inst, unsigned Imm,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]109 uint64_t Address, const void *Decoder);
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]110static DecodeStatus DecodeMSRSystemRegister(MCInst &Inst, unsigned Imm,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]111 uint64_t Address, const void *Decoder);
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]112static DecodeStatus DecodeThreeAddrSRegInstruction(MCInst &Inst, uint32_t insn,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]113 uint64_t Address,
114 const void *Decoder);
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]115static DecodeStatus DecodeMoveImmInstruction(MCInst &Inst, uint32_t insn,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]116 uint64_t Address,
117 const void *Decoder);
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]118static DecodeStatus DecodeUnsignedLdStInstruction(MCInst &Inst, uint32_t insn,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]119 uint64_t Address,
120 const void *Decoder);
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]121static DecodeStatus DecodeSignedLdStInstruction(MCInst &Inst, uint32_t insn,
122 uint64_t Address,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]123 const void *Decoder);
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]124static DecodeStatus DecodeExclusiveLdStInstruction(MCInst &Inst, uint32_t insn,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]125 uint64_t Address,
126 const void *Decoder);
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]127static DecodeStatus DecodePairLdStInstruction(MCInst &Inst, uint32_t insn,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]128 uint64_t Address,
129 const void *Decoder);
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]130static DecodeStatus DecodeAddSubERegInstruction(MCInst &Inst, uint32_t insn,
131 uint64_t Address,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]132 const void *Decoder);
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]133static DecodeStatus DecodeLogicalImmInstruction(MCInst &Inst, uint32_t insn,
134 uint64_t Address,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]135 const void *Decoder);
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]136static DecodeStatus DecodeModImmInstruction(MCInst &Inst, uint32_t insn,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]137 uint64_t Address,
138 const void *Decoder);
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]139static DecodeStatus DecodeModImmTiedInstruction(MCInst &Inst, uint32_t insn,
140 uint64_t Address,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]141 const void *Decoder);
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]142static DecodeStatus DecodeAdrInstruction(MCInst &Inst, uint32_t insn,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]143 uint64_t Address, const void *Decoder);
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]144static DecodeStatus DecodeBaseAddSubImm(MCInst &Inst, uint32_t insn,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]145 uint64_t Address, const void *Decoder);
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]146static DecodeStatus DecodeUnconditionalBranch(MCInst &Inst, uint32_t insn,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]147 uint64_t Address,
148 const void *Decoder);
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]149static DecodeStatus DecodeSystemPStateInstruction(MCInst &Inst, uint32_t insn,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]150 uint64_t Address,
151 const void *Decoder);
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]152static DecodeStatus DecodeTestAndBranch(MCInst &Inst, uint32_t insn,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]153 uint64_t Address, const void *Decoder);
154
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]155static DecodeStatus DecodeFMOVLaneInstruction(MCInst &Inst, unsigned Insn,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]156 uint64_t Address,
157 const void *Decoder);
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]158static DecodeStatus DecodeVecShiftR64Imm(MCInst &Inst, unsigned Imm,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]159 uint64_t Addr, const void *Decoder);
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]160static DecodeStatus DecodeVecShiftR64ImmNarrow(MCInst &Inst, unsigned Imm,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]161 uint64_t Addr,
162 const void *Decoder);
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]163static DecodeStatus DecodeVecShiftR32Imm(MCInst &Inst, unsigned Imm,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]164 uint64_t Addr, const void *Decoder);
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]165static DecodeStatus DecodeVecShiftR32ImmNarrow(MCInst &Inst, unsigned Imm,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]166 uint64_t Addr,
167 const void *Decoder);
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]168static DecodeStatus DecodeVecShiftR16Imm(MCInst &Inst, unsigned Imm,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]169 uint64_t Addr, const void *Decoder);
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]170static DecodeStatus DecodeVecShiftR16ImmNarrow(MCInst &Inst, unsigned Imm,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]171 uint64_t Addr,
172 const void *Decoder);
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]173static DecodeStatus DecodeVecShiftR8Imm(MCInst &Inst, unsigned Imm,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]174 uint64_t Addr, const void *Decoder);
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]175static DecodeStatus DecodeVecShiftL64Imm(MCInst &Inst, unsigned Imm,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]176 uint64_t Addr, const void *Decoder);
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]177static DecodeStatus DecodeVecShiftL32Imm(MCInst &Inst, unsigned Imm,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]178 uint64_t Addr, const void *Decoder);
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]179static DecodeStatus DecodeVecShiftL16Imm(MCInst &Inst, unsigned Imm,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]180 uint64_t Addr, const void *Decoder);
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]181static DecodeStatus DecodeVecShiftL8Imm(MCInst &Inst, unsigned Imm,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]182 uint64_t Addr, const void *Decoder);
Vladimir Sukharev5f6f60d2015-06-02 10:58:41 +0000[diff] [blame]183static DecodeStatus DecodeWSeqPairsClassRegisterClass(MCInst &Inst,
184 unsigned RegNo,
185 uint64_t Addr,
186 const void *Decoder);
187static DecodeStatus DecodeXSeqPairsClassRegisterClass(MCInst &Inst,
188 unsigned RegNo,
189 uint64_t Addr,
190 const void *Decoder);
Sander de Smalen81fcf862018-02-06 13:13:21 +0000[diff] [blame^]191static DecodeStatus DecodeSVELogicalImmInstruction(llvm::MCInst &Inst,
192 uint32_t insn,
193 uint64_t Address,
194 const void *Decoder);
Sam Parker6d42de72017-08-11 13:14:00 +0000[diff] [blame]195template<int Bits>
196static DecodeStatus DecodeSImm(llvm::MCInst &Inst, uint64_t Imm,
197 uint64_t Address, const void *Decoder);
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]198
199static bool Check(DecodeStatus &Out, DecodeStatus In) {
200 switch (In) {
201 case MCDisassembler::Success:
202 // Out stays the same.
203 return true;
204 case MCDisassembler::SoftFail:
205 Out = In;
206 return true;
207 case MCDisassembler::Fail:
208 Out = In;
209 return false;
210 }
211 llvm_unreachable("Invalid DecodeStatus!");
212}
213
214#include "AArch64GenDisassemblerTables.inc"
215#include "AArch64GenInstrInfo.inc"
216
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]217#define Success MCDisassembler::Success
218#define Fail MCDisassembler::Fail
219#define SoftFail MCDisassembler::SoftFail
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]220
221static MCDisassembler *createAArch64Disassembler(const Target &T,
222 const MCSubtargetInfo &STI,
223 MCContext &Ctx) {
224 return new AArch64Disassembler(STI, Ctx);
225}
226
227DecodeStatus AArch64Disassembler::getInstruction(MCInst &MI, uint64_t &Size,
Rafael Espindola7fc5b872014-11-12 02:04:27 +0000[diff] [blame]228 ArrayRef<uint8_t> Bytes,
Rafael Espindola4aa6bea2014-11-10 18:11:10 +0000[diff] [blame]229 uint64_t Address,
230 raw_ostream &OS,
231 raw_ostream &CS) const {
232 CommentStream = &CS;
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]233
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]234 Size = 0;
235 // We want to read exactly 4 bytes of data.
Rafael Espindola7fc5b872014-11-12 02:04:27 +0000[diff] [blame]236 if (Bytes.size() < 4)
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]237 return Fail;
238 Size = 4;
239
240 // Encoded as a small-endian 32-bit word in the stream.
Rafael Espindola4aa6bea2014-11-10 18:11:10 +0000[diff] [blame]241 uint32_t Insn =
242 (Bytes[3] << 24) | (Bytes[2] << 16) | (Bytes[1] << 8) | (Bytes[0] << 0);
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]243
244 // Calling the auto-generated decoder function.
Rafael Espindola4aa6bea2014-11-10 18:11:10 +0000[diff] [blame]245 return decodeInstruction(DecoderTable32, MI, Insn, Address, this, STI);
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]246}
247
Daniel Sanders50f17232015-09-15 16:17:27 +0000[diff] [blame]248static MCSymbolizer *
249createAArch64ExternalSymbolizer(const Triple &TT, LLVMOpInfoCallback GetOpInfo,
250 LLVMSymbolLookupCallback SymbolLookUp,
251 void *DisInfo, MCContext *Ctx,
252 std::unique_ptr<MCRelocationInfo> &&RelInfo) {
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]253 return new AArch64ExternalSymbolizer(*Ctx, std::move(RelInfo), GetOpInfo,
254 SymbolLookUp, DisInfo);
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]255}
256
257extern "C" void LLVMInitializeAArch64Disassembler() {
Mehdi Aminif42454b2016-10-09 23:00:34 +0000[diff] [blame]258 TargetRegistry::RegisterMCDisassembler(getTheAArch64leTarget(),
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]259 createAArch64Disassembler);
Mehdi Aminif42454b2016-10-09 23:00:34 +0000[diff] [blame]260 TargetRegistry::RegisterMCDisassembler(getTheAArch64beTarget(),
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]261 createAArch64Disassembler);
Mehdi Aminif42454b2016-10-09 23:00:34 +0000[diff] [blame]262 TargetRegistry::RegisterMCSymbolizer(getTheAArch64leTarget(),
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]263 createAArch64ExternalSymbolizer);
Mehdi Aminif42454b2016-10-09 23:00:34 +0000[diff] [blame]264 TargetRegistry::RegisterMCSymbolizer(getTheAArch64beTarget(),
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]265 createAArch64ExternalSymbolizer);
266
Mehdi Aminif42454b2016-10-09 23:00:34 +0000[diff] [blame]267 TargetRegistry::RegisterMCDisassembler(getTheARM64Target(),
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]268 createAArch64Disassembler);
Mehdi Aminif42454b2016-10-09 23:00:34 +0000[diff] [blame]269 TargetRegistry::RegisterMCSymbolizer(getTheARM64Target(),
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]270 createAArch64ExternalSymbolizer);
271}
272
273static const unsigned FPR128DecoderTable[] = {
274 AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3, AArch64::Q4,
275 AArch64::Q5, AArch64::Q6, AArch64::Q7, AArch64::Q8, AArch64::Q9,
276 AArch64::Q10, AArch64::Q11, AArch64::Q12, AArch64::Q13, AArch64::Q14,
277 AArch64::Q15, AArch64::Q16, AArch64::Q17, AArch64::Q18, AArch64::Q19,
278 AArch64::Q20, AArch64::Q21, AArch64::Q22, AArch64::Q23, AArch64::Q24,
279 AArch64::Q25, AArch64::Q26, AArch64::Q27, AArch64::Q28, AArch64::Q29,
280 AArch64::Q30, AArch64::Q31
281};
282
283static DecodeStatus DecodeFPR128RegisterClass(MCInst &Inst, unsigned RegNo,
284 uint64_t Addr,
285 const void *Decoder) {
286 if (RegNo > 31)
287 return Fail;
288
289 unsigned Register = FPR128DecoderTable[RegNo];
Jim Grosbache9119e42015-05-13 18:37:00 +0000[diff] [blame]290 Inst.addOperand(MCOperand::createReg(Register));
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]291 return Success;
292}
293
294static DecodeStatus DecodeFPR128_loRegisterClass(MCInst &Inst, unsigned RegNo,
295 uint64_t Addr,
296 const void *Decoder) {
297 if (RegNo > 15)
298 return Fail;
299 return DecodeFPR128RegisterClass(Inst, RegNo, Addr, Decoder);
300}
301
302static const unsigned FPR64DecoderTable[] = {
303 AArch64::D0, AArch64::D1, AArch64::D2, AArch64::D3, AArch64::D4,
304 AArch64::D5, AArch64::D6, AArch64::D7, AArch64::D8, AArch64::D9,
305 AArch64::D10, AArch64::D11, AArch64::D12, AArch64::D13, AArch64::D14,
306 AArch64::D15, AArch64::D16, AArch64::D17, AArch64::D18, AArch64::D19,
307 AArch64::D20, AArch64::D21, AArch64::D22, AArch64::D23, AArch64::D24,
308 AArch64::D25, AArch64::D26, AArch64::D27, AArch64::D28, AArch64::D29,
309 AArch64::D30, AArch64::D31
310};
311
312static DecodeStatus DecodeFPR64RegisterClass(MCInst &Inst, unsigned RegNo,
313 uint64_t Addr,
314 const void *Decoder) {
315 if (RegNo > 31)
316 return Fail;
317
318 unsigned Register = FPR64DecoderTable[RegNo];
Jim Grosbache9119e42015-05-13 18:37:00 +0000[diff] [blame]319 Inst.addOperand(MCOperand::createReg(Register));
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]320 return Success;
321}
322
323static const unsigned FPR32DecoderTable[] = {
324 AArch64::S0, AArch64::S1, AArch64::S2, AArch64::S3, AArch64::S4,
325 AArch64::S5, AArch64::S6, AArch64::S7, AArch64::S8, AArch64::S9,
326 AArch64::S10, AArch64::S11, AArch64::S12, AArch64::S13, AArch64::S14,
327 AArch64::S15, AArch64::S16, AArch64::S17, AArch64::S18, AArch64::S19,
328 AArch64::S20, AArch64::S21, AArch64::S22, AArch64::S23, AArch64::S24,
329 AArch64::S25, AArch64::S26, AArch64::S27, AArch64::S28, AArch64::S29,
330 AArch64::S30, AArch64::S31
331};
332
333static DecodeStatus DecodeFPR32RegisterClass(MCInst &Inst, unsigned RegNo,
334 uint64_t Addr,
335 const void *Decoder) {
336 if (RegNo > 31)
337 return Fail;
338
339 unsigned Register = FPR32DecoderTable[RegNo];
Jim Grosbache9119e42015-05-13 18:37:00 +0000[diff] [blame]340 Inst.addOperand(MCOperand::createReg(Register));
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]341 return Success;
342}
343
344static const unsigned FPR16DecoderTable[] = {
345 AArch64::H0, AArch64::H1, AArch64::H2, AArch64::H3, AArch64::H4,
346 AArch64::H5, AArch64::H6, AArch64::H7, AArch64::H8, AArch64::H9,
347 AArch64::H10, AArch64::H11, AArch64::H12, AArch64::H13, AArch64::H14,
348 AArch64::H15, AArch64::H16, AArch64::H17, AArch64::H18, AArch64::H19,
349 AArch64::H20, AArch64::H21, AArch64::H22, AArch64::H23, AArch64::H24,
350 AArch64::H25, AArch64::H26, AArch64::H27, AArch64::H28, AArch64::H29,
351 AArch64::H30, AArch64::H31
352};
353
354static DecodeStatus DecodeFPR16RegisterClass(MCInst &Inst, unsigned RegNo,
355 uint64_t Addr,
356 const void *Decoder) {
357 if (RegNo > 31)
358 return Fail;
359
360 unsigned Register = FPR16DecoderTable[RegNo];
Jim Grosbache9119e42015-05-13 18:37:00 +0000[diff] [blame]361 Inst.addOperand(MCOperand::createReg(Register));
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]362 return Success;
363}
364
365static const unsigned FPR8DecoderTable[] = {
366 AArch64::B0, AArch64::B1, AArch64::B2, AArch64::B3, AArch64::B4,
367 AArch64::B5, AArch64::B6, AArch64::B7, AArch64::B8, AArch64::B9,
368 AArch64::B10, AArch64::B11, AArch64::B12, AArch64::B13, AArch64::B14,
369 AArch64::B15, AArch64::B16, AArch64::B17, AArch64::B18, AArch64::B19,
370 AArch64::B20, AArch64::B21, AArch64::B22, AArch64::B23, AArch64::B24,
371 AArch64::B25, AArch64::B26, AArch64::B27, AArch64::B28, AArch64::B29,
372 AArch64::B30, AArch64::B31
373};
374
375static DecodeStatus DecodeFPR8RegisterClass(MCInst &Inst, unsigned RegNo,
376 uint64_t Addr,
377 const void *Decoder) {
378 if (RegNo > 31)
379 return Fail;
380
381 unsigned Register = FPR8DecoderTable[RegNo];
Jim Grosbache9119e42015-05-13 18:37:00 +0000[diff] [blame]382 Inst.addOperand(MCOperand::createReg(Register));
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]383 return Success;
384}
385
386static const unsigned GPR64DecoderTable[] = {
387 AArch64::X0, AArch64::X1, AArch64::X2, AArch64::X3, AArch64::X4,
388 AArch64::X5, AArch64::X6, AArch64::X7, AArch64::X8, AArch64::X9,
389 AArch64::X10, AArch64::X11, AArch64::X12, AArch64::X13, AArch64::X14,
390 AArch64::X15, AArch64::X16, AArch64::X17, AArch64::X18, AArch64::X19,
391 AArch64::X20, AArch64::X21, AArch64::X22, AArch64::X23, AArch64::X24,
392 AArch64::X25, AArch64::X26, AArch64::X27, AArch64::X28, AArch64::FP,
393 AArch64::LR, AArch64::XZR
394};
395
396static DecodeStatus DecodeGPR64RegisterClass(MCInst &Inst, unsigned RegNo,
397 uint64_t Addr,
398 const void *Decoder) {
399 if (RegNo > 31)
400 return Fail;
401
402 unsigned Register = GPR64DecoderTable[RegNo];
Jim Grosbache9119e42015-05-13 18:37:00 +0000[diff] [blame]403 Inst.addOperand(MCOperand::createReg(Register));
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]404 return Success;
405}
406
407static DecodeStatus DecodeGPR64spRegisterClass(MCInst &Inst, unsigned RegNo,
408 uint64_t Addr,
409 const void *Decoder) {
410 if (RegNo > 31)
411 return Fail;
412 unsigned Register = GPR64DecoderTable[RegNo];
413 if (Register == AArch64::XZR)
414 Register = AArch64::SP;
Jim Grosbache9119e42015-05-13 18:37:00 +0000[diff] [blame]415 Inst.addOperand(MCOperand::createReg(Register));
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]416 return Success;
417}
418
419static const unsigned GPR32DecoderTable[] = {
420 AArch64::W0, AArch64::W1, AArch64::W2, AArch64::W3, AArch64::W4,
421 AArch64::W5, AArch64::W6, AArch64::W7, AArch64::W8, AArch64::W9,
422 AArch64::W10, AArch64::W11, AArch64::W12, AArch64::W13, AArch64::W14,
423 AArch64::W15, AArch64::W16, AArch64::W17, AArch64::W18, AArch64::W19,
424 AArch64::W20, AArch64::W21, AArch64::W22, AArch64::W23, AArch64::W24,
425 AArch64::W25, AArch64::W26, AArch64::W27, AArch64::W28, AArch64::W29,
426 AArch64::W30, AArch64::WZR
427};
428
429static DecodeStatus DecodeGPR32RegisterClass(MCInst &Inst, unsigned RegNo,
430 uint64_t Addr,
431 const void *Decoder) {
432 if (RegNo > 31)
433 return Fail;
434
435 unsigned Register = GPR32DecoderTable[RegNo];
Jim Grosbache9119e42015-05-13 18:37:00 +0000[diff] [blame]436 Inst.addOperand(MCOperand::createReg(Register));
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]437 return Success;
438}
439
440static DecodeStatus DecodeGPR32spRegisterClass(MCInst &Inst, unsigned RegNo,
441 uint64_t Addr,
442 const void *Decoder) {
443 if (RegNo > 31)
444 return Fail;
445
446 unsigned Register = GPR32DecoderTable[RegNo];
447 if (Register == AArch64::WZR)
448 Register = AArch64::WSP;
Jim Grosbache9119e42015-05-13 18:37:00 +0000[diff] [blame]449 Inst.addOperand(MCOperand::createReg(Register));
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]450 return Success;
451}
Florian Hahn91f11e52017-11-07 16:45:48 +0000[diff] [blame]452static const unsigned ZPRDecoderTable[] = {
453 AArch64::Z0, AArch64::Z1, AArch64::Z2, AArch64::Z3,
454 AArch64::Z4, AArch64::Z5, AArch64::Z6, AArch64::Z7,
455 AArch64::Z8, AArch64::Z9, AArch64::Z10, AArch64::Z11,
456 AArch64::Z12, AArch64::Z13, AArch64::Z14, AArch64::Z15,
457 AArch64::Z16, AArch64::Z17, AArch64::Z18, AArch64::Z19,
458 AArch64::Z20, AArch64::Z21, AArch64::Z22, AArch64::Z23,
459 AArch64::Z24, AArch64::Z25, AArch64::Z26, AArch64::Z27,
460 AArch64::Z28, AArch64::Z29, AArch64::Z30, AArch64::Z31
461};
462
463static DecodeStatus DecodeZPRRegisterClass(MCInst &Inst, unsigned RegNo,
464 uint64_t Address,
465 const void* Decoder) {
466 if (RegNo > 31)
467 return Fail;
468
469 unsigned Register = ZPRDecoderTable[RegNo];
470 Inst.addOperand(MCOperand::createReg(Register));
471 return Success;
472}
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]473
Sander de Smalencd6be962017-12-20 11:02:42 +0000[diff] [blame]474static const unsigned PPRDecoderTable[] = {
475 AArch64::P0, AArch64::P1, AArch64::P2, AArch64::P3,
476 AArch64::P4, AArch64::P5, AArch64::P6, AArch64::P7,
477 AArch64::P8, AArch64::P9, AArch64::P10, AArch64::P11,
478 AArch64::P12, AArch64::P13, AArch64::P14, AArch64::P15
479};
480
481static DecodeStatus DecodePPRRegisterClass(MCInst &Inst, unsigned RegNo,
482 uint64_t Addr, const void *Decoder) {
483 if (RegNo > 15)
484 return Fail;
485
486 unsigned Register = PPRDecoderTable[RegNo];
487 Inst.addOperand(MCOperand::createReg(Register));
488 return Success;
489}
490
Sander de Smalendc5e0812018-01-03 10:15:46 +0000[diff] [blame]491static DecodeStatus DecodePPR_3bRegisterClass(MCInst &Inst, unsigned RegNo,
492 uint64_t Addr,
493 const void* Decoder) {
494 if (RegNo > 7)
495 return Fail;
496
497 // Just reuse the PPR decode table
498 return DecodePPRRegisterClass(Inst, RegNo, Addr, Decoder);
499}
500
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]501static const unsigned VectorDecoderTable[] = {
502 AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3, AArch64::Q4,
503 AArch64::Q5, AArch64::Q6, AArch64::Q7, AArch64::Q8, AArch64::Q9,
504 AArch64::Q10, AArch64::Q11, AArch64::Q12, AArch64::Q13, AArch64::Q14,
505 AArch64::Q15, AArch64::Q16, AArch64::Q17, AArch64::Q18, AArch64::Q19,
506 AArch64::Q20, AArch64::Q21, AArch64::Q22, AArch64::Q23, AArch64::Q24,
507 AArch64::Q25, AArch64::Q26, AArch64::Q27, AArch64::Q28, AArch64::Q29,
508 AArch64::Q30, AArch64::Q31
509};
510
511static DecodeStatus DecodeVectorRegisterClass(MCInst &Inst, unsigned RegNo,
512 uint64_t Addr,
513 const void *Decoder) {
514 if (RegNo > 31)
515 return Fail;
516
517 unsigned Register = VectorDecoderTable[RegNo];
Jim Grosbache9119e42015-05-13 18:37:00 +0000[diff] [blame]518 Inst.addOperand(MCOperand::createReg(Register));
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]519 return Success;
520}
521
522static const unsigned QQDecoderTable[] = {
523 AArch64::Q0_Q1, AArch64::Q1_Q2, AArch64::Q2_Q3, AArch64::Q3_Q4,
524 AArch64::Q4_Q5, AArch64::Q5_Q6, AArch64::Q6_Q7, AArch64::Q7_Q8,
525 AArch64::Q8_Q9, AArch64::Q9_Q10, AArch64::Q10_Q11, AArch64::Q11_Q12,
526 AArch64::Q12_Q13, AArch64::Q13_Q14, AArch64::Q14_Q15, AArch64::Q15_Q16,
527 AArch64::Q16_Q17, AArch64::Q17_Q18, AArch64::Q18_Q19, AArch64::Q19_Q20,
528 AArch64::Q20_Q21, AArch64::Q21_Q22, AArch64::Q22_Q23, AArch64::Q23_Q24,
529 AArch64::Q24_Q25, AArch64::Q25_Q26, AArch64::Q26_Q27, AArch64::Q27_Q28,
530 AArch64::Q28_Q29, AArch64::Q29_Q30, AArch64::Q30_Q31, AArch64::Q31_Q0
531};
532
533static DecodeStatus DecodeQQRegisterClass(MCInst &Inst, unsigned RegNo,
534 uint64_t Addr, const void *Decoder) {
535 if (RegNo > 31)
536 return Fail;
537 unsigned Register = QQDecoderTable[RegNo];
Jim Grosbache9119e42015-05-13 18:37:00 +0000[diff] [blame]538 Inst.addOperand(MCOperand::createReg(Register));
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]539 return Success;
540}
541
542static const unsigned QQQDecoderTable[] = {
543 AArch64::Q0_Q1_Q2, AArch64::Q1_Q2_Q3, AArch64::Q2_Q3_Q4,
544 AArch64::Q3_Q4_Q5, AArch64::Q4_Q5_Q6, AArch64::Q5_Q6_Q7,
545 AArch64::Q6_Q7_Q8, AArch64::Q7_Q8_Q9, AArch64::Q8_Q9_Q10,
546 AArch64::Q9_Q10_Q11, AArch64::Q10_Q11_Q12, AArch64::Q11_Q12_Q13,
547 AArch64::Q12_Q13_Q14, AArch64::Q13_Q14_Q15, AArch64::Q14_Q15_Q16,
548 AArch64::Q15_Q16_Q17, AArch64::Q16_Q17_Q18, AArch64::Q17_Q18_Q19,
549 AArch64::Q18_Q19_Q20, AArch64::Q19_Q20_Q21, AArch64::Q20_Q21_Q22,
550 AArch64::Q21_Q22_Q23, AArch64::Q22_Q23_Q24, AArch64::Q23_Q24_Q25,
551 AArch64::Q24_Q25_Q26, AArch64::Q25_Q26_Q27, AArch64::Q26_Q27_Q28,
552 AArch64::Q27_Q28_Q29, AArch64::Q28_Q29_Q30, AArch64::Q29_Q30_Q31,
553 AArch64::Q30_Q31_Q0, AArch64::Q31_Q0_Q1
554};
555
556static DecodeStatus DecodeQQQRegisterClass(MCInst &Inst, unsigned RegNo,
557 uint64_t Addr, const void *Decoder) {
558 if (RegNo > 31)
559 return Fail;
560 unsigned Register = QQQDecoderTable[RegNo];
Jim Grosbache9119e42015-05-13 18:37:00 +0000[diff] [blame]561 Inst.addOperand(MCOperand::createReg(Register));
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]562 return Success;
563}
564
565static const unsigned QQQQDecoderTable[] = {
566 AArch64::Q0_Q1_Q2_Q3, AArch64::Q1_Q2_Q3_Q4, AArch64::Q2_Q3_Q4_Q5,
567 AArch64::Q3_Q4_Q5_Q6, AArch64::Q4_Q5_Q6_Q7, AArch64::Q5_Q6_Q7_Q8,
568 AArch64::Q6_Q7_Q8_Q9, AArch64::Q7_Q8_Q9_Q10, AArch64::Q8_Q9_Q10_Q11,
569 AArch64::Q9_Q10_Q11_Q12, AArch64::Q10_Q11_Q12_Q13, AArch64::Q11_Q12_Q13_Q14,
570 AArch64::Q12_Q13_Q14_Q15, AArch64::Q13_Q14_Q15_Q16, AArch64::Q14_Q15_Q16_Q17,
571 AArch64::Q15_Q16_Q17_Q18, AArch64::Q16_Q17_Q18_Q19, AArch64::Q17_Q18_Q19_Q20,
572 AArch64::Q18_Q19_Q20_Q21, AArch64::Q19_Q20_Q21_Q22, AArch64::Q20_Q21_Q22_Q23,
573 AArch64::Q21_Q22_Q23_Q24, AArch64::Q22_Q23_Q24_Q25, AArch64::Q23_Q24_Q25_Q26,
574 AArch64::Q24_Q25_Q26_Q27, AArch64::Q25_Q26_Q27_Q28, AArch64::Q26_Q27_Q28_Q29,
575 AArch64::Q27_Q28_Q29_Q30, AArch64::Q28_Q29_Q30_Q31, AArch64::Q29_Q30_Q31_Q0,
576 AArch64::Q30_Q31_Q0_Q1, AArch64::Q31_Q0_Q1_Q2
577};
578
579static DecodeStatus DecodeQQQQRegisterClass(MCInst &Inst, unsigned RegNo,
580 uint64_t Addr,
581 const void *Decoder) {
582 if (RegNo > 31)
583 return Fail;
584 unsigned Register = QQQQDecoderTable[RegNo];
Jim Grosbache9119e42015-05-13 18:37:00 +0000[diff] [blame]585 Inst.addOperand(MCOperand::createReg(Register));
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]586 return Success;
587}
588
589static const unsigned DDDecoderTable[] = {
590 AArch64::D0_D1, AArch64::D1_D2, AArch64::D2_D3, AArch64::D3_D4,
591 AArch64::D4_D5, AArch64::D5_D6, AArch64::D6_D7, AArch64::D7_D8,
592 AArch64::D8_D9, AArch64::D9_D10, AArch64::D10_D11, AArch64::D11_D12,
593 AArch64::D12_D13, AArch64::D13_D14, AArch64::D14_D15, AArch64::D15_D16,
594 AArch64::D16_D17, AArch64::D17_D18, AArch64::D18_D19, AArch64::D19_D20,
595 AArch64::D20_D21, AArch64::D21_D22, AArch64::D22_D23, AArch64::D23_D24,
596 AArch64::D24_D25, AArch64::D25_D26, AArch64::D26_D27, AArch64::D27_D28,
597 AArch64::D28_D29, AArch64::D29_D30, AArch64::D30_D31, AArch64::D31_D0
598};
599
600static DecodeStatus DecodeDDRegisterClass(MCInst &Inst, unsigned RegNo,
601 uint64_t Addr, const void *Decoder) {
602 if (RegNo > 31)
603 return Fail;
604 unsigned Register = DDDecoderTable[RegNo];
Jim Grosbache9119e42015-05-13 18:37:00 +0000[diff] [blame]605 Inst.addOperand(MCOperand::createReg(Register));
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]606 return Success;
607}
608
609static const unsigned DDDDecoderTable[] = {
610 AArch64::D0_D1_D2, AArch64::D1_D2_D3, AArch64::D2_D3_D4,
611 AArch64::D3_D4_D5, AArch64::D4_D5_D6, AArch64::D5_D6_D7,
612 AArch64::D6_D7_D8, AArch64::D7_D8_D9, AArch64::D8_D9_D10,
613 AArch64::D9_D10_D11, AArch64::D10_D11_D12, AArch64::D11_D12_D13,
614 AArch64::D12_D13_D14, AArch64::D13_D14_D15, AArch64::D14_D15_D16,
615 AArch64::D15_D16_D17, AArch64::D16_D17_D18, AArch64::D17_D18_D19,
616 AArch64::D18_D19_D20, AArch64::D19_D20_D21, AArch64::D20_D21_D22,
617 AArch64::D21_D22_D23, AArch64::D22_D23_D24, AArch64::D23_D24_D25,
618 AArch64::D24_D25_D26, AArch64::D25_D26_D27, AArch64::D26_D27_D28,
619 AArch64::D27_D28_D29, AArch64::D28_D29_D30, AArch64::D29_D30_D31,
620 AArch64::D30_D31_D0, AArch64::D31_D0_D1
621};
622
623static DecodeStatus DecodeDDDRegisterClass(MCInst &Inst, unsigned RegNo,
624 uint64_t Addr, const void *Decoder) {
625 if (RegNo > 31)
626 return Fail;
627 unsigned Register = DDDDecoderTable[RegNo];
Jim Grosbache9119e42015-05-13 18:37:00 +0000[diff] [blame]628 Inst.addOperand(MCOperand::createReg(Register));
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]629 return Success;
630}
631
632static const unsigned DDDDDecoderTable[] = {
633 AArch64::D0_D1_D2_D3, AArch64::D1_D2_D3_D4, AArch64::D2_D3_D4_D5,
634 AArch64::D3_D4_D5_D6, AArch64::D4_D5_D6_D7, AArch64::D5_D6_D7_D8,
635 AArch64::D6_D7_D8_D9, AArch64::D7_D8_D9_D10, AArch64::D8_D9_D10_D11,
636 AArch64::D9_D10_D11_D12, AArch64::D10_D11_D12_D13, AArch64::D11_D12_D13_D14,
637 AArch64::D12_D13_D14_D15, AArch64::D13_D14_D15_D16, AArch64::D14_D15_D16_D17,
638 AArch64::D15_D16_D17_D18, AArch64::D16_D17_D18_D19, AArch64::D17_D18_D19_D20,
639 AArch64::D18_D19_D20_D21, AArch64::D19_D20_D21_D22, AArch64::D20_D21_D22_D23,
640 AArch64::D21_D22_D23_D24, AArch64::D22_D23_D24_D25, AArch64::D23_D24_D25_D26,
641 AArch64::D24_D25_D26_D27, AArch64::D25_D26_D27_D28, AArch64::D26_D27_D28_D29,
642 AArch64::D27_D28_D29_D30, AArch64::D28_D29_D30_D31, AArch64::D29_D30_D31_D0,
643 AArch64::D30_D31_D0_D1, AArch64::D31_D0_D1_D2
644};
645
646static DecodeStatus DecodeDDDDRegisterClass(MCInst &Inst, unsigned RegNo,
647 uint64_t Addr,
648 const void *Decoder) {
649 if (RegNo > 31)
650 return Fail;
651 unsigned Register = DDDDDecoderTable[RegNo];
Jim Grosbache9119e42015-05-13 18:37:00 +0000[diff] [blame]652 Inst.addOperand(MCOperand::createReg(Register));
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]653 return Success;
654}
655
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]656static DecodeStatus DecodeFixedPointScaleImm32(MCInst &Inst, unsigned Imm,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]657 uint64_t Addr,
658 const void *Decoder) {
659 // scale{5} is asserted as 1 in tblgen.
Tom Coxon2c13e712014-09-30 16:23:16 +0000[diff] [blame]660 Imm |= 0x20;
Jim Grosbache9119e42015-05-13 18:37:00 +0000[diff] [blame]661 Inst.addOperand(MCOperand::createImm(64 - Imm));
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]662 return Success;
663}
664
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]665static DecodeStatus DecodeFixedPointScaleImm64(MCInst &Inst, unsigned Imm,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]666 uint64_t Addr,
667 const void *Decoder) {
Jim Grosbache9119e42015-05-13 18:37:00 +0000[diff] [blame]668 Inst.addOperand(MCOperand::createImm(64 - Imm));
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]669 return Success;
670}
671
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]672static DecodeStatus DecodePCRelLabel19(MCInst &Inst, unsigned Imm,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]673 uint64_t Addr, const void *Decoder) {
674 int64_t ImmVal = Imm;
675 const AArch64Disassembler *Dis =
676 static_cast<const AArch64Disassembler *>(Decoder);
677
678 // Sign-extend 19-bit immediate.
679 if (ImmVal & (1 << (19 - 1)))
680 ImmVal |= ~((1LL << 19) - 1);
681
Alexey Samsonov729b12e2014-09-02 16:19:41 +0000[diff] [blame]682 if (!Dis->tryAddingSymbolicOperand(Inst, ImmVal * 4, Addr,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]683 Inst.getOpcode() != AArch64::LDRXl, 0, 4))
Jim Grosbache9119e42015-05-13 18:37:00 +0000[diff] [blame]684 Inst.addOperand(MCOperand::createImm(ImmVal));
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]685 return Success;
686}
687
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]688static DecodeStatus DecodeMemExtend(MCInst &Inst, unsigned Imm,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]689 uint64_t Address, const void *Decoder) {
Jim Grosbache9119e42015-05-13 18:37:00 +0000[diff] [blame]690 Inst.addOperand(MCOperand::createImm((Imm >> 1) & 1));
691 Inst.addOperand(MCOperand::createImm(Imm & 1));
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]692 return Success;
693}
694
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]695static DecodeStatus DecodeMRSSystemRegister(MCInst &Inst, unsigned Imm,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]696 uint64_t Address,
697 const void *Decoder) {
Jim Grosbache9119e42015-05-13 18:37:00 +0000[diff] [blame]698 Inst.addOperand(MCOperand::createImm(Imm));
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]699
Tom Coxone493f172014-10-01 10:13:59 +0000[diff] [blame]700 // Every system register in the encoding space is valid with the syntax
701 // S<op0>_<op1>_<Cn>_<Cm>_<op2>, so decoding system registers always succeeds.
702 return Success;
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]703}
704
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]705static DecodeStatus DecodeMSRSystemRegister(MCInst &Inst, unsigned Imm,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]706 uint64_t Address,
707 const void *Decoder) {
Jim Grosbache9119e42015-05-13 18:37:00 +0000[diff] [blame]708 Inst.addOperand(MCOperand::createImm(Imm));
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]709
Tom Coxone493f172014-10-01 10:13:59 +0000[diff] [blame]710 return Success;
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]711}
712
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]713static DecodeStatus DecodeFMOVLaneInstruction(MCInst &Inst, unsigned Insn,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]714 uint64_t Address,
715 const void *Decoder) {
716 // This decoder exists to add the dummy Lane operand to the MCInst, which must
717 // be 1 in assembly but has no other real manifestation.
718 unsigned Rd = fieldFromInstruction(Insn, 0, 5);
719 unsigned Rn = fieldFromInstruction(Insn, 5, 5);
720 unsigned IsToVec = fieldFromInstruction(Insn, 16, 1);
721
722 if (IsToVec) {
723 DecodeFPR128RegisterClass(Inst, Rd, Address, Decoder);
724 DecodeGPR64RegisterClass(Inst, Rn, Address, Decoder);
725 } else {
726 DecodeGPR64RegisterClass(Inst, Rd, Address, Decoder);
727 DecodeFPR128RegisterClass(Inst, Rn, Address, Decoder);
728 }
729
730 // Add the lane
Jim Grosbache9119e42015-05-13 18:37:00 +0000[diff] [blame]731 Inst.addOperand(MCOperand::createImm(1));
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]732
733 return Success;
734}
735
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]736static DecodeStatus DecodeVecShiftRImm(MCInst &Inst, unsigned Imm,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]737 unsigned Add) {
Jim Grosbache9119e42015-05-13 18:37:00 +0000[diff] [blame]738 Inst.addOperand(MCOperand::createImm(Add - Imm));
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]739 return Success;
740}
741
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]742static DecodeStatus DecodeVecShiftLImm(MCInst &Inst, unsigned Imm,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]743 unsigned Add) {
Jim Grosbache9119e42015-05-13 18:37:00 +0000[diff] [blame]744 Inst.addOperand(MCOperand::createImm((Imm + Add) & (Add - 1)));
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]745 return Success;
746}
747
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]748static DecodeStatus DecodeVecShiftR64Imm(MCInst &Inst, unsigned Imm,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]749 uint64_t Addr, const void *Decoder) {
750 return DecodeVecShiftRImm(Inst, Imm, 64);
751}
752
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]753static DecodeStatus DecodeVecShiftR64ImmNarrow(MCInst &Inst, unsigned Imm,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]754 uint64_t Addr,
755 const void *Decoder) {
756 return DecodeVecShiftRImm(Inst, Imm | 0x20, 64);
757}
758
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]759static DecodeStatus DecodeVecShiftR32Imm(MCInst &Inst, unsigned Imm,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]760 uint64_t Addr, const void *Decoder) {
761 return DecodeVecShiftRImm(Inst, Imm, 32);
762}
763
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]764static DecodeStatus DecodeVecShiftR32ImmNarrow(MCInst &Inst, unsigned Imm,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]765 uint64_t Addr,
766 const void *Decoder) {
767 return DecodeVecShiftRImm(Inst, Imm | 0x10, 32);
768}
769
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]770static DecodeStatus DecodeVecShiftR16Imm(MCInst &Inst, unsigned Imm,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]771 uint64_t Addr, const void *Decoder) {
772 return DecodeVecShiftRImm(Inst, Imm, 16);
773}
774
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]775static DecodeStatus DecodeVecShiftR16ImmNarrow(MCInst &Inst, unsigned Imm,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]776 uint64_t Addr,
777 const void *Decoder) {
778 return DecodeVecShiftRImm(Inst, Imm | 0x8, 16);
779}
780
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]781static DecodeStatus DecodeVecShiftR8Imm(MCInst &Inst, unsigned Imm,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]782 uint64_t Addr, const void *Decoder) {
783 return DecodeVecShiftRImm(Inst, Imm, 8);
784}
785
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]786static DecodeStatus DecodeVecShiftL64Imm(MCInst &Inst, unsigned Imm,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]787 uint64_t Addr, const void *Decoder) {
788 return DecodeVecShiftLImm(Inst, Imm, 64);
789}
790
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]791static DecodeStatus DecodeVecShiftL32Imm(MCInst &Inst, unsigned Imm,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]792 uint64_t Addr, const void *Decoder) {
793 return DecodeVecShiftLImm(Inst, Imm, 32);
794}
795
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]796static DecodeStatus DecodeVecShiftL16Imm(MCInst &Inst, unsigned Imm,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]797 uint64_t Addr, const void *Decoder) {
798 return DecodeVecShiftLImm(Inst, Imm, 16);
799}
800
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]801static DecodeStatus DecodeVecShiftL8Imm(MCInst &Inst, unsigned Imm,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]802 uint64_t Addr, const void *Decoder) {
803 return DecodeVecShiftLImm(Inst, Imm, 8);
804}
805
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]806static DecodeStatus DecodeThreeAddrSRegInstruction(MCInst &Inst, uint32_t insn,
807 uint64_t Addr,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]808 const void *Decoder) {
809 unsigned Rd = fieldFromInstruction(insn, 0, 5);
810 unsigned Rn = fieldFromInstruction(insn, 5, 5);
811 unsigned Rm = fieldFromInstruction(insn, 16, 5);
812 unsigned shiftHi = fieldFromInstruction(insn, 22, 2);
813 unsigned shiftLo = fieldFromInstruction(insn, 10, 6);
814 unsigned shift = (shiftHi << 6) | shiftLo;
815 switch (Inst.getOpcode()) {
816 default:
817 return Fail;
818 case AArch64::ADDWrs:
819 case AArch64::ADDSWrs:
820 case AArch64::SUBWrs:
821 case AArch64::SUBSWrs:
822 // if shift == '11' then ReservedValue()
823 if (shiftHi == 0x3)
824 return Fail;
Simon Pilgrimcb07d672017-07-07 16:40:06 +0000[diff] [blame]825 LLVM_FALLTHROUGH;
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]826 case AArch64::ANDWrs:
827 case AArch64::ANDSWrs:
828 case AArch64::BICWrs:
829 case AArch64::BICSWrs:
830 case AArch64::ORRWrs:
831 case AArch64::ORNWrs:
832 case AArch64::EORWrs:
833 case AArch64::EONWrs: {
834 // if sf == '0' and imm6<5> == '1' then ReservedValue()
835 if (shiftLo >> 5 == 1)
836 return Fail;
837 DecodeGPR32RegisterClass(Inst, Rd, Addr, Decoder);
838 DecodeGPR32RegisterClass(Inst, Rn, Addr, Decoder);
839 DecodeGPR32RegisterClass(Inst, Rm, Addr, Decoder);
840 break;
841 }
842 case AArch64::ADDXrs:
843 case AArch64::ADDSXrs:
844 case AArch64::SUBXrs:
845 case AArch64::SUBSXrs:
846 // if shift == '11' then ReservedValue()
847 if (shiftHi == 0x3)
848 return Fail;
Simon Pilgrimcb07d672017-07-07 16:40:06 +0000[diff] [blame]849 LLVM_FALLTHROUGH;
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]850 case AArch64::ANDXrs:
851 case AArch64::ANDSXrs:
852 case AArch64::BICXrs:
853 case AArch64::BICSXrs:
854 case AArch64::ORRXrs:
855 case AArch64::ORNXrs:
856 case AArch64::EORXrs:
857 case AArch64::EONXrs:
858 DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder);
859 DecodeGPR64RegisterClass(Inst, Rn, Addr, Decoder);
860 DecodeGPR64RegisterClass(Inst, Rm, Addr, Decoder);
861 break;
862 }
863
Jim Grosbache9119e42015-05-13 18:37:00 +0000[diff] [blame]864 Inst.addOperand(MCOperand::createImm(shift));
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]865 return Success;
866}
867
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]868static DecodeStatus DecodeMoveImmInstruction(MCInst &Inst, uint32_t insn,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]869 uint64_t Addr,
870 const void *Decoder) {
871 unsigned Rd = fieldFromInstruction(insn, 0, 5);
872 unsigned imm = fieldFromInstruction(insn, 5, 16);
873 unsigned shift = fieldFromInstruction(insn, 21, 2);
874 shift <<= 4;
875 switch (Inst.getOpcode()) {
876 default:
877 return Fail;
878 case AArch64::MOVZWi:
879 case AArch64::MOVNWi:
880 case AArch64::MOVKWi:
881 if (shift & (1U << 5))
882 return Fail;
883 DecodeGPR32RegisterClass(Inst, Rd, Addr, Decoder);
884 break;
885 case AArch64::MOVZXi:
886 case AArch64::MOVNXi:
887 case AArch64::MOVKXi:
888 DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder);
889 break;
890 }
891
892 if (Inst.getOpcode() == AArch64::MOVKWi ||
893 Inst.getOpcode() == AArch64::MOVKXi)
894 Inst.addOperand(Inst.getOperand(0));
895
Jim Grosbache9119e42015-05-13 18:37:00 +0000[diff] [blame]896 Inst.addOperand(MCOperand::createImm(imm));
897 Inst.addOperand(MCOperand::createImm(shift));
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]898 return Success;
899}
900
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]901static DecodeStatus DecodeUnsignedLdStInstruction(MCInst &Inst, uint32_t insn,
902 uint64_t Addr,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]903 const void *Decoder) {
904 unsigned Rt = fieldFromInstruction(insn, 0, 5);
905 unsigned Rn = fieldFromInstruction(insn, 5, 5);
906 unsigned offset = fieldFromInstruction(insn, 10, 12);
907 const AArch64Disassembler *Dis =
908 static_cast<const AArch64Disassembler *>(Decoder);
909
910 switch (Inst.getOpcode()) {
911 default:
912 return Fail;
913 case AArch64::PRFMui:
914 // Rt is an immediate in prefetch.
Jim Grosbache9119e42015-05-13 18:37:00 +0000[diff] [blame]915 Inst.addOperand(MCOperand::createImm(Rt));
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]916 break;
917 case AArch64::STRBBui:
918 case AArch64::LDRBBui:
919 case AArch64::LDRSBWui:
920 case AArch64::STRHHui:
921 case AArch64::LDRHHui:
922 case AArch64::LDRSHWui:
923 case AArch64::STRWui:
924 case AArch64::LDRWui:
925 DecodeGPR32RegisterClass(Inst, Rt, Addr, Decoder);
926 break;
927 case AArch64::LDRSBXui:
928 case AArch64::LDRSHXui:
929 case AArch64::LDRSWui:
930 case AArch64::STRXui:
931 case AArch64::LDRXui:
932 DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder);
933 break;
934 case AArch64::LDRQui:
935 case AArch64::STRQui:
936 DecodeFPR128RegisterClass(Inst, Rt, Addr, Decoder);
937 break;
938 case AArch64::LDRDui:
939 case AArch64::STRDui:
940 DecodeFPR64RegisterClass(Inst, Rt, Addr, Decoder);
941 break;
942 case AArch64::LDRSui:
943 case AArch64::STRSui:
944 DecodeFPR32RegisterClass(Inst, Rt, Addr, Decoder);
945 break;
946 case AArch64::LDRHui:
947 case AArch64::STRHui:
948 DecodeFPR16RegisterClass(Inst, Rt, Addr, Decoder);
949 break;
950 case AArch64::LDRBui:
951 case AArch64::STRBui:
952 DecodeFPR8RegisterClass(Inst, Rt, Addr, Decoder);
953 break;
954 }
955
956 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder);
957 if (!Dis->tryAddingSymbolicOperand(Inst, offset, Addr, Fail, 0, 4))
Jim Grosbache9119e42015-05-13 18:37:00 +0000[diff] [blame]958 Inst.addOperand(MCOperand::createImm(offset));
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]959 return Success;
960}
961
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]962static DecodeStatus DecodeSignedLdStInstruction(MCInst &Inst, uint32_t insn,
963 uint64_t Addr,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]964 const void *Decoder) {
965 unsigned Rt = fieldFromInstruction(insn, 0, 5);
966 unsigned Rn = fieldFromInstruction(insn, 5, 5);
967 int64_t offset = fieldFromInstruction(insn, 12, 9);
968
969 // offset is a 9-bit signed immediate, so sign extend it to
970 // fill the unsigned.
971 if (offset & (1 << (9 - 1)))
972 offset |= ~((1LL << 9) - 1);
973
974 // First operand is always the writeback to the address register, if needed.
975 switch (Inst.getOpcode()) {
976 default:
977 break;
978 case AArch64::LDRSBWpre:
979 case AArch64::LDRSHWpre:
980 case AArch64::STRBBpre:
981 case AArch64::LDRBBpre:
982 case AArch64::STRHHpre:
983 case AArch64::LDRHHpre:
984 case AArch64::STRWpre:
985 case AArch64::LDRWpre:
986 case AArch64::LDRSBWpost:
987 case AArch64::LDRSHWpost:
988 case AArch64::STRBBpost:
989 case AArch64::LDRBBpost:
990 case AArch64::STRHHpost:
991 case AArch64::LDRHHpost:
992 case AArch64::STRWpost:
993 case AArch64::LDRWpost:
994 case AArch64::LDRSBXpre:
995 case AArch64::LDRSHXpre:
996 case AArch64::STRXpre:
997 case AArch64::LDRSWpre:
998 case AArch64::LDRXpre:
999 case AArch64::LDRSBXpost:
1000 case AArch64::LDRSHXpost:
1001 case AArch64::STRXpost:
1002 case AArch64::LDRSWpost:
1003 case AArch64::LDRXpost:
1004 case AArch64::LDRQpre:
1005 case AArch64::STRQpre:
1006 case AArch64::LDRQpost:
1007 case AArch64::STRQpost:
1008 case AArch64::LDRDpre:
1009 case AArch64::STRDpre:
1010 case AArch64::LDRDpost:
1011 case AArch64::STRDpost:
1012 case AArch64::LDRSpre:
1013 case AArch64::STRSpre:
1014 case AArch64::LDRSpost:
1015 case AArch64::STRSpost:
1016 case AArch64::LDRHpre:
1017 case AArch64::STRHpre:
1018 case AArch64::LDRHpost:
1019 case AArch64::STRHpost:
1020 case AArch64::LDRBpre:
1021 case AArch64::STRBpre:
1022 case AArch64::LDRBpost:
1023 case AArch64::STRBpost:
1024 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder);
1025 break;
1026 }
1027
1028 switch (Inst.getOpcode()) {
1029 default:
1030 return Fail;
1031 case AArch64::PRFUMi:
1032 // Rt is an immediate in prefetch.
Jim Grosbache9119e42015-05-13 18:37:00 +0000[diff] [blame]1033 Inst.addOperand(MCOperand::createImm(Rt));
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1034 break;
1035 case AArch64::STURBBi:
1036 case AArch64::LDURBBi:
1037 case AArch64::LDURSBWi:
1038 case AArch64::STURHHi:
1039 case AArch64::LDURHHi:
1040 case AArch64::LDURSHWi:
1041 case AArch64::STURWi:
1042 case AArch64::LDURWi:
1043 case AArch64::LDTRSBWi:
1044 case AArch64::LDTRSHWi:
1045 case AArch64::STTRWi:
1046 case AArch64::LDTRWi:
1047 case AArch64::STTRHi:
1048 case AArch64::LDTRHi:
1049 case AArch64::LDTRBi:
1050 case AArch64::STTRBi:
1051 case AArch64::LDRSBWpre:
1052 case AArch64::LDRSHWpre:
1053 case AArch64::STRBBpre:
1054 case AArch64::LDRBBpre:
1055 case AArch64::STRHHpre:
1056 case AArch64::LDRHHpre:
1057 case AArch64::STRWpre:
1058 case AArch64::LDRWpre:
1059 case AArch64::LDRSBWpost:
1060 case AArch64::LDRSHWpost:
1061 case AArch64::STRBBpost:
1062 case AArch64::LDRBBpost:
1063 case AArch64::STRHHpost:
1064 case AArch64::LDRHHpost:
1065 case AArch64::STRWpost:
1066 case AArch64::LDRWpost:
1067 DecodeGPR32RegisterClass(Inst, Rt, Addr, Decoder);
1068 break;
1069 case AArch64::LDURSBXi:
1070 case AArch64::LDURSHXi:
1071 case AArch64::LDURSWi:
1072 case AArch64::STURXi:
1073 case AArch64::LDURXi:
1074 case AArch64::LDTRSBXi:
1075 case AArch64::LDTRSHXi:
1076 case AArch64::LDTRSWi:
1077 case AArch64::STTRXi:
1078 case AArch64::LDTRXi:
1079 case AArch64::LDRSBXpre:
1080 case AArch64::LDRSHXpre:
1081 case AArch64::STRXpre:
1082 case AArch64::LDRSWpre:
1083 case AArch64::LDRXpre:
1084 case AArch64::LDRSBXpost:
1085 case AArch64::LDRSHXpost:
1086 case AArch64::STRXpost:
1087 case AArch64::LDRSWpost:
1088 case AArch64::LDRXpost:
1089 DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder);
1090 break;
1091 case AArch64::LDURQi:
1092 case AArch64::STURQi:
1093 case AArch64::LDRQpre:
1094 case AArch64::STRQpre:
1095 case AArch64::LDRQpost:
1096 case AArch64::STRQpost:
1097 DecodeFPR128RegisterClass(Inst, Rt, Addr, Decoder);
1098 break;
1099 case AArch64::LDURDi:
1100 case AArch64::STURDi:
1101 case AArch64::LDRDpre:
1102 case AArch64::STRDpre:
1103 case AArch64::LDRDpost:
1104 case AArch64::STRDpost:
1105 DecodeFPR64RegisterClass(Inst, Rt, Addr, Decoder);
1106 break;
1107 case AArch64::LDURSi:
1108 case AArch64::STURSi:
1109 case AArch64::LDRSpre:
1110 case AArch64::STRSpre:
1111 case AArch64::LDRSpost:
1112 case AArch64::STRSpost:
1113 DecodeFPR32RegisterClass(Inst, Rt, Addr, Decoder);
1114 break;
1115 case AArch64::LDURHi:
1116 case AArch64::STURHi:
1117 case AArch64::LDRHpre:
1118 case AArch64::STRHpre:
1119 case AArch64::LDRHpost:
1120 case AArch64::STRHpost:
1121 DecodeFPR16RegisterClass(Inst, Rt, Addr, Decoder);
1122 break;
1123 case AArch64::LDURBi:
1124 case AArch64::STURBi:
1125 case AArch64::LDRBpre:
1126 case AArch64::STRBpre:
1127 case AArch64::LDRBpost:
1128 case AArch64::STRBpost:
1129 DecodeFPR8RegisterClass(Inst, Rt, Addr, Decoder);
1130 break;
1131 }
1132
1133 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder);
Jim Grosbache9119e42015-05-13 18:37:00 +0000[diff] [blame]1134 Inst.addOperand(MCOperand::createImm(offset));
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1135
1136 bool IsLoad = fieldFromInstruction(insn, 22, 1);
1137 bool IsIndexed = fieldFromInstruction(insn, 10, 2) != 0;
1138 bool IsFP = fieldFromInstruction(insn, 26, 1);
1139
1140 // Cannot write back to a transfer register (but xzr != sp).
1141 if (IsLoad && IsIndexed && !IsFP && Rn != 31 && Rt == Rn)
1142 return SoftFail;
1143
1144 return Success;
1145}
1146
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]1147static DecodeStatus DecodeExclusiveLdStInstruction(MCInst &Inst, uint32_t insn,
1148 uint64_t Addr,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1149 const void *Decoder) {
1150 unsigned Rt = fieldFromInstruction(insn, 0, 5);
1151 unsigned Rn = fieldFromInstruction(insn, 5, 5);
1152 unsigned Rt2 = fieldFromInstruction(insn, 10, 5);
1153 unsigned Rs = fieldFromInstruction(insn, 16, 5);
1154
1155 unsigned Opcode = Inst.getOpcode();
1156 switch (Opcode) {
1157 default:
1158 return Fail;
1159 case AArch64::STLXRW:
1160 case AArch64::STLXRB:
1161 case AArch64::STLXRH:
1162 case AArch64::STXRW:
1163 case AArch64::STXRB:
1164 case AArch64::STXRH:
1165 DecodeGPR32RegisterClass(Inst, Rs, Addr, Decoder);
Justin Bognerb03fd122016-08-17 05:10:15 +0000[diff] [blame]1166 LLVM_FALLTHROUGH;
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1167 case AArch64::LDARW:
1168 case AArch64::LDARB:
1169 case AArch64::LDARH:
1170 case AArch64::LDAXRW:
1171 case AArch64::LDAXRB:
1172 case AArch64::LDAXRH:
1173 case AArch64::LDXRW:
1174 case AArch64::LDXRB:
1175 case AArch64::LDXRH:
1176 case AArch64::STLRW:
1177 case AArch64::STLRB:
1178 case AArch64::STLRH:
Vladimir Sukharevd49cb8f2015-04-16 15:30:43 +0000[diff] [blame]1179 case AArch64::STLLRW:
1180 case AArch64::STLLRB:
1181 case AArch64::STLLRH:
1182 case AArch64::LDLARW:
1183 case AArch64::LDLARB:
1184 case AArch64::LDLARH:
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1185 DecodeGPR32RegisterClass(Inst, Rt, Addr, Decoder);
1186 break;
1187 case AArch64::STLXRX:
1188 case AArch64::STXRX:
1189 DecodeGPR32RegisterClass(Inst, Rs, Addr, Decoder);
Justin Bognerb03fd122016-08-17 05:10:15 +0000[diff] [blame]1190 LLVM_FALLTHROUGH;
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1191 case AArch64::LDARX:
1192 case AArch64::LDAXRX:
1193 case AArch64::LDXRX:
1194 case AArch64::STLRX:
Vladimir Sukharevd49cb8f2015-04-16 15:30:43 +0000[diff] [blame]1195 case AArch64::LDLARX:
1196 case AArch64::STLLRX:
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1197 DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder);
1198 break;
1199 case AArch64::STLXPW:
1200 case AArch64::STXPW:
1201 DecodeGPR32RegisterClass(Inst, Rs, Addr, Decoder);
Justin Bognerb03fd122016-08-17 05:10:15 +0000[diff] [blame]1202 LLVM_FALLTHROUGH;
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1203 case AArch64::LDAXPW:
1204 case AArch64::LDXPW:
1205 DecodeGPR32RegisterClass(Inst, Rt, Addr, Decoder);
1206 DecodeGPR32RegisterClass(Inst, Rt2, Addr, Decoder);
1207 break;
1208 case AArch64::STLXPX:
1209 case AArch64::STXPX:
1210 DecodeGPR32RegisterClass(Inst, Rs, Addr, Decoder);
Justin Bognerb03fd122016-08-17 05:10:15 +0000[diff] [blame]1211 LLVM_FALLTHROUGH;
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1212 case AArch64::LDAXPX:
1213 case AArch64::LDXPX:
1214 DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder);
1215 DecodeGPR64RegisterClass(Inst, Rt2, Addr, Decoder);
1216 break;
1217 }
1218
1219 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder);
1220
1221 // You shouldn't load to the same register twice in an instruction...
1222 if ((Opcode == AArch64::LDAXPW || Opcode == AArch64::LDXPW ||
1223 Opcode == AArch64::LDAXPX || Opcode == AArch64::LDXPX) &&
1224 Rt == Rt2)
1225 return SoftFail;
1226
1227 return Success;
1228}
1229
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]1230static DecodeStatus DecodePairLdStInstruction(MCInst &Inst, uint32_t insn,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1231 uint64_t Addr,
1232 const void *Decoder) {
1233 unsigned Rt = fieldFromInstruction(insn, 0, 5);
1234 unsigned Rn = fieldFromInstruction(insn, 5, 5);
1235 unsigned Rt2 = fieldFromInstruction(insn, 10, 5);
1236 int64_t offset = fieldFromInstruction(insn, 15, 7);
1237 bool IsLoad = fieldFromInstruction(insn, 22, 1);
1238
1239 // offset is a 7-bit signed immediate, so sign extend it to
1240 // fill the unsigned.
1241 if (offset & (1 << (7 - 1)))
1242 offset |= ~((1LL << 7) - 1);
1243
1244 unsigned Opcode = Inst.getOpcode();
1245 bool NeedsDisjointWritebackTransfer = false;
1246
1247 // First operand is always writeback of base register.
1248 switch (Opcode) {
1249 default:
1250 break;
1251 case AArch64::LDPXpost:
1252 case AArch64::STPXpost:
1253 case AArch64::LDPSWpost:
1254 case AArch64::LDPXpre:
1255 case AArch64::STPXpre:
1256 case AArch64::LDPSWpre:
1257 case AArch64::LDPWpost:
1258 case AArch64::STPWpost:
1259 case AArch64::LDPWpre:
1260 case AArch64::STPWpre:
1261 case AArch64::LDPQpost:
1262 case AArch64::STPQpost:
1263 case AArch64::LDPQpre:
1264 case AArch64::STPQpre:
1265 case AArch64::LDPDpost:
1266 case AArch64::STPDpost:
1267 case AArch64::LDPDpre:
1268 case AArch64::STPDpre:
1269 case AArch64::LDPSpost:
1270 case AArch64::STPSpost:
1271 case AArch64::LDPSpre:
1272 case AArch64::STPSpre:
1273 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder);
1274 break;
1275 }
1276
1277 switch (Opcode) {
1278 default:
1279 return Fail;
1280 case AArch64::LDPXpost:
1281 case AArch64::STPXpost:
1282 case AArch64::LDPSWpost:
1283 case AArch64::LDPXpre:
1284 case AArch64::STPXpre:
1285 case AArch64::LDPSWpre:
1286 NeedsDisjointWritebackTransfer = true;
Justin Bognerb03fd122016-08-17 05:10:15 +0000[diff] [blame]1287 LLVM_FALLTHROUGH;
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1288 case AArch64::LDNPXi:
1289 case AArch64::STNPXi:
1290 case AArch64::LDPXi:
1291 case AArch64::STPXi:
1292 case AArch64::LDPSWi:
1293 DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder);
1294 DecodeGPR64RegisterClass(Inst, Rt2, Addr, Decoder);
1295 break;
1296 case AArch64::LDPWpost:
1297 case AArch64::STPWpost:
1298 case AArch64::LDPWpre:
1299 case AArch64::STPWpre:
1300 NeedsDisjointWritebackTransfer = true;
Justin Bognerb03fd122016-08-17 05:10:15 +0000[diff] [blame]1301 LLVM_FALLTHROUGH;
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1302 case AArch64::LDNPWi:
1303 case AArch64::STNPWi:
1304 case AArch64::LDPWi:
1305 case AArch64::STPWi:
1306 DecodeGPR32RegisterClass(Inst, Rt, Addr, Decoder);
1307 DecodeGPR32RegisterClass(Inst, Rt2, Addr, Decoder);
1308 break;
1309 case AArch64::LDNPQi:
1310 case AArch64::STNPQi:
1311 case AArch64::LDPQpost:
1312 case AArch64::STPQpost:
1313 case AArch64::LDPQi:
1314 case AArch64::STPQi:
1315 case AArch64::LDPQpre:
1316 case AArch64::STPQpre:
1317 DecodeFPR128RegisterClass(Inst, Rt, Addr, Decoder);
1318 DecodeFPR128RegisterClass(Inst, Rt2, Addr, Decoder);
1319 break;
1320 case AArch64::LDNPDi:
1321 case AArch64::STNPDi:
1322 case AArch64::LDPDpost:
1323 case AArch64::STPDpost:
1324 case AArch64::LDPDi:
1325 case AArch64::STPDi:
1326 case AArch64::LDPDpre:
1327 case AArch64::STPDpre:
1328 DecodeFPR64RegisterClass(Inst, Rt, Addr, Decoder);
1329 DecodeFPR64RegisterClass(Inst, Rt2, Addr, Decoder);
1330 break;
1331 case AArch64::LDNPSi:
1332 case AArch64::STNPSi:
1333 case AArch64::LDPSpost:
1334 case AArch64::STPSpost:
1335 case AArch64::LDPSi:
1336 case AArch64::STPSi:
1337 case AArch64::LDPSpre:
1338 case AArch64::STPSpre:
1339 DecodeFPR32RegisterClass(Inst, Rt, Addr, Decoder);
1340 DecodeFPR32RegisterClass(Inst, Rt2, Addr, Decoder);
1341 break;
1342 }
1343
1344 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder);
Jim Grosbache9119e42015-05-13 18:37:00 +0000[diff] [blame]1345 Inst.addOperand(MCOperand::createImm(offset));
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1346
1347 // You shouldn't load to the same register twice in an instruction...
1348 if (IsLoad && Rt == Rt2)
1349 return SoftFail;
1350
1351 // ... or do any operation that writes-back to a transfer register. But note
1352 // that "stp xzr, xzr, [sp], #4" is fine because xzr and sp are different.
1353 if (NeedsDisjointWritebackTransfer && Rn != 31 && (Rt == Rn || Rt2 == Rn))
1354 return SoftFail;
1355
1356 return Success;
1357}
1358
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]1359static DecodeStatus DecodeAddSubERegInstruction(MCInst &Inst, uint32_t insn,
1360 uint64_t Addr,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1361 const void *Decoder) {
1362 unsigned Rd = fieldFromInstruction(insn, 0, 5);
1363 unsigned Rn = fieldFromInstruction(insn, 5, 5);
1364 unsigned Rm = fieldFromInstruction(insn, 16, 5);
1365 unsigned extend = fieldFromInstruction(insn, 10, 6);
1366
1367 unsigned shift = extend & 0x7;
1368 if (shift > 4)
1369 return Fail;
1370
1371 switch (Inst.getOpcode()) {
1372 default:
1373 return Fail;
1374 case AArch64::ADDWrx:
1375 case AArch64::SUBWrx:
1376 DecodeGPR32spRegisterClass(Inst, Rd, Addr, Decoder);
1377 DecodeGPR32spRegisterClass(Inst, Rn, Addr, Decoder);
1378 DecodeGPR32RegisterClass(Inst, Rm, Addr, Decoder);
1379 break;
1380 case AArch64::ADDSWrx:
1381 case AArch64::SUBSWrx:
1382 DecodeGPR32RegisterClass(Inst, Rd, Addr, Decoder);
1383 DecodeGPR32spRegisterClass(Inst, Rn, Addr, Decoder);
1384 DecodeGPR32RegisterClass(Inst, Rm, Addr, Decoder);
1385 break;
1386 case AArch64::ADDXrx:
1387 case AArch64::SUBXrx:
1388 DecodeGPR64spRegisterClass(Inst, Rd, Addr, Decoder);
1389 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder);
1390 DecodeGPR32RegisterClass(Inst, Rm, Addr, Decoder);
1391 break;
1392 case AArch64::ADDSXrx:
1393 case AArch64::SUBSXrx:
1394 DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder);
1395 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder);
1396 DecodeGPR32RegisterClass(Inst, Rm, Addr, Decoder);
1397 break;
1398 case AArch64::ADDXrx64:
1399 case AArch64::SUBXrx64:
1400 DecodeGPR64spRegisterClass(Inst, Rd, Addr, Decoder);
1401 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder);
1402 DecodeGPR64RegisterClass(Inst, Rm, Addr, Decoder);
1403 break;
1404 case AArch64::SUBSXrx64:
1405 case AArch64::ADDSXrx64:
1406 DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder);
1407 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder);
1408 DecodeGPR64RegisterClass(Inst, Rm, Addr, Decoder);
1409 break;
1410 }
1411
Jim Grosbache9119e42015-05-13 18:37:00 +0000[diff] [blame]1412 Inst.addOperand(MCOperand::createImm(extend));
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1413 return Success;
1414}
1415
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]1416static DecodeStatus DecodeLogicalImmInstruction(MCInst &Inst, uint32_t insn,
1417 uint64_t Addr,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1418 const void *Decoder) {
1419 unsigned Rd = fieldFromInstruction(insn, 0, 5);
1420 unsigned Rn = fieldFromInstruction(insn, 5, 5);
1421 unsigned Datasize = fieldFromInstruction(insn, 31, 1);
1422 unsigned imm;
1423
1424 if (Datasize) {
1425 if (Inst.getOpcode() == AArch64::ANDSXri)
1426 DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder);
1427 else
1428 DecodeGPR64spRegisterClass(Inst, Rd, Addr, Decoder);
1429 DecodeGPR64RegisterClass(Inst, Rn, Addr, Decoder);
1430 imm = fieldFromInstruction(insn, 10, 13);
1431 if (!AArch64_AM::isValidDecodeLogicalImmediate(imm, 64))
1432 return Fail;
1433 } else {
1434 if (Inst.getOpcode() == AArch64::ANDSWri)
1435 DecodeGPR32RegisterClass(Inst, Rd, Addr, Decoder);
1436 else
1437 DecodeGPR32spRegisterClass(Inst, Rd, Addr, Decoder);
1438 DecodeGPR32RegisterClass(Inst, Rn, Addr, Decoder);
1439 imm = fieldFromInstruction(insn, 10, 12);
1440 if (!AArch64_AM::isValidDecodeLogicalImmediate(imm, 32))
1441 return Fail;
1442 }
Jim Grosbache9119e42015-05-13 18:37:00 +0000[diff] [blame]1443 Inst.addOperand(MCOperand::createImm(imm));
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1444 return Success;
1445}
1446
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]1447static DecodeStatus DecodeModImmInstruction(MCInst &Inst, uint32_t insn,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1448 uint64_t Addr,
1449 const void *Decoder) {
1450 unsigned Rd = fieldFromInstruction(insn, 0, 5);
1451 unsigned cmode = fieldFromInstruction(insn, 12, 4);
1452 unsigned imm = fieldFromInstruction(insn, 16, 3) << 5;
1453 imm |= fieldFromInstruction(insn, 5, 5);
1454
1455 if (Inst.getOpcode() == AArch64::MOVID)
1456 DecodeFPR64RegisterClass(Inst, Rd, Addr, Decoder);
1457 else
1458 DecodeVectorRegisterClass(Inst, Rd, Addr, Decoder);
1459
Jim Grosbache9119e42015-05-13 18:37:00 +0000[diff] [blame]1460 Inst.addOperand(MCOperand::createImm(imm));
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1461
1462 switch (Inst.getOpcode()) {
1463 default:
1464 break;
1465 case AArch64::MOVIv4i16:
1466 case AArch64::MOVIv8i16:
1467 case AArch64::MVNIv4i16:
1468 case AArch64::MVNIv8i16:
1469 case AArch64::MOVIv2i32:
1470 case AArch64::MOVIv4i32:
1471 case AArch64::MVNIv2i32:
1472 case AArch64::MVNIv4i32:
Jim Grosbache9119e42015-05-13 18:37:00 +0000[diff] [blame]1473 Inst.addOperand(MCOperand::createImm((cmode & 6) << 2));
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1474 break;
1475 case AArch64::MOVIv2s_msl:
1476 case AArch64::MOVIv4s_msl:
1477 case AArch64::MVNIv2s_msl:
1478 case AArch64::MVNIv4s_msl:
Jim Grosbache9119e42015-05-13 18:37:00 +0000[diff] [blame]1479 Inst.addOperand(MCOperand::createImm(cmode & 1 ? 0x110 : 0x108));
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1480 break;
1481 }
1482
1483 return Success;
1484}
1485
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]1486static DecodeStatus DecodeModImmTiedInstruction(MCInst &Inst, uint32_t insn,
1487 uint64_t Addr,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1488 const void *Decoder) {
1489 unsigned Rd = fieldFromInstruction(insn, 0, 5);
1490 unsigned cmode = fieldFromInstruction(insn, 12, 4);
1491 unsigned imm = fieldFromInstruction(insn, 16, 3) << 5;
1492 imm |= fieldFromInstruction(insn, 5, 5);
1493
1494 // Tied operands added twice.
1495 DecodeVectorRegisterClass(Inst, Rd, Addr, Decoder);
1496 DecodeVectorRegisterClass(Inst, Rd, Addr, Decoder);
1497
Jim Grosbache9119e42015-05-13 18:37:00 +0000[diff] [blame]1498 Inst.addOperand(MCOperand::createImm(imm));
1499 Inst.addOperand(MCOperand::createImm((cmode & 6) << 2));
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1500
1501 return Success;
1502}
1503
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]1504static DecodeStatus DecodeAdrInstruction(MCInst &Inst, uint32_t insn,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1505 uint64_t Addr, const void *Decoder) {
1506 unsigned Rd = fieldFromInstruction(insn, 0, 5);
1507 int64_t imm = fieldFromInstruction(insn, 5, 19) << 2;
1508 imm |= fieldFromInstruction(insn, 29, 2);
1509 const AArch64Disassembler *Dis =
1510 static_cast<const AArch64Disassembler *>(Decoder);
1511
1512 // Sign-extend the 21-bit immediate.
1513 if (imm & (1 << (21 - 1)))
1514 imm |= ~((1LL << 21) - 1);
1515
1516 DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder);
1517 if (!Dis->tryAddingSymbolicOperand(Inst, imm, Addr, Fail, 0, 4))
Jim Grosbache9119e42015-05-13 18:37:00 +0000[diff] [blame]1518 Inst.addOperand(MCOperand::createImm(imm));
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1519
1520 return Success;
1521}
1522
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]1523static DecodeStatus DecodeBaseAddSubImm(MCInst &Inst, uint32_t insn,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1524 uint64_t Addr, const void *Decoder) {
1525 unsigned Rd = fieldFromInstruction(insn, 0, 5);
1526 unsigned Rn = fieldFromInstruction(insn, 5, 5);
1527 unsigned Imm = fieldFromInstruction(insn, 10, 14);
1528 unsigned S = fieldFromInstruction(insn, 29, 1);
1529 unsigned Datasize = fieldFromInstruction(insn, 31, 1);
1530
1531 unsigned ShifterVal = (Imm >> 12) & 3;
1532 unsigned ImmVal = Imm & 0xFFF;
1533 const AArch64Disassembler *Dis =
1534 static_cast<const AArch64Disassembler *>(Decoder);
1535
1536 if (ShifterVal != 0 && ShifterVal != 1)
1537 return Fail;
1538
1539 if (Datasize) {
1540 if (Rd == 31 && !S)
1541 DecodeGPR64spRegisterClass(Inst, Rd, Addr, Decoder);
1542 else
1543 DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder);
1544 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder);
1545 } else {
1546 if (Rd == 31 && !S)
1547 DecodeGPR32spRegisterClass(Inst, Rd, Addr, Decoder);
1548 else
1549 DecodeGPR32RegisterClass(Inst, Rd, Addr, Decoder);
1550 DecodeGPR32spRegisterClass(Inst, Rn, Addr, Decoder);
1551 }
1552
1553 if (!Dis->tryAddingSymbolicOperand(Inst, Imm, Addr, Fail, 0, 4))
Jim Grosbache9119e42015-05-13 18:37:00 +0000[diff] [blame]1554 Inst.addOperand(MCOperand::createImm(ImmVal));
1555 Inst.addOperand(MCOperand::createImm(12 * ShifterVal));
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1556 return Success;
1557}
1558
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]1559static DecodeStatus DecodeUnconditionalBranch(MCInst &Inst, uint32_t insn,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1560 uint64_t Addr,
1561 const void *Decoder) {
1562 int64_t imm = fieldFromInstruction(insn, 0, 26);
1563 const AArch64Disassembler *Dis =
1564 static_cast<const AArch64Disassembler *>(Decoder);
1565
1566 // Sign-extend the 26-bit immediate.
1567 if (imm & (1 << (26 - 1)))
1568 imm |= ~((1LL << 26) - 1);
1569
Alexey Samsonov729b12e2014-09-02 16:19:41 +0000[diff] [blame]1570 if (!Dis->tryAddingSymbolicOperand(Inst, imm * 4, Addr, true, 0, 4))
Jim Grosbache9119e42015-05-13 18:37:00 +0000[diff] [blame]1571 Inst.addOperand(MCOperand::createImm(imm));
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1572
1573 return Success;
1574}
1575
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]1576static DecodeStatus DecodeSystemPStateInstruction(MCInst &Inst, uint32_t insn,
1577 uint64_t Addr,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1578 const void *Decoder) {
1579 uint64_t op1 = fieldFromInstruction(insn, 16, 3);
1580 uint64_t op2 = fieldFromInstruction(insn, 5, 3);
1581 uint64_t crm = fieldFromInstruction(insn, 8, 4);
1582
1583 uint64_t pstate_field = (op1 << 3) | op2;
1584
Oliver Stannard911ea202015-11-26 15:32:30 +0000[diff] [blame]1585 if ((pstate_field == AArch64PState::PAN ||
1586 pstate_field == AArch64PState::UAO) && crm > 1)
Alexandros Lamprineas1bab1912015-10-05 13:42:31 +0000[diff] [blame]1587 return Fail;
1588
Jim Grosbache9119e42015-05-13 18:37:00 +0000[diff] [blame]1589 Inst.addOperand(MCOperand::createImm(pstate_field));
1590 Inst.addOperand(MCOperand::createImm(crm));
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1591
Tim Northovere6ae6762016-07-05 21:23:04 +0000[diff] [blame]1592 const AArch64Disassembler *Dis =
Vladimir Sukhareva98f6892015-04-16 12:15:27 +0000[diff] [blame]1593 static_cast<const AArch64Disassembler *>(Decoder);
Tim Northovere6ae6762016-07-05 21:23:04 +0000[diff] [blame]1594 auto PState = AArch64PState::lookupPStateByEncoding(pstate_field);
1595 if (PState && PState->haveFeatures(Dis->getSubtargetInfo().getFeatureBits()))
1596 return Success;
1597 return Fail;
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1598}
1599
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]1600static DecodeStatus DecodeTestAndBranch(MCInst &Inst, uint32_t insn,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1601 uint64_t Addr, const void *Decoder) {
1602 uint64_t Rt = fieldFromInstruction(insn, 0, 5);
1603 uint64_t bit = fieldFromInstruction(insn, 31, 1) << 5;
1604 bit |= fieldFromInstruction(insn, 19, 5);
1605 int64_t dst = fieldFromInstruction(insn, 5, 14);
1606 const AArch64Disassembler *Dis =
1607 static_cast<const AArch64Disassembler *>(Decoder);
1608
1609 // Sign-extend 14-bit immediate.
1610 if (dst & (1 << (14 - 1)))
1611 dst |= ~((1LL << 14) - 1);
1612
1613 if (fieldFromInstruction(insn, 31, 1) == 0)
1614 DecodeGPR32RegisterClass(Inst, Rt, Addr, Decoder);
1615 else
1616 DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder);
Jim Grosbache9119e42015-05-13 18:37:00 +0000[diff] [blame]1617 Inst.addOperand(MCOperand::createImm(bit));
Alexey Samsonov729b12e2014-09-02 16:19:41 +0000[diff] [blame]1618 if (!Dis->tryAddingSymbolicOperand(Inst, dst * 4, Addr, true, 0, 4))
Jim Grosbache9119e42015-05-13 18:37:00 +0000[diff] [blame]1619 Inst.addOperand(MCOperand::createImm(dst));
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1620
1621 return Success;
1622}
Vladimir Sukharev5f6f60d2015-06-02 10:58:41 +0000[diff] [blame]1623
1624static DecodeStatus DecodeGPRSeqPairsClassRegisterClass(MCInst &Inst,
1625 unsigned RegClassID,
1626 unsigned RegNo,
1627 uint64_t Addr,
1628 const void *Decoder) {
1629 // Register number must be even (see CASP instruction)
1630 if (RegNo & 0x1)
1631 return Fail;
1632
1633 unsigned Register = AArch64MCRegisterClasses[RegClassID].getRegister(RegNo);
1634 Inst.addOperand(MCOperand::createReg(Register));
1635 return Success;
1636}
1637
1638static DecodeStatus DecodeWSeqPairsClassRegisterClass(MCInst &Inst,
1639 unsigned RegNo,
1640 uint64_t Addr,
1641 const void *Decoder) {
Junmo Park45513a82016-07-15 22:42:52 +0000[diff] [blame]1642 return DecodeGPRSeqPairsClassRegisterClass(Inst,
Vladimir Sukharev5f6f60d2015-06-02 10:58:41 +0000[diff] [blame]1643 AArch64::WSeqPairsClassRegClassID,
1644 RegNo, Addr, Decoder);
1645}
1646
1647static DecodeStatus DecodeXSeqPairsClassRegisterClass(MCInst &Inst,
1648 unsigned RegNo,
1649 uint64_t Addr,
1650 const void *Decoder) {
Junmo Park45513a82016-07-15 22:42:52 +0000[diff] [blame]1651 return DecodeGPRSeqPairsClassRegisterClass(Inst,
Vladimir Sukharev5f6f60d2015-06-02 10:58:41 +0000[diff] [blame]1652 AArch64::XSeqPairsClassRegClassID,
1653 RegNo, Addr, Decoder);
1654}
Sam Parker6d42de72017-08-11 13:14:00 +0000[diff] [blame]1655
Sander de Smalen81fcf862018-02-06 13:13:21 +0000[diff] [blame^]1656static DecodeStatus DecodeSVELogicalImmInstruction(llvm::MCInst &Inst,
1657 uint32_t insn,
1658 uint64_t Addr,
1659 const void *Decoder) {
1660 unsigned Zdn = fieldFromInstruction(insn, 0, 5);
1661 unsigned imm = fieldFromInstruction(insn, 5, 13);
1662 if (!AArch64_AM::isValidDecodeLogicalImmediate(imm, 64))
1663 return Fail;
1664
1665 // The same (tied) operand is added twice to the instruction.
1666 DecodeZPRRegisterClass(Inst, Zdn, Addr, Decoder);
1667 DecodeZPRRegisterClass(Inst, Zdn, Addr, Decoder);
1668 Inst.addOperand(MCOperand::createImm(imm));
1669 return Success;
1670}
1671
Sam Parker6d42de72017-08-11 13:14:00 +0000[diff] [blame]1672template<int Bits>
1673static DecodeStatus DecodeSImm(llvm::MCInst &Inst, uint64_t Imm,
1674 uint64_t Address, const void *Decoder) {
1675 if (Imm & ~((1LL << Bits) - 1))
1676 return Fail;
1677
1678 // Imm is a signed immediate, so sign extend it.
1679 if (Imm & (1 << (Bits - 1)))
1680 Imm |= ~((1LL << Bits) - 1);
1681
1682 Inst.addOperand(MCOperand::createImm(Imm));
1683 return Success;
1684}
1685