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Zoran Jovanovicada38ef2014-03-27 12:38:40 +00001//===-- MipsAsmBackend.h - Mips Asm Backend ------------------------------===//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file defines the MipsAsmBackend class.
11//
12//===----------------------------------------------------------------------===//
13//
14
Benjamin Kramera7c40ef2014-08-13 16:26:38 +000015#ifndef LLVM_LIB_TARGET_MIPS_MCTARGETDESC_MIPSASMBACKEND_H
16#define LLVM_LIB_TARGET_MIPS_MCTARGETDESC_MIPSASMBACKEND_H
Zoran Jovanovicada38ef2014-03-27 12:38:40 +000017
18#include "MCTargetDesc/MipsFixupKinds.h"
Daniel Sanders50f17232015-09-15 16:17:27 +000019#include "llvm/ADT/Triple.h"
Chandler Carruthd9903882015-01-14 11:23:27 +000020#include "llvm/MC/MCAsmBackend.h"
Zoran Jovanovicada38ef2014-03-27 12:38:40 +000021
22namespace llvm {
23
24class MCAssembler;
Aaron Ballmanbe648a32014-03-27 14:10:00 +000025struct MCFixupKindInfo;
Zoran Jovanovicada38ef2014-03-27 12:38:40 +000026class MCObjectWriter;
Simon Atanasyan6d795862017-09-07 12:54:26 +000027class MCRegisterInfo;
Aleksandar Beserminjia5949432018-10-16 08:27:28 +000028class MCSymbolELF;
Simon Atanasyan6d795862017-09-07 12:54:26 +000029class Target;
Zoran Jovanovicada38ef2014-03-27 12:38:40 +000030
31class MipsAsmBackend : public MCAsmBackend {
Simon Atanasyan6d795862017-09-07 12:54:26 +000032 Triple TheTriple;
Simon Atanasyan117665582017-09-21 10:44:26 +000033 bool IsN32;
Zoran Jovanovicada38ef2014-03-27 12:38:40 +000034
35public:
Simon Atanasyan6d795862017-09-07 12:54:26 +000036 MipsAsmBackend(const Target &T, const MCRegisterInfo &MRI, const Triple &TT,
Simon Atanasyan117665582017-09-21 10:44:26 +000037 StringRef CPU, bool N32)
Peter Collingbourne571a3302018-05-21 17:57:19 +000038 : MCAsmBackend(TT.isLittleEndian() ? support::little : support::big),
39 TheTriple(TT), IsN32(N32) {}
Zoran Jovanovicada38ef2014-03-27 12:38:40 +000040
Peter Collingbournedcd7d6c2018-05-21 19:20:29 +000041 std::unique_ptr<MCObjectTargetWriter>
42 createObjectTargetWriter() const override;
Zoran Jovanovicada38ef2014-03-27 12:38:40 +000043
Rafael Espindola801b42d2017-06-23 22:52:36 +000044 void applyFixup(const MCAssembler &Asm, const MCFixup &Fixup,
45 const MCValue &Target, MutableArrayRef<char> Data,
Peter Smith57f661b2018-06-06 09:40:06 +000046 uint64_t Value, bool IsResolved,
47 const MCSubtargetInfo *STI) const override;
Zoran Jovanovicada38ef2014-03-27 12:38:40 +000048
David Majnemerce108422016-01-19 23:05:27 +000049 Optional<MCFixupKind> getFixupKind(StringRef Name) const override;
Craig Topper56c590a2014-04-29 07:58:02 +000050 const MCFixupKindInfo &getFixupKindInfo(MCFixupKind Kind) const override;
Zoran Jovanovicada38ef2014-03-27 12:38:40 +000051
Craig Topper56c590a2014-04-29 07:58:02 +000052 unsigned getNumFixupKinds() const override {
Zoran Jovanovicada38ef2014-03-27 12:38:40 +000053 return Mips::NumTargetFixupKinds;
54 }
55
56 /// @name Target Relaxation Interfaces
57 /// @{
58
59 /// MayNeedRelaxation - Check whether the given instruction may need
60 /// relaxation.
61 ///
62 /// \param Inst - The instruction to test.
Peter Smith57f661b2018-06-06 09:40:06 +000063 bool mayNeedRelaxation(const MCInst &Inst,
64 const MCSubtargetInfo &STI) const override {
Zoran Jovanovicada38ef2014-03-27 12:38:40 +000065 return false;
66 }
67
68 /// fixupNeedsRelaxation - Target specific predicate for whether a given
69 /// fixup requires the associated instruction to be relaxed.
70 bool fixupNeedsRelaxation(const MCFixup &Fixup, uint64_t Value,
71 const MCRelaxableFragment *DF,
Craig Topper56c590a2014-04-29 07:58:02 +000072 const MCAsmLayout &Layout) const override {
Zoran Jovanovicada38ef2014-03-27 12:38:40 +000073 // FIXME.
Craig Topper35b2f752014-06-19 06:10:58 +000074 llvm_unreachable("RelaxInstruction() unimplemented");
Zoran Jovanovicada38ef2014-03-27 12:38:40 +000075 return false;
76 }
77
78 /// RelaxInstruction - Relax the instruction in the given fragment
79 /// to the next wider instruction.
80 ///
81 /// \param Inst - The instruction to relax, which may be the same
82 /// as the output.
83 /// \param [out] Res On return, the relaxed instruction.
Nirav Dave86030622016-07-11 14:23:53 +000084 void relaxInstruction(const MCInst &Inst, const MCSubtargetInfo &STI,
85 MCInst &Res) const override {}
Zoran Jovanovicada38ef2014-03-27 12:38:40 +000086
87 /// @}
88
Peter Collingbourne571a3302018-05-21 17:57:19 +000089 bool writeNopData(raw_ostream &OS, uint64_t Count) const override;
Zoran Jovanovicada38ef2014-03-27 12:38:40 +000090
Simon Atanasyan3a44bcf2018-06-01 16:37:42 +000091 bool shouldForceRelocation(const MCAssembler &Asm, const MCFixup &Fixup,
92 const MCValue &Target) override;
93
Aleksandar Beserminjia5949432018-10-16 08:27:28 +000094 bool isMicroMips(const MCSymbol *Sym) const override;
Zoran Jovanovicada38ef2014-03-27 12:38:40 +000095}; // class MipsAsmBackend
96
Alexander Kornienkof00654e2015-06-23 09:49:53 +000097} // namespace
Zoran Jovanovicada38ef2014-03-27 12:38:40 +000098
99#endif