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gerrit-public.fairphone.software / toolchain / llvm-project / 81fe1fbf4abd00b24e078a80cb15a2d2c1343f11 / . / llvm / lib / Target / PowerPC / PPCScheduleP8.td
blob: ff39dfda7016d3e8a6d977f4d88d111a919c8f47 [file] [log] [blame]
Will Schmidteba49232014-12-03 18:46:30 +0000[diff] [blame]1//===-- PPCScheduleP8.td - PPC P8 Scheduling Definitions ---*- tablegen -*-===//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file defines the itinerary class data for the POWER8 processor.
11//
12//===----------------------------------------------------------------------===//
13
14// Scheduling for the P8 involves tracking two types of resources:
15// 1. The dispatch bundle slots
16// 2. The functional unit resources
17
18// Dispatch units:
19def P8_DU1 : FuncUnit;
20def P8_DU2 : FuncUnit;
21def P8_DU3 : FuncUnit;
22def P8_DU4 : FuncUnit;
23def P8_DU5 : FuncUnit;
24def P8_DU6 : FuncUnit;
25def P8_DU7 : FuncUnit; // Only branch instructions will use DU7,DU8
26def P8_DU8 : FuncUnit;
27
28// 10 insns per cycle (2-LU, 2-LSU, 2-FXU, 2-FPU, 1-CRU, 1-BRU).
29
30def P8_LU1 : FuncUnit; // Loads or fixed-point operations 1
31def P8_LU2 : FuncUnit; // Loads or fixed-point operations 2
32
33// Load/Store pipelines can handle Stores, fixed-point loads, and simple
34// fixed-point operations.
35def P8_LSU1 : FuncUnit; // Load/Store pipeline 1
36def P8_LSU2 : FuncUnit; // Load/Store pipeline 2
37
38// Fixed Point unit
39def P8_FXU1 : FuncUnit; // FX pipeline 1
40def P8_FXU2 : FuncUnit; // FX pipeline 2
41
42// The Floating-Point Unit (FPU) and Vector Media Extension (VMX) units
43// are combined on P7 and newer into a Vector Scalar Unit (VSU).
44// The P8 Instruction latency documents still refers to the unit as the
45// FPU, so keep in mind that FPU==VSU.
46// In contrast to the P7, the VMX units on P8 are symmetric, so no need to
47// split vector integer ops or 128-bit load/store/perms to the specific units.
48def P8_FPU1 : FuncUnit; // VS pipeline 1
49def P8_FPU2 : FuncUnit; // VS pipeline 2
50
51def P8_CRU : FuncUnit; // CR unit (CR logicals and move-from-SPRs)
52def P8_BRU : FuncUnit; // BR unit
53
54def P8Itineraries : ProcessorItineraries<
55 [P8_DU1, P8_DU2, P8_DU3, P8_DU4, P8_DU5, P8_DU6, P8_DU7, P8_DU8,
56 P8_LU1, P8_LU2, P8_LSU1, P8_LSU2, P8_FXU1, P8_FXU2,
57 P8_FPU1, P8_FPU2, P8_CRU, P8_BRU], [], [
58 InstrItinData<IIC_IntSimple , [InstrStage<1, [P8_DU1, P8_DU2, P8_DU3,
59 P8_DU4, P8_DU5, P8_DU6], 0>,
60 InstrStage<1, [P8_FXU1, P8_FXU2,
61 P8_LU1, P8_LU2,
62 P8_LSU1, P8_LSU2]>],
63 [1, 1, 1]>,
64 InstrItinData<IIC_IntGeneral , [InstrStage<1, [P8_DU1, P8_DU2, P8_DU3,
65 P8_DU4, P8_DU5, P8_DU6], 0>,
66 InstrStage<1, [P8_FXU1, P8_FXU2, P8_LU1,
67 P8_LU2, P8_LSU1, P8_LSU2]>],
68 [1, 1, 1]>,
Hal Finkel11d3c562015-02-01 17:52:16 +0000[diff] [blame]69 InstrItinData<IIC_IntISEL, [InstrStage<1, [P8_DU1], 0>,
70 InstrStage<1, [P8_FXU1, P8_FXU2], 0>,
71 InstrStage<1, [P8_BRU]>],
72 [1, 1, 1, 1]>,
Will Schmidteba49232014-12-03 18:46:30 +0000[diff] [blame]73 InstrItinData<IIC_IntCompare , [InstrStage<1, [P8_DU1, P8_DU2, P8_DU3,
74 P8_DU4, P8_DU5, P8_DU6], 0>,
75 InstrStage<1, [P8_FXU1, P8_FXU2]>],
76 [1, 1, 1]>,
77 InstrItinData<IIC_IntDivW , [InstrStage<1, [P8_DU1, P8_DU2, P8_DU3,
78 P8_DU4, P8_DU5, P8_DU6], 0>,
79 InstrStage<15, [P8_FXU1, P8_FXU2]>],
80 [15, 1, 1]>,
81 InstrItinData<IIC_IntDivD , [InstrStage<1, [P8_DU1, P8_DU2, P8_DU3,
82 P8_DU4, P8_DU5, P8_DU6], 0>,
83 InstrStage<23, [P8_FXU1, P8_FXU2]>],
84 [23, 1, 1]>,
85 InstrItinData<IIC_IntMulHW , [InstrStage<1, [P8_DU1, P8_DU2, P8_DU3,
86 P8_DU4, P8_DU5, P8_DU6], 0>,
87 InstrStage<1, [P8_FXU1, P8_FXU2]>],
88 [4, 1, 1]>,
89 InstrItinData<IIC_IntMulHWU , [InstrStage<1, [P8_DU1, P8_DU2, P8_DU3,
90 P8_DU4, P8_DU5, P8_DU6], 0>,
91 InstrStage<1, [P8_FXU1, P8_FXU2]>],
92 [4, 1, 1]>,
QingShan Zhangf1b0b472018-09-18 02:05:18 +0000[diff] [blame]93 InstrItinData<IIC_IntMulHD , [InstrStage<1, [P8_DU1, P8_DU2, P8_DU3,
94 P8_DU4, P8_DU5, P8_DU6], 0>,
95 InstrStage<1, [P8_FXU1, P8_FXU2]>],
96 [4, 1, 1]>,
Will Schmidteba49232014-12-03 18:46:30 +0000[diff] [blame]97 InstrItinData<IIC_IntMulLI , [InstrStage<1, [P8_DU1, P8_DU2, P8_DU3,
98 P8_DU4, P8_DU5, P8_DU6], 0>,
99 InstrStage<1, [P8_FXU1, P8_FXU2]>],
100 [4, 1, 1]>,
101 InstrItinData<IIC_IntRotate , [InstrStage<1, [P8_DU1, P8_DU2, P8_DU3,
102 P8_DU4, P8_DU5, P8_DU6], 0>,
103 InstrStage<1, [P8_FXU1, P8_FXU2]>],
104 [1, 1, 1]>,
105 InstrItinData<IIC_IntRotateD , [InstrStage<1, [P8_DU1, P8_DU2, P8_DU3,
106 P8_DU4, P8_DU5, P8_DU6], 0>,
107 InstrStage<1, [P8_FXU1, P8_FXU2]>],
108 [1, 1, 1]>,
QingShan Zhangc2b6c542018-09-03 03:14:29 +0000[diff] [blame]109 InstrItinData<IIC_IntRotateDI , [InstrStage<1, [P8_DU1, P8_DU2, P8_DU3,
110 P8_DU4, P8_DU5, P8_DU6], 0>,
111 InstrStage<1, [P8_FXU1, P8_FXU2]>],
112 [1, 1, 1]>,
Will Schmidteba49232014-12-03 18:46:30 +0000[diff] [blame]113 InstrItinData<IIC_IntShift , [InstrStage<1, [P8_DU1, P8_DU2, P8_DU3,
114 P8_DU4, P8_DU5, P8_DU6], 0>,
115 InstrStage<1, [P8_FXU1, P8_FXU2]>],
116 [1, 1, 1]>,
117 InstrItinData<IIC_IntTrapW , [InstrStage<1, [P8_DU1, P8_DU2, P8_DU3,
118 P8_DU4, P8_DU5, P8_DU6], 0>,
119 InstrStage<1, [P8_FXU1, P8_FXU2]>],
120 [1, 1]>,
121 InstrItinData<IIC_IntTrapD , [InstrStage<1, [P8_DU1, P8_DU2, P8_DU3,
122 P8_DU4, P8_DU5, P8_DU6], 0>,
123 InstrStage<1, [P8_FXU1, P8_FXU2]>],
124 [1, 1]>,
125 InstrItinData<IIC_BrB , [InstrStage<1, [P8_DU7, P8_DU8], 0>,
126 InstrStage<1, [P8_BRU]>],
127 [3, 1, 1]>,
128 // FIXME - the Br* groups below are not branch related, so should probably
129 // be renamed.
130 // IIC_BrCR consists of the cr* instructions. (crand,crnor,creqv, etc).
131 // and should be 'First' in dispatch.
132 InstrItinData<IIC_BrCR , [InstrStage<1, [P8_DU1], 0>,
133 InstrStage<1, [P8_CRU]>],
134 [3, 1, 1]>,
135 // IIC_BrMCR consists of the mcrf instruction.
136 InstrItinData<IIC_BrMCR , [InstrStage<1, [P8_DU1, P8_DU2, P8_DU3,
137 P8_DU4, P8_DU5, P8_DU6], 0>,
138 InstrStage<1, [P8_CRU]>],
139 [3, 1, 1]>,
140 // IIC_BrMCRX consists of mcrxr (obsolete instruction) and mtcrf, which
141 // should be first in the dispatch group.
142 InstrItinData<IIC_BrMCRX , [InstrStage<1, [P8_DU1], 0>,
143 InstrStage<1, [P8_FXU1, P8_FXU2]>],
144 [3, 1, 1]>,
145 InstrItinData<IIC_BrMCRX , [InstrStage<1, [P8_DU1], 0>,
146 InstrStage<1, [P8_FXU1, P8_FXU2]>],
147 [3, 1]>,
148 InstrItinData<IIC_LdStLoad , [InstrStage<1, [P8_DU1, P8_DU2, P8_DU3,
149 P8_DU4, P8_DU5, P8_DU6], 0>,
150 InstrStage<1, [P8_LSU1, P8_LSU2,
151 P8_LU1, P8_LU2]>],
152 [2, 1, 1]>,
153 InstrItinData<IIC_LdStLoadUpd , [InstrStage<1, [P8_DU1], 0>,
154 InstrStage<1, [P8_DU2], 0>,
155 InstrStage<1, [P8_LSU1, P8_LSU2,
156 P8_LU1, P8_LU2 ], 0>,
157 InstrStage<1, [P8_FXU1, P8_FXU2]>],
158 [2, 2, 1, 1]>,
159 // Update-Indexed form loads/stores are no longer first and last in the
160 // dispatch group. They are simply cracked, so require DU1,DU2.
161 InstrItinData<IIC_LdStLoadUpdX, [InstrStage<1, [P8_DU1], 0>,
162 InstrStage<1, [P8_DU2], 0>,
163 InstrStage<1, [P8_LSU1, P8_LSU2,
164 P8_LU1, P8_LU2], 0>,
165 InstrStage<1, [P8_FXU1, P8_FXU2]>],
166 [3, 3, 1, 1]>,
167 InstrItinData<IIC_LdStLD , [InstrStage<1, [P8_DU1, P8_DU2, P8_DU3,
168 P8_DU4, P8_DU5, P8_DU6], 0>,
169 InstrStage<1, [P8_LSU1, P8_LSU2,
170 P8_LU1, P8_LU2]>],
171 [2, 1, 1]>,
172 InstrItinData<IIC_LdStLDU , [InstrStage<1, [P8_DU1], 0>,
173 InstrStage<1, [P8_DU2], 0>,
174 InstrStage<1, [P8_LSU1, P8_LSU2,
175 P8_LU1, P8_LU2], 0>,
176 InstrStage<1, [P8_FXU1, P8_FXU2]>],
177 [2, 2, 1, 1]>,
178 InstrItinData<IIC_LdStLDUX , [InstrStage<1, [P8_DU1], 0>,
179 InstrStage<1, [P8_DU2], 0>,
180 InstrStage<1, [P8_LSU1, P8_LSU2,
181 P8_LU1, P8_LU2], 0>,
182 InstrStage<1, [P8_FXU1, P8_FXU2]>],
183 [3, 3, 1, 1]>,
184 InstrItinData<IIC_LdStLFD , [InstrStage<1, [P8_DU1, P8_DU2, P8_DU3,
185 P8_DU4, P8_DU5, P8_DU6], 0>,
186 InstrStage<1, [P8_LU1, P8_LU2]>],
187 [3, 1, 1]>,
188 InstrItinData<IIC_LdStLVecX , [InstrStage<1, [P8_DU1, P8_DU2, P8_DU3,
189 P8_DU4, P8_DU5, P8_DU6], 0>,
190 InstrStage<1, [P8_LU1, P8_LU2]>],
191 [3, 1, 1]>,
192 InstrItinData<IIC_LdStLFDU , [InstrStage<1, [P8_DU1], 0>,
193 InstrStage<1, [P8_DU2], 0>,
194 InstrStage<1, [P8_LU1, P8_LU2], 0>,
195 InstrStage<1, [P8_FXU1, P8_FXU2]>],
196 [3, 3, 1, 1]>,
197 InstrItinData<IIC_LdStLFDUX , [InstrStage<1, [P8_DU1], 0>,
198 InstrStage<1, [P8_DU2], 0>,
199 InstrStage<1, [P8_LU1, P8_LU2], 0>,
200 InstrStage<1, [P8_FXU1, P8_FXU2]>],
201 [3, 3, 1, 1]>,
202 InstrItinData<IIC_LdStLHA , [InstrStage<1, [P8_DU1], 0>,
203 InstrStage<1, [P8_DU2], 0>,
204 InstrStage<1, [P8_LSU1, P8_LSU2,
205 P8_LU1, P8_LU2], 0>,
206 InstrStage<1, [P8_FXU1, P8_FXU2,
207 P8_LU1, P8_LU2]>],
208 [3, 1, 1]>,
209 InstrItinData<IIC_LdStLHAU , [InstrStage<1, [P8_DU1], 0>,
210 InstrStage<1, [P8_DU2], 0>,
211 InstrStage<1, [P8_LSU1, P8_LSU2,
212 P8_LU1, P8_LU2], 0>,
213 InstrStage<1, [P8_FXU1, P8_FXU2]>,
214 InstrStage<1, [P8_FXU1, P8_FXU2]>],
215 [4, 4, 1, 1]>,
216 // first+last in dispatch group.
217 InstrItinData<IIC_LdStLHAUX , [InstrStage<1, [P8_DU1], 0>,
218 InstrStage<1, [P8_DU2], 0>,
219 InstrStage<1, [P8_DU3], 0>,
220 InstrStage<1, [P8_DU4], 0>,
221 InstrStage<1, [P8_DU5], 0>,
222 InstrStage<1, [P8_DU6], 0>,
223 InstrStage<1, [P8_LSU1, P8_LSU2,
224 P8_LU1, P8_LU2], 0>,
225 InstrStage<1, [P8_FXU1, P8_FXU2]>,
226 InstrStage<1, [P8_FXU1, P8_FXU2]>],
227 [4, 4, 1, 1]>,
228 InstrItinData<IIC_LdStLWA , [InstrStage<1, [P8_DU1], 0>,
229 InstrStage<1, [P8_DU2], 0>,
230 InstrStage<1, [P8_LSU1, P8_LSU2,
231 P8_LU1, P8_LU2]>,
232 InstrStage<1, [P8_FXU1, P8_FXU2]>],
233 [3, 1, 1]>,
234 InstrItinData<IIC_LdStLWARX, [InstrStage<1, [P8_DU1], 0>,
235 InstrStage<1, [P8_DU2], 0>,
236 InstrStage<1, [P8_DU3], 0>,
237 InstrStage<1, [P8_DU4], 0>,
238 InstrStage<1, [P8_LSU1, P8_LSU2,
239 P8_LU1, P8_LU2]>],
240 [3, 1, 1]>,
241 // first+last
242 InstrItinData<IIC_LdStLDARX, [InstrStage<1, [P8_DU1], 0>,
243 InstrStage<1, [P8_DU2], 0>,
244 InstrStage<1, [P8_DU3], 0>,
245 InstrStage<1, [P8_DU4], 0>,
246 InstrStage<1, [P8_DU5], 0>,
247 InstrStage<1, [P8_DU6], 0>,
248 InstrStage<1, [P8_LSU1, P8_LSU2,
249 P8_LU1, P8_LU2]>],
250 [3, 1, 1]>,
251 InstrItinData<IIC_LdStLMW , [InstrStage<1, [P8_DU1, P8_DU2, P8_DU3,
252 P8_DU4, P8_DU5, P8_DU6], 0>,
253 InstrStage<1, [P8_LSU1, P8_LSU2,
254 P8_LU1, P8_LU2]>],
255 [2, 1, 1]>,
256// Stores are dual-issued from the issue queue, so may only take up one
257// dispatch slot. The instruction will be broken into two IOPS. The agen
258// op is issued to the LSU, and the data op (register fetch) is issued
259// to either the LU (GPR store) or the VSU (FPR store).
260 InstrItinData<IIC_LdStStore , [InstrStage<1, [P8_DU1, P8_DU2, P8_DU3,
261 P8_DU4, P8_DU5, P8_DU6], 0>,
262 InstrStage<1, [P8_LSU1, P8_LSU2]>,
263 InstrStage<1, [P8_LU1, P8_LU2]>],
264 [1, 1, 1]>,
265 InstrItinData<IIC_LdStSTD , [InstrStage<1, [P8_DU1, P8_DU2, P8_DU3,
266 P8_DU4, P8_DU5, P8_DU6], 0>,
267 InstrStage<1, [P8_LU1, P8_LU2,
268 P8_LSU1, P8_LSU2]>]
269 [1, 1, 1]>,
Jinsong Ji9a0ed202018-11-20 15:11:42 +0000[diff] [blame]270 InstrItinData<IIC_LdStSTU , [InstrStage<1, [P8_DU1], 0>,
Will Schmidteba49232014-12-03 18:46:30 +0000[diff] [blame]271 InstrStage<1, [P8_DU2], 0>,
272 InstrStage<1, [P8_LU1, P8_LU2,
273 P8_LSU1, P8_LSU2], 0>,
274 InstrStage<1, [P8_FXU1, P8_FXU2]>],
275 [2, 1, 1, 1]>,
276 // First+last
Jinsong Ji9a0ed202018-11-20 15:11:42 +0000[diff] [blame]277 InstrItinData<IIC_LdStSTUX , [InstrStage<1, [P8_DU1], 0>,
Will Schmidteba49232014-12-03 18:46:30 +0000[diff] [blame]278 InstrStage<1, [P8_DU2], 0>,
279 InstrStage<1, [P8_DU3], 0>,
280 InstrStage<1, [P8_DU4], 0>,
281 InstrStage<1, [P8_DU5], 0>,
282 InstrStage<1, [P8_DU6], 0>,
283 InstrStage<1, [P8_LSU1, P8_LSU2], 0>,
284 InstrStage<1, [P8_FXU1, P8_FXU2]>,
285 InstrStage<1, [P8_FXU1, P8_FXU2]>],
286 [2, 1, 1, 1]>,
287 InstrItinData<IIC_LdStSTFD , [InstrStage<1, [P8_DU1, P8_DU2, P8_DU3,
288 P8_DU4, P8_DU5, P8_DU6], 0>,
289 InstrStage<1, [P8_LSU1, P8_LSU2], 0>,
290 InstrStage<1, [P8_FPU1, P8_FPU2]>],
291 [1, 1, 1]>,
292 InstrItinData<IIC_LdStSTFDU , [InstrStage<1, [P8_DU1], 0>,
293 InstrStage<1, [P8_DU2], 0>,
294 InstrStage<1, [P8_LSU1, P8_LSU2], 0>,
295 InstrStage<1, [P8_FXU1, P8_FXU2], 0>,
296 InstrStage<1, [P8_FPU1, P8_FPU2]>],
297 [2, 1, 1, 1]>,
298 InstrItinData<IIC_LdStSTVEBX , [InstrStage<1, [P8_DU1, P8_DU2, P8_DU3,
299 P8_DU4, P8_DU5, P8_DU6], 0>,
300 InstrStage<1, [P8_LSU1, P8_LSU2], 0>,
301 InstrStage<1, [P8_FPU1, P8_FPU2]>],
302 [1, 1, 1]>,
303 InstrItinData<IIC_LdStSTDCX , [InstrStage<1, [P8_DU1], 0>,
304 InstrStage<1, [P8_DU2], 0>,
305 InstrStage<1, [P8_DU3], 0>,
306 InstrStage<1, [P8_DU4], 0>,
307 InstrStage<1, [P8_DU5], 0>,
308 InstrStage<1, [P8_DU6], 0>,
309 InstrStage<1, [P8_LSU1, P8_LSU2], 0>,
310 InstrStage<1, [P8_LU1, P8_LU2]>],
311 [1, 1, 1]>,
312 InstrItinData<IIC_LdStSTWCX , [InstrStage<1, [P8_DU1], 0>,
313 InstrStage<1, [P8_DU2], 0>,
314 InstrStage<1, [P8_DU3], 0>,
315 InstrStage<1, [P8_DU4], 0>,
316 InstrStage<1, [P8_DU5], 0>,
317 InstrStage<1, [P8_DU6], 0>,
318 InstrStage<1, [P8_LSU1, P8_LSU2], 0>,
319 InstrStage<1, [P8_LU1, P8_LU2]>],
320 [1, 1, 1]>,
321 InstrItinData<IIC_SprMFCR , [InstrStage<1, [P8_DU1], 0>,
322 InstrStage<1, [P8_CRU]>],
323 [6, 1]>,
324 InstrItinData<IIC_SprMFCRF , [InstrStage<1, [P8_DU1], 0>,
325 InstrStage<1, [P8_CRU]>],
326 [3, 1]>,
327 InstrItinData<IIC_SprMTSPR , [InstrStage<1, [P8_DU1], 0>,
328 InstrStage<1, [P8_FXU1, P8_FXU2]>],
329 [4, 1]>, // mtctr
330 InstrItinData<IIC_FPGeneral , [InstrStage<1, [P8_DU1, P8_DU2, P8_DU3,
331 P8_DU4, P8_DU5, P8_DU6], 0>,
332 InstrStage<1, [P8_FPU1, P8_FPU2]>],
333 [5, 1, 1]>,
Hal Finkel8acae522015-07-14 20:02:02 +0000[diff] [blame]334 InstrItinData<IIC_FPAddSub , [InstrStage<1, [P8_DU1, P8_DU2, P8_DU3,
335 P8_DU4, P8_DU5, P8_DU6], 0>,
336 InstrStage<1, [P8_FPU1, P8_FPU2]>],
337 [5, 1, 1]>,
Will Schmidteba49232014-12-03 18:46:30 +0000[diff] [blame]338 InstrItinData<IIC_FPCompare , [InstrStage<1, [P8_DU1, P8_DU2, P8_DU3,
339 P8_DU4, P8_DU5, P8_DU6], 0>,
340 InstrStage<1, [P8_FPU1, P8_FPU2]>],
341 [8, 1, 1]>,
342 InstrItinData<IIC_FPDivD , [InstrStage<1, [P8_DU1, P8_DU2, P8_DU3,
343 P8_DU4, P8_DU5, P8_DU6], 0>,
344 InstrStage<1, [P8_FPU1, P8_FPU2]>],
345 [33, 1, 1]>,
346 InstrItinData<IIC_FPDivS , [InstrStage<1, [P8_DU1, P8_DU2, P8_DU3,
347 P8_DU4, P8_DU5, P8_DU6], 0>,
348 InstrStage<1, [P8_FPU1, P8_FPU2]>],
349 [27, 1, 1]>,
350 InstrItinData<IIC_FPSqrtD , [InstrStage<1, [P8_DU1, P8_DU2, P8_DU3,
351 P8_DU4, P8_DU5, P8_DU6], 0>,
352 InstrStage<1, [P8_FPU1, P8_FPU2]>],
353 [44, 1, 1]>,
354 InstrItinData<IIC_FPSqrtS , [InstrStage<1, [P8_DU1, P8_DU2, P8_DU3,
355 P8_DU4, P8_DU5, P8_DU6], 0>,
356 InstrStage<1, [P8_FPU1, P8_FPU2]>],
357 [32, 1, 1]>,
358 InstrItinData<IIC_FPFused , [InstrStage<1, [P8_DU1, P8_DU2, P8_DU3,
359 P8_DU4, P8_DU5, P8_DU6], 0>,
360 InstrStage<1, [P8_FPU1, P8_FPU2]>],
361 [5, 1, 1, 1]>,
362 InstrItinData<IIC_FPRes , [InstrStage<1, [P8_DU1, P8_DU2, P8_DU3,
363 P8_DU4, P8_DU5, P8_DU6], 0>,
364 InstrStage<1, [P8_FPU1, P8_FPU2]>],
365 [5, 1, 1]>,
366 InstrItinData<IIC_VecGeneral , [InstrStage<1, [P8_DU1], 0>,
367 InstrStage<1, [P8_FPU1, P8_FPU2]>],
368 [2, 1, 1]>,
369 InstrItinData<IIC_VecVSL , [InstrStage<1, [P8_DU1], 0>,
370 InstrStage<1, [P8_FPU1, P8_FPU2]>],
371 [2, 1, 1]>,
372 InstrItinData<IIC_VecVSR , [InstrStage<1, [P8_DU1], 0>,
373 InstrStage<1, [P8_FPU1, P8_FPU2]>],
374 [2, 1, 1]>,
375 InstrItinData<IIC_VecFP , [InstrStage<1, [P8_DU1], 0>,
376 InstrStage<1, [P8_FPU1, P8_FPU2]>],
377 [6, 1, 1]>,
378 InstrItinData<IIC_VecFPCompare, [InstrStage<1, [P8_DU1], 0>,
379 InstrStage<1, [P8_FPU1, P8_FPU2]>],
380 [6, 1, 1]>,
381 InstrItinData<IIC_VecFPRound , [InstrStage<1, [P8_DU1], 0>,
382 InstrStage<1, [P8_FPU1, P8_FPU2]>],
383 [6, 1, 1]>,
384 InstrItinData<IIC_VecComplex , [InstrStage<1, [P8_DU1], 0>,
385 InstrStage<1, [P8_FPU1, P8_FPU2]>],
386 [7, 1, 1]>,
387 InstrItinData<IIC_VecPerm , [InstrStage<1, [P8_DU1, P8_DU2], 0>,
Eric Christopher4a8208c2017-02-26 00:11:58 +0000[diff] [blame]388 InstrStage<1, [P8_FPU1, P8_FPU2]>],
Will Schmidteba49232014-12-03 18:46:30 +0000[diff] [blame]389 [3, 1, 1]>
390]>;
391
392// ===---------------------------------------------------------------------===//
393// P8 machine model for scheduling and other instruction cost heuristics.
394// P8 has an 8 insn dispatch group (6 non-branch, 2 branch) and can issue up
395// to 10 insns per cycle (2-LU, 2-LSU, 2-FXU, 2-FPU, 1-CRU, 1-BRU).
396
397def P8Model : SchedMachineModel {
398 let IssueWidth = 8; // up to 8 instructions dispatched per cycle.
399 // up to six non-branch instructions.
400 // up to two branches in a dispatch group.
401
Will Schmidteba49232014-12-03 18:46:30 +0000[diff] [blame]402 let LoadLatency = 3; // Optimistic load latency assuming bypass.
403 // This is overriden by OperandCycles if the
404 // Itineraries are queried instead.
405 let MispredictPenalty = 16;
406
Hal Finkel611b1272015-01-10 00:31:10 +0000[diff] [blame]407 // Try to make sure we have at least 10 dispatch groups in a loop.
408 let LoopMicroOpBufferSize = 60;
Hal Finkelb359b732015-01-09 15:51:16 +0000[diff] [blame]409
Matthias Braun17cb5792016-03-01 20:03:21 +0000[diff] [blame]410 let CompleteModel = 0;
411
Will Schmidteba49232014-12-03 18:46:30 +0000[diff] [blame]412 let Itineraries = P8Itineraries;
413}
414