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Dan Gohman0cfb5f82016-05-10 04:24:02 +00001//===- WebAssemblyPrepareForLiveIntervals.cpp - Prepare for LiveIntervals -===//
2//
Chandler Carruth2946cd72019-01-19 08:50:56 +00003// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
Dan Gohman0cfb5f82016-05-10 04:24:02 +00006//
7//===----------------------------------------------------------------------===//
8///
9/// \file
Adrian Prantl5f8f34e42018-05-01 15:54:18 +000010/// Fix up code to meet LiveInterval's requirements.
Dan Gohman0cfb5f82016-05-10 04:24:02 +000011///
12/// Some CodeGen passes don't preserve LiveInterval's requirements, because
13/// they run after register allocation and it isn't important. However,
14/// WebAssembly runs LiveIntervals in a late pass. This pass transforms code
15/// to meet LiveIntervals' requirements; primarily, it ensures that all
16/// virtual register uses have definitions (IMPLICIT_DEF definitions if
17/// nothing else).
18///
19//===----------------------------------------------------------------------===//
20
Dan Gohman0cfb5f82016-05-10 04:24:02 +000021#include "MCTargetDesc/WebAssemblyMCTargetDesc.h"
Chandler Carruth6bda14b2017-06-06 11:49:48 +000022#include "WebAssembly.h"
Dan Gohman0cfb5f82016-05-10 04:24:02 +000023#include "WebAssemblyMachineFunctionInfo.h"
24#include "WebAssemblySubtarget.h"
Dan Gohman4fc4e422016-10-24 19:49:43 +000025#include "WebAssemblyUtilities.h"
Dan Gohman0cfb5f82016-05-10 04:24:02 +000026#include "llvm/CodeGen/MachineFunctionPass.h"
27#include "llvm/CodeGen/MachineInstrBuilder.h"
28#include "llvm/CodeGen/MachineRegisterInfo.h"
29#include "llvm/CodeGen/Passes.h"
30#include "llvm/Support/Debug.h"
31#include "llvm/Support/raw_ostream.h"
32using namespace llvm;
33
34#define DEBUG_TYPE "wasm-prepare-for-live-intervals"
35
36namespace {
37class WebAssemblyPrepareForLiveIntervals final : public MachineFunctionPass {
38public:
39 static char ID; // Pass identification, replacement for typeid
40 WebAssemblyPrepareForLiveIntervals() : MachineFunctionPass(ID) {}
41
42private:
Mehdi Amini117296c2016-10-01 02:56:57 +000043 StringRef getPassName() const override {
Dan Gohman0cfb5f82016-05-10 04:24:02 +000044 return "WebAssembly Prepare For LiveIntervals";
45 }
46
47 void getAnalysisUsage(AnalysisUsage &AU) const override {
48 AU.setPreservesCFG();
49 MachineFunctionPass::getAnalysisUsage(AU);
50 }
51
52 bool runOnMachineFunction(MachineFunction &MF) override;
53};
54} // end anonymous namespace
55
56char WebAssemblyPrepareForLiveIntervals::ID = 0;
Jacob Gravelle40926452018-03-30 20:36:58 +000057INITIALIZE_PASS(WebAssemblyPrepareForLiveIntervals, DEBUG_TYPE,
58 "Fix up code for LiveIntervals", false, false)
59
Dan Gohman0cfb5f82016-05-10 04:24:02 +000060FunctionPass *llvm::createWebAssemblyPrepareForLiveIntervals() {
61 return new WebAssemblyPrepareForLiveIntervals();
62}
63
Dan Gohman0cfb5f82016-05-10 04:24:02 +000064// Test whether the given register has an ARGUMENT def.
Heejin Ahn18c56a02019-02-04 19:13:39 +000065static bool hasArgumentDef(unsigned Reg, const MachineRegisterInfo &MRI) {
Derek Schuff39bf39f2016-08-02 23:16:09 +000066 for (const auto &Def : MRI.def_instructions(Reg))
Dan Gohman4fc4e422016-10-24 19:49:43 +000067 if (WebAssembly::isArgument(Def))
Dan Gohman0cfb5f82016-05-10 04:24:02 +000068 return true;
69 return false;
70}
71
Heejin Ahnf208f632018-09-05 01:27:38 +000072bool WebAssemblyPrepareForLiveIntervals::runOnMachineFunction(
73 MachineFunction &MF) {
Nicola Zaghend34e60c2018-05-14 12:53:11 +000074 LLVM_DEBUG({
Dan Gohman0cfb5f82016-05-10 04:24:02 +000075 dbgs() << "********** Prepare For LiveIntervals **********\n"
76 << "********** Function: " << MF.getName() << '\n';
77 });
78
79 bool Changed = false;
80 MachineRegisterInfo &MRI = MF.getRegInfo();
81 const auto &TII = *MF.getSubtarget<WebAssemblySubtarget>().getInstrInfo();
82 MachineBasicBlock &Entry = *MF.begin();
83
84 assert(!mustPreserveAnalysisID(LiveIntervalsID) &&
85 "LiveIntervals shouldn't be active yet!");
86
87 // We don't preserve SSA form.
88 MRI.leaveSSA();
89
90 // BranchFolding and perhaps other passes don't preserve IMPLICIT_DEF
91 // instructions. LiveIntervals requires that all paths to virtual register
92 // uses provide a definition. Insert IMPLICIT_DEFs in the entry block to
93 // conservatively satisfy this.
94 //
95 // TODO: This is fairly heavy-handed; find a better approach.
96 //
Heejin Ahn18c56a02019-02-04 19:13:39 +000097 for (unsigned I = 0, E = MRI.getNumVirtRegs(); I < E; ++I) {
98 unsigned Reg = TargetRegisterInfo::index2VirtReg(I);
Dan Gohman0cfb5f82016-05-10 04:24:02 +000099
100 // Skip unused registers.
101 if (MRI.use_nodbg_empty(Reg))
102 continue;
103
104 // Skip registers that have an ARGUMENT definition.
Heejin Ahn18c56a02019-02-04 19:13:39 +0000105 if (hasArgumentDef(Reg, MRI))
Dan Gohman0cfb5f82016-05-10 04:24:02 +0000106 continue;
107
108 BuildMI(Entry, Entry.begin(), DebugLoc(),
109 TII.get(WebAssembly::IMPLICIT_DEF), Reg);
110 Changed = true;
111 }
112
113 // Move ARGUMENT_* instructions to the top of the entry block, so that their
114 // liveness reflects the fact that these really are live-in values.
Heejin Ahnf208f632018-09-05 01:27:38 +0000115 for (auto MII = Entry.begin(), MIE = Entry.end(); MII != MIE;) {
Dan Gohman4fc4e422016-10-24 19:49:43 +0000116 MachineInstr &MI = *MII++;
117 if (WebAssembly::isArgument(MI)) {
118 MI.removeFromParent();
119 Entry.insert(Entry.begin(), &MI);
Dan Gohman0cfb5f82016-05-10 04:24:02 +0000120 }
121 }
122
Matthias Braunf8422972017-12-13 02:51:04 +0000123 // Ok, we're now ready to run the LiveIntervals analysis again.
Dan Gohman0cfb5f82016-05-10 04:24:02 +0000124 MF.getProperties().set(MachineFunctionProperties::Property::TracksLiveness);
125
126 return Changed;
127}