| Dan Gohman | 10e730a | 2015-06-29 23:51:55 +0000 | [diff] [blame] | 1 | //- WebAssembly.td - Describe the WebAssembly Target Machine --*- tablegen -*-// | 
|  | 2 | // | 
| Chandler Carruth | 2946cd7 | 2019-01-19 08:50:56 +0000 | [diff] [blame] | 3 | // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. | 
|  | 4 | // See https://llvm.org/LICENSE.txt for license information. | 
|  | 5 | // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception | 
| Dan Gohman | 10e730a | 2015-06-29 23:51:55 +0000 | [diff] [blame] | 6 | // | 
|  | 7 | //===----------------------------------------------------------------------===// | 
| Dan Gohman | ad664b3 | 2015-12-08 03:33:51 +0000 | [diff] [blame] | 8 | /// | 
|  | 9 | /// \file | 
| Adrian Prantl | 5f8f34e4 | 2018-05-01 15:54:18 +0000 | [diff] [blame] | 10 | /// This is a target description file for the WebAssembly architecture, | 
| Dan Gohman | ad664b3 | 2015-12-08 03:33:51 +0000 | [diff] [blame] | 11 | /// which is also known as "wasm". | 
|  | 12 | /// | 
| Dan Gohman | 10e730a | 2015-06-29 23:51:55 +0000 | [diff] [blame] | 13 | //===----------------------------------------------------------------------===// | 
|  | 14 |  | 
|  | 15 | //===----------------------------------------------------------------------===// | 
|  | 16 | // Target-independent interfaces which we are implementing | 
|  | 17 | //===----------------------------------------------------------------------===// | 
|  | 18 |  | 
|  | 19 | include "llvm/Target/Target.td" | 
|  | 20 |  | 
|  | 21 | //===----------------------------------------------------------------------===// | 
|  | 22 | // WebAssembly Subtarget features. | 
|  | 23 | //===----------------------------------------------------------------------===// | 
|  | 24 |  | 
| Thomas Lively | 64a39a1 | 2019-01-10 22:32:11 +0000 | [diff] [blame] | 25 | def FeatureSIMD128 : SubtargetFeature<"simd128", "SIMDLevel", "SIMD128", | 
| JF Bastien | 03855df | 2015-07-01 23:41:25 +0000 | [diff] [blame] | 26 | "Enable 128-bit SIMD">; | 
| Thomas Lively | 64a39a1 | 2019-01-10 22:32:11 +0000 | [diff] [blame] | 27 |  | 
|  | 28 | def FeatureUnimplementedSIMD128 : | 
|  | 29 | SubtargetFeature<"unimplemented-simd128", | 
|  | 30 | "SIMDLevel", "UnimplementedSIMD128", | 
|  | 31 | "Enable 128-bit SIMD not yet implemented in engines", | 
|  | 32 | [FeatureSIMD128]>; | 
|  | 33 |  | 
| Derek Schuff | 18ba192 | 2017-08-30 18:07:45 +0000 | [diff] [blame] | 34 | def FeatureAtomics : SubtargetFeature<"atomics", "HasAtomics", "true", | 
|  | 35 | "Enable Atomics">; | 
| Dan Gohman | cdd48b8 | 2017-11-28 01:13:40 +0000 | [diff] [blame] | 36 | def FeatureNontrappingFPToInt : | 
|  | 37 | SubtargetFeature<"nontrapping-fptoint", | 
|  | 38 | "HasNontrappingFPToInt", "true", | 
|  | 39 | "Enable non-trapping float-to-int conversion operators">; | 
| Dan Gohman | 10e730a | 2015-06-29 23:51:55 +0000 | [diff] [blame] | 40 |  | 
| Dan Gohman | 5d2b935 | 2018-01-19 17:16:24 +0000 | [diff] [blame] | 41 | def FeatureSignExt : | 
|  | 42 | SubtargetFeature<"sign-ext", | 
|  | 43 | "HasSignExt", "true", | 
|  | 44 | "Enable sign extension operators">; | 
|  | 45 |  | 
| Heejin Ahn | 9386bde | 2018-02-24 00:40:50 +0000 | [diff] [blame] | 46 | def FeatureExceptionHandling : | 
|  | 47 | SubtargetFeature<"exception-handling", "HasExceptionHandling", "true", | 
|  | 48 | "Enable Wasm exception handling">; | 
|  | 49 |  | 
| Thomas Lively | 88058d4 | 2019-01-31 21:02:19 +0000 | [diff] [blame^] | 50 | def FeatureBulkMemory : | 
|  | 51 | SubtargetFeature<"bulk-memory", "HasBulkMemory", "true", | 
|  | 52 | "Enable bulk memory operations">; | 
|  | 53 |  | 
| Dan Gohman | 10e730a | 2015-06-29 23:51:55 +0000 | [diff] [blame] | 54 | //===----------------------------------------------------------------------===// | 
|  | 55 | // Architectures. | 
|  | 56 | //===----------------------------------------------------------------------===// | 
|  | 57 |  | 
|  | 58 | //===----------------------------------------------------------------------===// | 
|  | 59 | // Register File Description | 
|  | 60 | //===----------------------------------------------------------------------===// | 
|  | 61 |  | 
|  | 62 | include "WebAssemblyRegisterInfo.td" | 
|  | 63 |  | 
|  | 64 | //===----------------------------------------------------------------------===// | 
|  | 65 | // Instruction Descriptions | 
|  | 66 | //===----------------------------------------------------------------------===// | 
|  | 67 |  | 
|  | 68 | include "WebAssemblyInstrInfo.td" | 
|  | 69 |  | 
|  | 70 | def WebAssemblyInstrInfo : InstrInfo; | 
|  | 71 |  | 
|  | 72 | //===----------------------------------------------------------------------===// | 
|  | 73 | // WebAssembly Processors supported. | 
|  | 74 | //===----------------------------------------------------------------------===// | 
|  | 75 |  | 
| JF Bastien | 03855df | 2015-07-01 23:41:25 +0000 | [diff] [blame] | 76 | // Minimal Viable Product. | 
|  | 77 | def : ProcessorModel<"mvp", NoSchedModel, []>; | 
|  | 78 |  | 
| JF Bastien | 088c47e | 2015-07-27 23:25:54 +0000 | [diff] [blame] | 79 | // Generic processor: latest stable version. | 
|  | 80 | def : ProcessorModel<"generic", NoSchedModel, []>; | 
|  | 81 |  | 
| JF Bastien | 03855df | 2015-07-01 23:41:25 +0000 | [diff] [blame] | 82 | // Latest and greatest experimental version of WebAssembly. Bugs included! | 
| Derek Schuff | 18ba192 | 2017-08-30 18:07:45 +0000 | [diff] [blame] | 83 | def : ProcessorModel<"bleeding-edge", NoSchedModel, | 
| Thomas Lively | 936734b | 2018-11-10 00:11:14 +0000 | [diff] [blame] | 84 | [FeatureSIMD128, FeatureAtomics, | 
|  | 85 | FeatureNontrappingFPToInt, FeatureSignExt]>; | 
| Dan Gohman | 10e730a | 2015-06-29 23:51:55 +0000 | [diff] [blame] | 86 |  | 
|  | 87 | //===----------------------------------------------------------------------===// | 
|  | 88 | // Target Declaration | 
|  | 89 | //===----------------------------------------------------------------------===// | 
|  | 90 |  | 
| Derek Schuff | e482597 | 2018-03-20 20:06:35 +0000 | [diff] [blame] | 91 | def WebAssemblyAsmParser : AsmParser { | 
|  | 92 | // The physical register names are not in the binary format or asm text | 
|  | 93 | let ShouldEmitMatchRegisterName = 0; | 
|  | 94 | } | 
| Reid Kleckner | 440219d5 | 2018-03-21 21:46:47 +0000 | [diff] [blame] | 95 |  | 
| Sam Clegg | 16c1682 | 2018-05-10 22:16:44 +0000 | [diff] [blame] | 96 | def WebAssemblyAsmWriter : AsmWriter { | 
|  | 97 | string AsmWriterClassName  = "InstPrinter"; | 
|  | 98 | int PassSubtarget = 0; | 
|  | 99 | int Variant = 0; | 
|  | 100 | bit isMCAsmWriter = 1; | 
|  | 101 | } | 
|  | 102 |  | 
| Reid Kleckner | 440219d5 | 2018-03-21 21:46:47 +0000 | [diff] [blame] | 103 | def WebAssembly : Target { | 
|  | 104 | let InstructionSet = WebAssemblyInstrInfo; | 
|  | 105 | let AssemblyParsers  = [WebAssemblyAsmParser]; | 
| Sam Clegg | 16c1682 | 2018-05-10 22:16:44 +0000 | [diff] [blame] | 106 | let AssemblyWriters = [WebAssemblyAsmWriter]; | 
| Reid Kleckner | 440219d5 | 2018-03-21 21:46:47 +0000 | [diff] [blame] | 107 | } |