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Dan Gohman10e730a2015-06-29 23:51:55 +00001//- WebAssembly.td - Describe the WebAssembly Target Machine --*- tablegen -*-//
2//
Chandler Carruth2946cd72019-01-19 08:50:56 +00003// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
Dan Gohman10e730a2015-06-29 23:51:55 +00006//
7//===----------------------------------------------------------------------===//
Dan Gohmanad664b32015-12-08 03:33:51 +00008///
9/// \file
Adrian Prantl5f8f34e42018-05-01 15:54:18 +000010/// This is a target description file for the WebAssembly architecture,
Dan Gohmanad664b32015-12-08 03:33:51 +000011/// which is also known as "wasm".
12///
Dan Gohman10e730a2015-06-29 23:51:55 +000013//===----------------------------------------------------------------------===//
14
15//===----------------------------------------------------------------------===//
16// Target-independent interfaces which we are implementing
17//===----------------------------------------------------------------------===//
18
19include "llvm/Target/Target.td"
20
21//===----------------------------------------------------------------------===//
22// WebAssembly Subtarget features.
23//===----------------------------------------------------------------------===//
24
Thomas Lively64a39a12019-01-10 22:32:11 +000025def FeatureSIMD128 : SubtargetFeature<"simd128", "SIMDLevel", "SIMD128",
JF Bastien03855df2015-07-01 23:41:25 +000026 "Enable 128-bit SIMD">;
Thomas Lively64a39a12019-01-10 22:32:11 +000027
28def FeatureUnimplementedSIMD128 :
29 SubtargetFeature<"unimplemented-simd128",
30 "SIMDLevel", "UnimplementedSIMD128",
31 "Enable 128-bit SIMD not yet implemented in engines",
32 [FeatureSIMD128]>;
33
Derek Schuff18ba1922017-08-30 18:07:45 +000034def FeatureAtomics : SubtargetFeature<"atomics", "HasAtomics", "true",
35 "Enable Atomics">;
Dan Gohmancdd48b82017-11-28 01:13:40 +000036def FeatureNontrappingFPToInt :
37 SubtargetFeature<"nontrapping-fptoint",
38 "HasNontrappingFPToInt", "true",
39 "Enable non-trapping float-to-int conversion operators">;
Dan Gohman10e730a2015-06-29 23:51:55 +000040
Dan Gohman5d2b9352018-01-19 17:16:24 +000041def FeatureSignExt :
42 SubtargetFeature<"sign-ext",
43 "HasSignExt", "true",
44 "Enable sign extension operators">;
45
Heejin Ahn9386bde2018-02-24 00:40:50 +000046def FeatureExceptionHandling :
47 SubtargetFeature<"exception-handling", "HasExceptionHandling", "true",
48 "Enable Wasm exception handling">;
49
Thomas Lively88058d42019-01-31 21:02:19 +000050def FeatureBulkMemory :
51 SubtargetFeature<"bulk-memory", "HasBulkMemory", "true",
52 "Enable bulk memory operations">;
53
Dan Gohman10e730a2015-06-29 23:51:55 +000054//===----------------------------------------------------------------------===//
55// Architectures.
56//===----------------------------------------------------------------------===//
57
58//===----------------------------------------------------------------------===//
59// Register File Description
60//===----------------------------------------------------------------------===//
61
62include "WebAssemblyRegisterInfo.td"
63
64//===----------------------------------------------------------------------===//
65// Instruction Descriptions
66//===----------------------------------------------------------------------===//
67
68include "WebAssemblyInstrInfo.td"
69
70def WebAssemblyInstrInfo : InstrInfo;
71
72//===----------------------------------------------------------------------===//
73// WebAssembly Processors supported.
74//===----------------------------------------------------------------------===//
75
JF Bastien03855df2015-07-01 23:41:25 +000076// Minimal Viable Product.
77def : ProcessorModel<"mvp", NoSchedModel, []>;
78
JF Bastien088c47e2015-07-27 23:25:54 +000079// Generic processor: latest stable version.
80def : ProcessorModel<"generic", NoSchedModel, []>;
81
JF Bastien03855df2015-07-01 23:41:25 +000082// Latest and greatest experimental version of WebAssembly. Bugs included!
Derek Schuff18ba1922017-08-30 18:07:45 +000083def : ProcessorModel<"bleeding-edge", NoSchedModel,
Thomas Lively936734b2018-11-10 00:11:14 +000084 [FeatureSIMD128, FeatureAtomics,
85 FeatureNontrappingFPToInt, FeatureSignExt]>;
Dan Gohman10e730a2015-06-29 23:51:55 +000086
87//===----------------------------------------------------------------------===//
88// Target Declaration
89//===----------------------------------------------------------------------===//
90
Derek Schuffe4825972018-03-20 20:06:35 +000091def WebAssemblyAsmParser : AsmParser {
92 // The physical register names are not in the binary format or asm text
93 let ShouldEmitMatchRegisterName = 0;
94}
Reid Kleckner440219d52018-03-21 21:46:47 +000095
Sam Clegg16c16822018-05-10 22:16:44 +000096def WebAssemblyAsmWriter : AsmWriter {
97 string AsmWriterClassName = "InstPrinter";
98 int PassSubtarget = 0;
99 int Variant = 0;
100 bit isMCAsmWriter = 1;
101}
102
Reid Kleckner440219d52018-03-21 21:46:47 +0000103def WebAssembly : Target {
104 let InstructionSet = WebAssemblyInstrInfo;
105 let AssemblyParsers = [WebAssemblyAsmParser];
Sam Clegg16c16822018-05-10 22:16:44 +0000106 let AssemblyWriters = [WebAssemblyAsmWriter];
Reid Kleckner440219d52018-03-21 21:46:47 +0000107}