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gerrit-public.fairphone.software / toolchain / llvm-project / 882c43d703cd63889a5541bf8f2c014733cbbbee / . / llvm / lib / Target / AMDGPU / AMDGPUInstructionSelector.h
blob: d3c83a6a872a4b9f5cf3545a9de30f1787391509 [file] [log] [blame]
Tom Stellardca166212017-01-30 21:56:46 +0000[diff] [blame]1//===- AMDGPUInstructionSelector --------------------------------*- C++ -*-==//
2//
Chandler Carruth2946cd72019-01-19 08:50:56 +0000[diff] [blame]3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
Tom Stellardca166212017-01-30 21:56:46 +0000[diff] [blame]6//
7//===----------------------------------------------------------------------===//
8/// \file
9/// This file declares the targeting of the InstructionSelector class for
10/// AMDGPU.
11//===----------------------------------------------------------------------===//
12
13#ifndef LLVM_LIB_TARGET_AMDGPU_AMDGPUINSTRUCTIONSELECTOR_H
14#define LLVM_LIB_TARGET_AMDGPU_AMDGPUINSTRUCTIONSELECTOR_H
15
Yaxun Liu1a14bfa2017-03-27 14:04:01 +0000[diff] [blame]16#include "AMDGPU.h"
Matt Arsenaultb1cc4f52018-06-25 16:17:48 +0000[diff] [blame]17#include "AMDGPUArgumentUsageInfo.h"
Tom Stellardca166212017-01-30 21:56:46 +0000[diff] [blame]18#include "llvm/ADT/ArrayRef.h"
19#include "llvm/ADT/SmallVector.h"
Matt Arsenault2ab25f92019-07-01 16:06:02 +0000[diff] [blame]20#include "llvm/CodeGen/Register.h"
Chandler Carruth6bda14b2017-06-06 11:49:48 +0000[diff] [blame]21#include "llvm/CodeGen/GlobalISel/InstructionSelector.h"
Matt Arsenault3b7668a2019-07-01 13:34:26 +0000[diff] [blame]22#include "llvm/IR/InstrTypes.h"
Tom Stellardca166212017-01-30 21:56:46 +0000[diff] [blame]23
Tom Stellard1dc90202018-05-10 20:53:06 +0000[diff] [blame]24namespace {
25#define GET_GLOBALISEL_PREDICATE_BITSET
Tom Stellard5bfbae52018-07-11 20:59:01 +0000[diff] [blame]26#define AMDGPUSubtarget GCNSubtarget
Tom Stellard1dc90202018-05-10 20:53:06 +0000[diff] [blame]27#include "AMDGPUGenGlobalISel.inc"
28#undef GET_GLOBALISEL_PREDICATE_BITSET
Tom Stellard5bfbae52018-07-11 20:59:01 +0000[diff] [blame]29#undef AMDGPUSubtarget
Tom Stellard1dc90202018-05-10 20:53:06 +0000[diff] [blame]30}
31
Tom Stellardca166212017-01-30 21:56:46 +0000[diff] [blame]32namespace llvm {
33
34class AMDGPUInstrInfo;
35class AMDGPURegisterBankInfo;
Tom Stellard5bfbae52018-07-11 20:59:01 +0000[diff] [blame]36class GCNSubtarget;
Tom Stellardca166212017-01-30 21:56:46 +0000[diff] [blame]37class MachineInstr;
Matt Arsenault3ecab8e2019-09-19 16:26:14 +0000[diff] [blame]38class MachineIRBuilder;
Tom Stellardca166212017-01-30 21:56:46 +0000[diff] [blame]39class MachineOperand;
40class MachineRegisterInfo;
41class SIInstrInfo;
Matt Arsenaultb1cc4f52018-06-25 16:17:48 +0000[diff] [blame]42class SIMachineFunctionInfo;
Tom Stellardca166212017-01-30 21:56:46 +0000[diff] [blame]43class SIRegisterInfo;
Tom Stellardca166212017-01-30 21:56:46 +0000[diff] [blame]44
45class AMDGPUInstructionSelector : public InstructionSelector {
Matt Arsenault76f44f62019-09-28 03:41:13 +0000[diff] [blame]46private:
47 MachineRegisterInfo *MRI;
48
Tom Stellardca166212017-01-30 21:56:46 +0000[diff] [blame]49public:
Tom Stellard5bfbae52018-07-11 20:59:01 +0000[diff] [blame]50 AMDGPUInstructionSelector(const GCNSubtarget &STI,
Tom Stellard1dc90202018-05-10 20:53:06 +0000[diff] [blame]51 const AMDGPURegisterBankInfo &RBI,
52 const AMDGPUTargetMachine &TM);
Tom Stellardca166212017-01-30 21:56:46 +0000[diff] [blame]53
Amara Emersone14c91b2019-08-13 06:26:59 +0000[diff] [blame]54 bool select(MachineInstr &I) override;
Tom Stellard1dc90202018-05-10 20:53:06 +0000[diff] [blame]55 static const char *getName();
Daniel Sandersf76f3152017-11-16 00:46:35 +0000[diff] [blame]56
Matt Arsenault76f44f62019-09-28 03:41:13 +0000[diff] [blame]57 void setupMF(MachineFunction &MF, GISelKnownBits &KB,
58 CodeGenCoverage &CoverageInfo) override;
59
Tom Stellardca166212017-01-30 21:56:46 +0000[diff] [blame]60private:
61 struct GEPInfo {
62 const MachineInstr &GEP;
63 SmallVector<unsigned, 2> SgprParts;
64 SmallVector<unsigned, 2> VgprParts;
65 int64_t Imm;
66 GEPInfo(const MachineInstr &GEP) : GEP(GEP), Imm(0) { }
67 };
68
Tom Stellard79b5c382019-02-20 21:02:37 +0000[diff] [blame]69 bool isInstrUniform(const MachineInstr &MI) const;
Matt Arsenault2ab25f92019-07-01 16:06:02 +0000[diff] [blame]70 bool isVCC(Register Reg, const MachineRegisterInfo &MRI) const;
71
Tom Stellard1dc90202018-05-10 20:53:06 +0000[diff] [blame]72 /// tblgen-erated 'select' implementation.
73 bool selectImpl(MachineInstr &I, CodeGenCoverage &CoverageInfo) const;
74
Matt Arsenault0a52e9d2019-07-01 16:34:48 +0000[diff] [blame]75 MachineOperand getSubOperand64(MachineOperand &MO,
76 const TargetRegisterClass &SubRC,
77 unsigned SubIdx) const;
Tom Stellard1e0edad2018-05-10 21:20:10 +0000[diff] [blame]78 bool selectCOPY(MachineInstr &I) const;
Matt Arsenaulte1006252019-07-01 16:32:47 +0000[diff] [blame]79 bool selectPHI(MachineInstr &I) const;
Matt Arsenaultdbb6c032019-06-24 18:02:18 +0000[diff] [blame]80 bool selectG_TRUNC(MachineInstr &I) const;
Matt Arsenaultd7ffa2a2019-06-25 13:18:11 +0000[diff] [blame]81 bool selectG_SZA_EXT(MachineInstr &I) const;
Matt Arsenaultfdea5e02019-10-01 02:23:20 +0000[diff] [blame]82 bool selectG_SITOFP_UITOFP(MachineInstr &I) const;
Tom Stellardca166212017-01-30 21:56:46 +0000[diff] [blame]83 bool selectG_CONSTANT(MachineInstr &I) const;
Matt Arsenaultc8291c92019-07-15 19:50:07 +0000[diff] [blame]84 bool selectG_AND_OR_XOR(MachineInstr &I) const;
Matt Arsenaulte6d10f92019-07-09 14:05:11 +0000[diff] [blame]85 bool selectG_ADD_SUB(MachineInstr &I) const;
Matt Arsenault54167ea2019-10-01 01:23:13 +0000[diff] [blame]86 bool selectG_UADDO_USUBO(MachineInstr &I) const;
Tom Stellard41f32192019-02-28 23:37:48 +0000[diff] [blame]87 bool selectG_EXTRACT(MachineInstr &I) const;
Matt Arsenault9b7ffc42019-07-09 14:02:20 +0000[diff] [blame]88 bool selectG_MERGE_VALUES(MachineInstr &I) const;
Matt Arsenault872f38b2019-07-09 14:02:26 +0000[diff] [blame]89 bool selectG_UNMERGE_VALUES(MachineInstr &I) const;
Tom Stellardca166212017-01-30 21:56:46 +0000[diff] [blame]90 bool selectG_GEP(MachineInstr &I) const;
Tom Stellard3f1c6fe2018-06-21 23:38:20 +0000[diff] [blame]91 bool selectG_IMPLICIT_DEF(MachineInstr &I) const;
Tom Stellard33634d1b2019-03-01 00:50:26 +0000[diff] [blame]92 bool selectG_INSERT(MachineInstr &I) const;
Amara Emersone14c91b2019-08-13 06:26:59 +0000[diff] [blame]93 bool selectG_INTRINSIC(MachineInstr &I) const;
Matt Arsenault3ecab8e2019-09-19 16:26:14 +0000[diff] [blame]94
95 std::tuple<Register, unsigned, unsigned>
96 splitBufferOffsets(MachineIRBuilder &B, Register OrigOffset) const;
97
98 bool selectStoreIntrinsic(MachineInstr &MI, bool IsFormat) const;
99
Amara Emersone14c91b2019-08-13 06:26:59 +0000[diff] [blame]100 bool selectG_INTRINSIC_W_SIDE_EFFECTS(MachineInstr &I) const;
Matt Arsenault3b7668a2019-07-01 13:34:26 +0000[diff] [blame]101 int getS_CMPOpcode(CmpInst::Predicate P, unsigned Size) const;
Tom Stellard8b1c53b2019-06-17 16:27:43 +0000[diff] [blame]102 bool selectG_ICMP(MachineInstr &I) const;
Tom Stellardca166212017-01-30 21:56:46 +0000[diff] [blame]103 bool hasVgprParts(ArrayRef<GEPInfo> AddrInfo) const;
104 void getAddrModeInfo(const MachineInstr &Load, const MachineRegisterInfo &MRI,
105 SmallVectorImpl<GEPInfo> &AddrInfo) const;
106 bool selectSMRD(MachineInstr &I, ArrayRef<GEPInfo> AddrInfo) const;
Matt Arsenault3baf4d32019-08-01 03:09:15 +0000[diff] [blame]107
108 void initM0(MachineInstr &I) const;
Amara Emersone14c91b2019-08-13 06:26:59 +0000[diff] [blame]109 bool selectG_LOAD_ATOMICRMW(MachineInstr &I) const;
110 bool selectG_STORE(MachineInstr &I) const;
Tom Stellard8b1c53b2019-06-17 16:27:43 +0000[diff] [blame]111 bool selectG_SELECT(MachineInstr &I) const;
Matt Arsenault64642802019-07-01 15:39:27 +0000[diff] [blame]112 bool selectG_BRCOND(MachineInstr &I) const;
Matt Arsenaultcda82f02019-07-01 15:48:18 +0000[diff] [blame]113 bool selectG_FRAME_INDEX(MachineInstr &I) const;
Matt Arsenaultc34b4032019-09-09 15:46:13 +0000[diff] [blame]114 bool selectG_PTR_MASK(MachineInstr &I) const;
Tom Stellardca166212017-01-30 21:56:46 +0000[diff] [blame]115
Matt Arsenault4f64ade2019-07-01 15:18:56 +0000[diff] [blame]116 std::pair<Register, unsigned>
Matt Arsenault76f44f62019-09-28 03:41:13 +0000[diff] [blame]117 selectVOP3ModsImpl(Register Src) const;
Matt Arsenault4f64ade2019-07-01 15:18:56 +0000[diff] [blame]118
Tom Stellard1dc90202018-05-10 20:53:06 +0000[diff] [blame]119 InstructionSelector::ComplexRendererFns
Tom Stellard26fac0f2018-06-22 02:54:57 +0000[diff] [blame]120 selectVCSRC(MachineOperand &Root) const;
121
122 InstructionSelector::ComplexRendererFns
Tom Stellard1dc90202018-05-10 20:53:06 +0000[diff] [blame]123 selectVSRC0(MachineOperand &Root) const;
124
Tom Stellarddcc95e92018-05-11 05:44:16 +0000[diff] [blame]125 InstructionSelector::ComplexRendererFns
126 selectVOP3Mods0(MachineOperand &Root) const;
Tom Stellard46bbbc32018-06-13 22:30:47 +0000[diff] [blame]127 InstructionSelector::ComplexRendererFns
Matt Arsenault77e3e9c2019-09-09 18:29:45 +0000[diff] [blame]128 selectVOP3Mods0Clamp0OMod(MachineOperand &Root) const;
129 InstructionSelector::ComplexRendererFns
Tom Stellard9a653572018-06-22 02:34:29 +0000[diff] [blame]130 selectVOP3OMods(MachineOperand &Root) const;
131 InstructionSelector::ComplexRendererFns
Tom Stellard46bbbc32018-06-13 22:30:47 +0000[diff] [blame]132 selectVOP3Mods(MachineOperand &Root) const;
Tom Stellarddcc95e92018-05-11 05:44:16 +0000[diff] [blame]133
Tom Stellard79b5c382019-02-20 21:02:37 +0000[diff] [blame]134 InstructionSelector::ComplexRendererFns
Matt Arsenaultd6c1f5b2019-09-09 18:29:37 +0000[diff] [blame]135 selectVOP3OpSelMods0(MachineOperand &Root) const;
136 InstructionSelector::ComplexRendererFns
137 selectVOP3OpSelMods(MachineOperand &Root) const;
138
139 InstructionSelector::ComplexRendererFns
Tom Stellard79b5c382019-02-20 21:02:37 +0000[diff] [blame]140 selectSmrdImm(MachineOperand &Root) const;
141 InstructionSelector::ComplexRendererFns
142 selectSmrdImm32(MachineOperand &Root) const;
143 InstructionSelector::ComplexRendererFns
144 selectSmrdSgpr(MachineOperand &Root) const;
145
Matt Arsenault35c96592019-07-16 18:05:29 +0000[diff] [blame]146 template <bool Signed>
147 InstructionSelector::ComplexRendererFns
148 selectFlatOffsetImpl(MachineOperand &Root) const;
149 InstructionSelector::ComplexRendererFns
150 selectFlatOffset(MachineOperand &Root) const;
151
152 InstructionSelector::ComplexRendererFns
153 selectFlatOffsetSigned(MachineOperand &Root) const;
154
Matt Arsenault7161fb02019-07-16 19:22:21 +0000[diff] [blame]155 InstructionSelector::ComplexRendererFns
156 selectMUBUFScratchOffen(MachineOperand &Root) const;
157 InstructionSelector::ComplexRendererFns
158 selectMUBUFScratchOffset(MachineOperand &Root) const;
159
Matt Arsenault35940112019-08-01 00:53:38 +0000[diff] [blame]160 bool isDSOffsetLegal(const MachineRegisterInfo &MRI,
161 const MachineOperand &Base,
162 int64_t Offset, unsigned OffsetBits) const;
163
164 InstructionSelector::ComplexRendererFns
165 selectDS1Addr1Offset(MachineOperand &Root) const;
166
Matt Arsenault59b91aa2019-10-01 02:07:25 +0000[diff] [blame]167 void renderTruncImm32(MachineInstrBuilder &MIB,
168 const MachineInstr &MI) const;
169
Tom Stellardca166212017-01-30 21:56:46 +0000[diff] [blame]170 const SIInstrInfo &TII;
171 const SIRegisterInfo &TRI;
172 const AMDGPURegisterBankInfo &RBI;
Tom Stellard1dc90202018-05-10 20:53:06 +0000[diff] [blame]173 const AMDGPUTargetMachine &TM;
Tom Stellard5bfbae52018-07-11 20:59:01 +0000[diff] [blame]174 const GCNSubtarget &STI;
Tom Stellard1dc90202018-05-10 20:53:06 +0000[diff] [blame]175 bool EnableLateStructurizeCFG;
176#define GET_GLOBALISEL_PREDICATES_DECL
Tom Stellard5bfbae52018-07-11 20:59:01 +0000[diff] [blame]177#define AMDGPUSubtarget GCNSubtarget
Tom Stellard1dc90202018-05-10 20:53:06 +0000[diff] [blame]178#include "AMDGPUGenGlobalISel.inc"
179#undef GET_GLOBALISEL_PREDICATES_DECL
Tom Stellard5bfbae52018-07-11 20:59:01 +0000[diff] [blame]180#undef AMDGPUSubtarget
Tom Stellard1dc90202018-05-10 20:53:06 +0000[diff] [blame]181
182#define GET_GLOBALISEL_TEMPORARIES_DECL
183#include "AMDGPUGenGlobalISel.inc"
184#undef GET_GLOBALISEL_TEMPORARIES_DECL
Tom Stellardca166212017-01-30 21:56:46 +0000[diff] [blame]185};
186
187} // End llvm namespace.
188#endif