blob: 4c1f2a741e4764fb7177bed4060899a2ed031807 [file] [log] [blame]
David Peixotto6eecb282013-02-13 19:21:47 +00001;PR14492 - Tablegen incorrectly converts ARM tLDMIA_UPD pseudo to tLDMIA
2;RUN: llc -mtriple=thumbv7 < %s | FileCheck -check-prefix=EXPECTED %s
3;RUN: llc -mtriple=thumbv7 < %s | FileCheck %s
4
Stephen Lind24ab202013-07-14 06:24:09 +00005;EXPECTED-LABEL: foo:
6;CHECK-LABEL: foo:
David Peixotto6eecb282013-02-13 19:21:47 +00007define i32 @foo(i32* %a) nounwind optsize {
8entry:
David Blaikiea79ac142015-02-27 21:17:42 +00009 %0 = load i32, i32* %a, align 4
David Blaikie79e6c742015-02-27 19:29:02 +000010 %arrayidx1 = getelementptr inbounds i32, i32* %a, i32 1
David Blaikiea79ac142015-02-27 21:17:42 +000011 %1 = load i32, i32* %arrayidx1, align 4
David Blaikie79e6c742015-02-27 19:29:02 +000012 %arrayidx2 = getelementptr inbounds i32, i32* %a, i32 2
David Blaikiea79ac142015-02-27 21:17:42 +000013 %2 = load i32, i32* %arrayidx2, align 4
David Blaikie79e6c742015-02-27 19:29:02 +000014 %add.ptr = getelementptr inbounds i32, i32* %a, i32 3
David Peixotto6eecb282013-02-13 19:21:47 +000015;Make sure we do not have a duplicated register in the front of the reg list
16;EXPECTED: ldm [[BASE:r[0-9]+]]!, {[[REG:r[0-9]+]], {{r[0-9]+}},
17;CHECK-NOT: ldm [[BASE:r[0-9]+]]!, {[[REG:r[0-9]+]], [[REG]],
18 tail call void @bar(i32* %add.ptr) nounwind optsize
19 %add = add nsw i32 %1, %0
20 %add3 = add nsw i32 %add, %2
21 ret i32 %add3
22}
23
24declare void @bar(i32*) optsize