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gerrit-public.fairphone.software / toolchain / llvm-project / 91be65be656072a68b51a8c4e7bb751ea475d896 / . / llvm / test / CodeGen / ARM / fcmp-xo.ll
blob: c36ab09335532828ad4a991096682d76c6983623 [file] [log] [blame]
Christof Doumaa1e77c02018-03-28 10:02:26 +0000[diff] [blame]1; RUN: llc -mtriple=thumbv7m-arm-none-eabi -mattr=+execute-only,+fp-armv8 %s -o - | FileCheck --check-prefixes=CHECK,VMOVSR %s
2; RUN: llc -mtriple=thumbv7m-arm-none-eabi -mattr=+execute-only,+fp-armv8,+neon,+neonfp %s -o - | FileCheck --check-prefixes=CHECK,NEON %s
Christof Douma4a025cc2018-03-23 13:02:03 +0000[diff] [blame]3
Christof Doumaa1e77c02018-03-28 10:02:26 +0000[diff] [blame]4define arm_aapcs_vfpcc float @foo0() local_unnamed_addr {
5 %1 = fcmp nsz olt float undef, 0.000000e+00
6 %2 = select i1 %1, float -5.000000e-01, float 5.000000e-01
7 ret float %2
Christof Douma4a025cc2018-03-23 13:02:03 +0000[diff] [blame]8}
9; CHECK-LABEL: foo0
10; CHECK: vcmpe.f32 {{s[0-9]+}}, #0
11
12
Christof Doumaa1e77c02018-03-28 10:02:26 +0000[diff] [blame]13define arm_aapcs_vfpcc float @float1() local_unnamed_addr {
Christof Douma4a025cc2018-03-23 13:02:03 +0000[diff] [blame]14 br i1 undef, label %.end, label %1
15
16 %2 = fcmp nsz olt float undef, 1.000000e+00
17 %3 = select i1 %2, float -5.000000e-01, float 5.000000e-01
Christof Douma4a025cc2018-03-23 13:02:03 +0000[diff] [blame]18 br label %.end
19
20.end:
Christof Doumaa1e77c02018-03-28 10:02:26 +0000[diff] [blame]21 %4 = phi float [ undef, %0 ], [ %3, %1]
22 ret float %4
Christof Douma4a025cc2018-03-23 13:02:03 +0000[diff] [blame]23}
24; CHECK-LABEL: float1
25; CHECK: vmov.f32 [[FPREG:s[0-9]+]], #1.000000e+00
26; CHECK: vcmpe.f32 [[FPREG]], {{s[0-9]+}}
27
Christof Doumaa1e77c02018-03-28 10:02:26 +0000[diff] [blame]28define arm_aapcs_vfpcc float @float128() local_unnamed_addr {
29 %1 = fcmp nsz olt float undef, 128.000000e+00
30 %2 = select i1 %1, float -5.000000e-01, float 5.000000e-01
31 ret float %2
Christof Douma4a025cc2018-03-23 13:02:03 +0000[diff] [blame]32}
33; CHECK-LABEL: float128
34; CHECK: mov.w [[REG:r[0-9]+]], #1124073472
Christof Doumaa1e77c02018-03-28 10:02:26 +0000[diff] [blame]35; VMOVSR: vmov [[FPREG:s[0-9]+]], [[REG]]
36; VMOVSR: vcmpe.f32 [[FPREG]], {{s[0-9]+}}
37; NEON: vmov d2, [[REG]], [[REG]]
38; NEON: vcmpe.f32 s4, {{s[0-9]+}}
Christof Douma4a025cc2018-03-23 13:02:03 +0000[diff] [blame]39
40
Christof Doumaa1e77c02018-03-28 10:02:26 +0000[diff] [blame]41define arm_aapcs_vfpcc double @double1() local_unnamed_addr {
42 %1 = fcmp nsz olt double undef, 1.000000e+00
43 %2 = select i1 %1, double -5.000000e-01, double 5.000000e-01
44 ret double %2
Christof Douma4a025cc2018-03-23 13:02:03 +0000[diff] [blame]45}
46; CHECK-LABEL: double1
47; CHECK: vmov.f64 [[FPREG:d[0-9]+]], #1.000000e+00
48; CHECK: vcmpe.f64 [[FPREG]], {{d[0-9]+}}
49
Christof Doumaa1e77c02018-03-28 10:02:26 +0000[diff] [blame]50define arm_aapcs_vfpcc double @double128() local_unnamed_addr {
51 %1 = fcmp nsz olt double undef, 128.000000e+00
52 %2 = select i1 %1, double -5.000000e-01, double 5.000000e-01
53 ret double %2
Christof Douma4a025cc2018-03-23 13:02:03 +0000[diff] [blame]54}
55; CHECK-LABEL: double128
Christof Douma4a025cc2018-03-23 13:02:03 +0000[diff] [blame]56; CHECK: movs [[REGH:r[0-9]+]], #0
57; CHECK: movt [[REGH]], #16480
Christof Doumaa1e77c02018-03-28 10:02:26 +0000[diff] [blame]58; CHECK: movs [[REGL:r[0-9]+]], #0
Christof Douma4a025cc2018-03-23 13:02:03 +0000[diff] [blame]59; CHECK: vmov [[FPREG:d[0-9]+]], [[REGL]], [[REGH]]
60; CHECK: vcmpe.f64 [[FPREG]], {{d[0-9]+}}
61